| /kernel/linux/linux-5.10/include/asm-generic/ |
| D | tlb.h | 2 /* include/asm-generic/tlb.h
4 * Generic TLB shootdown code
35 * correct and efficient ordering of freeing pages and TLB invalidations.
40 * 2) TLB invalidate page
51 * Finish in particular will issue a (final) TLB invalidate and free
86 * tlb_flush_mmu_tlbonly() - does the TLB invalidate (and resets
89 * tlb_flush_mmu() - in addition to the above TLB invalidate, also frees
106 * flush the entire TLB irrespective of the range. For instance
125 * returns the smallest TLB entry size unmapped in this range.
138 * This might be useful if your architecture has size specific TLB
[all …]
|
| /kernel/linux/linux-5.10/mm/ |
| D | mmu_gather.c | 12 #include <asm/tlb.h>
16 static bool tlb_next_batch(struct mmu_gather *tlb) in tlb_next_batch() argument
20 batch = tlb->active; in tlb_next_batch()
22 tlb->active = batch->next; in tlb_next_batch()
26 if (tlb->batch_count == MAX_GATHER_BATCH_COUNT) in tlb_next_batch()
33 tlb->batch_count++; in tlb_next_batch()
38 tlb->active->next = batch; in tlb_next_batch()
39 tlb->active = batch; in tlb_next_batch()
44 static void tlb_batch_pages_flush(struct mmu_gather *tlb) in tlb_batch_pages_flush() argument
48 for (batch = &tlb->local; batch && batch->nr; batch = batch->next) { in tlb_batch_pages_flush()
[all …]
|
| /kernel/linux/linux-5.10/arch/arm64/include/asm/ |
| D | tlb.h | 3 * Based on arch/arm/include/asm/tlb.h
20 static void tlb_flush(struct mmu_gather *tlb);
22 #include <asm-generic/tlb.h>
29 static inline int tlb_get_level(struct mmu_gather *tlb) in tlb_get_level() argument
32 if (tlb->freed_tables) in tlb_get_level()
35 if (tlb->cleared_ptes && !(tlb->cleared_pmds || in tlb_get_level()
36 tlb->cleared_puds || in tlb_get_level()
37 tlb->cleared_p4ds)) in tlb_get_level()
40 if (tlb->cleared_pmds && !(tlb->cleared_ptes || in tlb_get_level()
41 tlb->cleared_puds || in tlb_get_level()
[all …]
|
| /kernel/linux/linux-5.10/arch/s390/include/asm/ |
| D | tlb.h | 6 * TLB flushing on s390 is complicated. The following requirement
14 * AND PURGE instruction that purges the TLB."
26 static inline void tlb_flush(struct mmu_gather *tlb);
27 static inline bool __tlb_remove_page_size(struct mmu_gather *tlb,
30 #define tlb_start_vma(tlb, vma) do { } while (0) argument
31 #define tlb_end_vma(tlb, vma) do { } while (0) argument
40 #include <asm-generic/tlb.h>
44 * tlb_ptep_clear_flush. In both flush modes the tlb for a page cache page
47 static inline bool __tlb_remove_page_size(struct mmu_gather *tlb, in __tlb_remove_page_size() argument
54 static inline void tlb_flush(struct mmu_gather *tlb) in tlb_flush() argument
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/powerpc/power8/ |
| D | translation.json | 5 "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 16G",
11 "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 16M",
17 "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 4K",
23 "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 64K",
29 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from anothe…
35 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another …
41 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 due to a data…
47 …"BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the loc…
53 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without d…
59 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 without confl…
[all …]
|
| /kernel/linux/linux-5.10/arch/mips/kvm/ |
| D | tlb.c | 6 * KVM/MIPS TLB handling, this file is part of the Linux host kernel so that
7 * TLB handlers run from KSEG0
26 #include <asm/tlb.h>
71 /* Structure defining an tlb entry data set. */
91 struct kvm_mips_tlb tlb; in kvm_mips_dump_guest_tlbs() local
98 tlb = vcpu->arch.guest_tlb[i]; in kvm_mips_dump_guest_tlbs()
99 kvm_info("TLB%c%3d Hi 0x%08lx ", in kvm_mips_dump_guest_tlbs()
100 (tlb.tlb_lo[0] | tlb.tlb_lo[1]) & ENTRYLO_V in kvm_mips_dump_guest_tlbs()
102 i, tlb.tlb_hi); in kvm_mips_dump_guest_tlbs()
104 (u64) mips3_tlbpfn_to_paddr(tlb.tlb_lo[0]), in kvm_mips_dump_guest_tlbs()
[all …]
|
| /kernel/linux/linux-5.10/arch/x86/include/asm/ |
| D | tlb.h | 5 #define tlb_start_vma(tlb, vma) do { } while (0) argument
6 #define tlb_end_vma(tlb, vma) do { } while (0) argument
7 #define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0) argument
10 static inline void tlb_flush(struct mmu_gather *tlb);
12 #include <asm-generic/tlb.h>
14 static inline void tlb_flush(struct mmu_gather *tlb) in tlb_flush() argument
17 unsigned int stride_shift = tlb_get_unmap_shift(tlb); in tlb_flush()
19 if (!tlb->fullmm && !tlb->need_flush_all) { in tlb_flush()
20 start = tlb->start; in tlb_flush()
21 end = tlb->end; in tlb_flush()
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/ |
| D | cache.json | 9 …ublicDescription": "L1 instruction TLB refill. This event counts any refill of the instruction L1 …
12 "BriefDescription": "L1 instruction TLB refill"
27 …"PublicDescription": "L1 data TLB refill. This event counts any refill of the data L1 TLB from the…
30 "BriefDescription": "L1 data TLB refill"
69 …blicDescription": "Level 1 data TLB access. This event counts any load or store operation which ac…
72 "BriefDescription": "Level 1 data TLB access."
75 …cription": "Level 1 instruction TLB access. This event counts any instruction fetch which accesses…
78 "BriefDescription": "Level 1 instruction TLB access"
99 …cDescription": "Attributable L2 data or unified TLB refill. This event counts on anyrefill of the …
102 "BriefDescription": "Attributable L2 data or unified TLB refill"
[all …]
|
| /kernel/linux/linux-5.10/arch/arm/include/asm/ |
| D | tlb.h | 3 * arch/arm/include/asm/tlb.h
8 * to use the "invalidate whole tlb" rather than "invalidate single
9 * tlb" for this.
23 #define tlb_flush(tlb) ((void) tlb) argument
25 #include <asm-generic/tlb.h>
37 #include <asm-generic/tlb.h>
40 __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte, unsigned long addr) in __pte_free_tlb() argument
50 __tlb_adjust_range(tlb, addr - PAGE_SIZE, 2 * PAGE_SIZE); in __pte_free_tlb()
53 tlb_remove_table(tlb, pte); in __pte_free_tlb()
57 __pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmdp, unsigned long addr) in __pmd_free_tlb() argument
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/arm64/ampere/emag/ |
| D | cache.json | 48 "PublicDescription": "Level 1 instruction TLB refill",
51 "BriefDescription": "L1I TLB refill"
66 "PublicDescription": "Level 1 data TLB refill",
69 "BriefDescription": "L1D TLB refill"
96 …blicDescription": "Level 1 data TLB access. This event counts any load or store operation which ac…
99 "BriefDescription": "L1D TLB access"
102 …cription": "Level 1 instruction TLB access. This event counts any instruction fetch which accesses…
105 "BriefDescription": "L1I TLB access"
108 …"PublicDescription": "Level 2 access to data TLB that caused a page table walk. This event counts …
111 "BriefDescription": "L2D TLB access"
[all …]
|
| /kernel/linux/linux-5.10/Documentation/x86/ |
| D | tlb.rst | 4 The TLB
10 1. Flush the entire TLB with a two-instruction sequence. This is
11 a quick operation, but it causes collateral damage: TLB entries
17 damage to other TLB entries.
23 entire TLB than doing 2^48/PAGE_SIZE individual flushes.
24 2. The contents of the TLB. If the TLB is empty, then there will
28 3. The size of the TLB. The larger the TLB, the more collateral
29 damage we do with a full flush. So, the larger the TLB, the
32 4. The microarchitecture. The TLB has become a multi-level
37 especially the contents of the TLB during a given flush. The
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/nios2/ |
| D | nios2.txt | 23 - altr,tlb-num-ways: Specifies the number of set-associativity ways in the TLB.
24 - altr,tlb-num-entries: Specifies the number of entries in the TLB.
25 - altr,tlb-ptr-sz: Specifies size of TLB pointer.
30 - altr,fast-tlb-miss-addr: Specifies CPU fast TLB miss exception address
52 altr,tlb-num-ways = <16>;
53 altr,tlb-num-entries = <128>;
54 altr,tlb-ptr-sz = <7>;
58 altr,fast-tlb-miss-addr = <0xc7fff400>;
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/icelake/ |
| D | virtual-memory.json | 4 …ompleted due to demand data loads whose address translations missed in the TLB and were mapped to …
15 …ompleted due to demand data loads whose address translations missed in the TLB and were mapped to …
26 …ed page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels. The page wa…
33 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
60 …blicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).…
71 …mpleted due to demand data stores whose address translations missed in the TLB and were mapped to …
82 …mpleted due to demand data stores whose address translations missed in the TLB and were mapped to …
93 …ed page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels. The page wa…
100 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s…
127 …ublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
[all …]
|
| /kernel/linux/linux-5.10/arch/sh/mm/ |
| D | Makefile | 30 debugfs-$(CONFIG_CPU_SH4) += tlb-debugfs.o
31 tlb-$(CONFIG_CPU_SH3) := tlb-sh3.o
32 tlb-$(CONFIG_CPU_SH4) := tlb-sh4.o tlb-urb.o
33 tlb-$(CONFIG_CPU_HAS_PTEAEX) := tlb-pteaex.o tlb-urb.o
34 obj-y += $(tlb-y)
|
| D | tlb-urb.c | 2 * arch/sh/mm/tlb-urb.c
4 * TLB entry wiring helpers for URB-equipped parts.
14 #include <asm/tlb.h>
18 * Load the entry for 'addr' into the TLB and wire the entry.
32 * Make sure we're not trying to wire the last TLB entry slot. in tlb_wire_entry()
39 * Insert this entry into the highest non-wired TLB slot (via in tlb_wire_entry()
46 /* Load the entry into the TLB */ in tlb_wire_entry()
62 * Unwire the last wired TLB entry.
65 * TLB entries in an arbitrary order. If you wire TLB entry N, followed
81 * Make sure we're not trying to unwire a TLB entry when none in tlb_unwire_entry()
|
| /kernel/linux/linux-5.10/arch/ia64/include/asm/ |
| D | tlb.h | 5 * Based on <asm-generic/tlb.h>.
11 * Removing a translation from a page table (including TLB-shootdown) is a four-step
22 * The Linux kernel defines several platform-specific hooks for TLB-shootdown. When
26 * tlb <- tlb_gather_mmu(mm, start, end); // start unmap for address space MM
29 * tlb_start_vma(tlb, vma);
31 * tlb_remove_tlb_entry(tlb, pte, address);
33 * tlb_remove_page(tlb, page);
36 * tlb_end_vma(tlb, vma);
39 * tlb_finish_mmu(tlb, start, end); // finish unmap for address space MM
48 #include <asm-generic/tlb.h>
|
| /kernel/linux/linux-5.10/sound/pci/trident/ |
| D | trident_memory.c | 7 * Trident 4DWave-NX memory page allocation (TLB area)
23 do { (trident)->tlb.entries[page] = cpu_to_le32((addr) & ~(SNDRV_TRIDENT_PAGE_SIZE-1)); \
24 (trident)->tlb.shadow_entries[page] = (ptr); } while (0)
26 (void*)((trident)->tlb.shadow_entries[page])
28 (dma_addr_t)le32_to_cpu((trident->tlb.entries[page]) & ~(SNDRV_TRIDENT_PAGE_SIZE - 1))
34 /* fill TLB entrie(s) corresponding to page with ptr */
36 /* fill TLB entrie(s) corresponding to page with silence pointer */
37 …page) __set_tlb_bus(trident, page, (unsigned long)trident->tlb.silent_page.area, trident->tlb.sile…
56 /* fill TLB entries -- we need to fill two entries */
67 …__set_tlb_bus(trident, page, (unsigned long)trident->tlb.silent_page.area, trident->tlb.silent_pag… in set_silent_tlb()
[all …]
|
| /kernel/linux/linux-5.10/arch/arc/mm/ |
| D | tlb.c | 3 * TLB Management (flush/create/diagnostics) for ARC700
33 * -In TLB Flush operations (Metal Fix MMU) there is a explicit command to
34 * flush Micro-TLBS. If TLB Index Reg is invalid prior to TLBIVUTLB cmd,
39 * -Reduced the duration of IRQ lockouts in TLB Flush routines
40 * -Multiple copies of TLB erase code separated into a "single" function
41 * -In TLB Flush routines, interrupt disabling moved UP to retrieve ASID
46 * flush is more than the size of TLB itself.
62 * ARC700 MMU-v1 had a Joint-TLB for Code and Data and is 2 way set-assoc.
67 * Although J-TLB is 2 way set assoc, ARC700 caches J-TLB into uTLBS which has
68 * much higher associativity. u-D-TLB is 8 ways, u-I-TLB is 4 ways.
[all …]
|
| /kernel/linux/linux-5.10/arch/arm/mm/ |
| D | tlb-v7.S | 3 * linux/arch/arm/mm/tlb-v7.S
8 * ARM architecture version 6 TLB handling functions.
9 * These assume a split I/D TLB.
22 * Invalidate a range of TLB entries in the specified address space.
47 ALT_SMP(mcr p15, 0, r0, c8, c3, 3) @ TLB invalidate U MVA all ASID (shareable)
49 ALT_SMP(mcr p15, 0, r0, c8, c3, 1) @ TLB invalidate U MVA (shareable)
51 ALT_UP(mcr p15, 0, r0, c8, c7, 1) @ TLB invalidate U MVA
63 * Invalidate a range of kernel TLB entries
76 ALT_SMP(mcr p15, 0, r0, c8, c3, 3) @ TLB invalidate U MVA all ASID (shareable)
78 ALT_SMP(mcr p15, 0, r0, c8, c3, 1) @ TLB invalidate U MVA (shareable)
[all …]
|
| D | tlb-v6.S | 3 * linux/arch/arm/mm/tlb-v6.S
7 * ARM architecture version 6 TLB handling functions.
8 * These assume a split I/D TLB.
23 * Invalidate a range of TLB entries in the specified address space.
46 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA (was 1)
48 mcrne p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA (was 1)
50 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA (was 1)
61 * Invalidate a range of kernel TLB entries
75 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA
76 mcr p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA
[all …]
|
| /kernel/linux/linux-5.10/arch/powerpc/include/asm/nohash/32/ |
| D | mmu-8xx.h | 11 * operations when written/read. A TLB entry is created when the Mx_RPN
15 #define SPRN_MI_CTR 784 /* Instruction TLB control register */
19 #define MI_RSV4I 0x08000000 /* Reserve 4 TLB entries */
21 #define MI_IDXMASK 0x00001f00 /* TLB index to be loaded */
50 * about the last instruction TLB miss. When MI_RPN is written, bits in
51 * this register are used to create the TLB entry.
60 * For the instruction TLB, it contains bits that get loaded into the
61 * TLB entry when the MI_RPN is written.
74 * causes a TLB entry to be created for the instruction TLB, using
87 #define SPRN_MD_CTR 792 /* Data TLB control register */
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/skylakex/ |
| D | virtual-memory.json | 17 … a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the wal…
27 …mpleted due to demand data stores whose address translations missed in the TLB and were mapped to …
42 "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
47 … by a code fetch. This implies it missed in the ITLB and further levels of TLB. The page walk can …
52 … "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
57 …hes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Se…
78 …blicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).…
129 … by a code fetch. This implies it missed in the ITLB and further levels of TLB, but the walk need …
139 … "PublicDescription": "Stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
144 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s…
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/cascadelakex/ |
| D | virtual-memory.json | 8 …mpleted due to demand data stores whose address translations missed in the TLB and were mapped to …
23 …"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page size…
28 … by a code fetch. This implies it missed in the ITLB and further levels of TLB. The page walk can …
38 … a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the wal…
69 …mpleted due to demand data stores whose address translations missed in the TLB and were mapped to …
79 … a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the wal…
84 … "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
89 …hes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Se…
109 …ompleted due to demand data loads whose address translations missed in the TLB and were mapped to …
119 …ompleted due to demand data loads whose address translations missed in the TLB and were mapped to …
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/skylake/ |
| D | virtual-memory.json | 3 … a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the wal…
13 …ompleted due to demand data loads whose address translations missed in the TLB and were mapped to …
23 …ompleted due to demand data loads whose address translations missed in the TLB and were mapped to …
33 …ompleted due to demand data loads whose address translations missed in the TLB and were mapped to …
43 …ed page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels. The page wa…
49 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
74 …blicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).…
84 … a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the wal…
94 …mpleted due to demand data stores whose address translations missed in the TLB and were mapped to …
104 …mpleted due to demand data stores whose address translations missed in the TLB and were mapped to …
[all …]
|
| /kernel/linux/linux-5.10/include/linux/ |
| D | io-pgtable.h | 22 * struct iommu_flush_ops - IOMMU callbacks for TLB and page table management.
24 * @tlb_flush_all: Synchronously invalidate the entire TLB context.
25 * @tlb_flush_walk: Synchronously invalidate all intermediate TLB state
28 * @tlb_flush_leaf: Synchronously invalidate all leaf TLB state for a virtual
30 * @tlb_add_page: Optional callback to queue up leaf TLB invalidation for a
31 * single page. IOMMUs that cannot batch TLB invalidation
60 * @tlb: TLB management callbacks for this set of tables.
77 * TLB maintenance when mapping as well as when unmapping.
101 const struct iommu_flush_ops *tlb; member
173 * the callback routines in cfg->tlb.
[all …]
|