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/kernel/linux/linux-5.10/drivers/media/platform/qcom/camss/
Dcamss-vfe.c1 // SPDX-License-Identifier: GPL-2.0
3 * camss-vfe.c
5 * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module
7 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
8 * Copyright (C) 2015-2018 Linaro Ltd.
10 #include <linux/clk.h>
20 #include <media/media-entity.h>
21 #include <media/v4l2-device.h>
22 #include <media/v4l2-subdev.h>
24 #include "camss-vfe.h"
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/kernel/linux/linux-5.10/drivers/i2c/busses/
Di2c-cbus-gpio.c4 * Copyright (C) 2004-2010 Nokia Corporation
40 struct gpio_desc *clk; member
42 struct gpio_desc *sel; member
46 * cbus_send_bit - sends one bit over the bus
52 gpiod_set_value(host->dat, bit ? 1 : 0); in cbus_send_bit()
53 gpiod_set_value(host->clk, 1); in cbus_send_bit()
54 gpiod_set_value(host->clk, 0); in cbus_send_bit()
58 * cbus_send_data - sends @len amount of data over the bus
67 for (i = len; i > 0; i--) in cbus_send_data()
68 cbus_send_bit(host, data & (1 << (i - 1))); in cbus_send_data()
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/kernel/linux/linux-5.10/drivers/media/i2c/
Dtw9910.c1 // SPDX-License-Identifier: GPL-2.0
13 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
18 #include <linux/clk.h>
26 #include <linux/v4l2-mediabus.h>
30 #include <media/v4l2-subdev.h>
41 #define OPFORM 0x03 /* Output Format Control Register */
43 #define OUTCTR1 0x05 /* Output Control I */
64 #define OUTCTR2 0x1B /* Output Control 2 */
136 #define IFSEL_S 0x10 /* 01 : S-video decoding */
146 /* 1 : ITU-R-656 compatible data sequence format */
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Dmt9v032.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/clk.h>
23 #include <linux/v4l2-mediabus.h>
27 #include <media/v4l2-ctrls.h>
28 #include <media/v4l2-device.h>
29 #include <media/v4l2-fwnode.h>
30 #include <media/v4l2-subdev.h>
203 struct clk *clk; member
228 struct regmap *map = mt9v032->regmap; in mt9v032_update_aec_agc()
229 u16 value = mt9v032->aec_agc; in mt9v032_update_aec_agc()
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Dmt9t112.c1 // SPDX-License-Identifier: GPL-2.0
14 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
20 * v4l-utils compliance tools will report errors.
23 #include <linux/clk.h>
30 #include <linux/v4l2-mediabus.h>
34 #include <media/v4l2-common.h>
35 #include <media/v4l2-image-sizes.h>
36 #include <media/v4l2-subdev.h>
95 struct clk *clk; member
158 msg[0].addr = client->addr; in __mt9t112_reg_read()
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Drj54n1cb0c.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/clk.h>
16 #include <linux/v4l2-mediabus.h>
20 #include <media/v4l2-device.h>
21 #include <media/v4l2-ctrls.h>
22 #include <media/v4l2-subdev.h>
154 struct clk *clk; member
162 unsigned short width; /* Output window */
164 unsigned short resize; /* Sensor * 1024 / resize = Output */
416 /* Clock dividers - these are default register values, divider = register + 1 */
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Dov6650.c1 // SPDX-License-Identifier: GPL-2.0-only
15 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
28 #include <linux/v4l2-mediabus.h>
31 #include <media/v4l2-clk.h>
32 #include <media/v4l2-ctrls.h>
33 #include <media/v4l2-device.h>
36 #define REG_GAIN 0x00 /* range 00 - 3F */
51 /* [5:0]: Internal Clock Pre-Scaler */
165 #define W_QCIF (DEF_HSTOP - DEF_HSTRT)
167 #define H_QCIF (DEF_VSTOP - DEF_VSTRT)
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Dmt9p031.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 2011, Javier Martin <javier.martin@vista-silicon.com>
12 #include <linux/clk.h>
27 #include <media/v4l2-async.h>
28 #include <media/v4l2-ctrls.h>
29 #include <media/v4l2-device.h>
30 #include <media/v4l2-subdev.h>
32 #include "aptina-pll.h"
130 struct clk *clk; member
166 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev); in mt9p031_set_output_control()
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Dov772x.c1 // SPDX-License-Identifier: GPL-2.0
12 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
17 #include <linux/clk.h>
26 #include <linux/v4l2-mediabus.h>
31 #include <media/v4l2-ctrls.h>
32 #include <media/v4l2-device.h>
33 #include <media/v4l2-event.h>
34 #include <media/v4l2-image-sizes.h>
35 #include <media/v4l2-subdev.h>
40 #define GAIN 0x00 /* AGC - Gain control gain setting */
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Dmt9t001.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2010-2011, Laurent Pinchart <laurent.pinchart@ideasonboard.com>
12 #include <linux/clk.h>
19 #include <linux/v4l2-mediabus.h>
22 #include <media/v4l2-ctrls.h>
23 #include <media/v4l2-device.h>
24 #include <media/v4l2-subdev.h>
119 struct clk *clk; member
153 struct i2c_client *client = v4l2_get_subdevdata(&mt9t001->subdev); in mt9t001_set_output_control()
154 u16 value = (mt9t001->output_control & ~clear) | set; in mt9t001_set_output_control()
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/kernel/linux/linux-5.10/sound/soc/sh/rcar/
Dadg.c1 // SPDX-License-Identifier: GPL-2.0
3 // Helper routines for R-Car sound ADG.
7 #include <linux/clk-provider.h>
29 struct clk *clk[CLKMAX]; member
30 struct clk *clkout[CLKOUTMAX];
49 ((pos) = adg->clk[i]); \
54 ((pos) = adg->clkout[i]); \
56 #define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg)
72 for (i = 3; i >= 0; i--) { in rsnd_adg_calculate_rbgx()
75 return (u32)((i << 8) | ((div / ratio) - 1)); in rsnd_adg_calculate_rbgx()
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/
Dti,dp83869.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - $ref: "ethernet-phy.yaml#"
14 - Dan Murphy <dmurphy@ti.com>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
23 the DP83869HM can run 1000BASE-X-to-1000BASE-T and 100BASE-FX-to-100BASE-TX
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Dti,dp83867.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - $ref: "ethernet-controller.yaml#"
14 - Dan Murphy <dmurphy@ti.com>
18 transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX
19 and 1000BASE-T Ethernet protocols.
34 ti,min-output-impedance:
37 MAC Interface Impedance control to set the programmable output impedance
40 ti,max-output-impedance:
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/kernel/linux/linux-5.10/sound/soc/meson/
Daxg-frddr.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
10 #include <linux/clk.h>
15 #include <sound/soc-dai.h>
17 #include "axg-fifo.h"
39 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_frddr_dai_prepare()
41 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_frddr_dai_prepare()
43 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_frddr_dai_prepare()
57 ret = clk_prepare_enable(fifo->pclk); in axg_frddr_dai_startup()
62 regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_FRDDR_PP_MODE, 0); in axg_frddr_dai_startup()
65 val = (fifo->depth / AXG_FIFO_BURST) - 1; in axg_frddr_dai_startup()
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Dt9015.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk.h>
51 struct clk *pclk;
57 struct snd_soc_component *component = dai->component; in t9015_dai_set_fmt()
70 return -EINVAL; in t9015_dai_set_fmt()
77 return -EINVAL; in t9015_dai_set_fmt()
87 .name = "t9015-hifi",
101 static const DECLARE_TLV_DB_MINMAX_MUTE(dac_vol_tlv, -9525, 0);
138 SND_SOC_DAPM_MUX("Right DAC Sel", SND_SOC_NOPM, 0, 0,
140 SND_SOC_DAPM_MUX("Left DAC Sel", SND_SOC_NOPM, 0, 0,
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Daxg-spdifout.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include <linux/clk.h>
11 #include <sound/soc-dai.h>
19 * applied when the related sel bits are cleared
61 struct clk *mclk;
62 struct clk *pclk;
97 axg_spdifout_enable(priv->map); in axg_spdifout_trigger()
103 axg_spdifout_disable(priv->map); in axg_spdifout_trigger()
107 return -EINVAL; in axg_spdifout_trigger()
116 regmap_update_bits(priv->map, SPDIFOUT_CTRL0, SPDIFOUT_CTRL0_VSET, in axg_spdifout_mute()
[all …]
Daxg-toddr.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <linux/clk.h>
14 #include <sound/soc-dai.h>
16 #include "axg-fifo.h"
45 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_toddr_dai_prepare()
47 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_toddr_dai_prepare()
49 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_toddr_dai_prepare()
67 type = 2; /* 4 samples of 16 bits - right justified */ in axg_toddr_dai_hw_params()
70 type = 4; /* 2 samples of 32 bits - right justified */ in axg_toddr_dai_hw_params()
73 return -EINVAL; in axg_toddr_dai_hw_params()
[all …]
/kernel/linux/linux-5.10/drivers/mmc/host/
Dsdhci_am654.c1 // SPDX-License-Identifier: GPL-2.0
3 * sdhci_am654.c - SDHCI driver for TI's AM654 SOCs
5 * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com
8 #include <linux/clk.h>
18 #include "sdhci-pltfm.h"
105 [MMC_TIMING_LEGACY] = {"ti,otap-del-sel-legacy",
106 "ti,itap-del-sel-legacy",
108 [MMC_TIMING_MMC_HS] = {"ti,otap-del-sel-mmc-hs",
109 "ti,itap-del-sel-mmc-hs",
111 [MMC_TIMING_SD_HS] = {"ti,otap-del-sel-sd-hs",
[all …]
/kernel/linux/linux-5.10/drivers/clk/imx/
Dclk-imx6q.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2011-2013 Freescale Semiconductor, Inc.
10 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
19 #include <dt-bindings/clock/imx6qdl-clock.h>
21 #include "clk.h"
149 return -ENOENT; in ldb_di_sel_by_clock_id()
160 return -ENOENT; in ldb_di_sel_by_clock_id()
170 int parent, child, sel; in of_assigned_ldb_sels() local
172 num_parents = of_count_phandle_with_args(node, "assigned-clock-parents", in of_assigned_ldb_sels()
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/kernel/linux/linux-5.10/include/linux/mfd/
Dstm32-timers.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 #include <linux/clk.h>
12 #include <linux/dma-mapping.h>
26 #define TIM_ARR 0x2c /* Auto-Reload Register */
31 #define TIM_BDTR 0x44 /* Break and Dead-Time Reg */
37 #define TIM_CR1_ARPE BIT(7) /* Auto-reload Preload Ena */
54 #define TIM_CCMR_CC1S (BIT(0) | BIT(1)) /* Capture/compare 1 sel */
56 #define TIM_CCMR_CC2S (BIT(8) | BIT(9)) /* Capture/compare 2 sel */
75 #define TIM_BDTR_AOE BIT(14) /* Automatic Output Enable */
76 #define TIM_BDTR_MOE BIT(15) /* Main Output Enable */
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/mediatek/
Dmt2712e.dtsi5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/mt2712-clk.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/memory/mt2712-larb-port.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/power/mt2712-power.h>
14 #include "mt2712-pinfunc.h"
18 interrupt-parent = <&sysirq>;
19 #address-cells = <2>;
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Dmt8516.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/mt8516-clk.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/phy/phy.h>
13 #include "mt8516-pinfunc.h"
17 interrupt-parent = <&sysirq>;
18 #address-cells = <2>;
19 #size-cells = <2>;
21 cluster0_opp: opp-table-0 {
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Dmt8183.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/mt8183-clk.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/reset-controller/mt8183-resets.h>
12 #include <dt-bindings/phy/phy.h>
13 #include "mt8183-pinfunc.h"
17 interrupt-parent = <&sysirq>;
18 #address-cells = <2>;
19 #size-cells = <2>;
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/kernel/linux/linux-5.10/drivers/regulator/
Dstm32-vrefbuf.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk.h>
32 struct clk *clk; member
47 ret = pm_runtime_get_sync(priv->dev); in stm32_vrefbuf_enable()
49 pm_runtime_put_noidle(priv->dev); in stm32_vrefbuf_enable()
53 val = readl_relaxed(priv->base + STM32_VREFBUF_CSR); in stm32_vrefbuf_enable()
55 writel_relaxed(val, priv->base + STM32_VREFBUF_CSR); in stm32_vrefbuf_enable()
59 * VRR to be set. That means output has reached expected value. in stm32_vrefbuf_enable()
63 ret = readl_poll_timeout(priv->base + STM32_VREFBUF_CSR, val, in stm32_vrefbuf_enable()
66 dev_err(&rdev->dev, "stm32 vrefbuf timed out!\n"); in stm32_vrefbuf_enable()
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/kernel/linux/linux-5.10/drivers/clk/
Dclk-si5341.c1 // SPDX-License-Identifier: GPL-2.0
14 #include <linux/clk.h>
15 #include <linux/clk-provider.h>
58 /* The output stages can be connected to any synth (full mux) */
72 struct clk_si5341_output clk[SI5341_MAX_NUM_OUTPUTS]; member
73 struct clk *input_clk[SI5341_NUM_INPUTS];
121 /* Input dividers (48-bit) */
130 /* Output configuration */
131 #define SI5341_OUT_CONFIG(output) \ argument
132 ((output)->data->reg_output_offset[(output)->index])
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