1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for Silicon Labs Si5340, Si5341, Si5342, Si5344 and Si5345
4 * Copyright (C) 2019 Topic Embedded Products
5 * Author: Mike Looijmans <mike.looijmans@topic.nl>
6 *
7 * The Si5341 has 10 outputs and 5 synthesizers.
8 * The Si5340 is a smaller version of the Si5341 with only 4 outputs.
9 * The Si5345 is similar to the Si5341, with the addition of fractional input
10 * dividers and automatic input selection.
11 * The Si5342 and Si5344 are smaller versions of the Si5345.
12 */
13
14 #include <linux/clk.h>
15 #include <linux/clk-provider.h>
16 #include <linux/delay.h>
17 #include <linux/gcd.h>
18 #include <linux/math64.h>
19 #include <linux/i2c.h>
20 #include <linux/module.h>
21 #include <linux/regmap.h>
22 #include <linux/slab.h>
23 #include <asm/unaligned.h>
24
25 #define SI5341_NUM_INPUTS 4
26
27 #define SI5340_MAX_NUM_OUTPUTS 4
28 #define SI5341_MAX_NUM_OUTPUTS 10
29 #define SI5342_MAX_NUM_OUTPUTS 2
30 #define SI5344_MAX_NUM_OUTPUTS 4
31 #define SI5345_MAX_NUM_OUTPUTS 10
32
33 #define SI5340_NUM_SYNTH 4
34 #define SI5341_NUM_SYNTH 5
35 #define SI5342_NUM_SYNTH 2
36 #define SI5344_NUM_SYNTH 4
37 #define SI5345_NUM_SYNTH 5
38
39 /* Range of the synthesizer fractional divider */
40 #define SI5341_SYNTH_N_MIN 10
41 #define SI5341_SYNTH_N_MAX 4095
42
43 /* The chip can get its input clock from 3 input pins or an XTAL */
44
45 /* There is one PLL running at 13500–14256 MHz */
46 #define SI5341_PLL_VCO_MIN 13500000000ull
47 #define SI5341_PLL_VCO_MAX 14256000000ull
48
49 /* The 5 frequency synthesizers obtain their input from the PLL */
50 struct clk_si5341_synth {
51 struct clk_hw hw;
52 struct clk_si5341 *data;
53 u8 index;
54 };
55 #define to_clk_si5341_synth(_hw) \
56 container_of(_hw, struct clk_si5341_synth, hw)
57
58 /* The output stages can be connected to any synth (full mux) */
59 struct clk_si5341_output {
60 struct clk_hw hw;
61 struct clk_si5341 *data;
62 u8 index;
63 };
64 #define to_clk_si5341_output(_hw) \
65 container_of(_hw, struct clk_si5341_output, hw)
66
67 struct clk_si5341 {
68 struct clk_hw hw;
69 struct regmap *regmap;
70 struct i2c_client *i2c_client;
71 struct clk_si5341_synth synth[SI5341_NUM_SYNTH];
72 struct clk_si5341_output clk[SI5341_MAX_NUM_OUTPUTS];
73 struct clk *input_clk[SI5341_NUM_INPUTS];
74 const char *input_clk_name[SI5341_NUM_INPUTS];
75 const u16 *reg_output_offset;
76 const u16 *reg_rdiv_offset;
77 u64 freq_vco; /* 13500–14256 MHz */
78 u8 num_outputs;
79 u8 num_synth;
80 u16 chip_id;
81 };
82 #define to_clk_si5341(_hw) container_of(_hw, struct clk_si5341, hw)
83
84 struct clk_si5341_output_config {
85 u8 out_format_drv_bits;
86 u8 out_cm_ampl_bits;
87 bool synth_master;
88 bool always_on;
89 };
90
91 #define SI5341_PAGE 0x0001
92 #define SI5341_PN_BASE 0x0002
93 #define SI5341_DEVICE_REV 0x0005
94 #define SI5341_STATUS 0x000C
95 #define SI5341_LOS 0x000D
96 #define SI5341_STATUS_STICKY 0x0011
97 #define SI5341_LOS_STICKY 0x0012
98 #define SI5341_SOFT_RST 0x001C
99 #define SI5341_IN_SEL 0x0021
100 #define SI5341_DEVICE_READY 0x00FE
101 #define SI5341_XAXB_CFG 0x090E
102 #define SI5341_IN_EN 0x0949
103 #define SI5341_INX_TO_PFD_EN 0x094A
104
105 /* Status bits */
106 #define SI5341_STATUS_SYSINCAL BIT(0)
107 #define SI5341_STATUS_LOSXAXB BIT(1)
108 #define SI5341_STATUS_LOSREF BIT(2)
109 #define SI5341_STATUS_LOL BIT(3)
110
111 /* Input selection */
112 #define SI5341_IN_SEL_MASK 0x06
113 #define SI5341_IN_SEL_SHIFT 1
114 #define SI5341_IN_SEL_REGCTRL 0x01
115 #define SI5341_INX_TO_PFD_SHIFT 4
116
117 /* XTAL config bits */
118 #define SI5341_XAXB_CFG_EXTCLK_EN BIT(0)
119 #define SI5341_XAXB_CFG_PDNB BIT(1)
120
121 /* Input dividers (48-bit) */
122 #define SI5341_IN_PDIV(x) (0x0208 + ((x) * 10))
123 #define SI5341_IN_PSET(x) (0x020E + ((x) * 10))
124 #define SI5341_PX_UPD 0x0230
125
126 /* PLL configuration */
127 #define SI5341_PLL_M_NUM 0x0235
128 #define SI5341_PLL_M_DEN 0x023B
129
130 /* Output configuration */
131 #define SI5341_OUT_CONFIG(output) \
132 ((output)->data->reg_output_offset[(output)->index])
133 #define SI5341_OUT_FORMAT(output) (SI5341_OUT_CONFIG(output) + 1)
134 #define SI5341_OUT_CM(output) (SI5341_OUT_CONFIG(output) + 2)
135 #define SI5341_OUT_MUX_SEL(output) (SI5341_OUT_CONFIG(output) + 3)
136 #define SI5341_OUT_R_REG(output) \
137 ((output)->data->reg_rdiv_offset[(output)->index])
138
139 /* Synthesize N divider */
140 #define SI5341_SYNTH_N_NUM(x) (0x0302 + ((x) * 11))
141 #define SI5341_SYNTH_N_DEN(x) (0x0308 + ((x) * 11))
142 #define SI5341_SYNTH_N_UPD(x) (0x030C + ((x) * 11))
143
144 /* Synthesizer output enable, phase bypass, power mode */
145 #define SI5341_SYNTH_N_CLK_TO_OUTX_EN 0x0A03
146 #define SI5341_SYNTH_N_PIBYP 0x0A04
147 #define SI5341_SYNTH_N_PDNB 0x0A05
148 #define SI5341_SYNTH_N_CLK_DIS 0x0B4A
149
150 #define SI5341_REGISTER_MAX 0xBFF
151
152 /* SI5341_OUT_CONFIG bits */
153 #define SI5341_OUT_CFG_PDN BIT(0)
154 #define SI5341_OUT_CFG_OE BIT(1)
155 #define SI5341_OUT_CFG_RDIV_FORCE2 BIT(2)
156
157 /* Static configuration (to be moved to firmware) */
158 struct si5341_reg_default {
159 u16 address;
160 u8 value;
161 };
162
163 static const char * const si5341_input_clock_names[] = {
164 "in0", "in1", "in2", "xtal"
165 };
166
167 /* Output configuration registers 0..9 are not quite logically organized */
168 /* Also for si5345 */
169 static const u16 si5341_reg_output_offset[] = {
170 0x0108,
171 0x010D,
172 0x0112,
173 0x0117,
174 0x011C,
175 0x0121,
176 0x0126,
177 0x012B,
178 0x0130,
179 0x013A,
180 };
181
182 /* for si5340, si5342 and si5344 */
183 static const u16 si5340_reg_output_offset[] = {
184 0x0112,
185 0x0117,
186 0x0126,
187 0x012B,
188 };
189
190 /* The location of the R divider registers */
191 static const u16 si5341_reg_rdiv_offset[] = {
192 0x024A,
193 0x024D,
194 0x0250,
195 0x0253,
196 0x0256,
197 0x0259,
198 0x025C,
199 0x025F,
200 0x0262,
201 0x0268,
202 };
203 static const u16 si5340_reg_rdiv_offset[] = {
204 0x0250,
205 0x0253,
206 0x025C,
207 0x025F,
208 };
209
210 /*
211 * Programming sequence from ClockBuilder, settings to initialize the system
212 * using only the XTAL input, without pre-divider.
213 * This also contains settings that aren't mentioned anywhere in the datasheet.
214 * The "known" settings like synth and output configuration are done later.
215 */
216 static const struct si5341_reg_default si5341_reg_defaults[] = {
217 { 0x0017, 0x3A }, /* INT mask (disable interrupts) */
218 { 0x0018, 0xFF }, /* INT mask */
219 { 0x0021, 0x0F }, /* Select XTAL as input */
220 { 0x0022, 0x00 }, /* Not in datasheet */
221 { 0x002B, 0x02 }, /* SPI config */
222 { 0x002C, 0x20 }, /* LOS enable for XTAL */
223 { 0x002D, 0x00 }, /* LOS timing */
224 { 0x002E, 0x00 },
225 { 0x002F, 0x00 },
226 { 0x0030, 0x00 },
227 { 0x0031, 0x00 },
228 { 0x0032, 0x00 },
229 { 0x0033, 0x00 },
230 { 0x0034, 0x00 },
231 { 0x0035, 0x00 },
232 { 0x0036, 0x00 },
233 { 0x0037, 0x00 },
234 { 0x0038, 0x00 }, /* LOS setting (thresholds) */
235 { 0x0039, 0x00 },
236 { 0x003A, 0x00 },
237 { 0x003B, 0x00 },
238 { 0x003C, 0x00 },
239 { 0x003D, 0x00 }, /* LOS setting (thresholds) end */
240 { 0x0041, 0x00 }, /* LOS0_DIV_SEL */
241 { 0x0042, 0x00 }, /* LOS1_DIV_SEL */
242 { 0x0043, 0x00 }, /* LOS2_DIV_SEL */
243 { 0x0044, 0x00 }, /* LOS3_DIV_SEL */
244 { 0x009E, 0x00 }, /* Not in datasheet */
245 { 0x0102, 0x01 }, /* Enable outputs */
246 { 0x013F, 0x00 }, /* Not in datasheet */
247 { 0x0140, 0x00 }, /* Not in datasheet */
248 { 0x0141, 0x40 }, /* OUT LOS */
249 { 0x0202, 0x00 }, /* XAXB_FREQ_OFFSET (=0)*/
250 { 0x0203, 0x00 },
251 { 0x0204, 0x00 },
252 { 0x0205, 0x00 },
253 { 0x0206, 0x00 }, /* PXAXB (2^x) */
254 { 0x0208, 0x00 }, /* Px divider setting (usually 0) */
255 { 0x0209, 0x00 },
256 { 0x020A, 0x00 },
257 { 0x020B, 0x00 },
258 { 0x020C, 0x00 },
259 { 0x020D, 0x00 },
260 { 0x020E, 0x00 },
261 { 0x020F, 0x00 },
262 { 0x0210, 0x00 },
263 { 0x0211, 0x00 },
264 { 0x0212, 0x00 },
265 { 0x0213, 0x00 },
266 { 0x0214, 0x00 },
267 { 0x0215, 0x00 },
268 { 0x0216, 0x00 },
269 { 0x0217, 0x00 },
270 { 0x0218, 0x00 },
271 { 0x0219, 0x00 },
272 { 0x021A, 0x00 },
273 { 0x021B, 0x00 },
274 { 0x021C, 0x00 },
275 { 0x021D, 0x00 },
276 { 0x021E, 0x00 },
277 { 0x021F, 0x00 },
278 { 0x0220, 0x00 },
279 { 0x0221, 0x00 },
280 { 0x0222, 0x00 },
281 { 0x0223, 0x00 },
282 { 0x0224, 0x00 },
283 { 0x0225, 0x00 },
284 { 0x0226, 0x00 },
285 { 0x0227, 0x00 },
286 { 0x0228, 0x00 },
287 { 0x0229, 0x00 },
288 { 0x022A, 0x00 },
289 { 0x022B, 0x00 },
290 { 0x022C, 0x00 },
291 { 0x022D, 0x00 },
292 { 0x022E, 0x00 },
293 { 0x022F, 0x00 }, /* Px divider setting (usually 0) end */
294 { 0x026B, 0x00 }, /* DESIGN_ID (ASCII string) */
295 { 0x026C, 0x00 },
296 { 0x026D, 0x00 },
297 { 0x026E, 0x00 },
298 { 0x026F, 0x00 },
299 { 0x0270, 0x00 },
300 { 0x0271, 0x00 },
301 { 0x0272, 0x00 }, /* DESIGN_ID (ASCII string) end */
302 { 0x0339, 0x1F }, /* N_FSTEP_MSK */
303 { 0x033B, 0x00 }, /* Nx_FSTEPW (Frequency step) */
304 { 0x033C, 0x00 },
305 { 0x033D, 0x00 },
306 { 0x033E, 0x00 },
307 { 0x033F, 0x00 },
308 { 0x0340, 0x00 },
309 { 0x0341, 0x00 },
310 { 0x0342, 0x00 },
311 { 0x0343, 0x00 },
312 { 0x0344, 0x00 },
313 { 0x0345, 0x00 },
314 { 0x0346, 0x00 },
315 { 0x0347, 0x00 },
316 { 0x0348, 0x00 },
317 { 0x0349, 0x00 },
318 { 0x034A, 0x00 },
319 { 0x034B, 0x00 },
320 { 0x034C, 0x00 },
321 { 0x034D, 0x00 },
322 { 0x034E, 0x00 },
323 { 0x034F, 0x00 },
324 { 0x0350, 0x00 },
325 { 0x0351, 0x00 },
326 { 0x0352, 0x00 },
327 { 0x0353, 0x00 },
328 { 0x0354, 0x00 },
329 { 0x0355, 0x00 },
330 { 0x0356, 0x00 },
331 { 0x0357, 0x00 },
332 { 0x0358, 0x00 }, /* Nx_FSTEPW (Frequency step) end */
333 { 0x0359, 0x00 }, /* Nx_DELAY */
334 { 0x035A, 0x00 },
335 { 0x035B, 0x00 },
336 { 0x035C, 0x00 },
337 { 0x035D, 0x00 },
338 { 0x035E, 0x00 },
339 { 0x035F, 0x00 },
340 { 0x0360, 0x00 },
341 { 0x0361, 0x00 },
342 { 0x0362, 0x00 }, /* Nx_DELAY end */
343 { 0x0802, 0x00 }, /* Not in datasheet */
344 { 0x0803, 0x00 }, /* Not in datasheet */
345 { 0x0804, 0x00 }, /* Not in datasheet */
346 { 0x090E, 0x02 }, /* XAXB_EXTCLK_EN=0 XAXB_PDNB=1 (use XTAL) */
347 { 0x091C, 0x04 }, /* ZDM_EN=4 (Normal mode) */
348 { 0x0943, 0x00 }, /* IO_VDD_SEL=0 (0=1v8, use 1=3v3) */
349 { 0x0949, 0x00 }, /* IN_EN (disable input clocks) */
350 { 0x094A, 0x00 }, /* INx_TO_PFD_EN (disabled) */
351 { 0x0A02, 0x00 }, /* Not in datasheet */
352 { 0x0B44, 0x0F }, /* PDIV_ENB (datasheet does not mention what it is) */
353 { 0x0B57, 0x10 }, /* VCO_RESET_CALCODE (not described in datasheet) */
354 { 0x0B58, 0x05 }, /* VCO_RESET_CALCODE (not described in datasheet) */
355 };
356
357 /* Read and interpret a 44-bit followed by a 32-bit value in the regmap */
si5341_decode_44_32(struct regmap * regmap,unsigned int reg,u64 * val1,u32 * val2)358 static int si5341_decode_44_32(struct regmap *regmap, unsigned int reg,
359 u64 *val1, u32 *val2)
360 {
361 int err;
362 u8 r[10];
363
364 err = regmap_bulk_read(regmap, reg, r, 10);
365 if (err < 0)
366 return err;
367
368 *val1 = ((u64)((r[5] & 0x0f) << 8 | r[4]) << 32) |
369 (get_unaligned_le32(r));
370 *val2 = get_unaligned_le32(&r[6]);
371
372 return 0;
373 }
374
si5341_encode_44_32(struct regmap * regmap,unsigned int reg,u64 n_num,u32 n_den)375 static int si5341_encode_44_32(struct regmap *regmap, unsigned int reg,
376 u64 n_num, u32 n_den)
377 {
378 u8 r[10];
379
380 /* Shift left as far as possible without overflowing */
381 while (!(n_num & BIT_ULL(43)) && !(n_den & BIT(31))) {
382 n_num <<= 1;
383 n_den <<= 1;
384 }
385
386 /* 44 bits (6 bytes) numerator */
387 put_unaligned_le32(n_num, r);
388 r[4] = (n_num >> 32) & 0xff;
389 r[5] = (n_num >> 40) & 0x0f;
390 /* 32 bits denominator */
391 put_unaligned_le32(n_den, &r[6]);
392
393 /* Program the fraction */
394 return regmap_bulk_write(regmap, reg, r, sizeof(r));
395 }
396
397 /* VCO, we assume it runs at a constant frequency */
si5341_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)398 static unsigned long si5341_clk_recalc_rate(struct clk_hw *hw,
399 unsigned long parent_rate)
400 {
401 struct clk_si5341 *data = to_clk_si5341(hw);
402 int err;
403 u64 res;
404 u64 m_num;
405 u32 m_den;
406 unsigned int shift;
407
408 /* Assume that PDIV is not being used, just read the PLL setting */
409 err = si5341_decode_44_32(data->regmap, SI5341_PLL_M_NUM,
410 &m_num, &m_den);
411 if (err < 0)
412 return 0;
413
414 if (!m_num || !m_den)
415 return 0;
416
417 /*
418 * Though m_num is 64-bit, only the upper bits are actually used. While
419 * calculating m_num and m_den, they are shifted as far as possible to
420 * the left. To avoid 96-bit division here, we just shift them back so
421 * we can do with just 64 bits.
422 */
423 shift = 0;
424 res = m_num;
425 while (res & 0xffff00000000ULL) {
426 ++shift;
427 res >>= 1;
428 }
429 res *= parent_rate;
430 do_div(res, (m_den >> shift));
431
432 /* We cannot return the actual frequency in 32 bit, store it locally */
433 data->freq_vco = res;
434
435 /* Report kHz since the value is out of range */
436 do_div(res, 1000);
437
438 return (unsigned long)res;
439 }
440
si5341_clk_get_selected_input(struct clk_si5341 * data)441 static int si5341_clk_get_selected_input(struct clk_si5341 *data)
442 {
443 int err;
444 u32 val;
445
446 err = regmap_read(data->regmap, SI5341_IN_SEL, &val);
447 if (err < 0)
448 return err;
449
450 return (val & SI5341_IN_SEL_MASK) >> SI5341_IN_SEL_SHIFT;
451 }
452
si5341_clk_get_parent(struct clk_hw * hw)453 static u8 si5341_clk_get_parent(struct clk_hw *hw)
454 {
455 struct clk_si5341 *data = to_clk_si5341(hw);
456 int res = si5341_clk_get_selected_input(data);
457
458 if (res < 0)
459 return 0; /* Apparently we cannot report errors */
460
461 return res;
462 }
463
si5341_clk_reparent(struct clk_si5341 * data,u8 index)464 static int si5341_clk_reparent(struct clk_si5341 *data, u8 index)
465 {
466 int err;
467 u8 val;
468
469 val = (index << SI5341_IN_SEL_SHIFT) & SI5341_IN_SEL_MASK;
470 /* Enable register-based input selection */
471 val |= SI5341_IN_SEL_REGCTRL;
472
473 err = regmap_update_bits(data->regmap,
474 SI5341_IN_SEL, SI5341_IN_SEL_REGCTRL | SI5341_IN_SEL_MASK, val);
475 if (err < 0)
476 return err;
477
478 if (index < 3) {
479 /* Enable input buffer for selected input */
480 err = regmap_update_bits(data->regmap,
481 SI5341_IN_EN, 0x07, BIT(index));
482 if (err < 0)
483 return err;
484
485 /* Enables the input to phase detector */
486 err = regmap_update_bits(data->regmap, SI5341_INX_TO_PFD_EN,
487 0x7 << SI5341_INX_TO_PFD_SHIFT,
488 BIT(index + SI5341_INX_TO_PFD_SHIFT));
489 if (err < 0)
490 return err;
491
492 /* Power down XTAL oscillator and buffer */
493 err = regmap_update_bits(data->regmap, SI5341_XAXB_CFG,
494 SI5341_XAXB_CFG_PDNB, 0);
495 if (err < 0)
496 return err;
497
498 /*
499 * Set the P divider to "1". There's no explanation in the
500 * datasheet of these registers, but the clockbuilder software
501 * programs a "1" when the input is being used.
502 */
503 err = regmap_write(data->regmap, SI5341_IN_PDIV(index), 1);
504 if (err < 0)
505 return err;
506
507 err = regmap_write(data->regmap, SI5341_IN_PSET(index), 1);
508 if (err < 0)
509 return err;
510
511 /* Set update PDIV bit */
512 err = regmap_write(data->regmap, SI5341_PX_UPD, BIT(index));
513 if (err < 0)
514 return err;
515 } else {
516 /* Disable all input buffers */
517 err = regmap_update_bits(data->regmap, SI5341_IN_EN, 0x07, 0);
518 if (err < 0)
519 return err;
520
521 /* Disable input to phase detector */
522 err = regmap_update_bits(data->regmap, SI5341_INX_TO_PFD_EN,
523 0x7 << SI5341_INX_TO_PFD_SHIFT, 0);
524 if (err < 0)
525 return err;
526
527 /* Power up XTAL oscillator and buffer */
528 err = regmap_update_bits(data->regmap, SI5341_XAXB_CFG,
529 SI5341_XAXB_CFG_PDNB, SI5341_XAXB_CFG_PDNB);
530 if (err < 0)
531 return err;
532 }
533
534 return 0;
535 }
536
si5341_clk_set_parent(struct clk_hw * hw,u8 index)537 static int si5341_clk_set_parent(struct clk_hw *hw, u8 index)
538 {
539 struct clk_si5341 *data = to_clk_si5341(hw);
540
541 return si5341_clk_reparent(data, index);
542 }
543
544 static const struct clk_ops si5341_clk_ops = {
545 .set_parent = si5341_clk_set_parent,
546 .get_parent = si5341_clk_get_parent,
547 .recalc_rate = si5341_clk_recalc_rate,
548 };
549
550 /* Synthesizers, there are 5 synthesizers that connect to any of the outputs */
551
552 /* The synthesizer is on if all power and enable bits are set */
si5341_synth_clk_is_on(struct clk_hw * hw)553 static int si5341_synth_clk_is_on(struct clk_hw *hw)
554 {
555 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
556 int err;
557 u32 val;
558 u8 index = synth->index;
559
560 err = regmap_read(synth->data->regmap,
561 SI5341_SYNTH_N_CLK_TO_OUTX_EN, &val);
562 if (err < 0)
563 return 0;
564
565 if (!(val & BIT(index)))
566 return 0;
567
568 err = regmap_read(synth->data->regmap, SI5341_SYNTH_N_PDNB, &val);
569 if (err < 0)
570 return 0;
571
572 if (!(val & BIT(index)))
573 return 0;
574
575 /* This bit must be 0 for the synthesizer to receive clock input */
576 err = regmap_read(synth->data->regmap, SI5341_SYNTH_N_CLK_DIS, &val);
577 if (err < 0)
578 return 0;
579
580 return !(val & BIT(index));
581 }
582
si5341_synth_clk_unprepare(struct clk_hw * hw)583 static void si5341_synth_clk_unprepare(struct clk_hw *hw)
584 {
585 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
586 u8 index = synth->index; /* In range 0..5 */
587 u8 mask = BIT(index);
588
589 /* Disable output */
590 regmap_update_bits(synth->data->regmap,
591 SI5341_SYNTH_N_CLK_TO_OUTX_EN, mask, 0);
592 /* Power down */
593 regmap_update_bits(synth->data->regmap,
594 SI5341_SYNTH_N_PDNB, mask, 0);
595 /* Disable clock input to synth (set to 1 to disable) */
596 regmap_update_bits(synth->data->regmap,
597 SI5341_SYNTH_N_CLK_DIS, mask, mask);
598 }
599
si5341_synth_clk_prepare(struct clk_hw * hw)600 static int si5341_synth_clk_prepare(struct clk_hw *hw)
601 {
602 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
603 int err;
604 u8 index = synth->index;
605 u8 mask = BIT(index);
606
607 /* Power up */
608 err = regmap_update_bits(synth->data->regmap,
609 SI5341_SYNTH_N_PDNB, mask, mask);
610 if (err < 0)
611 return err;
612
613 /* Enable clock input to synth (set bit to 0 to enable) */
614 err = regmap_update_bits(synth->data->regmap,
615 SI5341_SYNTH_N_CLK_DIS, mask, 0);
616 if (err < 0)
617 return err;
618
619 /* Enable output */
620 return regmap_update_bits(synth->data->regmap,
621 SI5341_SYNTH_N_CLK_TO_OUTX_EN, mask, mask);
622 }
623
624 /* Synth clock frequency: Fvco * n_den / n_den, with Fvco in 13500-14256 MHz */
si5341_synth_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)625 static unsigned long si5341_synth_clk_recalc_rate(struct clk_hw *hw,
626 unsigned long parent_rate)
627 {
628 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
629 u64 f;
630 u64 n_num;
631 u32 n_den;
632 int err;
633
634 err = si5341_decode_44_32(synth->data->regmap,
635 SI5341_SYNTH_N_NUM(synth->index), &n_num, &n_den);
636 if (err < 0)
637 return err;
638 /* Check for bogus/uninitialized settings */
639 if (!n_num || !n_den)
640 return 0;
641
642 /*
643 * n_num and n_den are shifted left as much as possible, so to prevent
644 * overflow in 64-bit math, we shift n_den 4 bits to the right
645 */
646 f = synth->data->freq_vco;
647 f *= n_den >> 4;
648
649 /* Now we need to to 64-bit division: f/n_num */
650 /* And compensate for the 4 bits we dropped */
651 f = div64_u64(f, (n_num >> 4));
652
653 return f;
654 }
655
si5341_synth_clk_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)656 static long si5341_synth_clk_round_rate(struct clk_hw *hw, unsigned long rate,
657 unsigned long *parent_rate)
658 {
659 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
660 u64 f;
661
662 /* The synthesizer accuracy is such that anything in range will work */
663 f = synth->data->freq_vco;
664 do_div(f, SI5341_SYNTH_N_MAX);
665 if (rate < f)
666 return f;
667
668 f = synth->data->freq_vco;
669 do_div(f, SI5341_SYNTH_N_MIN);
670 if (rate > f)
671 return f;
672
673 return rate;
674 }
675
si5341_synth_program(struct clk_si5341_synth * synth,u64 n_num,u32 n_den,bool is_integer)676 static int si5341_synth_program(struct clk_si5341_synth *synth,
677 u64 n_num, u32 n_den, bool is_integer)
678 {
679 int err;
680 u8 index = synth->index;
681
682 err = si5341_encode_44_32(synth->data->regmap,
683 SI5341_SYNTH_N_NUM(index), n_num, n_den);
684
685 err = regmap_update_bits(synth->data->regmap,
686 SI5341_SYNTH_N_PIBYP, BIT(index), is_integer ? BIT(index) : 0);
687 if (err < 0)
688 return err;
689
690 return regmap_write(synth->data->regmap,
691 SI5341_SYNTH_N_UPD(index), 0x01);
692 }
693
694
si5341_synth_clk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)695 static int si5341_synth_clk_set_rate(struct clk_hw *hw, unsigned long rate,
696 unsigned long parent_rate)
697 {
698 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
699 u64 n_num;
700 u32 n_den;
701 u32 r;
702 u32 g;
703 bool is_integer;
704
705 n_num = synth->data->freq_vco;
706
707 /* see if there's an integer solution */
708 r = do_div(n_num, rate);
709 is_integer = (r == 0);
710 if (is_integer) {
711 /* Integer divider equal to n_num */
712 n_den = 1;
713 } else {
714 /* Calculate a fractional solution */
715 g = gcd(r, rate);
716 n_den = rate / g;
717 n_num *= n_den;
718 n_num += r / g;
719 }
720
721 dev_dbg(&synth->data->i2c_client->dev,
722 "%s(%u): n=0x%llx d=0x%x %s\n", __func__,
723 synth->index, n_num, n_den,
724 is_integer ? "int" : "frac");
725
726 return si5341_synth_program(synth, n_num, n_den, is_integer);
727 }
728
729 static const struct clk_ops si5341_synth_clk_ops = {
730 .is_prepared = si5341_synth_clk_is_on,
731 .prepare = si5341_synth_clk_prepare,
732 .unprepare = si5341_synth_clk_unprepare,
733 .recalc_rate = si5341_synth_clk_recalc_rate,
734 .round_rate = si5341_synth_clk_round_rate,
735 .set_rate = si5341_synth_clk_set_rate,
736 };
737
si5341_output_clk_is_on(struct clk_hw * hw)738 static int si5341_output_clk_is_on(struct clk_hw *hw)
739 {
740 struct clk_si5341_output *output = to_clk_si5341_output(hw);
741 int err;
742 u32 val;
743
744 err = regmap_read(output->data->regmap,
745 SI5341_OUT_CONFIG(output), &val);
746 if (err < 0)
747 return err;
748
749 /* Bit 0=PDN, 1=OE so only a value of 0x2 enables the output */
750 return (val & 0x03) == SI5341_OUT_CFG_OE;
751 }
752
753 /* Disables and then powers down the output */
si5341_output_clk_unprepare(struct clk_hw * hw)754 static void si5341_output_clk_unprepare(struct clk_hw *hw)
755 {
756 struct clk_si5341_output *output = to_clk_si5341_output(hw);
757
758 regmap_update_bits(output->data->regmap,
759 SI5341_OUT_CONFIG(output),
760 SI5341_OUT_CFG_OE, 0);
761 regmap_update_bits(output->data->regmap,
762 SI5341_OUT_CONFIG(output),
763 SI5341_OUT_CFG_PDN, SI5341_OUT_CFG_PDN);
764 }
765
766 /* Powers up and then enables the output */
si5341_output_clk_prepare(struct clk_hw * hw)767 static int si5341_output_clk_prepare(struct clk_hw *hw)
768 {
769 struct clk_si5341_output *output = to_clk_si5341_output(hw);
770 int err;
771
772 err = regmap_update_bits(output->data->regmap,
773 SI5341_OUT_CONFIG(output),
774 SI5341_OUT_CFG_PDN, 0);
775 if (err < 0)
776 return err;
777
778 return regmap_update_bits(output->data->regmap,
779 SI5341_OUT_CONFIG(output),
780 SI5341_OUT_CFG_OE, SI5341_OUT_CFG_OE);
781 }
782
si5341_output_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)783 static unsigned long si5341_output_clk_recalc_rate(struct clk_hw *hw,
784 unsigned long parent_rate)
785 {
786 struct clk_si5341_output *output = to_clk_si5341_output(hw);
787 int err;
788 u32 val;
789 u32 r_divider;
790 u8 r[3];
791
792 err = regmap_bulk_read(output->data->regmap,
793 SI5341_OUT_R_REG(output), r, 3);
794 if (err < 0)
795 return err;
796
797 /* Calculate value as 24-bit integer*/
798 r_divider = r[2] << 16 | r[1] << 8 | r[0];
799
800 /* If Rx_REG is zero, the divider is disabled, so return a "0" rate */
801 if (!r_divider)
802 return 0;
803
804 /* Divider is 2*(Rx_REG+1) */
805 r_divider += 1;
806 r_divider <<= 1;
807
808 err = regmap_read(output->data->regmap,
809 SI5341_OUT_CONFIG(output), &val);
810 if (err < 0)
811 return err;
812
813 if (val & SI5341_OUT_CFG_RDIV_FORCE2)
814 r_divider = 2;
815
816 return parent_rate / r_divider;
817 }
818
si5341_output_clk_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)819 static long si5341_output_clk_round_rate(struct clk_hw *hw, unsigned long rate,
820 unsigned long *parent_rate)
821 {
822 unsigned long r;
823
824 if (!rate)
825 return 0;
826
827 r = *parent_rate >> 1;
828
829 /* If rate is an even divisor, no changes to parent required */
830 if (r && !(r % rate))
831 return (long)rate;
832
833 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
834 if (rate > 200000000) {
835 /* minimum r-divider is 2 */
836 r = 2;
837 } else {
838 /* Take a parent frequency near 400 MHz */
839 r = (400000000u / rate) & ~1;
840 }
841 *parent_rate = r * rate;
842 } else {
843 /* We cannot change our parent's rate, report what we can do */
844 r /= rate;
845 rate = *parent_rate / (r << 1);
846 }
847
848 return rate;
849 }
850
si5341_output_clk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)851 static int si5341_output_clk_set_rate(struct clk_hw *hw, unsigned long rate,
852 unsigned long parent_rate)
853 {
854 struct clk_si5341_output *output = to_clk_si5341_output(hw);
855 u32 r_div;
856 int err;
857 u8 r[3];
858
859 if (!rate)
860 return -EINVAL;
861
862 /* Frequency divider is (r_div + 1) * 2 */
863 r_div = (parent_rate / rate) >> 1;
864
865 if (r_div <= 1)
866 r_div = 0;
867 else if (r_div >= BIT(24))
868 r_div = BIT(24) - 1;
869 else
870 --r_div;
871
872 /* For a value of "2", we set the "OUT0_RDIV_FORCE2" bit */
873 err = regmap_update_bits(output->data->regmap,
874 SI5341_OUT_CONFIG(output),
875 SI5341_OUT_CFG_RDIV_FORCE2,
876 (r_div == 0) ? SI5341_OUT_CFG_RDIV_FORCE2 : 0);
877 if (err < 0)
878 return err;
879
880 /* Always write Rx_REG, because a zero value disables the divider */
881 r[0] = r_div ? (r_div & 0xff) : 1;
882 r[1] = (r_div >> 8) & 0xff;
883 r[2] = (r_div >> 16) & 0xff;
884 err = regmap_bulk_write(output->data->regmap,
885 SI5341_OUT_R_REG(output), r, 3);
886
887 return 0;
888 }
889
si5341_output_reparent(struct clk_si5341_output * output,u8 index)890 static int si5341_output_reparent(struct clk_si5341_output *output, u8 index)
891 {
892 return regmap_update_bits(output->data->regmap,
893 SI5341_OUT_MUX_SEL(output), 0x07, index);
894 }
895
si5341_output_set_parent(struct clk_hw * hw,u8 index)896 static int si5341_output_set_parent(struct clk_hw *hw, u8 index)
897 {
898 struct clk_si5341_output *output = to_clk_si5341_output(hw);
899
900 if (index >= output->data->num_synth)
901 return -EINVAL;
902
903 return si5341_output_reparent(output, index);
904 }
905
si5341_output_get_parent(struct clk_hw * hw)906 static u8 si5341_output_get_parent(struct clk_hw *hw)
907 {
908 struct clk_si5341_output *output = to_clk_si5341_output(hw);
909 u32 val;
910
911 regmap_read(output->data->regmap, SI5341_OUT_MUX_SEL(output), &val);
912
913 return val & 0x7;
914 }
915
916 static const struct clk_ops si5341_output_clk_ops = {
917 .is_prepared = si5341_output_clk_is_on,
918 .prepare = si5341_output_clk_prepare,
919 .unprepare = si5341_output_clk_unprepare,
920 .recalc_rate = si5341_output_clk_recalc_rate,
921 .round_rate = si5341_output_clk_round_rate,
922 .set_rate = si5341_output_clk_set_rate,
923 .set_parent = si5341_output_set_parent,
924 .get_parent = si5341_output_get_parent,
925 };
926
927 /*
928 * The chip can be bought in a pre-programmed version, or one can program the
929 * NVM in the chip to boot up in a preset mode. This routine tries to determine
930 * if that's the case, or if we need to reset and program everything from
931 * scratch. Returns negative error, or true/false.
932 */
si5341_is_programmed_already(struct clk_si5341 * data)933 static int si5341_is_programmed_already(struct clk_si5341 *data)
934 {
935 int err;
936 u8 r[4];
937
938 /* Read the PLL divider value, it must have a non-zero value */
939 err = regmap_bulk_read(data->regmap, SI5341_PLL_M_DEN,
940 r, ARRAY_SIZE(r));
941 if (err < 0)
942 return err;
943
944 return !!get_unaligned_le32(r);
945 }
946
947 static struct clk_hw *
of_clk_si5341_get(struct of_phandle_args * clkspec,void * _data)948 of_clk_si5341_get(struct of_phandle_args *clkspec, void *_data)
949 {
950 struct clk_si5341 *data = _data;
951 unsigned int idx = clkspec->args[1];
952 unsigned int group = clkspec->args[0];
953
954 switch (group) {
955 case 0:
956 if (idx >= data->num_outputs) {
957 dev_err(&data->i2c_client->dev,
958 "invalid output index %u\n", idx);
959 return ERR_PTR(-EINVAL);
960 }
961 return &data->clk[idx].hw;
962 case 1:
963 if (idx >= data->num_synth) {
964 dev_err(&data->i2c_client->dev,
965 "invalid synthesizer index %u\n", idx);
966 return ERR_PTR(-EINVAL);
967 }
968 return &data->synth[idx].hw;
969 case 2:
970 if (idx > 0) {
971 dev_err(&data->i2c_client->dev,
972 "invalid PLL index %u\n", idx);
973 return ERR_PTR(-EINVAL);
974 }
975 return &data->hw;
976 default:
977 dev_err(&data->i2c_client->dev, "invalid group %u\n", group);
978 return ERR_PTR(-EINVAL);
979 }
980 }
981
si5341_probe_chip_id(struct clk_si5341 * data)982 static int si5341_probe_chip_id(struct clk_si5341 *data)
983 {
984 int err;
985 u8 reg[4];
986 u16 model;
987
988 err = regmap_bulk_read(data->regmap, SI5341_PN_BASE, reg,
989 ARRAY_SIZE(reg));
990 if (err < 0) {
991 dev_err(&data->i2c_client->dev, "Failed to read chip ID\n");
992 return err;
993 }
994
995 model = get_unaligned_le16(reg);
996
997 dev_info(&data->i2c_client->dev, "Chip: %x Grade: %u Rev: %u\n",
998 model, reg[2], reg[3]);
999
1000 switch (model) {
1001 case 0x5340:
1002 data->num_outputs = SI5340_MAX_NUM_OUTPUTS;
1003 data->num_synth = SI5340_NUM_SYNTH;
1004 data->reg_output_offset = si5340_reg_output_offset;
1005 data->reg_rdiv_offset = si5340_reg_rdiv_offset;
1006 break;
1007 case 0x5341:
1008 data->num_outputs = SI5341_MAX_NUM_OUTPUTS;
1009 data->num_synth = SI5341_NUM_SYNTH;
1010 data->reg_output_offset = si5341_reg_output_offset;
1011 data->reg_rdiv_offset = si5341_reg_rdiv_offset;
1012 break;
1013 case 0x5342:
1014 data->num_outputs = SI5342_MAX_NUM_OUTPUTS;
1015 data->num_synth = SI5342_NUM_SYNTH;
1016 data->reg_output_offset = si5340_reg_output_offset;
1017 data->reg_rdiv_offset = si5340_reg_rdiv_offset;
1018 break;
1019 case 0x5344:
1020 data->num_outputs = SI5344_MAX_NUM_OUTPUTS;
1021 data->num_synth = SI5344_NUM_SYNTH;
1022 data->reg_output_offset = si5340_reg_output_offset;
1023 data->reg_rdiv_offset = si5340_reg_rdiv_offset;
1024 break;
1025 case 0x5345:
1026 data->num_outputs = SI5345_MAX_NUM_OUTPUTS;
1027 data->num_synth = SI5345_NUM_SYNTH;
1028 data->reg_output_offset = si5341_reg_output_offset;
1029 data->reg_rdiv_offset = si5341_reg_rdiv_offset;
1030 break;
1031 default:
1032 dev_err(&data->i2c_client->dev, "Model '%x' not supported\n",
1033 model);
1034 return -EINVAL;
1035 }
1036
1037 data->chip_id = model;
1038
1039 return 0;
1040 }
1041
1042 /* Read active settings into the regmap cache for later reference */
si5341_read_settings(struct clk_si5341 * data)1043 static int si5341_read_settings(struct clk_si5341 *data)
1044 {
1045 int err;
1046 u8 i;
1047 u8 r[10];
1048
1049 err = regmap_bulk_read(data->regmap, SI5341_PLL_M_NUM, r, 10);
1050 if (err < 0)
1051 return err;
1052
1053 err = regmap_bulk_read(data->regmap,
1054 SI5341_SYNTH_N_CLK_TO_OUTX_EN, r, 3);
1055 if (err < 0)
1056 return err;
1057
1058 err = regmap_bulk_read(data->regmap,
1059 SI5341_SYNTH_N_CLK_DIS, r, 1);
1060 if (err < 0)
1061 return err;
1062
1063 for (i = 0; i < data->num_synth; ++i) {
1064 err = regmap_bulk_read(data->regmap,
1065 SI5341_SYNTH_N_NUM(i), r, 10);
1066 if (err < 0)
1067 return err;
1068 }
1069
1070 for (i = 0; i < data->num_outputs; ++i) {
1071 err = regmap_bulk_read(data->regmap,
1072 data->reg_output_offset[i], r, 4);
1073 if (err < 0)
1074 return err;
1075
1076 err = regmap_bulk_read(data->regmap,
1077 data->reg_rdiv_offset[i], r, 3);
1078 if (err < 0)
1079 return err;
1080 }
1081
1082 return 0;
1083 }
1084
si5341_write_multiple(struct clk_si5341 * data,const struct si5341_reg_default * values,unsigned int num_values)1085 static int si5341_write_multiple(struct clk_si5341 *data,
1086 const struct si5341_reg_default *values, unsigned int num_values)
1087 {
1088 unsigned int i;
1089 int res;
1090
1091 for (i = 0; i < num_values; ++i) {
1092 res = regmap_write(data->regmap,
1093 values[i].address, values[i].value);
1094 if (res < 0) {
1095 dev_err(&data->i2c_client->dev,
1096 "Failed to write %#x:%#x\n",
1097 values[i].address, values[i].value);
1098 return res;
1099 }
1100 }
1101
1102 return 0;
1103 }
1104
1105 static const struct si5341_reg_default si5341_preamble[] = {
1106 { 0x0B25, 0x00 },
1107 { 0x0502, 0x01 },
1108 { 0x0505, 0x03 },
1109 { 0x0957, 0x17 },
1110 { 0x0B4E, 0x1A },
1111 };
1112
1113 static const struct si5341_reg_default si5345_preamble[] = {
1114 { 0x0B25, 0x00 },
1115 { 0x0540, 0x01 },
1116 };
1117
si5341_send_preamble(struct clk_si5341 * data)1118 static int si5341_send_preamble(struct clk_si5341 *data)
1119 {
1120 int res;
1121 u32 revision;
1122
1123 /* For revision 2 and up, the values are slightly different */
1124 res = regmap_read(data->regmap, SI5341_DEVICE_REV, &revision);
1125 if (res < 0)
1126 return res;
1127
1128 /* Write "preamble" as specified by datasheet */
1129 res = regmap_write(data->regmap, 0xB24, revision < 2 ? 0xD8 : 0xC0);
1130 if (res < 0)
1131 return res;
1132
1133 /* The si5342..si5345 require a different preamble */
1134 if (data->chip_id > 0x5341)
1135 res = si5341_write_multiple(data,
1136 si5345_preamble, ARRAY_SIZE(si5345_preamble));
1137 else
1138 res = si5341_write_multiple(data,
1139 si5341_preamble, ARRAY_SIZE(si5341_preamble));
1140 if (res < 0)
1141 return res;
1142
1143 /* Datasheet specifies a 300ms wait after sending the preamble */
1144 msleep(300);
1145
1146 return 0;
1147 }
1148
1149 /* Perform a soft reset and write post-amble */
si5341_finalize_defaults(struct clk_si5341 * data)1150 static int si5341_finalize_defaults(struct clk_si5341 *data)
1151 {
1152 int res;
1153 u32 revision;
1154
1155 res = regmap_read(data->regmap, SI5341_DEVICE_REV, &revision);
1156 if (res < 0)
1157 return res;
1158
1159 dev_dbg(&data->i2c_client->dev, "%s rev=%u\n", __func__, revision);
1160
1161 res = regmap_write(data->regmap, SI5341_SOFT_RST, 0x01);
1162 if (res < 0)
1163 return res;
1164
1165 /* The si5342..si5345 have an additional post-amble */
1166 if (data->chip_id > 0x5341) {
1167 res = regmap_write(data->regmap, 0x540, 0x0);
1168 if (res < 0)
1169 return res;
1170 }
1171
1172 /* Datasheet does not explain these nameless registers */
1173 res = regmap_write(data->regmap, 0xB24, revision < 2 ? 0xDB : 0xC3);
1174 if (res < 0)
1175 return res;
1176 res = regmap_write(data->regmap, 0x0B25, 0x02);
1177 if (res < 0)
1178 return res;
1179
1180 return 0;
1181 }
1182
1183
1184 static const struct regmap_range si5341_regmap_volatile_range[] = {
1185 regmap_reg_range(0x000C, 0x0012), /* Status */
1186 regmap_reg_range(0x001C, 0x001E), /* reset, finc/fdec */
1187 regmap_reg_range(0x00E2, 0x00FE), /* NVM, interrupts, device ready */
1188 /* Update bits for P divider and synth config */
1189 regmap_reg_range(SI5341_PX_UPD, SI5341_PX_UPD),
1190 regmap_reg_range(SI5341_SYNTH_N_UPD(0), SI5341_SYNTH_N_UPD(0)),
1191 regmap_reg_range(SI5341_SYNTH_N_UPD(1), SI5341_SYNTH_N_UPD(1)),
1192 regmap_reg_range(SI5341_SYNTH_N_UPD(2), SI5341_SYNTH_N_UPD(2)),
1193 regmap_reg_range(SI5341_SYNTH_N_UPD(3), SI5341_SYNTH_N_UPD(3)),
1194 regmap_reg_range(SI5341_SYNTH_N_UPD(4), SI5341_SYNTH_N_UPD(4)),
1195 };
1196
1197 static const struct regmap_access_table si5341_regmap_volatile = {
1198 .yes_ranges = si5341_regmap_volatile_range,
1199 .n_yes_ranges = ARRAY_SIZE(si5341_regmap_volatile_range),
1200 };
1201
1202 /* Pages 0, 1, 2, 3, 9, A, B are valid, so there are 12 pages */
1203 static const struct regmap_range_cfg si5341_regmap_ranges[] = {
1204 {
1205 .range_min = 0,
1206 .range_max = SI5341_REGISTER_MAX,
1207 .selector_reg = SI5341_PAGE,
1208 .selector_mask = 0xff,
1209 .selector_shift = 0,
1210 .window_start = 0,
1211 .window_len = 256,
1212 },
1213 };
1214
si5341_wait_device_ready(struct i2c_client * client)1215 static int si5341_wait_device_ready(struct i2c_client *client)
1216 {
1217 int count;
1218
1219 /* Datasheet warns: Any attempt to read or write any register other
1220 * than DEVICE_READY before DEVICE_READY reads as 0x0F may corrupt the
1221 * NVM programming and may corrupt the register contents, as they are
1222 * read from NVM. Note that this includes accesses to the PAGE register.
1223 * Also: DEVICE_READY is available on every register page, so no page
1224 * change is needed to read it.
1225 * Do this outside regmap to avoid automatic PAGE register access.
1226 * May take up to 300ms to complete.
1227 */
1228 for (count = 0; count < 15; ++count) {
1229 s32 result = i2c_smbus_read_byte_data(client,
1230 SI5341_DEVICE_READY);
1231 if (result < 0)
1232 return result;
1233 if (result == 0x0F)
1234 return 0;
1235 msleep(20);
1236 }
1237 dev_err(&client->dev, "timeout waiting for DEVICE_READY\n");
1238 return -EIO;
1239 }
1240
1241 static const struct regmap_config si5341_regmap_config = {
1242 .reg_bits = 8,
1243 .val_bits = 8,
1244 .cache_type = REGCACHE_RBTREE,
1245 .ranges = si5341_regmap_ranges,
1246 .num_ranges = ARRAY_SIZE(si5341_regmap_ranges),
1247 .max_register = SI5341_REGISTER_MAX,
1248 .volatile_table = &si5341_regmap_volatile,
1249 };
1250
si5341_dt_parse_dt(struct i2c_client * client,struct clk_si5341_output_config * config)1251 static int si5341_dt_parse_dt(struct i2c_client *client,
1252 struct clk_si5341_output_config *config)
1253 {
1254 struct device_node *child;
1255 struct device_node *np = client->dev.of_node;
1256 u32 num;
1257 u32 val;
1258
1259 memset(config, 0, sizeof(struct clk_si5341_output_config) *
1260 SI5341_MAX_NUM_OUTPUTS);
1261
1262 for_each_child_of_node(np, child) {
1263 if (of_property_read_u32(child, "reg", &num)) {
1264 dev_err(&client->dev, "missing reg property of %s\n",
1265 child->name);
1266 goto put_child;
1267 }
1268
1269 if (num >= SI5341_MAX_NUM_OUTPUTS) {
1270 dev_err(&client->dev, "invalid clkout %d\n", num);
1271 goto put_child;
1272 }
1273
1274 if (!of_property_read_u32(child, "silabs,format", &val)) {
1275 /* Set cm and ampl conservatively to 3v3 settings */
1276 switch (val) {
1277 case 1: /* normal differential */
1278 config[num].out_cm_ampl_bits = 0x33;
1279 break;
1280 case 2: /* low-power differential */
1281 config[num].out_cm_ampl_bits = 0x13;
1282 break;
1283 case 4: /* LVCMOS */
1284 config[num].out_cm_ampl_bits = 0x33;
1285 /* Set SI recommended impedance for LVCMOS */
1286 config[num].out_format_drv_bits |= 0xc0;
1287 break;
1288 default:
1289 dev_err(&client->dev,
1290 "invalid silabs,format %u for %u\n",
1291 val, num);
1292 goto put_child;
1293 }
1294 config[num].out_format_drv_bits &= ~0x07;
1295 config[num].out_format_drv_bits |= val & 0x07;
1296 /* Always enable the SYNC feature */
1297 config[num].out_format_drv_bits |= 0x08;
1298 }
1299
1300 if (!of_property_read_u32(child, "silabs,common-mode", &val)) {
1301 if (val > 0xf) {
1302 dev_err(&client->dev,
1303 "invalid silabs,common-mode %u\n",
1304 val);
1305 goto put_child;
1306 }
1307 config[num].out_cm_ampl_bits &= 0xf0;
1308 config[num].out_cm_ampl_bits |= val & 0x0f;
1309 }
1310
1311 if (!of_property_read_u32(child, "silabs,amplitude", &val)) {
1312 if (val > 0xf) {
1313 dev_err(&client->dev,
1314 "invalid silabs,amplitude %u\n",
1315 val);
1316 goto put_child;
1317 }
1318 config[num].out_cm_ampl_bits &= 0x0f;
1319 config[num].out_cm_ampl_bits |= (val << 4) & 0xf0;
1320 }
1321
1322 if (of_property_read_bool(child, "silabs,disable-high"))
1323 config[num].out_format_drv_bits |= 0x10;
1324
1325 config[num].synth_master =
1326 of_property_read_bool(child, "silabs,synth-master");
1327
1328 config[num].always_on =
1329 of_property_read_bool(child, "always-on");
1330 }
1331
1332 return 0;
1333
1334 put_child:
1335 of_node_put(child);
1336 return -EINVAL;
1337 }
1338
1339 /*
1340 * If not pre-configured, calculate and set the PLL configuration manually.
1341 * For low-jitter performance, the PLL should be set such that the synthesizers
1342 * only need integer division.
1343 * Without any user guidance, we'll set the PLL to 14GHz, which still allows
1344 * the chip to generate any frequency on its outputs, but jitter performance
1345 * may be sub-optimal.
1346 */
si5341_initialize_pll(struct clk_si5341 * data)1347 static int si5341_initialize_pll(struct clk_si5341 *data)
1348 {
1349 struct device_node *np = data->i2c_client->dev.of_node;
1350 u32 m_num = 0;
1351 u32 m_den = 0;
1352 int sel;
1353
1354 if (of_property_read_u32(np, "silabs,pll-m-num", &m_num)) {
1355 dev_err(&data->i2c_client->dev,
1356 "PLL configuration requires silabs,pll-m-num\n");
1357 }
1358 if (of_property_read_u32(np, "silabs,pll-m-den", &m_den)) {
1359 dev_err(&data->i2c_client->dev,
1360 "PLL configuration requires silabs,pll-m-den\n");
1361 }
1362
1363 if (!m_num || !m_den) {
1364 dev_err(&data->i2c_client->dev,
1365 "PLL configuration invalid, assume 14GHz\n");
1366 sel = si5341_clk_get_selected_input(data);
1367 if (sel < 0)
1368 return sel;
1369
1370 m_den = clk_get_rate(data->input_clk[sel]) / 10;
1371 m_num = 1400000000;
1372 }
1373
1374 return si5341_encode_44_32(data->regmap,
1375 SI5341_PLL_M_NUM, m_num, m_den);
1376 }
1377
si5341_clk_select_active_input(struct clk_si5341 * data)1378 static int si5341_clk_select_active_input(struct clk_si5341 *data)
1379 {
1380 int res;
1381 int err;
1382 int i;
1383
1384 res = si5341_clk_get_selected_input(data);
1385 if (res < 0)
1386 return res;
1387
1388 /* If the current register setting is invalid, pick the first input */
1389 if (!data->input_clk[res]) {
1390 dev_dbg(&data->i2c_client->dev,
1391 "Input %d not connected, rerouting\n", res);
1392 res = -ENODEV;
1393 for (i = 0; i < SI5341_NUM_INPUTS; ++i) {
1394 if (data->input_clk[i]) {
1395 res = i;
1396 break;
1397 }
1398 }
1399 if (res < 0) {
1400 dev_err(&data->i2c_client->dev,
1401 "No clock input available\n");
1402 return res;
1403 }
1404 }
1405
1406 /* Make sure the selected clock is also enabled and routed */
1407 err = si5341_clk_reparent(data, res);
1408 if (err < 0)
1409 return err;
1410
1411 err = clk_prepare_enable(data->input_clk[res]);
1412 if (err < 0)
1413 return err;
1414
1415 return res;
1416 }
1417
si5341_probe(struct i2c_client * client,const struct i2c_device_id * id)1418 static int si5341_probe(struct i2c_client *client,
1419 const struct i2c_device_id *id)
1420 {
1421 struct clk_si5341 *data;
1422 struct clk_init_data init;
1423 struct clk *input;
1424 const char *root_clock_name;
1425 const char *synth_clock_names[SI5341_NUM_SYNTH];
1426 int err;
1427 unsigned int i;
1428 struct clk_si5341_output_config config[SI5341_MAX_NUM_OUTPUTS];
1429 bool initialization_required;
1430 u32 status;
1431
1432 data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL);
1433 if (!data)
1434 return -ENOMEM;
1435
1436 data->i2c_client = client;
1437
1438 /* Must be done before otherwise touching hardware */
1439 err = si5341_wait_device_ready(client);
1440 if (err)
1441 return err;
1442
1443 for (i = 0; i < SI5341_NUM_INPUTS; ++i) {
1444 input = devm_clk_get(&client->dev, si5341_input_clock_names[i]);
1445 if (IS_ERR(input)) {
1446 if (PTR_ERR(input) == -EPROBE_DEFER)
1447 return -EPROBE_DEFER;
1448 data->input_clk_name[i] = si5341_input_clock_names[i];
1449 } else {
1450 data->input_clk[i] = input;
1451 data->input_clk_name[i] = __clk_get_name(input);
1452 }
1453 }
1454
1455 err = si5341_dt_parse_dt(client, config);
1456 if (err)
1457 return err;
1458
1459 if (of_property_read_string(client->dev.of_node, "clock-output-names",
1460 &init.name))
1461 init.name = client->dev.of_node->name;
1462 root_clock_name = init.name;
1463
1464 data->regmap = devm_regmap_init_i2c(client, &si5341_regmap_config);
1465 if (IS_ERR(data->regmap))
1466 return PTR_ERR(data->regmap);
1467
1468 i2c_set_clientdata(client, data);
1469
1470 err = si5341_probe_chip_id(data);
1471 if (err < 0)
1472 return err;
1473
1474 if (of_property_read_bool(client->dev.of_node, "silabs,reprogram")) {
1475 initialization_required = true;
1476 } else {
1477 err = si5341_is_programmed_already(data);
1478 if (err < 0)
1479 return err;
1480
1481 initialization_required = !err;
1482 }
1483
1484 if (initialization_required) {
1485 /* Populate the regmap cache in preparation for "cache only" */
1486 err = si5341_read_settings(data);
1487 if (err < 0)
1488 return err;
1489
1490 err = si5341_send_preamble(data);
1491 if (err < 0)
1492 return err;
1493
1494 /*
1495 * We intend to send all 'final' register values in a single
1496 * transaction. So cache all register writes until we're done
1497 * configuring.
1498 */
1499 regcache_cache_only(data->regmap, true);
1500
1501 /* Write the configuration pairs from the firmware blob */
1502 err = si5341_write_multiple(data, si5341_reg_defaults,
1503 ARRAY_SIZE(si5341_reg_defaults));
1504 if (err < 0)
1505 return err;
1506 }
1507
1508 /* Input must be up and running at this point */
1509 err = si5341_clk_select_active_input(data);
1510 if (err < 0)
1511 return err;
1512
1513 if (initialization_required) {
1514 /* PLL configuration is required */
1515 err = si5341_initialize_pll(data);
1516 if (err < 0)
1517 return err;
1518 }
1519
1520 /* Register the PLL */
1521 init.parent_names = data->input_clk_name;
1522 init.num_parents = SI5341_NUM_INPUTS;
1523 init.ops = &si5341_clk_ops;
1524 init.flags = 0;
1525 data->hw.init = &init;
1526
1527 err = devm_clk_hw_register(&client->dev, &data->hw);
1528 if (err) {
1529 dev_err(&client->dev, "clock registration failed\n");
1530 return err;
1531 }
1532
1533 init.num_parents = 1;
1534 init.parent_names = &root_clock_name;
1535 init.ops = &si5341_synth_clk_ops;
1536 for (i = 0; i < data->num_synth; ++i) {
1537 synth_clock_names[i] = devm_kasprintf(&client->dev, GFP_KERNEL,
1538 "%s.N%u", client->dev.of_node->name, i);
1539 init.name = synth_clock_names[i];
1540 data->synth[i].index = i;
1541 data->synth[i].data = data;
1542 data->synth[i].hw.init = &init;
1543 err = devm_clk_hw_register(&client->dev, &data->synth[i].hw);
1544 if (err) {
1545 dev_err(&client->dev,
1546 "synth N%u registration failed\n", i);
1547 }
1548 }
1549
1550 init.num_parents = data->num_synth;
1551 init.parent_names = synth_clock_names;
1552 init.ops = &si5341_output_clk_ops;
1553 for (i = 0; i < data->num_outputs; ++i) {
1554 init.name = kasprintf(GFP_KERNEL, "%s.%d",
1555 client->dev.of_node->name, i);
1556 init.flags = config[i].synth_master ? CLK_SET_RATE_PARENT : 0;
1557 data->clk[i].index = i;
1558 data->clk[i].data = data;
1559 data->clk[i].hw.init = &init;
1560 if (config[i].out_format_drv_bits & 0x07) {
1561 regmap_write(data->regmap,
1562 SI5341_OUT_FORMAT(&data->clk[i]),
1563 config[i].out_format_drv_bits);
1564 regmap_write(data->regmap,
1565 SI5341_OUT_CM(&data->clk[i]),
1566 config[i].out_cm_ampl_bits);
1567 }
1568 err = devm_clk_hw_register(&client->dev, &data->clk[i].hw);
1569 kfree(init.name); /* clock framework made a copy of the name */
1570 if (err) {
1571 dev_err(&client->dev,
1572 "output %u registration failed\n", i);
1573 return err;
1574 }
1575 if (config[i].always_on)
1576 clk_prepare(data->clk[i].hw.clk);
1577 }
1578
1579 err = devm_of_clk_add_hw_provider(&client->dev, of_clk_si5341_get,
1580 data);
1581 if (err) {
1582 dev_err(&client->dev, "unable to add clk provider\n");
1583 return err;
1584 }
1585
1586 if (initialization_required) {
1587 /* Synchronize */
1588 regcache_cache_only(data->regmap, false);
1589 err = regcache_sync(data->regmap);
1590 if (err < 0)
1591 return err;
1592
1593 err = si5341_finalize_defaults(data);
1594 if (err < 0)
1595 return err;
1596 }
1597
1598 /* wait for device to report input clock present and PLL lock */
1599 err = regmap_read_poll_timeout(data->regmap, SI5341_STATUS, status,
1600 !(status & (SI5341_STATUS_LOSREF | SI5341_STATUS_LOL)),
1601 10000, 250000);
1602 if (err) {
1603 dev_err(&client->dev, "Error waiting for input clock or PLL lock\n");
1604 return err;
1605 }
1606
1607 /* clear sticky alarm bits from initialization */
1608 err = regmap_write(data->regmap, SI5341_STATUS_STICKY, 0);
1609 if (err) {
1610 dev_err(&client->dev, "unable to clear sticky status\n");
1611 return err;
1612 }
1613
1614 /* Free the names, clk framework makes copies */
1615 for (i = 0; i < data->num_synth; ++i)
1616 devm_kfree(&client->dev, (void *)synth_clock_names[i]);
1617
1618 return 0;
1619 }
1620
1621 static const struct i2c_device_id si5341_id[] = {
1622 { "si5340", 0 },
1623 { "si5341", 1 },
1624 { "si5342", 2 },
1625 { "si5344", 4 },
1626 { "si5345", 5 },
1627 { }
1628 };
1629 MODULE_DEVICE_TABLE(i2c, si5341_id);
1630
1631 static const struct of_device_id clk_si5341_of_match[] = {
1632 { .compatible = "silabs,si5340" },
1633 { .compatible = "silabs,si5341" },
1634 { .compatible = "silabs,si5342" },
1635 { .compatible = "silabs,si5344" },
1636 { .compatible = "silabs,si5345" },
1637 { }
1638 };
1639 MODULE_DEVICE_TABLE(of, clk_si5341_of_match);
1640
1641 static struct i2c_driver si5341_driver = {
1642 .driver = {
1643 .name = "si5341",
1644 .of_match_table = clk_si5341_of_match,
1645 },
1646 .probe = si5341_probe,
1647 .id_table = si5341_id,
1648 };
1649 module_i2c_driver(si5341_driver);
1650
1651 MODULE_AUTHOR("Mike Looijmans <mike.looijmans@topic.nl>");
1652 MODULE_DESCRIPTION("Si5341 driver");
1653 MODULE_LICENSE("GPL");
1654