Home
last modified time | relevance | path

Searched full:dwc3 (Results 1 – 25 of 121) sorted by relevance

12345

/kernel/linux/linux-5.10/drivers/usb/dwc3/
DMakefile5 obj-$(CONFIG_USB_DWC3) += dwc3.o
7 dwc3-y := core.o
10 dwc3-y += trace.o
14 dwc3-y += host.o
18 dwc3-y += gadget.o ep0.o
22 dwc3-y += drd.o
26 dwc3-y += ulpi.o
30 dwc3-y += debugfs.o
45 obj-$(CONFIG_USB_DWC3_OMAP) += dwc3-omap.o
46 obj-$(CONFIG_USB_DWC3_EXYNOS) += dwc3-exynos.o
[all …]
Ddwc3-haps.c3 * dwc3-haps.c - Synopsys HAPS PCI Specific glue layer
20 * @dwc3: child dwc3 platform_device
24 struct platform_device *dwc3; member
56 dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO); in dwc3_haps_probe()
57 if (!dwc->dwc3) in dwc3_haps_probe()
71 ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res)); in dwc3_haps_probe()
73 dev_err(dev, "couldn't add resources to dwc3 device\n"); in dwc3_haps_probe()
78 dwc->dwc3->dev.parent = dev; in dwc3_haps_probe()
80 ret = platform_device_add_properties(dwc->dwc3, initial_properties); in dwc3_haps_probe()
84 ret = platform_device_add(dwc->dwc3); in dwc3_haps_probe()
[all …]
Ddwc3-pci.c3 * dwc3-pci.c - PCI Specific glue layer
56 * @dwc3: child dwc3 platform_device
63 struct platform_device *dwc3; member
212 struct platform_device *dwc3 = dwc->dwc3; in dwc3_pci_resume_work() local
215 ret = pm_runtime_get_sync(&dwc3->dev); in dwc3_pci_resume_work()
217 pm_runtime_put_sync_autosuspend(&dwc3->dev); in dwc3_pci_resume_work()
221 pm_runtime_mark_last_busy(&dwc3->dev); in dwc3_pci_resume_work()
222 pm_runtime_put_sync_autosuspend(&dwc3->dev); in dwc3_pci_resume_work()
246 dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO); in dwc3_pci_probe()
247 if (!dwc->dwc3) in dwc3_pci_probe()
[all …]
Dcore.c47 static int dwc3_get_dr_mode(struct dwc3 *dwc) in dwc3_get_dr_mode()
90 !DWC3_VER_IS_PRIOR(DWC3, 330A)) in dwc3_get_dr_mode()
105 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode) in dwc3_set_prtcap()
117 static int dwc3_core_soft_reset(struct dwc3 *dwc);
121 struct dwc3 *dwc = work_to_dwc(work); in __dwc3_set_mode()
231 void dwc3_set_mode(struct dwc3 *dwc, u32 mode) in dwc3_set_mode()
247 struct dwc3 *dwc = dep->dwc; in dwc3_core_fifo_space()
263 static int dwc3_core_soft_reset(struct dwc3 *dwc) in dwc3_core_soft_reset()
270 * XHCI driver will reset the host block. If dwc3 was configured for in dwc3_core_soft_reset()
316 * @dwc3: Pointer to our controller context structure
[all …]
Ddwc3-qcom.c4 * Inspired by dwc3-of-simple.c
69 struct platform_device *dwc3; member
264 if (usb_get_maximum_speed(&qcom->dwc3->dev) >= USB_SPEED_SUPER || in dwc3_qcom_interconnect_init()
265 usb_get_maximum_speed(&qcom->dwc3->dev) == USB_SPEED_UNKNOWN) in dwc3_qcom_interconnect_init()
408 struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3); in qcom_dwc3_resume_irq()
422 /* Configure dwc3 to use UTMI clock as PIPE clock not present */ in dwc3_qcom_select_utmi_clk()
586 qcom->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO); in dwc3_qcom_acpi_register_core()
587 if (!qcom->dwc3) in dwc3_qcom_acpi_register_core()
590 qcom->dwc3->dev.parent = dev; in dwc3_qcom_acpi_register_core()
591 qcom->dwc3->dev.type = dev->type; in dwc3_qcom_acpi_register_core()
[all …]
Dep0.c30 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
31 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
38 struct dwc3 *dwc; in dwc3_ep0_prepare_one_trb()
66 struct dwc3 *dwc; in dwc3_ep0_start_trans()
90 struct dwc3 *dwc = dep->dwc; in __dwc3_gadget_ep0_queue()
193 struct dwc3 *dwc = dep->dwc; in dwc3_gadget_ep0_queue()
221 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc) in dwc3_ep0_stall_and_restart()
249 struct dwc3 *dwc = dep->dwc; in __dwc3_gadget_ep0_set_halt()
259 struct dwc3 *dwc = dep->dwc; in dwc3_gadget_ep0_set_halt()
270 void dwc3_ep0_out_start(struct dwc3 *dwc) in dwc3_ep0_out_start()
[all …]
Dgadget.c41 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) in dwc3_gadget_set_test_mode()
72 int dwc3_gadget_get_link_state(struct dwc3 *dwc) in dwc3_gadget_get_link_state()
89 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state) in dwc3_gadget_set_link_state()
98 if (!DWC3_VER_IS_PRIOR(DWC3, 194A)) { in dwc3_gadget_set_link_state()
125 if (!DWC3_VER_IS_PRIOR(DWC3, 194A)) in dwc3_gadget_set_link_state()
178 struct dwc3 *dwc = dep->dwc; in dwc3_gadget_del_and_unmap_request()
211 struct dwc3 *dwc = dep->dwc; in dwc3_gadget_giveback()
230 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned int cmd, in dwc3_send_gadget_generic_command()
261 static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
276 struct dwc3 *dwc = dep->dwc; in dwc3_send_gadget_ep_cmd()
[all …]
Ddrd.c19 static void dwc3_otg_disable_events(struct dwc3 *dwc, u32 disable_mask) in dwc3_otg_disable_events()
27 static void dwc3_otg_enable_events(struct dwc3 *dwc, u32 enable_mask) in dwc3_otg_enable_events()
35 static void dwc3_otg_clear_events(struct dwc3 *dwc) in dwc3_otg_clear_events()
54 struct dwc3 *dwc = _dwc; in dwc3_otg_thread_irq()
72 struct dwc3 *dwc = _dwc; in dwc3_otg_irq()
93 static void dwc3_otgregs_init(struct dwc3 *dwc) in dwc3_otgregs_init()
137 static int dwc3_otg_get_irq(struct dwc3 *dwc) in dwc3_otg_get_irq()
167 void dwc3_otg_init(struct dwc3 *dwc) in dwc3_otg_init()
186 void dwc3_otg_exit(struct dwc3 *dwc) in dwc3_otg_exit()
195 void dwc3_otg_host_init(struct dwc3 *dwc) in dwc3_otg_host_init()
[all …]
Dcore.h75 /* DWC3 registers memory space boundries */
652 struct dwc3 *dwc;
700 struct dwc3 *dwc;
886 * @status: internal dwc3 request status tracking
934 * struct dwc3 - representation of our controller
1016 * @has_hibernation: true when dwc3 was configured with Hibernation
1017 * @sysdev_is_parent: true when dwc3 device has a parent driver
1068 struct dwc3 { struct
1270 #define work_to_dwc(w) (container_of((w), struct dwc3, drd_work)) argument
1421 * DWC3 Features to be used as Driver Data
[all …]
Ddwc3-of-simple.c3 * dwc3-of-simple.c - OF glue layer for simple integrations
9 * This is a combination of the old dwc3-qcom.c by Ivan T. Ivanov
52 if (of_device_is_compatible(np, "rockchip,rk3399-dwc3")) in dwc3_of_simple_probe()
174 { .compatible = "rockchip,rk3399-dwc3" },
175 { .compatible = "xlnx,zynqmp-dwc3" },
177 { .compatible = "sprd,sc9860-dwc3" },
178 { .compatible = "allwinner,sun50i-h6-dwc3" },
179 { .compatible = "hisilicon,hi3670-dwc3" },
180 { .compatible = "intel,keembay-dwc3" },
190 .name = "dwc3-of-simple",
Ddwc3-st.c3 * dwc3-st.c Support for dwc3 platform devices on ST Microelectronics platforms
5 * This is a small driver for the dwc3 to provide the glue logic
14 * Inspired by dwc3-omap.c and dwc3-exynos.c.
78 * struct st_dwc3 - dwc3-st driver private structure
254 child = of_get_child_by_name(node, "dwc3"); in st_dwc3_probe()
256 dev_err(&pdev->dev, "failed to find dwc3 core node\n"); in st_dwc3_probe()
264 dev_err(dev, "failed to add dwc3 core\n"); in st_dwc3_probe()
270 dev_err(dev, "failed to find dwc3 core device\n"); in st_dwc3_probe()
359 { .compatible = "st,stih407-dwc3" },
369 .name = "usb-st-dwc3",
Ddwc3-keystone.c3 * dwc3-keystone.c - Keystone Specific Glue layer
140 if (of_device_is_compatible(node, "ti,am654-dwc3")) in kdwc3_probe()
162 dev_err(&pdev->dev, "failed to create dwc3 core\n"); in kdwc3_probe()
194 if (!of_device_is_compatible(node, "ti,am654-dwc3")) in kdwc3_remove()
211 { .compatible = "ti,keystone-dwc3", },
212 { .compatible = "ti,am654-dwc3" },
221 .name = "keystone-dwc3",
228 MODULE_ALIAS("platform:keystone-dwc3");
DKconfig13 module, the module will be called dwc3.ko.
21 Select this if you have ULPI type PHY attached to your DWC3
25 bool "DWC3 Mode Selection"
34 Select this when you want to use DWC3 in host mode only,
41 Select this when you want to use DWC3 in gadget mode only,
49 This is the default mode of working of DWC3 controller where
Ddebugfs.c282 struct dwc3 *dwc = s->private; in dwc3_host_lsp()
312 struct dwc3 *dwc = s->private; in dwc3_gadget_lsp()
326 struct dwc3 *dwc = s->private; in dwc3_lsp_show()
360 struct dwc3 *dwc = s->private; in dwc3_lsp_write()
390 struct dwc3 *dwc = s->private; in dwc3_mode_show()
424 struct dwc3 *dwc = s->private; in dwc3_mode_write()
458 struct dwc3 *dwc = s->private; in dwc3_testmode_show()
503 struct dwc3 *dwc = s->private; in dwc3_testmode_write()
541 struct dwc3 *dwc = s->private; in dwc3_link_state_show()
576 struct dwc3 *dwc = s->private; in dwc3_link_state_write()
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/usb/
Ddwc3-st.txt1 ST DWC3 glue logic
3 This file documents the parameters for the dwc3-st driver.
4 This driver controls the glue logic used to configure the dwc3 core on
8 - compatible : must be "st,stih407-dwc3"
32 The dwc3 core should be added as subnode to ST DWC3 glue as shown in the
33 example below. The DT binding details of dwc3 can be found in:
34 Documentation/devicetree/bindings/usb/dwc3.txt
37 is "otg", which isn't supported by this SoC. Valid dr_mode values for dwc3-st are either "host"
44 st_dwc3: dwc3@8f94000 {
45 compatible = "st,stih407-dwc3";
[all …]
Dqcom,dwc3.yaml4 $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml#
7 title: Qualcomm SuperSpeed DWC3 USB SoC controller
16 - qcom,msm8996-dwc3
17 - qcom,msm8998-dwc3
18 - qcom,sc7180-dwc3
19 - qcom,sdm845-dwc3
20 - const: qcom,dwc3
99 Used when dwc3 operates without SSPHY and only
106 "^dwc3@[0-9a-f]+$":
109 A child node must exist to represent the core DWC3 IP block
[all …]
Drockchip,dwc3.txt1 Rockchip SuperSpeed DWC3 USB SoC controller
4 - compatible: should contain "rockchip,rk3399-dwc3" for rk3399 SoC
15 A child node must exist to represent the core DWC3 IP block. The name of
16 the node is not important. The content of the node is defined in dwc3.txt.
25 compatible = "rockchip,rk3399-dwc3";
33 usbdrd_dwc3_0: dwc3@fe800000 {
34 compatible = "snps,dwc3";
42 compatible = "rockchip,rk3399-dwc3";
50 usbdrd_dwc3_1: dwc3@fe900000 {
51 compatible = "snps,dwc3";
Ddwc3.txt1 synopsys DWC3 CORE
3 DWC3- USB3 CONTROLLER. Complies to the generic USB binding properties
7 - compatible: must be "snps,dwc3"
9 - interrupts: Interrupts used by the dwc3 controller.
19 "qcom,dwc3"
23 "sprd,sc9860-dwc3"
24 "st,stih407-dwc3"
25 "ti,am437x-dwc3"
26 "ti,dwc3"
27 "ti,keystone-dwc3"
[all …]
Dintel,keembay-dwc3.yaml4 $id: http://devicetree.org/schemas/usb/intel,keembay-dwc3.yaml#
7 title: Intel Keem Bay DWC3 USB controller
14 const: intel,keembay-dwc3
37 "^dwc3@[0-9a-f]+$":
40 A child node must exist to represent the core DWC3 IP block.
41 The content of the node is defined in dwc3.txt.
61 compatible = "intel,keembay-dwc3";
71 dwc3@34000000 {
72 compatible = "snps,dwc3";
Domap-usb.txt46 OMAP DWC3 GLUE
48 * "ti,dwc3" for OMAP5 and DRA7
49 * "ti,am437x-dwc3" for AM437x
60 - extcon : phandle for the extcon device omap dwc3 uses to detect
65 The dwc3 core should be added as subnode to omap dwc3 glue.
66 - dwc3 :
67 The binding details of dwc3 can be found in:
68 Documentation/devicetree/bindings/usb/dwc3.txt
71 compatible = "ti,dwc3";
Dexynos-usb.txt68 DWC3
71 "samsung,exynos5250-dwusb3": for USB 3.0 DWC3 controller on
73 "samsung,exynos5433-dwusb3": for USB 3.0 DWC3 controller on
75 "samsung,exynos7-dwusb3": for USB 3.0 DWC3 controller on Exynos7.
93 The dwc3 core should be added as subnode to Exynos dwc3 glue.
94 - dwc3 :
95 The binding details of dwc3 can be found in:
96 Documentation/devicetree/bindings/usb/dwc3.txt
109 dwc3 {
110 compatible = "synopsys,dwc3";
Ddwc3-xilinx.txt1 Xilinx SuperSpeed DWC3 USB SoC controller
4 - compatible: Should contain "xlnx,zynqmp-dwc3"
13 A child node must exist to represent the core DWC3 IP block. The name of
14 the node is not important. The content of the node is defined in dwc3.txt.
21 compatible = "xlnx,zynqmp-dwc3";
26 dwc3@fe200000 {
27 compatible = "snps,dwc3";
Dti,keystone-dwc3.yaml4 $id: http://devicetree.org/schemas/usb/ti,keystone-dwc3.yaml#
16 - ti,keystone-dwc3
17 - ti,am654-dwc3
68 description: This is the node representing the DWC3 controller instance
69 Documentation/devicetree/bindings/usb/dwc3.txt
85 dwc3@2680000 {
86 compatible = "ti,keystone-dwc3";
95 compatible = "synopsys,dwc3";
Ddwc3-cavium.txt1 Cavium SuperSpeed DWC3 USB SoC controller
7 A child node must exist to represent the core DWC3 IP block. The name of
8 the node is not important. The content of the node is defined in dwc3.txt.
23 compatible = "cavium,octeon-7130-xhci", "synopsys,dwc3";
Damlogic,meson-g12a-usb-ctrl.yaml8 title: Amlogic Meson G12A DWC3 USB SoC Controller Glue
14 The Amlogic G12A embeds a DWC3 USB IP Core configured for USB2 and USB3
18 A glue connects the DWC3 core to USB2 PHYs and optionally to an USB3 PHY.
22 The DWC3 Glue controls the PHY routing and power, an interrupt line is
25 The Amlogic A1 embeds a DWC3 USB IP Core configured for USB2 in
226 dwc3: usb@ff500000 {
227 compatible = "snps,dwc3";

12345