1 // SPDX-License-Identifier: GPL-2.0
2 /**
3 * dwc3-pci.c - PCI Specific glue layer
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/slab.h>
14 #include <linux/pci.h>
15 #include <linux/workqueue.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/platform_device.h>
18 #include <linux/gpio/consumer.h>
19 #include <linux/gpio/machine.h>
20 #include <linux/acpi.h>
21 #include <linux/delay.h>
22
23 #define PCI_DEVICE_ID_INTEL_BYT 0x0f37
24 #define PCI_DEVICE_ID_INTEL_MRFLD 0x119e
25 #define PCI_DEVICE_ID_INTEL_BSW 0x22b7
26 #define PCI_DEVICE_ID_INTEL_SPTLP 0x9d30
27 #define PCI_DEVICE_ID_INTEL_SPTH 0xa130
28 #define PCI_DEVICE_ID_INTEL_BXT 0x0aaa
29 #define PCI_DEVICE_ID_INTEL_BXT_M 0x1aaa
30 #define PCI_DEVICE_ID_INTEL_APL 0x5aaa
31 #define PCI_DEVICE_ID_INTEL_KBP 0xa2b0
32 #define PCI_DEVICE_ID_INTEL_CMLLP 0x02ee
33 #define PCI_DEVICE_ID_INTEL_CMLH 0x06ee
34 #define PCI_DEVICE_ID_INTEL_GLK 0x31aa
35 #define PCI_DEVICE_ID_INTEL_CNPLP 0x9dee
36 #define PCI_DEVICE_ID_INTEL_CNPH 0xa36e
37 #define PCI_DEVICE_ID_INTEL_CNPV 0xa3b0
38 #define PCI_DEVICE_ID_INTEL_ICLLP 0x34ee
39 #define PCI_DEVICE_ID_INTEL_EHLLP 0x4b7e
40 #define PCI_DEVICE_ID_INTEL_TGPLP 0xa0ee
41 #define PCI_DEVICE_ID_INTEL_TGPH 0x43ee
42 #define PCI_DEVICE_ID_INTEL_JSP 0x4dee
43 #define PCI_DEVICE_ID_INTEL_ADLS 0x7ae1
44
45 #define PCI_INTEL_BXT_DSM_GUID "732b85d5-b7a7-4a1b-9ba0-4bbd00ffd511"
46 #define PCI_INTEL_BXT_FUNC_PMU_PWR 4
47 #define PCI_INTEL_BXT_STATE_D0 0
48 #define PCI_INTEL_BXT_STATE_D3 3
49
50 #define GP_RWBAR 1
51 #define GP_RWREG1 0xa0
52 #define GP_RWREG1_ULPI_REFCLK_DISABLE (1 << 17)
53
54 /**
55 * struct dwc3_pci - Driver private structure
56 * @dwc3: child dwc3 platform_device
57 * @pci: our link to PCI bus
58 * @guid: _DSM GUID
59 * @has_dsm_for_pm: true for devices which need to run _DSM on runtime PM
60 * @wakeup_work: work for asynchronous resume
61 */
62 struct dwc3_pci {
63 struct platform_device *dwc3;
64 struct pci_dev *pci;
65
66 guid_t guid;
67
68 unsigned int has_dsm_for_pm:1;
69 struct work_struct wakeup_work;
70 };
71
72 static const struct acpi_gpio_params reset_gpios = { 0, 0, false };
73 static const struct acpi_gpio_params cs_gpios = { 1, 0, false };
74
75 static const struct acpi_gpio_mapping acpi_dwc3_byt_gpios[] = {
76 { "reset-gpios", &reset_gpios, 1 },
77 { "cs-gpios", &cs_gpios, 1 },
78 { },
79 };
80
81 static struct gpiod_lookup_table platform_bytcr_gpios = {
82 .dev_id = "0000:00:16.0",
83 .table = {
84 GPIO_LOOKUP("INT33FC:00", 54, "reset", GPIO_ACTIVE_HIGH),
85 GPIO_LOOKUP("INT33FC:02", 14, "cs", GPIO_ACTIVE_HIGH),
86 {}
87 },
88 };
89
dwc3_byt_enable_ulpi_refclock(struct pci_dev * pci)90 static int dwc3_byt_enable_ulpi_refclock(struct pci_dev *pci)
91 {
92 void __iomem *reg;
93 u32 value;
94
95 reg = pcim_iomap(pci, GP_RWBAR, 0);
96 if (!reg)
97 return -ENOMEM;
98
99 value = readl(reg + GP_RWREG1);
100 if (!(value & GP_RWREG1_ULPI_REFCLK_DISABLE))
101 goto unmap; /* ULPI refclk already enabled */
102
103 value &= ~GP_RWREG1_ULPI_REFCLK_DISABLE;
104 writel(value, reg + GP_RWREG1);
105 /* This comes from the Intel Android x86 tree w/o any explanation */
106 msleep(100);
107 unmap:
108 pcim_iounmap(pci, reg);
109 return 0;
110 }
111
112 static const struct property_entry dwc3_pci_intel_properties[] = {
113 PROPERTY_ENTRY_STRING("dr_mode", "peripheral"),
114 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
115 {}
116 };
117
118 static const struct property_entry dwc3_pci_mrfld_properties[] = {
119 PROPERTY_ENTRY_STRING("dr_mode", "otg"),
120 PROPERTY_ENTRY_STRING("linux,extcon-name", "mrfld_bcove_pwrsrc"),
121 PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"),
122 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
123 PROPERTY_ENTRY_BOOL("snps,usb2-gadget-lpm-disable"),
124 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
125 {}
126 };
127
128 static const struct property_entry dwc3_pci_amd_properties[] = {
129 PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"),
130 PROPERTY_ENTRY_U8("snps,lpm-nyet-threshold", 0xf),
131 PROPERTY_ENTRY_BOOL("snps,u2exit_lfps_quirk"),
132 PROPERTY_ENTRY_BOOL("snps,u2ss_inp3_quirk"),
133 PROPERTY_ENTRY_BOOL("snps,req_p1p2p3_quirk"),
134 PROPERTY_ENTRY_BOOL("snps,del_p1p2p3_quirk"),
135 PROPERTY_ENTRY_BOOL("snps,del_phy_power_chg_quirk"),
136 PROPERTY_ENTRY_BOOL("snps,lfps_filter_quirk"),
137 PROPERTY_ENTRY_BOOL("snps,rx_detect_poll_quirk"),
138 PROPERTY_ENTRY_BOOL("snps,tx_de_emphasis_quirk"),
139 PROPERTY_ENTRY_U8("snps,tx_de_emphasis", 1),
140 /* FIXME these quirks should be removed when AMD NL tapes out */
141 PROPERTY_ENTRY_BOOL("snps,disable_scramble_quirk"),
142 PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"),
143 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
144 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
145 {}
146 };
147
dwc3_pci_quirks(struct dwc3_pci * dwc)148 static int dwc3_pci_quirks(struct dwc3_pci *dwc)
149 {
150 struct pci_dev *pdev = dwc->pci;
151
152 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
153 if (pdev->device == PCI_DEVICE_ID_INTEL_BXT ||
154 pdev->device == PCI_DEVICE_ID_INTEL_BXT_M ||
155 pdev->device == PCI_DEVICE_ID_INTEL_EHLLP) {
156 guid_parse(PCI_INTEL_BXT_DSM_GUID, &dwc->guid);
157 dwc->has_dsm_for_pm = true;
158 }
159
160 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) {
161 struct gpio_desc *gpio;
162 int ret;
163
164 /* On BYT the FW does not always enable the refclock */
165 ret = dwc3_byt_enable_ulpi_refclock(pdev);
166 if (ret)
167 return ret;
168
169 ret = devm_acpi_dev_add_driver_gpios(&pdev->dev,
170 acpi_dwc3_byt_gpios);
171 if (ret)
172 dev_dbg(&pdev->dev, "failed to add mapping table\n");
173
174 /*
175 * A lot of BYT devices lack ACPI resource entries for
176 * the GPIOs, add a fallback mapping to the reference
177 * design GPIOs which all boards seem to use.
178 */
179 gpiod_add_lookup_table(&platform_bytcr_gpios);
180
181 /*
182 * These GPIOs will turn on the USB2 PHY. Note that we have to
183 * put the gpio descriptors again here because the phy driver
184 * might want to grab them, too.
185 */
186 gpio = gpiod_get_optional(&pdev->dev, "cs", GPIOD_OUT_LOW);
187 if (IS_ERR(gpio))
188 return PTR_ERR(gpio);
189
190 gpiod_set_value_cansleep(gpio, 1);
191 gpiod_put(gpio);
192
193 gpio = gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_LOW);
194 if (IS_ERR(gpio))
195 return PTR_ERR(gpio);
196
197 if (gpio) {
198 gpiod_set_value_cansleep(gpio, 1);
199 gpiod_put(gpio);
200 usleep_range(10000, 11000);
201 }
202 }
203 }
204
205 return 0;
206 }
207
208 #ifdef CONFIG_PM
dwc3_pci_resume_work(struct work_struct * work)209 static void dwc3_pci_resume_work(struct work_struct *work)
210 {
211 struct dwc3_pci *dwc = container_of(work, struct dwc3_pci, wakeup_work);
212 struct platform_device *dwc3 = dwc->dwc3;
213 int ret;
214
215 ret = pm_runtime_get_sync(&dwc3->dev);
216 if (ret) {
217 pm_runtime_put_sync_autosuspend(&dwc3->dev);
218 return;
219 }
220
221 pm_runtime_mark_last_busy(&dwc3->dev);
222 pm_runtime_put_sync_autosuspend(&dwc3->dev);
223 }
224 #endif
225
dwc3_pci_probe(struct pci_dev * pci,const struct pci_device_id * id)226 static int dwc3_pci_probe(struct pci_dev *pci, const struct pci_device_id *id)
227 {
228 struct property_entry *p = (struct property_entry *)id->driver_data;
229 struct dwc3_pci *dwc;
230 struct resource res[2];
231 int ret;
232 struct device *dev = &pci->dev;
233
234 ret = pcim_enable_device(pci);
235 if (ret) {
236 dev_err(dev, "failed to enable pci device\n");
237 return -ENODEV;
238 }
239
240 pci_set_master(pci);
241
242 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
243 if (!dwc)
244 return -ENOMEM;
245
246 dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO);
247 if (!dwc->dwc3)
248 return -ENOMEM;
249
250 memset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res));
251
252 res[0].start = pci_resource_start(pci, 0);
253 res[0].end = pci_resource_end(pci, 0);
254 res[0].name = "dwc_usb3";
255 res[0].flags = IORESOURCE_MEM;
256
257 res[1].start = pci->irq;
258 res[1].name = "dwc_usb3";
259 res[1].flags = IORESOURCE_IRQ;
260
261 ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res));
262 if (ret) {
263 dev_err(dev, "couldn't add resources to dwc3 device\n");
264 goto err;
265 }
266
267 dwc->pci = pci;
268 dwc->dwc3->dev.parent = dev;
269 ACPI_COMPANION_SET(&dwc->dwc3->dev, ACPI_COMPANION(dev));
270
271 ret = platform_device_add_properties(dwc->dwc3, p);
272 if (ret < 0)
273 goto err;
274
275 ret = dwc3_pci_quirks(dwc);
276 if (ret)
277 goto err;
278
279 ret = platform_device_add(dwc->dwc3);
280 if (ret) {
281 dev_err(dev, "failed to register dwc3 device\n");
282 goto err;
283 }
284
285 device_init_wakeup(dev, true);
286 pci_set_drvdata(pci, dwc);
287 pm_runtime_put(dev);
288 #ifdef CONFIG_PM
289 INIT_WORK(&dwc->wakeup_work, dwc3_pci_resume_work);
290 #endif
291
292 return 0;
293 err:
294 platform_device_put(dwc->dwc3);
295 return ret;
296 }
297
dwc3_pci_remove(struct pci_dev * pci)298 static void dwc3_pci_remove(struct pci_dev *pci)
299 {
300 struct dwc3_pci *dwc = pci_get_drvdata(pci);
301 struct pci_dev *pdev = dwc->pci;
302
303 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT)
304 gpiod_remove_lookup_table(&platform_bytcr_gpios);
305 #ifdef CONFIG_PM
306 cancel_work_sync(&dwc->wakeup_work);
307 #endif
308 device_init_wakeup(&pci->dev, false);
309 pm_runtime_get(&pci->dev);
310 platform_device_unregister(dwc->dwc3);
311 }
312
313 static const struct pci_device_id dwc3_pci_id_table[] = {
314 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BSW),
315 (kernel_ulong_t) &dwc3_pci_intel_properties },
316
317 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BYT),
318 (kernel_ulong_t) &dwc3_pci_intel_properties, },
319
320 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MRFLD),
321 (kernel_ulong_t) &dwc3_pci_mrfld_properties, },
322
323 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLLP),
324 (kernel_ulong_t) &dwc3_pci_intel_properties, },
325
326 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLH),
327 (kernel_ulong_t) &dwc3_pci_intel_properties, },
328
329 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTLP),
330 (kernel_ulong_t) &dwc3_pci_intel_properties, },
331
332 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTH),
333 (kernel_ulong_t) &dwc3_pci_intel_properties, },
334
335 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT),
336 (kernel_ulong_t) &dwc3_pci_intel_properties, },
337
338 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT_M),
339 (kernel_ulong_t) &dwc3_pci_intel_properties, },
340
341 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_APL),
342 (kernel_ulong_t) &dwc3_pci_intel_properties, },
343
344 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_KBP),
345 (kernel_ulong_t) &dwc3_pci_intel_properties, },
346
347 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_GLK),
348 (kernel_ulong_t) &dwc3_pci_intel_properties, },
349
350 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPLP),
351 (kernel_ulong_t) &dwc3_pci_intel_properties, },
352
353 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPH),
354 (kernel_ulong_t) &dwc3_pci_intel_properties, },
355
356 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPV),
357 (kernel_ulong_t) &dwc3_pci_intel_properties, },
358
359 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICLLP),
360 (kernel_ulong_t) &dwc3_pci_intel_properties, },
361
362 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_EHLLP),
363 (kernel_ulong_t) &dwc3_pci_intel_properties, },
364
365 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGPLP),
366 (kernel_ulong_t) &dwc3_pci_intel_properties, },
367
368 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGPH),
369 (kernel_ulong_t) &dwc3_pci_intel_properties, },
370
371 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_JSP),
372 (kernel_ulong_t) &dwc3_pci_intel_properties, },
373
374 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADLS),
375 (kernel_ulong_t) &dwc3_pci_intel_properties, },
376
377 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_NL_USB),
378 (kernel_ulong_t) &dwc3_pci_amd_properties, },
379 { } /* Terminating Entry */
380 };
381 MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table);
382
383 #if defined(CONFIG_PM) || defined(CONFIG_PM_SLEEP)
dwc3_pci_dsm(struct dwc3_pci * dwc,int param)384 static int dwc3_pci_dsm(struct dwc3_pci *dwc, int param)
385 {
386 union acpi_object *obj;
387 union acpi_object tmp;
388 union acpi_object argv4 = ACPI_INIT_DSM_ARGV4(1, &tmp);
389
390 if (!dwc->has_dsm_for_pm)
391 return 0;
392
393 tmp.type = ACPI_TYPE_INTEGER;
394 tmp.integer.value = param;
395
396 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dwc->pci->dev), &dwc->guid,
397 1, PCI_INTEL_BXT_FUNC_PMU_PWR, &argv4);
398 if (!obj) {
399 dev_err(&dwc->pci->dev, "failed to evaluate _DSM\n");
400 return -EIO;
401 }
402
403 ACPI_FREE(obj);
404
405 return 0;
406 }
407 #endif /* CONFIG_PM || CONFIG_PM_SLEEP */
408
409 #ifdef CONFIG_PM
dwc3_pci_runtime_suspend(struct device * dev)410 static int dwc3_pci_runtime_suspend(struct device *dev)
411 {
412 struct dwc3_pci *dwc = dev_get_drvdata(dev);
413
414 if (device_can_wakeup(dev))
415 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);
416
417 return -EBUSY;
418 }
419
dwc3_pci_runtime_resume(struct device * dev)420 static int dwc3_pci_runtime_resume(struct device *dev)
421 {
422 struct dwc3_pci *dwc = dev_get_drvdata(dev);
423 int ret;
424
425 ret = dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
426 if (ret)
427 return ret;
428
429 queue_work(pm_wq, &dwc->wakeup_work);
430
431 return 0;
432 }
433 #endif /* CONFIG_PM */
434
435 #ifdef CONFIG_PM_SLEEP
dwc3_pci_suspend(struct device * dev)436 static int dwc3_pci_suspend(struct device *dev)
437 {
438 struct dwc3_pci *dwc = dev_get_drvdata(dev);
439
440 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);
441 }
442
dwc3_pci_resume(struct device * dev)443 static int dwc3_pci_resume(struct device *dev)
444 {
445 struct dwc3_pci *dwc = dev_get_drvdata(dev);
446
447 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
448 }
449 #endif /* CONFIG_PM_SLEEP */
450
451 static const struct dev_pm_ops dwc3_pci_dev_pm_ops = {
452 SET_SYSTEM_SLEEP_PM_OPS(dwc3_pci_suspend, dwc3_pci_resume)
453 SET_RUNTIME_PM_OPS(dwc3_pci_runtime_suspend, dwc3_pci_runtime_resume,
454 NULL)
455 };
456
457 static struct pci_driver dwc3_pci_driver = {
458 .name = "dwc3-pci",
459 .id_table = dwc3_pci_id_table,
460 .probe = dwc3_pci_probe,
461 .remove = dwc3_pci_remove,
462 .driver = {
463 .pm = &dwc3_pci_dev_pm_ops,
464 }
465 };
466
467 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
468 MODULE_LICENSE("GPL v2");
469 MODULE_DESCRIPTION("DesignWare USB3 PCI Glue Layer");
470
471 module_pci_driver(dwc3_pci_driver);
472