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/kernel/linux/linux-5.10/drivers/tty/serial/
Dzs.h1 /* SPDX-License-Identifier: GPL-2.0 */
29 int tx_stopped; /* Output is suspended. */
38 * Per-SCC state for locking and the interrupt handler.
53 #define ZS_BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
79 #define RES_EXT_INT 0x10 /* Reset Ext. Status Interrupts */
81 #define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */
82 #define RES_Tx_P 0x28 /* Reset TxINT Pending */
83 #define ERR_RES 0x30 /* Error Reset */
84 #define RES_H_IUS 0x38 /* Reset highest IUS */
86 #define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */
[all …]
Dip22zilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
32 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
58 #define RES_EXT_INT 0x10 /* Reset Ext. Status Interrupts */
60 #define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */
61 #define RES_Tx_P 0x28 /* Reset TxINT Pending */
62 #define ERR_RES 0x30 /* Error Reset */
63 #define RES_H_IUS 0x38 /* Reset highest IUS */
65 #define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */
66 #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
67 #define RES_EOM_L 0xC0 /* Reset EOM latch */
[all …]
Dsunzilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
24 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
50 #define RES_EXT_INT 0x10 /* Reset Ext. Status Interrupts */
52 #define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */
53 #define RES_Tx_P 0x28 /* Reset TxINT Pending */
54 #define ERR_RES 0x30 /* Error Reset */
55 #define RES_H_IUS 0x38 /* Reset highest IUS */
57 #define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */
58 #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
59 #define RES_EOM_L 0xC0 /* Reset EOM latch */
[all …]
Dpmac_zilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
25 * of "escc" node (ie. ch-a or ch-b)
74 if (uap->flags & PMACZILOG_FLAG_IS_CHANNEL_A) in pmz_get_port_A()
76 return uap->mate; in pmz_get_port_A()
88 writeb(reg, port->control_reg); in read_zsreg()
89 return readb(port->control_reg); in read_zsreg()
95 writeb(reg, port->control_reg); in write_zsreg()
96 writeb(value, port->control_reg); in write_zsreg()
101 return readb(port->data_reg); in read_zsdata()
106 writeb(data, port->data_reg); in write_zsdata()
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/kernel/linux/linux-5.10/drivers/net/hamradio/
Dz8530.h1 /* SPDX-License-Identifier: GPL-2.0 */
26 #define RES_EXT_INT 0x10 /* Reset Ext. Status Interrupts */
28 #define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */
29 #define RES_Tx_P 0x28 /* Reset TxINT Pending */
30 #define ERR_RES 0x30 /* Error Reset */
31 #define RES_H_IUS 0x38 /* Reset highest IUS */
33 #define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */
34 #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
35 #define RES_EOM_L 0xC0 /* Reset EOM latch */
39 #define EXT_INT_ENAB 0x1 /* Ext Int Enable */
[all …]
/kernel/linux/linux-5.10/drivers/net/wan/
Dz85230.h1 /* SPDX-License-Identifier: GPL-2.0 */
19 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
47 #define RES_EXT_INT 0x10 /* Reset Ext. Status Interrupts */
49 #define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */
50 #define RES_Tx_P 0x28 /* Reset TxINT Pending */
51 #define ERR_RES 0x30 /* Error Reset */
52 #define RES_H_IUS 0x38 /* Reset highest IUS */
54 #define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */
55 #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
56 #define RES_EOM_L 0xC0 /* Reset EOM latch */
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/kernel/linux/linux-5.10/sound/soc/codecs/
Dcpcap.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2017 - 2018 Sebastian Reichel <sre@kernel.org>
8 * Copyright (C) 2007 - 2009 Motorola, Inc.
14 #include <linux/mfd/motorola-cpcap.h>
19 /* Register 513 CPCAP_REG_CC --- CODEC */
37 /* Register 514 CPCAP_REG_CDI --- CODEC Digital Audio Interface */
54 /* Register 515 CPCAP_REG_SDAC --- Stereo DAC */
68 /* Register 516 CPCAP_REG_SDACDI --- Stereo DAC Digital Audio Interface */
84 /* Register 517 CPCAP_REG_TXI --- TX Interface */
102 /* Register 518 CPCAP_REG_TXMP --- Mic Gain */
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/watchdog/
Dfsl-imx-wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/fsl-imx-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Anson Huang <Anson.Huang@nxp.com>
13 - $ref: "watchdog.yaml#"
18 - const: fsl,imx21-wdt
19 - items:
20 - enum:
21 - fsl,imx8mm-wdt
[all …]
/kernel/linux/linux-5.10/sound/hda/ext/
Dhdac_ext_stream.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * hdac-ext-stream.c - HD-audio extended stream operations.
19 * snd_hdac_ext_stream_init - initialize each stream (aka device)
20 * @bus: HD-audio core bus
21 * @stream: HD-audio ext core stream object to initialize
33 if (bus->ppcap) { in snd_hdac_ext_stream_init()
34 stream->pphc_addr = bus->ppcap + AZX_PPHC_BASE + in snd_hdac_ext_stream_init()
37 stream->pplc_addr = bus->ppcap + AZX_PPLC_BASE + in snd_hdac_ext_stream_init()
38 AZX_PPLC_MULTI * bus->num_streams + in snd_hdac_ext_stream_init()
42 if (bus->spbcap) { in snd_hdac_ext_stream_init()
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/sprd/
Dwhale2.dtsi6 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 #include <dt-bindings/clock/sprd,sc9860-clk.h>
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "simple-bus";
18 #address-cells = <2>;
19 #size-cells = <2>;
67 ap-apb {
68 compatible = "simple-bus";
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/kernel/linux/linux-5.10/drivers/staging/comedi/drivers/
Drtd520.c1 // SPDX-License-Identifier: GPL-2.0+
6 * COMEDI - Linux Control and Measurement Device Interface
13 * Devices: [Real Time Devices] DM7520HR-1 (DM7520), DM7520HR-8,
14 * PCI4520 (PCI4520), PCI4520-8
16 * Status: Works. Only tested on DM7520-8. Not SMP safe.
24 * The PCI4520 is a PCI card. The DM7520 is a PC/104-plus card.
30 * 2 bits output
40 * These boards can support external multiplexors and multi-board
71 * Analog-In supports instruction and command mode.
73 * With DMA, you can sample at 1.15Mhz with 70% idle on a 400Mhz K6-2
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/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dimx6ul-kontron-n6x1x-som-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/gpio/gpio.h>
12 stdout-path = &uart4;
17 cs-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
18 pinctrl-names = "default";
19 pinctrl-0 = <&pinctrl_ecspi2>;
22 spi-flash@0 {
23 compatible = "mxicy,mx25v8035f", "jedec,spi-nor";
24 spi-max-frequency = <50000000>;
30 pinctrl-names = "default";
[all …]
Dimx6sx-sdb.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 /dts-v1/;
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
13 compatible = "fsl,imx6sx-sdb", "fsl,imx6sx";
16 stdout-path = &uart1;
24 backlight_display: backlight-display {
25 compatible = "pwm-backlight";
27 brightness-levels = <0 4 8 16 32 64 128 255>;
28 default-brightness-level = <6>;
[all …]
Dimx7-tqma7.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR X11
6 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
13 /* 512 MB - default configuration */
19 cpu-supply = <&sw1a_reg>;
23 pinctrl-names = "default";
24 pinctrl-0 = <&pinctrl_i2c1>;
25 clock-frequency = <100000>;
29 pinctrl-names = "default";
30 pinctrl-0 = <&pinctrl_pmic1>;
36 regulator-min-microvolt = <700000>;
[all …]
Dimx6qdl-sabresd.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/imx6qdl-clock.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
12 stdout-path = &uart1;
20 reg_usb_otg_vbus: regulator-usb-otg-vbus {
21 compatible = "regulator-fixed";
22 regulator-name = "usb_otg_vbus";
23 regulator-min-microvolt = <5000000>;
24 regulator-max-microvolt = <5000000>;
[all …]
Dsun8i-v3s.dtsi4 * This file is dual-licensed: you can use it either under the terms
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/clock/sun8i-v3s-ccu.h>
45 #include <dt-bindings/reset/sun8i-v3s-ccu.h>
46 #include <dt-bindings/clock/sun8i-de2.h>
49 #address-cells = <1>;
50 #size-cells = <1>;
51 interrupt-parent = <&gic>;
54 #address-cells = <1>;
55 #size-cells = <1>;
[all …]
Dimx7d-sdb.dts1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 /dts-v1/;
11 compatible = "fsl,imx7d-sdb", "fsl,imx7d";
14 stdout-path = &uart1;
22 gpio-keys {
23 compatible = "gpio-keys";
24 pinctrl-names = "default";
25 pinctrl-0 = <&pinctrl_gpio_keys>;
27 volume-up {
31 wakeup-source;
[all …]
/kernel/linux/linux-5.10/arch/powerpc/boot/
Dwrapper2 # SPDX-License-Identifier: GPL-2.0-only
7 # and/or a device-tree blob, and creates a bootable zImage for a
11 # -o zImage specify output file
12 # -p platform specify platform (links in $platform.o)
13 # -i initrd specify initrd file
14 # -d devtree specify device-tree blob
15 # -s tree.dts specify device-tree source file (needs dtc installed)
16 # -e esm_blob specify ESM blob for secure images
17 # -c cache $kernel.strip.gz (use if present & newer, else make)
18 # -C prefix specify command prefix for cross-building tools
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/kernel/linux/linux-5.10/drivers/watchdog/
Dimx2_wdt.c1 // SPDX-License-Identifier: GPL-2.0
14 * ---- -----
15 * Registers: 32-bit 16-bit
34 #define DRIVER_NAME "imx2-wdt"
37 #define IMX2_WDT_WCR_WT (0xFF << 8) /* -> Watchdog Timeout Field */
38 #define IMX2_WDT_WCR_WDA BIT(5) /* -> External Reset WDOG_B */
39 #define IMX2_WDT_WCR_SRS BIT(4) /* -> Software Reset Signal */
40 #define IMX2_WDT_WCR_WRE BIT(3) /* -> WDOG Reset Enable */
41 #define IMX2_WDT_WCR_WDE BIT(2) /* -> Watchdog Enable */
42 #define IMX2_WDT_WCR_WDZST BIT(0) /* -> Watchdog timer Suspend */
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/
Dimx8mp-evk.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
12 compatible = "fsl,imx8mp-evk", "fsl,imx8mp";
15 stdout-path = &uart2;
18 gpio-leds {
19 compatible = "gpio-leds";
20 pinctrl-names = "default";
21 pinctrl-0 = <&pinctrl_gpio_led>;
26 default-state = "on";
36 reg_usdhc2_vmmc: regulator-usdhc2 {
[all …]
Dimx8mq-phanbell.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright 2017-2019 NXP
6 /dts-v1/;
9 #include <dt-bindings/interrupt-controller/irq.h>
13 compatible = "google,imx8mq-phanbell", "fsl,imx8mq";
16 stdout-path = &uart1;
24 pmic_osc: clock-pmic {
25 compatible = "fixed-clock";
26 #clock-cells = <0>;
27 clock-frequency = <32768>;
[all …]
Dimx8mq-librem5-devkit.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 Purism SPC
6 /dts-v1/;
8 #include "dt-bindings/input/input.h"
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include "dt-bindings/pwm/pwm.h"
11 #include "dt-bindings/usb/pd.h"
16 compatible = "purism,librem5-devkit", "fsl,imx8mq";
18 backlight_dsi: backlight-dsi {
19 compatible = "pwm-backlight";
[all …]
Dimx8mq-sr-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (C) 2018 Jon Nettleton <jon@solid-run.com>
9 reg_vdd_3v3: regulator-vdd-3v3 {
10 compatible = "regulator-fixed";
11 regulator-always-on;
12 regulator-name = "vdd_3v3";
13 regulator-min-microvolt = <3300000>;
14 regulator-max-microvolt = <3300000>;
19 pinctrl-names = "default";
20 pinctrl-0 = <&pinctrl_fec1>;
[all …]
/kernel/linux/linux-5.10/drivers/hid/
Dhid-wiimote-core.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (c) 2011-2013 David Herrmann <dh.herrmann@gmail.com>
17 #include "hid-ids.h"
18 #include "hid-wiimote.h"
20 /* output queue handling */
28 if (!hdev->ll_driver->output_report) in wiimote_hid_send()
29 return -ENODEV; in wiimote_hid_send()
33 return -ENOMEM; in wiimote_hid_send()
50 spin_lock_irqsave(&wdata->queue.lock, flags); in wiimote_queue_worker()
52 while (wdata->queue.head != wdata->queue.tail) { in wiimote_queue_worker()
[all …]
/kernel/linux/linux-5.10/drivers/counter/
D104-quad-8.c1 // SPDX-License-Identifier: GPL-2.0
3 * Counter driver for the ACCES 104-QUAD-8
6 * This driver supports the ACCES 104-QUAD-8 and ACCES 104-QUAD-4.
27 MODULE_PARM_DESC(base, "ACCES 104-QUAD-8 base addresses");
32 * struct quad8_iio - IIO device private data structure
65 /* Borrow Toggle flip-flop */
67 /* Carry Toggle flip-flop */
73 /* Reset and Load Signal Decoders */
77 /* Input / Output Control Register */
81 /* Reset Byte Pointer (three byte data pointer) */
[all …]

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