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/kernel/linux/linux-5.10/arch/arm64/boot/dts/mediatek/
Dmt6797.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 #include <dt-bindings/clock/mt6797-clk.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/mt6797-pinfunc.h>
14 interrupt-parent = <&sysirq>;
15 #address-cells = <2>;
16 #size-cells = <2>;
19 compatible = "arm,psci-0.2";
24 #address-cells = <1>;
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/i2c/
Dnvidia,tegra186-bpmp-i2c.txt1 NVIDIA Tegra186 BPMP I2C controller
4 devices, such as the I2C controller for the power management I2C bus. Software
6 transactions on that I2C bus. This binding describes an I2C bus that is
9 The BPMP I2C node must be located directly inside the main BPMP node. See
10 ../firmware/nvidia,tegra186-bpmp.txt for details of the BPMP binding.
12 This node represents an I2C controller. See ../i2c/i2c.txt for details of the
13 core I2C binding.
16 - compatible:
19 - "nvidia,tegra186-bpmp-i2c".
20 - #address-cells: Address cells for I2C device address.
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Di2c-rk3x.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-rk3x.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip RK3xxx I2C controller
10 This driver interfaces with the native I2C controller present in Rockchip
14 - $ref: /schemas/i2c/i2c-controller.yaml#
17 - Heiko Stuebner <heiko@sntech.de>
23 - const: rockchip,rv1108-i2c
24 - const: rockchip,rk3066-i2c
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Dst,stm32-i2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/st,stm32-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: I2C controller embedded in STMicroelectronics STM32 I2C platform
10 - Pierre-Yves MORDRET <pierre-yves.mordret@st.com>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
14 - if:
19 - st,stm32f7-i2c
20 - st,stm32mp15-i2c
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Di2c-pxa.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-pxa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell MMP I2C controller bindings
10 - Rob Herring <robh+dt@kernel.org>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
14 - if:
17 - mrvl,i2c-polling
20 - interrupts
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Dcdns,i2c-r1p10.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/i2c/cdns,i2c-r1p10.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Cadence I2C controller Device Tree Bindings
10 - Michal Simek <michal.simek@xilinx.com>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
18 - cdns,i2c-r1p10 # cadence i2c controller version 1.0
19 - cdns,i2c-r1p14 # cadence i2c controller version 1.4
30 clock-frequency:
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Dnuvoton,npcm7xx-i2c.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/i2c/nuvoton,npcm7xx-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: nuvoton NPCM7XX I2C Controller Device Tree Bindings
10 The NPCM750x includes sixteen I2C bus controllers. All Controllers support
11 both master and slave mode. Each controller can switch between master and slave
12 at run time (i.e. IPMB mode). Each controller has two 16 byte HW FIFO for TX and
16 - Tali Perry <tali.perry1@gmail.com>
20 const: nuvoton,npcm7xx-i2c
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Di2c-pxa-pci-ce4100.txt1 CE4100 I2C
2 ----------
4 CE4100 has one PCI device which is described as the I2C-Controller. This
5 PCI device has three PCI-bars, each bar contains a complete I2C
6 controller. So we have a total of three independent I2C-Controllers
8 The driver is probed via the PCI-ID and is gathering the information of
10 Grant Likely recommended to use the ranges property to map the PCI-Bar
12 of the specific I2C controller. This were his exact words:
22 non-zero if you had 2 or more devices mapped off
30 ------------------------------------------------
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Dingenic,i2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/ingenic,i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ingenic SoCs I2C controller devicetree bindings
10 - Paul Cercueil <paul@crapouillou.net>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
17 pattern: "^i2c@[0-9a-f]+$"
21 - enum:
22 - ingenic,jz4770-i2c
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Dsnps,designware-i2c.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/i2c/snps,designware-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare APB I2C Controller
10 - Jarkko Nikula <jarkko.nikula@linux.intel.com>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
14 - if:
19 const: mscc,ocelot-i2c
28 - description: Generic Synopsys DesignWare I2C controller
[all …]
Di2c-imx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-imx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Inter IC (I2C) and High Speed Inter IC (HS-I2C) for i.MX
10 - Wolfram Sang <wolfram@the-dreams.de>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
18 - const: fsl,imx1-i2c
19 - const: fsl,imx21-i2c
20 - const: fsl,vf610-i2c
[all …]
Damlogic,meson6-i2c.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/i2c/amlogic,meson6-i2c.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Amlogic Meson I2C Controller
11 - Neil Armstrong <narmstrong@baylibre.com>
12 - Beniamino Galvani <b.galvani@gmail.com>
15 - $ref: /schemas/i2c/i2c-controller.yaml#
20 - amlogic,meson6-i2c # Meson6, Meson8 and compatible SoCs
21 - amlogic,meson-gxbb-i2c # GXBB and compatible SoCs
[all …]
Dsocionext,uniphier-i2c.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/i2c/socionext,uniphier-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UniPhier I2C controller (FIFO-less)
10 - Masahiro Yamada <yamada.masahiro@socionext.com>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
17 const: socionext,uniphier-i2c
28 clock-frequency:
33 - compatible
[all …]
Dbrcm,brcmstb-i2c.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/i2c/brcm,brcmstb-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom STB BSC IIC Master Controller
10 - Kamal Dasu <kdasu.kdev@gmail.com>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
18 - brcm,bcm2711-hdmi-i2c
19 - brcm,brcmstb-i2c
20 - brcm,brcmper-i2c
[all …]
/kernel/linux/linux-5.10/drivers/i2c/busses/
Di2c-cadence.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * I2C bus driver for the Cadence I2C controller.
5 * Copyright (C) 2009 - 2014 Xilinx, Inc.
10 #include <linux/i2c.h>
18 /* Register offsets for the I2C device. */
21 #define CDNS_I2C_ADDR_OFFSET 0x08 /* I2C Address Register, RW */
22 #define CDNS_I2C_DATA_OFFSET 0x0C /* I2C Data Register, RW */
57 * I2C Address Register Bit mask definitions
59 * bits. A write access to this register always initiates a transfer if the I2C
62 #define CDNS_I2C_ADDR_MASK 0x000003FF /* I2C Address Mask */
[all …]
Di2c-designware-pcidrv.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Synopsys DesignWare I2C adapter driver (master only).
5 * Based on the TI DAVINCI I2C adapter driver.
16 #include <linux/i2c.h>
26 #include "i2c-designware-core.h"
28 #define DRIVER_NAME "i2c-designware-pci"
88 struct dw_i2c_dev *dev = dev_get_drvdata(&pdev->dev); in mfld_setup()
90 switch (pdev->device) { in mfld_setup()
92 dev->timings.bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ; in mfld_setup()
96 c->bus_num = pdev->device - 0x817 + 3; in mfld_setup()
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/fsi/
Dfsi.txt4 The FSI bus is probe-able, so the OS is able to enumerate FSI slaves, and
6 nodes to probed engines. This allows for fsi engines to expose non-probeable
8 that is an I2C master - the I2C bus can be described by the device tree under
13 the fsi-master-* binding specifications.
18 fsi-master {
19 /* top-level of FSI bus topology, bound to an FSI master driver and
22 fsi-slave@<link,id> {
26 fsi-slave-engine@<addr> {
32 fsi-slave-engine@<addr> {
39 Note that since the bus is probe-able, some (or all) of the topology may
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/ti/
Dk3-j7200-main.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "mmio-sram";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 atf-sram@0 {
21 scm_conf: scm-conf@100000 {
22 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
24 #address-cells = <1>;
25 #size-cells = <1>;
[all …]
Dk3-j721e-mcu-wakeup.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "ti,k2g-sci";
11 ti,host-id = <12>;
13 mbox-names = "rx", "tx";
18 reg-names = "debug_messages";
21 k3_pds: power-controller {
22 compatible = "ti,sci-pm-domain";
23 #power-domain-cells = <2>;
27 compatible = "ti,k2g-sci-clk";
[all …]
/kernel/linux/linux-5.10/include/linux/i3c/
Dmaster.h1 /* SPDX-License-Identifier: GPL-2.0 */
14 #include <linux/i2c.h>
31 * struct i3c_i2c_dev_desc - Common part of the I3C/I2C device descriptor
32 * @node: node element used to insert the slot into the I2C or I3C device
35 * I2C/I3C transfers
39 * This structure is describing common I3C/I2C dev information.
54 * struct i2c_dev_boardinfo - I2C device board information
55 * @node: used to insert the boardinfo object in the I2C boardinfo list
56 * @base: regular I2C board information
58 * the I2C device limitations
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/kernel/linux/linux-5.10/Documentation/i2c/busses/
Di2c-i801.rst2 Kernel driver i2c-i801
7 * Intel 82801AA and 82801AB (ICH and ICH0 - part of the
9 * Intel 82801BA (ICH2 - part of the '815E' chipset)
51 On Intel Patsburg and later chipsets, both the normal host SMBus controller
55 - Mark Studebaker <mdsxyz123@yahoo.com>
56 - Jean Delvare <jdelvare@suse.de>
60 -----------------
71 0x08 disable the I2C block read functionality
78 -----------
82 Intel's '810' chipset for Celeron-based PCs, '810E' chipset for
[all …]
/kernel/linux/linux-5.10/drivers/input/touchscreen/
Degalax_ts.c1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for EETI eGalax Multiple Touch Controller
10 /* EETI eGalax serial touch screen controller is a I2C based multiple
11 * touch screen controller, it supports 5 point multiple touch. */
14 - auto idle mode support
18 #include <linux/i2c.h>
30 * Mouse Mode: some panel may configure the controller to mouse mode,
67 struct input_dev *input_dev = ts->input_dev; in egalax_ts_interrupt()
68 struct i2c_client *client = ts->client; in egalax_ts_interrupt()
70 int id, ret, x, y, z; in egalax_ts_interrupt() local
[all …]
/kernel/linux/linux-5.10/drivers/iio/imu/st_lsm6dsx/
Dst_lsm6dsx.h1 /* SPDX-License-Identifier: GPL-2.0-only */
26 #define ST_LSM6DS3TRC_DEV_NAME "lsm6ds3tr-c"
28 #define ST_LSM9DS1_DEV_NAME "lsm9ds1-imu"
136 * struct st_lsm6dsx_fifo_ops - ST IMU FIFO settings
158 * struct st_lsm6dsx_hw_ts_settings - ST IMU hw timer settings
174 * struct st_lsm6dsx_shub_settings - ST IMU hw i2c controller settings
177 * @pullup_en: i2c controller pull-up register info (addr + mask).
186 * @pause: controller pause value.
229 * struct st_lsm6dsx_ext_dev_settings - i2c controller slave settings
230 * @i2c_addr: I2c slave address list.
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dste-u300-syscon-clock.txt1 Clock bindings for ST-Ericsson U300 System Controller Clocks
3 Bindings for the gated system controller clocks:
6 - compatible: must be "stericsson,u300-syscon-clk"
7 - #clock-cells: must be <0>
8 - clock-type: specifies the type of clock:
12 - clock-id: specifies the clock in the type range
15 - clocks: parent clock(s)
19 Type: ID: Clock:
20 -------------------
29 1 1 I2C bus 0 clock
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/soc/qcom/
Dqcom,geni-se.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/soc/qcom/qcom,geni-se.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: GENI Serial Engine QUP Wrapper Controller
10 - Mukesh Savaliya <msavaliy@codeaurora.org>
11 - Akash Asthana <akashast@codeaurora.org>
16 like UART, SPI, I2C, I3C, etc. A single QUP module can provide upto 8 Serial
18 Wrapper controller is modeled as a node with zero or more child nodes each
24 - qcom,geni-se-qup
[all …]

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