1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J7200 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_main { 9 msmc_ram: sram@70000000 { 10 compatible = "mmio-sram"; 11 reg = <0x00 0x70000000 0x00 0x100000>; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 ranges = <0x00 0x00 0x70000000 0x100000>; 15 16 atf-sram@0 { 17 reg = <0x00 0x20000>; 18 }; 19 }; 20 21 scm_conf: scm-conf@100000 { 22 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 23 reg = <0x00 0x00100000 0x00 0x1c000>; 24 #address-cells = <1>; 25 #size-cells = <1>; 26 ranges = <0x00 0x00 0x00100000 0x1c000>; 27 28 serdes_ln_ctrl: mux-controller@4080 { 29 compatible = "mmio-mux"; 30 #mux-control-cells = <1>; 31 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ 32 <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */ 33 }; 34 35 usb_serdes_mux: mux-controller@4000 { 36 compatible = "mmio-mux"; 37 #mux-control-cells = <1>; 38 mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ 39 }; 40 }; 41 42 gic500: interrupt-controller@1800000 { 43 compatible = "arm,gic-v3"; 44 #address-cells = <2>; 45 #size-cells = <2>; 46 ranges; 47 #interrupt-cells = <3>; 48 interrupt-controller; 49 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 50 <0x00 0x01900000 0x00 0x100000>; /* GICR */ 51 52 /* vcpumntirq: virtual CPU interface maintenance interrupt */ 53 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 54 55 gic_its: msi-controller@1820000 { 56 compatible = "arm,gic-v3-its"; 57 reg = <0x00 0x01820000 0x00 0x10000>; 58 socionext,synquacer-pre-its = <0x1000000 0x400000>; 59 msi-controller; 60 #msi-cells = <1>; 61 }; 62 }; 63 64 main_gpio_intr: interrupt-controller0 { 65 compatible = "ti,sci-intr"; 66 ti,intr-trigger-type = <1>; 67 interrupt-controller; 68 interrupt-parent = <&gic500>; 69 #interrupt-cells = <1>; 70 ti,sci = <&dmsc>; 71 ti,sci-dev-id = <131>; 72 ti,interrupt-ranges = <8 392 56>; 73 }; 74 75 main_navss: bus@30000000 { 76 compatible = "simple-mfd"; 77 #address-cells = <2>; 78 #size-cells = <2>; 79 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; 80 ti,sci-dev-id = <199>; 81 dma-coherent; 82 dma-ranges; 83 84 main_navss_intr: interrupt-controller1 { 85 compatible = "ti,sci-intr"; 86 ti,intr-trigger-type = <4>; 87 interrupt-controller; 88 interrupt-parent = <&gic500>; 89 #interrupt-cells = <1>; 90 ti,sci = <&dmsc>; 91 ti,sci-dev-id = <213>; 92 ti,interrupt-ranges = <0 64 64>, 93 <64 448 64>, 94 <128 672 64>; 95 }; 96 97 main_udmass_inta: msi-controller@33d00000 { 98 compatible = "ti,sci-inta"; 99 reg = <0x00 0x33d00000 0x00 0x100000>; 100 interrupt-controller; 101 #interrupt-cells = <0>; 102 interrupt-parent = <&main_navss_intr>; 103 msi-controller; 104 ti,sci = <&dmsc>; 105 ti,sci-dev-id = <209>; 106 ti,interrupt-ranges = <0 0 256>; 107 }; 108 109 secure_proxy_main: mailbox@32c00000 { 110 compatible = "ti,am654-secure-proxy"; 111 #mbox-cells = <1>; 112 reg-names = "target_data", "rt", "scfg"; 113 reg = <0x00 0x32c00000 0x00 0x100000>, 114 <0x00 0x32400000 0x00 0x100000>, 115 <0x00 0x32800000 0x00 0x100000>; 116 interrupt-names = "rx_011"; 117 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 118 }; 119 120 main_ringacc: ringacc@3c000000 { 121 compatible = "ti,am654-navss-ringacc"; 122 reg = <0x00 0x3c000000 0x00 0x400000>, 123 <0x00 0x38000000 0x00 0x400000>, 124 <0x00 0x31120000 0x00 0x100>, 125 <0x00 0x33000000 0x00 0x40000>; 126 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 127 ti,num-rings = <1024>; 128 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 129 ti,sci = <&dmsc>; 130 ti,sci-dev-id = <211>; 131 msi-parent = <&main_udmass_inta>; 132 }; 133 134 main_udmap: dma-controller@31150000 { 135 compatible = "ti,j721e-navss-main-udmap"; 136 reg = <0x00 0x31150000 0x00 0x100>, 137 <0x00 0x34000000 0x00 0x100000>, 138 <0x00 0x35000000 0x00 0x100000>; 139 reg-names = "gcfg", "rchanrt", "tchanrt"; 140 msi-parent = <&main_udmass_inta>; 141 #dma-cells = <1>; 142 143 ti,sci = <&dmsc>; 144 ti,sci-dev-id = <212>; 145 ti,ringacc = <&main_ringacc>; 146 147 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 148 <0x0f>, /* TX_HCHAN */ 149 <0x10>; /* TX_UHCHAN */ 150 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 151 <0x0b>, /* RX_HCHAN */ 152 <0x0c>; /* RX_UHCHAN */ 153 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 154 }; 155 156 cpts@310d0000 { 157 compatible = "ti,j721e-cpts"; 158 reg = <0x00 0x310d0000 0x00 0x400>; 159 reg-names = "cpts"; 160 clocks = <&k3_clks 201 1>; 161 clock-names = "cpts"; 162 interrupts-extended = <&main_navss_intr 391>; 163 interrupt-names = "cpts"; 164 ti,cpts-periodic-outputs = <6>; 165 ti,cpts-ext-ts-inputs = <8>; 166 }; 167 }; 168 169 main_pmx0: pinctrl@11c000 { 170 compatible = "pinctrl-single"; 171 /* Proxy 0 addressing */ 172 reg = <0x00 0x11c000 0x00 0x2b4>; 173 #pinctrl-cells = <1>; 174 pinctrl-single,register-width = <32>; 175 pinctrl-single,function-mask = <0xffffffff>; 176 }; 177 178 main_uart0: serial@2800000 { 179 compatible = "ti,j721e-uart", "ti,am654-uart"; 180 reg = <0x00 0x02800000 0x00 0x100>; 181 reg-shift = <2>; 182 reg-io-width = <4>; 183 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 184 clock-frequency = <48000000>; 185 current-speed = <115200>; 186 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 187 clocks = <&k3_clks 146 2>; 188 clock-names = "fclk"; 189 }; 190 191 main_uart1: serial@2810000 { 192 compatible = "ti,j721e-uart", "ti,am654-uart"; 193 reg = <0x00 0x02810000 0x00 0x100>; 194 reg-shift = <2>; 195 reg-io-width = <4>; 196 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 197 clock-frequency = <48000000>; 198 current-speed = <115200>; 199 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; 200 clocks = <&k3_clks 278 2>; 201 clock-names = "fclk"; 202 }; 203 204 main_uart2: serial@2820000 { 205 compatible = "ti,j721e-uart", "ti,am654-uart"; 206 reg = <0x00 0x02820000 0x00 0x100>; 207 reg-shift = <2>; 208 reg-io-width = <4>; 209 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 210 clock-frequency = <48000000>; 211 current-speed = <115200>; 212 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; 213 clocks = <&k3_clks 279 2>; 214 clock-names = "fclk"; 215 }; 216 217 main_uart3: serial@2830000 { 218 compatible = "ti,j721e-uart", "ti,am654-uart"; 219 reg = <0x00 0x02830000 0x00 0x100>; 220 reg-shift = <2>; 221 reg-io-width = <4>; 222 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 223 clock-frequency = <48000000>; 224 current-speed = <115200>; 225 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; 226 clocks = <&k3_clks 280 2>; 227 clock-names = "fclk"; 228 }; 229 230 main_uart4: serial@2840000 { 231 compatible = "ti,j721e-uart", "ti,am654-uart"; 232 reg = <0x00 0x02840000 0x00 0x100>; 233 reg-shift = <2>; 234 reg-io-width = <4>; 235 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 236 clock-frequency = <48000000>; 237 current-speed = <115200>; 238 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; 239 clocks = <&k3_clks 281 2>; 240 clock-names = "fclk"; 241 }; 242 243 main_uart5: serial@2850000 { 244 compatible = "ti,j721e-uart", "ti,am654-uart"; 245 reg = <0x00 0x02850000 0x00 0x100>; 246 reg-shift = <2>; 247 reg-io-width = <4>; 248 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 249 clock-frequency = <48000000>; 250 current-speed = <115200>; 251 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; 252 clocks = <&k3_clks 282 2>; 253 clock-names = "fclk"; 254 }; 255 256 main_uart6: serial@2860000 { 257 compatible = "ti,j721e-uart", "ti,am654-uart"; 258 reg = <0x00 0x02860000 0x00 0x100>; 259 reg-shift = <2>; 260 reg-io-width = <4>; 261 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 262 clock-frequency = <48000000>; 263 current-speed = <115200>; 264 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; 265 clocks = <&k3_clks 283 2>; 266 clock-names = "fclk"; 267 }; 268 269 main_uart7: serial@2870000 { 270 compatible = "ti,j721e-uart", "ti,am654-uart"; 271 reg = <0x00 0x02870000 0x00 0x100>; 272 reg-shift = <2>; 273 reg-io-width = <4>; 274 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 275 clock-frequency = <48000000>; 276 current-speed = <115200>; 277 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; 278 clocks = <&k3_clks 284 2>; 279 clock-names = "fclk"; 280 }; 281 282 main_uart8: serial@2880000 { 283 compatible = "ti,j721e-uart", "ti,am654-uart"; 284 reg = <0x00 0x02880000 0x00 0x100>; 285 reg-shift = <2>; 286 reg-io-width = <4>; 287 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 288 clock-frequency = <48000000>; 289 current-speed = <115200>; 290 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; 291 clocks = <&k3_clks 285 2>; 292 clock-names = "fclk"; 293 }; 294 295 main_uart9: serial@2890000 { 296 compatible = "ti,j721e-uart", "ti,am654-uart"; 297 reg = <0x00 0x02890000 0x00 0x100>; 298 reg-shift = <2>; 299 reg-io-width = <4>; 300 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 301 clock-frequency = <48000000>; 302 current-speed = <115200>; 303 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; 304 clocks = <&k3_clks 286 2>; 305 clock-names = "fclk"; 306 }; 307 308 main_i2c0: i2c@2000000 { 309 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 310 reg = <0x00 0x2000000 0x00 0x100>; 311 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 312 #address-cells = <1>; 313 #size-cells = <0>; 314 clock-names = "fck"; 315 clocks = <&k3_clks 187 1>; 316 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; 317 }; 318 319 main_i2c1: i2c@2010000 { 320 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 321 reg = <0x00 0x2010000 0x00 0x100>; 322 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 323 #address-cells = <1>; 324 #size-cells = <0>; 325 clock-names = "fck"; 326 clocks = <&k3_clks 188 1>; 327 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; 328 }; 329 330 main_i2c2: i2c@2020000 { 331 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 332 reg = <0x00 0x2020000 0x00 0x100>; 333 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 334 #address-cells = <1>; 335 #size-cells = <0>; 336 clock-names = "fck"; 337 clocks = <&k3_clks 189 1>; 338 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; 339 }; 340 341 main_i2c3: i2c@2030000 { 342 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 343 reg = <0x00 0x2030000 0x00 0x100>; 344 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 345 #address-cells = <1>; 346 #size-cells = <0>; 347 clock-names = "fck"; 348 clocks = <&k3_clks 190 1>; 349 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 350 }; 351 352 main_i2c4: i2c@2040000 { 353 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 354 reg = <0x00 0x2040000 0x00 0x100>; 355 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 356 #address-cells = <1>; 357 #size-cells = <0>; 358 clock-names = "fck"; 359 clocks = <&k3_clks 191 1>; 360 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 361 }; 362 363 main_i2c5: i2c@2050000 { 364 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 365 reg = <0x00 0x2050000 0x00 0x100>; 366 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 367 #address-cells = <1>; 368 #size-cells = <0>; 369 clock-names = "fck"; 370 clocks = <&k3_clks 192 1>; 371 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 372 }; 373 374 main_i2c6: i2c@2060000 { 375 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 376 reg = <0x00 0x2060000 0x00 0x100>; 377 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 378 #address-cells = <1>; 379 #size-cells = <0>; 380 clock-names = "fck"; 381 clocks = <&k3_clks 193 1>; 382 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; 383 }; 384 385 main_sdhci0: mmc@4f80000 { 386 compatible = "ti,j7200-sdhci-8bit", "ti,j721e-sdhci-8bit"; 387 reg = <0x00 0x04f80000 0x00 0x260>, <0x00 0x4f88000 0x00 0x134>; 388 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 389 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; 390 clock-names = "clk_xin", "clk_ahb"; 391 clocks = <&k3_clks 91 3>, <&k3_clks 91 0>; 392 ti,otap-del-sel-legacy = <0x0>; 393 ti,otap-del-sel-mmc-hs = <0x0>; 394 ti,otap-del-sel-ddr52 = <0x6>; 395 ti,otap-del-sel-hs200 = <0x8>; 396 ti,otap-del-sel-hs400 = <0x0>; 397 ti,strobe-sel = <0x77>; 398 ti,trm-icp = <0x8>; 399 bus-width = <8>; 400 mmc-ddr-1_8v; 401 dma-coherent; 402 }; 403 404 main_sdhci1: mmc@4fb0000 { 405 compatible = "ti,j7200-sdhci-4bit", "ti,j721e-sdhci-4bit"; 406 reg = <0x00 0x04fb0000 0x00 0x260>, <0x00 0x4fb8000 0x00 0x134>; 407 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 408 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; 409 clock-names = "clk_xin", "clk_ahb"; 410 clocks = <&k3_clks 92 2>, <&k3_clks 92 1>; 411 ti,otap-del-sel-legacy = <0x0>; 412 ti,otap-del-sel-sd-hs = <0x0>; 413 ti,otap-del-sel-sdr12 = <0xf>; 414 ti,otap-del-sel-sdr25 = <0xf>; 415 ti,otap-del-sel-sdr50 = <0xc>; 416 ti,otap-del-sel-sdr104 = <0x5>; 417 ti,otap-del-sel-ddr50 = <0xc>; 418 no-1-8-v; 419 dma-coherent; 420 }; 421 422 usbss0: cdns-usb@4104000 { 423 compatible = "ti,j721e-usb"; 424 reg = <0x00 0x4104000 0x00 0x100>; 425 dma-coherent; 426 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; 427 clocks = <&k3_clks 288 12>, <&k3_clks 288 3>; 428 clock-names = "ref", "lpm"; 429 assigned-clocks = <&k3_clks 288 12>; /* USB2_REFCLK */ 430 assigned-clock-parents = <&k3_clks 288 13>; /* HFOSC0 */ 431 #address-cells = <2>; 432 #size-cells = <2>; 433 ranges; 434 435 usb0: usb@6000000 { 436 compatible = "cdns,usb3"; 437 reg = <0x00 0x6000000 0x00 0x10000>, 438 <0x00 0x6010000 0x00 0x10000>, 439 <0x00 0x6020000 0x00 0x10000>; 440 reg-names = "otg", "xhci", "dev"; 441 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 442 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 443 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 444 interrupt-names = "host", 445 "peripheral", 446 "otg"; 447 maximum-speed = "super-speed"; 448 dr_mode = "otg"; 449 cdns,phyrst-a-enable; 450 }; 451 }; 452}; 453