1 /* 2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 16 #ifndef __ES8311_CODEC_H__ 17 #define __ES8311_CODEC_H__ 18 19 /* 20 * ES8311_REGISTER NAME_REG_REGISTER ADDRESS 21 */ 22 #define ES8311_RESET_REG00 0x00 /* reset digital,csm,clock manager etc. */ 23 24 /* 25 * Clock Scheme Register definition 26 */ 27 #define ES8311_CLK_MANAGER_REG01 0x01 /* select clk src for mclk, enable clock for codec */ 28 #define ES8311_CLK_MANAGER_REG02 0x02 /* clk divider and clk multiplier */ 29 #define ES8311_CLK_MANAGER_REG03 0x03 /* adc fsmode and osr */ 30 #define ES8311_CLK_MANAGER_REG04 0x04 /* dac osr */ 31 #define ES8311_CLK_MANAGER_REG05 0x05 /* clk divier for adc and dac */ 32 #define ES8311_CLK_MANAGER_REG06 0x06 /* bclk inverter and divider */ 33 #define ES8311_CLK_MANAGER_REG07 0x07 /* tri-state, lrck divider */ 34 #define ES8311_CLK_MANAGER_REG08 0x08 /* lrck divider */ 35 #define ES8311_SDPIN_REG09 0x09 /* dac serial digital port */ 36 #define ES8311_SDPOUT_REG0A 0x0A /* adc serial digital port */ 37 #define ES8311_SYSTEM_REG0B 0x0B /* system */ 38 #define ES8311_SYSTEM_REG0C 0x0C /* system */ 39 #define ES8311_SYSTEM_REG0D 0x0D /* system, power up/down */ 40 #define ES8311_SYSTEM_REG0E 0x0E /* system, power up/down */ 41 #define ES8311_SYSTEM_REG0F 0x0F /* system, low power */ 42 #define ES8311_SYSTEM_REG10 0x10 /* system */ 43 #define ES8311_SYSTEM_REG11 0x11 /* system */ 44 #define ES8311_SYSTEM_REG12 0x12 /* system, Enable DAC */ 45 #define ES8311_SYSTEM_REG13 0x13 /* system */ 46 #define ES8311_SYSTEM_REG14 0x14 /* system, select DMIC, select analog pga gain */ 47 #define ES8311_ADC_REG15 0x15 /* ADC, adc ramp rate, dmic sense */ 48 #define ES8311_ADC_REG16 0x16 /* ADC */ 49 #define ES8311_ADC_REG17 0x17 /* ADC, volume */ 50 #define ES8311_ADC_REG18 0x18 /* ADC, alc enable and winsize */ 51 #define ES8311_ADC_REG19 0x19 /* ADC, alc maxlevel */ 52 #define ES8311_ADC_REG1A 0x1A /* ADC, alc automute */ 53 #define ES8311_ADC_REG1B 0x1B /* ADC, alc automute, adc hpf s1 */ 54 #define ES8311_ADC_REG1C 0x1C /* ADC, equalizer, hpf s2 */ 55 #define ES8311_DAC_REG31 0x31 /* DAC, mute */ 56 #define ES8311_DAC_REG32 0x32 /* DAC, volume */ 57 #define ES8311_DAC_REG33 0x33 /* DAC, offset */ 58 #define ES8311_DAC_REG34 0x34 /* DAC, drc enable, drc winsize */ 59 #define ES8311_DAC_REG35 0x35 /* DAC, drc maxlevel, minilevel */ 60 #define ES8311_DAC_REG37 0x37 /* DAC, ramprate */ 61 #define ES8311_GPIO_REG44 0x44 /* GPIO, dac2adc for test */ 62 #define ES8311_GP_REG45 0x45 /* GP CONTROL */ 63 #define ES8311_CHD1_REGFD 0xFD /* CHIP ID1 */ 64 #define ES8311_CHD2_REGFE 0xFE /* CHIP ID2 */ 65 #define ES8311_CHVER_REGFF 0xFF /* VERSION */ 66 67 #define ES8311_MAX_REGISTER 0xFF 68 69 #define ES8311_PDN_DAC_BIT (1 << 1) 70 71 #define CODEC_DEVICE_ADDR 0x30 /* 0011 00x */ 72 73 typedef enum { 74 HI_CODEC_SAMPLE_RATE_8K = 8, 75 HI_CODEC_SAMPLE_RATE_16K = 16, 76 HI_CODEC_SAMPLE_RATE_32K = 32, 77 HI_CODEC_SAMPLE_RATE_48K = 48, 78 } hi_codec_sample_rate; 79 80 typedef enum { 81 HI_CODEC_RESOLUTION_16BIT = 16, 82 HI_CODEC_RESOLUTION_24BIT = 24, 83 } hi_codec_resolution; 84 85 typedef struct { 86 hi_codec_sample_rate sample_rate; 87 hi_codec_resolution resolution; 88 } hi_codec_attribute; 89 90 hi_u32 hi_codec_init(const hi_codec_attribute *codec_attr); 91 92 #endif 93