1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004-2017 Cavium, Inc.
7 * Copyright (C) 2008 Wind River Systems
8 */
9
10 #include <linux/etherdevice.h>
11 #include <linux/of_platform.h>
12 #include <linux/of_fdt.h>
13 #include <linux/libfdt.h>
14
15 #include <asm/octeon/octeon.h>
16 #include <asm/octeon/cvmx-helper-board.h>
17
18 #ifdef CONFIG_USB
19 #include <linux/usb/ehci_def.h>
20 #include <linux/usb/ehci_pdriver.h>
21 #include <linux/usb/ohci_pdriver.h>
22 #include <asm/octeon/cvmx-uctlx-defs.h>
23
24 #define CVMX_UAHCX_EHCI_USBCMD (CVMX_ADD_IO_SEG(0x00016F0000000010ull))
25 #define CVMX_UAHCX_OHCI_USBCMD (CVMX_ADD_IO_SEG(0x00016F0000000408ull))
26
27 static DEFINE_MUTEX(octeon2_usb_clocks_mutex);
28
29 static int octeon2_usb_clock_start_cnt;
30
octeon2_usb_reset(void)31 static int __init octeon2_usb_reset(void)
32 {
33 union cvmx_uctlx_clk_rst_ctl clk_rst_ctl;
34 u32 ucmd;
35
36 if (!OCTEON_IS_OCTEON2())
37 return 0;
38
39 clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0));
40 if (clk_rst_ctl.s.hrst) {
41 ucmd = cvmx_read64_uint32(CVMX_UAHCX_EHCI_USBCMD);
42 ucmd &= ~CMD_RUN;
43 cvmx_write64_uint32(CVMX_UAHCX_EHCI_USBCMD, ucmd);
44 mdelay(2);
45 ucmd |= CMD_RESET;
46 cvmx_write64_uint32(CVMX_UAHCX_EHCI_USBCMD, ucmd);
47 ucmd = cvmx_read64_uint32(CVMX_UAHCX_OHCI_USBCMD);
48 ucmd |= CMD_RUN;
49 cvmx_write64_uint32(CVMX_UAHCX_OHCI_USBCMD, ucmd);
50 }
51
52 return 0;
53 }
54 arch_initcall(octeon2_usb_reset);
55
octeon2_usb_clocks_start(struct device * dev)56 static void octeon2_usb_clocks_start(struct device *dev)
57 {
58 u64 div;
59 union cvmx_uctlx_if_ena if_ena;
60 union cvmx_uctlx_clk_rst_ctl clk_rst_ctl;
61 union cvmx_uctlx_uphy_portx_ctl_status port_ctl_status;
62 int i;
63 unsigned long io_clk_64_to_ns;
64 u32 clock_rate = 12000000;
65 bool is_crystal_clock = false;
66
67
68 mutex_lock(&octeon2_usb_clocks_mutex);
69
70 octeon2_usb_clock_start_cnt++;
71 if (octeon2_usb_clock_start_cnt != 1)
72 goto exit;
73
74 io_clk_64_to_ns = 64000000000ull / octeon_get_io_clock_rate();
75
76 if (dev->of_node) {
77 struct device_node *uctl_node;
78 const char *clock_type;
79
80 uctl_node = of_get_parent(dev->of_node);
81 if (!uctl_node) {
82 dev_err(dev, "No UCTL device node\n");
83 goto exit;
84 }
85 i = of_property_read_u32(uctl_node,
86 "refclk-frequency", &clock_rate);
87 if (i) {
88 dev_err(dev, "No UCTL \"refclk-frequency\"\n");
89 goto exit;
90 }
91 i = of_property_read_string(uctl_node,
92 "refclk-type", &clock_type);
93
94 if (!i && strcmp("crystal", clock_type) == 0)
95 is_crystal_clock = true;
96 }
97
98 /*
99 * Step 1: Wait for voltages stable. That surely happened
100 * before starting the kernel.
101 *
102 * Step 2: Enable SCLK of UCTL by writing UCTL0_IF_ENA[EN] = 1
103 */
104 if_ena.u64 = 0;
105 if_ena.s.en = 1;
106 cvmx_write_csr(CVMX_UCTLX_IF_ENA(0), if_ena.u64);
107
108 for (i = 0; i <= 1; i++) {
109 port_ctl_status.u64 =
110 cvmx_read_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0));
111 /* Set txvreftune to 15 to obtain compliant 'eye' diagram. */
112 port_ctl_status.s.txvreftune = 15;
113 port_ctl_status.s.txrisetune = 1;
114 port_ctl_status.s.txpreemphasistune = 1;
115 cvmx_write_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0),
116 port_ctl_status.u64);
117 }
118
119 /* Step 3: Configure the reference clock, PHY, and HCLK */
120 clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0));
121
122 /*
123 * If the UCTL looks like it has already been started, skip
124 * the initialization, otherwise bus errors are obtained.
125 */
126 if (clk_rst_ctl.s.hrst)
127 goto end_clock;
128 /* 3a */
129 clk_rst_ctl.s.p_por = 1;
130 clk_rst_ctl.s.hrst = 0;
131 clk_rst_ctl.s.p_prst = 0;
132 clk_rst_ctl.s.h_clkdiv_rst = 0;
133 clk_rst_ctl.s.o_clkdiv_rst = 0;
134 clk_rst_ctl.s.h_clkdiv_en = 0;
135 clk_rst_ctl.s.o_clkdiv_en = 0;
136 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
137
138 /* 3b */
139 clk_rst_ctl.s.p_refclk_sel = is_crystal_clock ? 0 : 1;
140 switch (clock_rate) {
141 default:
142 pr_err("Invalid UCTL clock rate of %u, using 12000000 instead\n",
143 clock_rate);
144 fallthrough;
145 case 12000000:
146 clk_rst_ctl.s.p_refclk_div = 0;
147 break;
148 case 24000000:
149 clk_rst_ctl.s.p_refclk_div = 1;
150 break;
151 case 48000000:
152 clk_rst_ctl.s.p_refclk_div = 2;
153 break;
154 }
155 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
156
157 /* 3c */
158 div = octeon_get_io_clock_rate() / 130000000ull;
159
160 switch (div) {
161 case 0:
162 div = 1;
163 break;
164 case 1:
165 case 2:
166 case 3:
167 case 4:
168 break;
169 case 5:
170 div = 4;
171 break;
172 case 6:
173 case 7:
174 div = 6;
175 break;
176 case 8:
177 case 9:
178 case 10:
179 case 11:
180 div = 8;
181 break;
182 default:
183 div = 12;
184 break;
185 }
186 clk_rst_ctl.s.h_div = div;
187 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
188 /* Read it back, */
189 clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0));
190 clk_rst_ctl.s.h_clkdiv_en = 1;
191 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
192 /* 3d */
193 clk_rst_ctl.s.h_clkdiv_rst = 1;
194 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
195
196 /* 3e: delay 64 io clocks */
197 ndelay(io_clk_64_to_ns);
198
199 /*
200 * Step 4: Program the power-on reset field in the UCTL
201 * clock-reset-control register.
202 */
203 clk_rst_ctl.s.p_por = 0;
204 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
205
206 /* Step 5: Wait 3 ms for the PHY clock to start. */
207 mdelay(3);
208
209 /* Steps 6..9 for ATE only, are skipped. */
210
211 /* Step 10: Configure the OHCI_CLK48 and OHCI_CLK12 clocks. */
212 /* 10a */
213 clk_rst_ctl.s.o_clkdiv_rst = 1;
214 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
215
216 /* 10b */
217 clk_rst_ctl.s.o_clkdiv_en = 1;
218 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
219
220 /* 10c */
221 ndelay(io_clk_64_to_ns);
222
223 /*
224 * Step 11: Program the PHY reset field:
225 * UCTL0_CLK_RST_CTL[P_PRST] = 1
226 */
227 clk_rst_ctl.s.p_prst = 1;
228 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
229
230 /* Step 11b */
231 udelay(1);
232
233 /* Step 11c */
234 clk_rst_ctl.s.p_prst = 0;
235 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
236
237 /* Step 11d */
238 mdelay(1);
239
240 /* Step 11e */
241 clk_rst_ctl.s.p_prst = 1;
242 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
243
244 /* Step 12: Wait 1 uS. */
245 udelay(1);
246
247 /* Step 13: Program the HRESET_N field: UCTL0_CLK_RST_CTL[HRST] = 1 */
248 clk_rst_ctl.s.hrst = 1;
249 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
250
251 end_clock:
252 /* Set uSOF cycle period to 60,000 bits. */
253 cvmx_write_csr(CVMX_UCTLX_EHCI_FLA(0), 0x20ull);
254
255 exit:
256 mutex_unlock(&octeon2_usb_clocks_mutex);
257 }
258
octeon2_usb_clocks_stop(void)259 static void octeon2_usb_clocks_stop(void)
260 {
261 mutex_lock(&octeon2_usb_clocks_mutex);
262 octeon2_usb_clock_start_cnt--;
263 mutex_unlock(&octeon2_usb_clocks_mutex);
264 }
265
octeon_ehci_power_on(struct platform_device * pdev)266 static int octeon_ehci_power_on(struct platform_device *pdev)
267 {
268 octeon2_usb_clocks_start(&pdev->dev);
269 return 0;
270 }
271
octeon_ehci_power_off(struct platform_device * pdev)272 static void octeon_ehci_power_off(struct platform_device *pdev)
273 {
274 octeon2_usb_clocks_stop();
275 }
276
277 static struct usb_ehci_pdata octeon_ehci_pdata = {
278 /* Octeon EHCI matches CPU endianness. */
279 #ifdef __BIG_ENDIAN
280 .big_endian_mmio = 1,
281 #endif
282 /*
283 * We can DMA from anywhere. But the descriptors must be in
284 * the lower 4GB.
285 */
286 .dma_mask_64 = 0,
287 .power_on = octeon_ehci_power_on,
288 .power_off = octeon_ehci_power_off,
289 };
290
octeon_ehci_hw_start(struct device * dev)291 static void __init octeon_ehci_hw_start(struct device *dev)
292 {
293 union cvmx_uctlx_ehci_ctl ehci_ctl;
294
295 octeon2_usb_clocks_start(dev);
296
297 ehci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_EHCI_CTL(0));
298 /* Use 64-bit addressing. */
299 ehci_ctl.s.ehci_64b_addr_en = 1;
300 ehci_ctl.s.l2c_addr_msb = 0;
301 #ifdef __BIG_ENDIAN
302 ehci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */
303 ehci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */
304 #else
305 ehci_ctl.s.l2c_buff_emod = 0; /* not swapped. */
306 ehci_ctl.s.l2c_desc_emod = 0; /* not swapped. */
307 ehci_ctl.s.inv_reg_a2 = 1;
308 #endif
309 cvmx_write_csr(CVMX_UCTLX_EHCI_CTL(0), ehci_ctl.u64);
310
311 octeon2_usb_clocks_stop();
312 }
313
octeon_ehci_device_init(void)314 static int __init octeon_ehci_device_init(void)
315 {
316 struct platform_device *pd;
317 struct device_node *ehci_node;
318 int ret = 0;
319
320 ehci_node = of_find_node_by_name(NULL, "ehci");
321 if (!ehci_node)
322 return 0;
323
324 pd = of_find_device_by_node(ehci_node);
325 of_node_put(ehci_node);
326 if (!pd)
327 return 0;
328
329 pd->dev.platform_data = &octeon_ehci_pdata;
330 octeon_ehci_hw_start(&pd->dev);
331 put_device(&pd->dev);
332
333 return ret;
334 }
335 device_initcall(octeon_ehci_device_init);
336
octeon_ohci_power_on(struct platform_device * pdev)337 static int octeon_ohci_power_on(struct platform_device *pdev)
338 {
339 octeon2_usb_clocks_start(&pdev->dev);
340 return 0;
341 }
342
octeon_ohci_power_off(struct platform_device * pdev)343 static void octeon_ohci_power_off(struct platform_device *pdev)
344 {
345 octeon2_usb_clocks_stop();
346 }
347
348 static struct usb_ohci_pdata octeon_ohci_pdata = {
349 /* Octeon OHCI matches CPU endianness. */
350 #ifdef __BIG_ENDIAN
351 .big_endian_mmio = 1,
352 #endif
353 .power_on = octeon_ohci_power_on,
354 .power_off = octeon_ohci_power_off,
355 };
356
octeon_ohci_hw_start(struct device * dev)357 static void __init octeon_ohci_hw_start(struct device *dev)
358 {
359 union cvmx_uctlx_ohci_ctl ohci_ctl;
360
361 octeon2_usb_clocks_start(dev);
362
363 ohci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_OHCI_CTL(0));
364 ohci_ctl.s.l2c_addr_msb = 0;
365 #ifdef __BIG_ENDIAN
366 ohci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */
367 ohci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */
368 #else
369 ohci_ctl.s.l2c_buff_emod = 0; /* not swapped. */
370 ohci_ctl.s.l2c_desc_emod = 0; /* not swapped. */
371 ohci_ctl.s.inv_reg_a2 = 1;
372 #endif
373 cvmx_write_csr(CVMX_UCTLX_OHCI_CTL(0), ohci_ctl.u64);
374
375 octeon2_usb_clocks_stop();
376 }
377
octeon_ohci_device_init(void)378 static int __init octeon_ohci_device_init(void)
379 {
380 struct platform_device *pd;
381 struct device_node *ohci_node;
382 int ret = 0;
383
384 ohci_node = of_find_node_by_name(NULL, "ohci");
385 if (!ohci_node)
386 return 0;
387
388 pd = of_find_device_by_node(ohci_node);
389 of_node_put(ohci_node);
390 if (!pd)
391 return 0;
392
393 pd->dev.platform_data = &octeon_ohci_pdata;
394 octeon_ohci_hw_start(&pd->dev);
395 put_device(&pd->dev);
396
397 return ret;
398 }
399 device_initcall(octeon_ohci_device_init);
400
401 #endif /* CONFIG_USB */
402
403 /* Octeon Random Number Generator. */
octeon_rng_device_init(void)404 static int __init octeon_rng_device_init(void)
405 {
406 struct platform_device *pd;
407 int ret = 0;
408
409 struct resource rng_resources[] = {
410 {
411 .flags = IORESOURCE_MEM,
412 .start = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS),
413 .end = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS) + 0xf
414 }, {
415 .flags = IORESOURCE_MEM,
416 .start = cvmx_build_io_address(8, 0),
417 .end = cvmx_build_io_address(8, 0) + 0x7
418 }
419 };
420
421 pd = platform_device_alloc("octeon_rng", -1);
422 if (!pd) {
423 ret = -ENOMEM;
424 goto out;
425 }
426
427 ret = platform_device_add_resources(pd, rng_resources,
428 ARRAY_SIZE(rng_resources));
429 if (ret)
430 goto fail;
431
432 ret = platform_device_add(pd);
433 if (ret)
434 goto fail;
435
436 return ret;
437 fail:
438 platform_device_put(pd);
439
440 out:
441 return ret;
442 }
443 device_initcall(octeon_rng_device_init);
444
445 static const struct of_device_id octeon_ids[] __initconst = {
446 { .compatible = "simple-bus", },
447 { .compatible = "cavium,octeon-6335-uctl", },
448 { .compatible = "cavium,octeon-5750-usbn", },
449 { .compatible = "cavium,octeon-3860-bootbus", },
450 { .compatible = "cavium,mdio-mux", },
451 { .compatible = "gpio-leds", },
452 { .compatible = "cavium,octeon-7130-usb-uctl", },
453 {},
454 };
455
octeon_has_88e1145(void)456 static bool __init octeon_has_88e1145(void)
457 {
458 return !OCTEON_IS_MODEL(OCTEON_CN52XX) &&
459 !OCTEON_IS_MODEL(OCTEON_CN6XXX) &&
460 !OCTEON_IS_MODEL(OCTEON_CN56XX);
461 }
462
octeon_has_fixed_link(int ipd_port)463 static bool __init octeon_has_fixed_link(int ipd_port)
464 {
465 switch (cvmx_sysinfo_get()->board_type) {
466 case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
467 case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
468 case CVMX_BOARD_TYPE_CN3020_EVB_HS5:
469 case CVMX_BOARD_TYPE_CUST_NB5:
470 case CVMX_BOARD_TYPE_EBH3100:
471 /* Port 1 on these boards is always gigabit. */
472 return ipd_port == 1;
473 case CVMX_BOARD_TYPE_BBGW_REF:
474 /* Ports 0 and 1 connect to the switch. */
475 return ipd_port == 0 || ipd_port == 1;
476 }
477 return false;
478 }
479
octeon_fdt_set_phy(int eth,int phy_addr)480 static void __init octeon_fdt_set_phy(int eth, int phy_addr)
481 {
482 const __be32 *phy_handle;
483 const __be32 *alt_phy_handle;
484 const __be32 *reg;
485 u32 phandle;
486 int phy;
487 int alt_phy;
488 const char *p;
489 int current_len;
490 char new_name[20];
491
492 phy_handle = fdt_getprop(initial_boot_params, eth, "phy-handle", NULL);
493 if (!phy_handle)
494 return;
495
496 phandle = be32_to_cpup(phy_handle);
497 phy = fdt_node_offset_by_phandle(initial_boot_params, phandle);
498
499 alt_phy_handle = fdt_getprop(initial_boot_params, eth, "cavium,alt-phy-handle", NULL);
500 if (alt_phy_handle) {
501 u32 alt_phandle = be32_to_cpup(alt_phy_handle);
502
503 alt_phy = fdt_node_offset_by_phandle(initial_boot_params, alt_phandle);
504 } else {
505 alt_phy = -1;
506 }
507
508 if (phy_addr < 0 || phy < 0) {
509 /* Delete the PHY things */
510 fdt_nop_property(initial_boot_params, eth, "phy-handle");
511 /* This one may fail */
512 fdt_nop_property(initial_boot_params, eth, "cavium,alt-phy-handle");
513 if (phy >= 0)
514 fdt_nop_node(initial_boot_params, phy);
515 if (alt_phy >= 0)
516 fdt_nop_node(initial_boot_params, alt_phy);
517 return;
518 }
519
520 if (phy_addr >= 256 && alt_phy > 0) {
521 const struct fdt_property *phy_prop;
522 struct fdt_property *alt_prop;
523 fdt32_t phy_handle_name;
524
525 /* Use the alt phy node instead.*/
526 phy_prop = fdt_get_property(initial_boot_params, eth, "phy-handle", NULL);
527 phy_handle_name = phy_prop->nameoff;
528 fdt_nop_node(initial_boot_params, phy);
529 fdt_nop_property(initial_boot_params, eth, "phy-handle");
530 alt_prop = fdt_get_property_w(initial_boot_params, eth, "cavium,alt-phy-handle", NULL);
531 alt_prop->nameoff = phy_handle_name;
532 phy = alt_phy;
533 }
534
535 phy_addr &= 0xff;
536
537 if (octeon_has_88e1145()) {
538 fdt_nop_property(initial_boot_params, phy, "marvell,reg-init");
539 memset(new_name, 0, sizeof(new_name));
540 strcpy(new_name, "marvell,88e1145");
541 p = fdt_getprop(initial_boot_params, phy, "compatible",
542 ¤t_len);
543 if (p && current_len >= strlen(new_name))
544 fdt_setprop_inplace(initial_boot_params, phy,
545 "compatible", new_name, current_len);
546 }
547
548 reg = fdt_getprop(initial_boot_params, phy, "reg", NULL);
549 if (phy_addr == be32_to_cpup(reg))
550 return;
551
552 fdt_setprop_inplace_cell(initial_boot_params, phy, "reg", phy_addr);
553
554 snprintf(new_name, sizeof(new_name), "ethernet-phy@%x", phy_addr);
555
556 p = fdt_get_name(initial_boot_params, phy, ¤t_len);
557 if (p && current_len == strlen(new_name))
558 fdt_set_name(initial_boot_params, phy, new_name);
559 else
560 pr_err("Error: could not rename ethernet phy: <%s>", p);
561 }
562
octeon_fdt_set_mac_addr(int n,u64 * pmac)563 static void __init octeon_fdt_set_mac_addr(int n, u64 *pmac)
564 {
565 const u8 *old_mac;
566 int old_len;
567 u8 new_mac[6];
568 u64 mac = *pmac;
569 int r;
570
571 old_mac = fdt_getprop(initial_boot_params, n, "local-mac-address",
572 &old_len);
573 if (!old_mac || old_len != 6 || is_valid_ether_addr(old_mac))
574 return;
575
576 new_mac[0] = (mac >> 40) & 0xff;
577 new_mac[1] = (mac >> 32) & 0xff;
578 new_mac[2] = (mac >> 24) & 0xff;
579 new_mac[3] = (mac >> 16) & 0xff;
580 new_mac[4] = (mac >> 8) & 0xff;
581 new_mac[5] = mac & 0xff;
582
583 r = fdt_setprop_inplace(initial_boot_params, n, "local-mac-address",
584 new_mac, sizeof(new_mac));
585
586 if (r) {
587 pr_err("Setting \"local-mac-address\" failed %d", r);
588 return;
589 }
590 *pmac = mac + 1;
591 }
592
octeon_fdt_rm_ethernet(int node)593 static void __init octeon_fdt_rm_ethernet(int node)
594 {
595 const __be32 *phy_handle;
596
597 phy_handle = fdt_getprop(initial_boot_params, node, "phy-handle", NULL);
598 if (phy_handle) {
599 u32 ph = be32_to_cpup(phy_handle);
600 int p = fdt_node_offset_by_phandle(initial_boot_params, ph);
601
602 if (p >= 0)
603 fdt_nop_node(initial_boot_params, p);
604 }
605 fdt_nop_node(initial_boot_params, node);
606 }
607
_octeon_rx_tx_delay(int eth,int rx_delay,int tx_delay)608 static void __init _octeon_rx_tx_delay(int eth, int rx_delay, int tx_delay)
609 {
610 fdt_setprop_inplace_cell(initial_boot_params, eth, "rx-delay",
611 rx_delay);
612 fdt_setprop_inplace_cell(initial_boot_params, eth, "tx-delay",
613 tx_delay);
614 }
615
octeon_rx_tx_delay(int eth,int iface,int port)616 static void __init octeon_rx_tx_delay(int eth, int iface, int port)
617 {
618 switch (cvmx_sysinfo_get()->board_type) {
619 case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
620 if (iface == 0) {
621 if (port == 0) {
622 /*
623 * Boards with gigabit WAN ports need a
624 * different setting that is compatible with
625 * 100 Mbit settings
626 */
627 _octeon_rx_tx_delay(eth, 0xc, 0x0c);
628 return;
629 } else if (port == 1) {
630 /* Different config for switch port. */
631 _octeon_rx_tx_delay(eth, 0x0, 0x0);
632 return;
633 }
634 }
635 break;
636 case CVMX_BOARD_TYPE_UBNT_E100:
637 if (iface == 0 && port <= 2) {
638 _octeon_rx_tx_delay(eth, 0x0, 0x10);
639 return;
640 }
641 break;
642 }
643 fdt_nop_property(initial_boot_params, eth, "rx-delay");
644 fdt_nop_property(initial_boot_params, eth, "tx-delay");
645 }
646
octeon_fdt_pip_port(int iface,int i,int p,int max)647 static void __init octeon_fdt_pip_port(int iface, int i, int p, int max)
648 {
649 char name_buffer[20];
650 int eth;
651 int phy_addr;
652 int ipd_port;
653 int fixed_link;
654
655 snprintf(name_buffer, sizeof(name_buffer), "ethernet@%x", p);
656 eth = fdt_subnode_offset(initial_boot_params, iface, name_buffer);
657 if (eth < 0)
658 return;
659 if (p > max) {
660 pr_debug("Deleting port %x:%x\n", i, p);
661 octeon_fdt_rm_ethernet(eth);
662 return;
663 }
664 if (OCTEON_IS_MODEL(OCTEON_CN68XX))
665 ipd_port = (0x100 * i) + (0x10 * p) + 0x800;
666 else
667 ipd_port = 16 * i + p;
668
669 phy_addr = cvmx_helper_board_get_mii_address(ipd_port);
670 octeon_fdt_set_phy(eth, phy_addr);
671
672 fixed_link = fdt_subnode_offset(initial_boot_params, eth, "fixed-link");
673 if (fixed_link < 0)
674 WARN_ON(octeon_has_fixed_link(ipd_port));
675 else if (!octeon_has_fixed_link(ipd_port))
676 fdt_nop_node(initial_boot_params, fixed_link);
677 octeon_rx_tx_delay(eth, i, p);
678 }
679
octeon_fdt_pip_iface(int pip,int idx)680 static void __init octeon_fdt_pip_iface(int pip, int idx)
681 {
682 char name_buffer[20];
683 int iface;
684 int p;
685 int count = 0;
686
687 snprintf(name_buffer, sizeof(name_buffer), "interface@%d", idx);
688 iface = fdt_subnode_offset(initial_boot_params, pip, name_buffer);
689 if (iface < 0)
690 return;
691
692 if (cvmx_helper_interface_enumerate(idx) == 0)
693 count = cvmx_helper_ports_on_interface(idx);
694
695 for (p = 0; p < 16; p++)
696 octeon_fdt_pip_port(iface, idx, p, count - 1);
697 }
698
octeon_fill_mac_addresses(void)699 void __init octeon_fill_mac_addresses(void)
700 {
701 const char *alias_prop;
702 char name_buffer[20];
703 u64 mac_addr_base;
704 int aliases;
705 int pip;
706 int i;
707
708 aliases = fdt_path_offset(initial_boot_params, "/aliases");
709 if (aliases < 0)
710 return;
711
712 mac_addr_base =
713 ((octeon_bootinfo->mac_addr_base[0] & 0xffull)) << 40 |
714 ((octeon_bootinfo->mac_addr_base[1] & 0xffull)) << 32 |
715 ((octeon_bootinfo->mac_addr_base[2] & 0xffull)) << 24 |
716 ((octeon_bootinfo->mac_addr_base[3] & 0xffull)) << 16 |
717 ((octeon_bootinfo->mac_addr_base[4] & 0xffull)) << 8 |
718 (octeon_bootinfo->mac_addr_base[5] & 0xffull);
719
720 for (i = 0; i < 2; i++) {
721 int mgmt;
722
723 snprintf(name_buffer, sizeof(name_buffer), "mix%d", i);
724 alias_prop = fdt_getprop(initial_boot_params, aliases,
725 name_buffer, NULL);
726 if (!alias_prop)
727 continue;
728 mgmt = fdt_path_offset(initial_boot_params, alias_prop);
729 if (mgmt < 0)
730 continue;
731 octeon_fdt_set_mac_addr(mgmt, &mac_addr_base);
732 }
733
734 alias_prop = fdt_getprop(initial_boot_params, aliases, "pip", NULL);
735 if (!alias_prop)
736 return;
737
738 pip = fdt_path_offset(initial_boot_params, alias_prop);
739 if (pip < 0)
740 return;
741
742 for (i = 0; i <= 4; i++) {
743 int iface;
744 int p;
745
746 snprintf(name_buffer, sizeof(name_buffer), "interface@%d", i);
747 iface = fdt_subnode_offset(initial_boot_params, pip,
748 name_buffer);
749 if (iface < 0)
750 continue;
751 for (p = 0; p < 16; p++) {
752 int eth;
753
754 snprintf(name_buffer, sizeof(name_buffer),
755 "ethernet@%x", p);
756 eth = fdt_subnode_offset(initial_boot_params, iface,
757 name_buffer);
758 if (eth < 0)
759 continue;
760 octeon_fdt_set_mac_addr(eth, &mac_addr_base);
761 }
762 }
763 }
764
octeon_prune_device_tree(void)765 int __init octeon_prune_device_tree(void)
766 {
767 int i, max_port, uart_mask;
768 const char *pip_path;
769 const char *alias_prop;
770 char name_buffer[20];
771 int aliases;
772
773 if (fdt_check_header(initial_boot_params))
774 panic("Corrupt Device Tree.");
775
776 WARN(octeon_bootinfo->board_type == CVMX_BOARD_TYPE_CUST_DSR1000N,
777 "Built-in DTB booting is deprecated on %s. Please switch to use appended DTB.",
778 cvmx_board_type_to_string(octeon_bootinfo->board_type));
779
780 aliases = fdt_path_offset(initial_boot_params, "/aliases");
781 if (aliases < 0) {
782 pr_err("Error: No /aliases node in device tree.");
783 return -EINVAL;
784 }
785
786 if (OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))
787 max_port = 2;
788 else if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))
789 max_port = 1;
790 else
791 max_port = 0;
792
793 if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E)
794 max_port = 0;
795
796 for (i = 0; i < 2; i++) {
797 int mgmt;
798
799 snprintf(name_buffer, sizeof(name_buffer),
800 "mix%d", i);
801 alias_prop = fdt_getprop(initial_boot_params, aliases,
802 name_buffer, NULL);
803 if (alias_prop) {
804 mgmt = fdt_path_offset(initial_boot_params, alias_prop);
805 if (mgmt < 0)
806 continue;
807 if (i >= max_port) {
808 pr_debug("Deleting mix%d\n", i);
809 octeon_fdt_rm_ethernet(mgmt);
810 fdt_nop_property(initial_boot_params, aliases,
811 name_buffer);
812 } else {
813 int phy_addr = cvmx_helper_board_get_mii_address(CVMX_HELPER_BOARD_MGMT_IPD_PORT + i);
814
815 octeon_fdt_set_phy(mgmt, phy_addr);
816 }
817 }
818 }
819
820 pip_path = fdt_getprop(initial_boot_params, aliases, "pip", NULL);
821 if (pip_path) {
822 int pip = fdt_path_offset(initial_boot_params, pip_path);
823
824 if (pip >= 0)
825 for (i = 0; i <= 4; i++)
826 octeon_fdt_pip_iface(pip, i);
827 }
828
829 /* I2C */
830 if (OCTEON_IS_MODEL(OCTEON_CN52XX) ||
831 OCTEON_IS_MODEL(OCTEON_CN63XX) ||
832 OCTEON_IS_MODEL(OCTEON_CN68XX) ||
833 OCTEON_IS_MODEL(OCTEON_CN56XX))
834 max_port = 2;
835 else
836 max_port = 1;
837
838 for (i = 0; i < 2; i++) {
839 int i2c;
840
841 snprintf(name_buffer, sizeof(name_buffer),
842 "twsi%d", i);
843 alias_prop = fdt_getprop(initial_boot_params, aliases,
844 name_buffer, NULL);
845
846 if (alias_prop) {
847 i2c = fdt_path_offset(initial_boot_params, alias_prop);
848 if (i2c < 0)
849 continue;
850 if (i >= max_port) {
851 pr_debug("Deleting twsi%d\n", i);
852 fdt_nop_node(initial_boot_params, i2c);
853 fdt_nop_property(initial_boot_params, aliases,
854 name_buffer);
855 }
856 }
857 }
858
859 /* SMI/MDIO */
860 if (OCTEON_IS_MODEL(OCTEON_CN68XX))
861 max_port = 4;
862 else if (OCTEON_IS_MODEL(OCTEON_CN52XX) ||
863 OCTEON_IS_MODEL(OCTEON_CN63XX) ||
864 OCTEON_IS_MODEL(OCTEON_CN56XX))
865 max_port = 2;
866 else
867 max_port = 1;
868
869 for (i = 0; i < 2; i++) {
870 int i2c;
871
872 snprintf(name_buffer, sizeof(name_buffer),
873 "smi%d", i);
874 alias_prop = fdt_getprop(initial_boot_params, aliases,
875 name_buffer, NULL);
876 if (alias_prop) {
877 i2c = fdt_path_offset(initial_boot_params, alias_prop);
878 if (i2c < 0)
879 continue;
880 if (i >= max_port) {
881 pr_debug("Deleting smi%d\n", i);
882 fdt_nop_node(initial_boot_params, i2c);
883 fdt_nop_property(initial_boot_params, aliases,
884 name_buffer);
885 }
886 }
887 }
888
889 /* Serial */
890 uart_mask = 3;
891
892 /* Right now CN52XX is the only chip with a third uart */
893 if (OCTEON_IS_MODEL(OCTEON_CN52XX))
894 uart_mask |= 4; /* uart2 */
895
896 for (i = 0; i < 3; i++) {
897 int uart;
898
899 snprintf(name_buffer, sizeof(name_buffer),
900 "uart%d", i);
901 alias_prop = fdt_getprop(initial_boot_params, aliases,
902 name_buffer, NULL);
903
904 if (alias_prop) {
905 uart = fdt_path_offset(initial_boot_params, alias_prop);
906 if (uart_mask & (1 << i)) {
907 __be32 f;
908
909 f = cpu_to_be32(octeon_get_io_clock_rate());
910 fdt_setprop_inplace(initial_boot_params,
911 uart, "clock-frequency",
912 &f, sizeof(f));
913 continue;
914 }
915 pr_debug("Deleting uart%d\n", i);
916 fdt_nop_node(initial_boot_params, uart);
917 fdt_nop_property(initial_boot_params, aliases,
918 name_buffer);
919 }
920 }
921
922 /* Compact Flash */
923 alias_prop = fdt_getprop(initial_boot_params, aliases,
924 "cf0", NULL);
925 if (alias_prop) {
926 union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
927 unsigned long base_ptr, region_base, region_size;
928 unsigned long region1_base = 0;
929 unsigned long region1_size = 0;
930 int cs, bootbus;
931 bool is_16bit = false;
932 bool is_true_ide = false;
933 __be32 new_reg[6];
934 __be32 *ranges;
935 int len;
936
937 int cf = fdt_path_offset(initial_boot_params, alias_prop);
938
939 base_ptr = 0;
940 if (octeon_bootinfo->major_version == 1
941 && octeon_bootinfo->minor_version >= 1) {
942 if (octeon_bootinfo->compact_flash_common_base_addr)
943 base_ptr = octeon_bootinfo->compact_flash_common_base_addr;
944 } else {
945 base_ptr = 0x1d000800;
946 }
947
948 if (!base_ptr)
949 goto no_cf;
950
951 /* Find CS0 region. */
952 for (cs = 0; cs < 8; cs++) {
953 mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));
954 region_base = mio_boot_reg_cfg.s.base << 16;
955 region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
956 if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
957 && base_ptr < region_base + region_size) {
958 is_16bit = mio_boot_reg_cfg.s.width;
959 break;
960 }
961 }
962 if (cs >= 7) {
963 /* cs and cs + 1 are CS0 and CS1, both must be less than 8. */
964 goto no_cf;
965 }
966
967 if (!(base_ptr & 0xfffful)) {
968 /*
969 * Boot loader signals availability of DMA (true_ide
970 * mode) by setting low order bits of base_ptr to
971 * zero.
972 */
973
974 /* Asume that CS1 immediately follows. */
975 mio_boot_reg_cfg.u64 =
976 cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs + 1));
977 region1_base = mio_boot_reg_cfg.s.base << 16;
978 region1_size = (mio_boot_reg_cfg.s.size + 1) << 16;
979 if (!mio_boot_reg_cfg.s.en)
980 goto no_cf;
981 is_true_ide = true;
982
983 } else {
984 fdt_nop_property(initial_boot_params, cf, "cavium,true-ide");
985 fdt_nop_property(initial_boot_params, cf, "cavium,dma-engine-handle");
986 if (!is_16bit) {
987 __be32 width = cpu_to_be32(8);
988
989 fdt_setprop_inplace(initial_boot_params, cf,
990 "cavium,bus-width", &width, sizeof(width));
991 }
992 }
993 new_reg[0] = cpu_to_be32(cs);
994 new_reg[1] = cpu_to_be32(0);
995 new_reg[2] = cpu_to_be32(0x10000);
996 new_reg[3] = cpu_to_be32(cs + 1);
997 new_reg[4] = cpu_to_be32(0);
998 new_reg[5] = cpu_to_be32(0x10000);
999 fdt_setprop_inplace(initial_boot_params, cf,
1000 "reg", new_reg, sizeof(new_reg));
1001
1002 bootbus = fdt_parent_offset(initial_boot_params, cf);
1003 if (bootbus < 0)
1004 goto no_cf;
1005 ranges = fdt_getprop_w(initial_boot_params, bootbus, "ranges", &len);
1006 if (!ranges || len < (5 * 8 * sizeof(__be32)))
1007 goto no_cf;
1008
1009 ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32);
1010 ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff);
1011 ranges[(cs * 5) + 4] = cpu_to_be32(region_size);
1012 if (is_true_ide) {
1013 cs++;
1014 ranges[(cs * 5) + 2] = cpu_to_be32(region1_base >> 32);
1015 ranges[(cs * 5) + 3] = cpu_to_be32(region1_base & 0xffffffff);
1016 ranges[(cs * 5) + 4] = cpu_to_be32(region1_size);
1017 }
1018 goto end_cf;
1019 no_cf:
1020 fdt_nop_node(initial_boot_params, cf);
1021
1022 end_cf:
1023 ;
1024 }
1025
1026 /* 8 char LED */
1027 alias_prop = fdt_getprop(initial_boot_params, aliases,
1028 "led0", NULL);
1029 if (alias_prop) {
1030 union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
1031 unsigned long base_ptr, region_base, region_size;
1032 int cs, bootbus;
1033 __be32 new_reg[6];
1034 __be32 *ranges;
1035 int len;
1036 int led = fdt_path_offset(initial_boot_params, alias_prop);
1037
1038 base_ptr = octeon_bootinfo->led_display_base_addr;
1039 if (base_ptr == 0)
1040 goto no_led;
1041 /* Find CS0 region. */
1042 for (cs = 0; cs < 8; cs++) {
1043 mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));
1044 region_base = mio_boot_reg_cfg.s.base << 16;
1045 region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
1046 if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
1047 && base_ptr < region_base + region_size)
1048 break;
1049 }
1050
1051 if (cs > 7)
1052 goto no_led;
1053
1054 new_reg[0] = cpu_to_be32(cs);
1055 new_reg[1] = cpu_to_be32(0x20);
1056 new_reg[2] = cpu_to_be32(0x20);
1057 new_reg[3] = cpu_to_be32(cs);
1058 new_reg[4] = cpu_to_be32(0);
1059 new_reg[5] = cpu_to_be32(0x20);
1060 fdt_setprop_inplace(initial_boot_params, led,
1061 "reg", new_reg, sizeof(new_reg));
1062
1063 bootbus = fdt_parent_offset(initial_boot_params, led);
1064 if (bootbus < 0)
1065 goto no_led;
1066 ranges = fdt_getprop_w(initial_boot_params, bootbus, "ranges", &len);
1067 if (!ranges || len < (5 * 8 * sizeof(__be32)))
1068 goto no_led;
1069
1070 ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32);
1071 ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff);
1072 ranges[(cs * 5) + 4] = cpu_to_be32(region_size);
1073 goto end_led;
1074
1075 no_led:
1076 fdt_nop_node(initial_boot_params, led);
1077 end_led:
1078 ;
1079 }
1080
1081 #ifdef CONFIG_USB
1082 /* OHCI/UHCI USB */
1083 alias_prop = fdt_getprop(initial_boot_params, aliases,
1084 "uctl", NULL);
1085 if (alias_prop) {
1086 int uctl = fdt_path_offset(initial_boot_params, alias_prop);
1087
1088 if (uctl >= 0 && (!OCTEON_IS_MODEL(OCTEON_CN6XXX) ||
1089 octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC2E)) {
1090 pr_debug("Deleting uctl\n");
1091 fdt_nop_node(initial_boot_params, uctl);
1092 fdt_nop_property(initial_boot_params, aliases, "uctl");
1093 } else if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E ||
1094 octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC4E) {
1095 /* Missing "refclk-type" defaults to crystal. */
1096 fdt_nop_property(initial_boot_params, uctl, "refclk-type");
1097 }
1098 }
1099
1100 /* DWC2 USB */
1101 alias_prop = fdt_getprop(initial_boot_params, aliases,
1102 "usbn", NULL);
1103 if (alias_prop) {
1104 int usbn = fdt_path_offset(initial_boot_params, alias_prop);
1105
1106 if (usbn >= 0 && (current_cpu_type() == CPU_CAVIUM_OCTEON2 ||
1107 !octeon_has_feature(OCTEON_FEATURE_USB))) {
1108 pr_debug("Deleting usbn\n");
1109 fdt_nop_node(initial_boot_params, usbn);
1110 fdt_nop_property(initial_boot_params, aliases, "usbn");
1111 } else {
1112 __be32 new_f[1];
1113 enum cvmx_helper_board_usb_clock_types c;
1114
1115 c = __cvmx_helper_board_usb_get_clock_type();
1116 switch (c) {
1117 case USB_CLOCK_TYPE_REF_48:
1118 new_f[0] = cpu_to_be32(48000000);
1119 fdt_setprop_inplace(initial_boot_params, usbn,
1120 "refclk-frequency", new_f, sizeof(new_f));
1121 fallthrough;
1122 case USB_CLOCK_TYPE_REF_12:
1123 /* Missing "refclk-type" defaults to external. */
1124 fdt_nop_property(initial_boot_params, usbn, "refclk-type");
1125 break;
1126 default:
1127 break;
1128 }
1129 }
1130 }
1131 #endif
1132
1133 return 0;
1134 }
1135
octeon_publish_devices(void)1136 static int __init octeon_publish_devices(void)
1137 {
1138 return of_platform_populate(NULL, octeon_ids, NULL, NULL);
1139 }
1140 arch_initcall(octeon_publish_devices);
1141