1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Kernel-based Virtual Machine driver for Linux
4 *
5 * This module enables machines with Intel VT-x extensions to run virtual
6 * machines without emulation or binary translation.
7 *
8 * MMU support
9 *
10 * Copyright (C) 2006 Qumranet, Inc.
11 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
12 *
13 * Authors:
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Avi Kivity <avi@qumranet.com>
16 */
17
18 /*
19 * We need the mmu code to access both 32-bit and 64-bit guest ptes,
20 * so the code in this file is compiled twice, once per pte size.
21 */
22
23 #if PTTYPE == 64
24 #define pt_element_t u64
25 #define guest_walker guest_walker64
26 #define FNAME(name) paging##64_##name
27 #define PT_BASE_ADDR_MASK GUEST_PT64_BASE_ADDR_MASK
28 #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
29 #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
30 #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
31 #define PT_LEVEL_BITS PT64_LEVEL_BITS
32 #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT
33 #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT
34 #define PT_HAVE_ACCESSED_DIRTY(mmu) true
35 #ifdef CONFIG_X86_64
36 #define PT_MAX_FULL_LEVELS PT64_ROOT_MAX_LEVEL
37 #define CMPXCHG cmpxchg
38 #else
39 #define CMPXCHG cmpxchg64
40 #define PT_MAX_FULL_LEVELS 2
41 #endif
42 #elif PTTYPE == 32
43 #define pt_element_t u32
44 #define guest_walker guest_walker32
45 #define FNAME(name) paging##32_##name
46 #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
47 #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl)
48 #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl)
49 #define PT_INDEX(addr, level) PT32_INDEX(addr, level)
50 #define PT_LEVEL_BITS PT32_LEVEL_BITS
51 #define PT_MAX_FULL_LEVELS 2
52 #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT
53 #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT
54 #define PT_HAVE_ACCESSED_DIRTY(mmu) true
55 #define CMPXCHG cmpxchg
56 #elif PTTYPE == PTTYPE_EPT
57 #define pt_element_t u64
58 #define guest_walker guest_walkerEPT
59 #define FNAME(name) ept_##name
60 #define PT_BASE_ADDR_MASK GUEST_PT64_BASE_ADDR_MASK
61 #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
62 #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
63 #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
64 #define PT_LEVEL_BITS PT64_LEVEL_BITS
65 #define PT_GUEST_DIRTY_SHIFT 9
66 #define PT_GUEST_ACCESSED_SHIFT 8
67 #define PT_HAVE_ACCESSED_DIRTY(mmu) ((mmu)->ept_ad)
68 #define CMPXCHG cmpxchg64
69 #define PT_MAX_FULL_LEVELS PT64_ROOT_MAX_LEVEL
70 #else
71 #error Invalid PTTYPE value
72 #endif
73
74 #define PT_GUEST_DIRTY_MASK (1 << PT_GUEST_DIRTY_SHIFT)
75 #define PT_GUEST_ACCESSED_MASK (1 << PT_GUEST_ACCESSED_SHIFT)
76
77 #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl)
78 #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PG_LEVEL_4K)
79
80 /*
81 * The guest_walker structure emulates the behavior of the hardware page
82 * table walker.
83 */
84 struct guest_walker {
85 int level;
86 unsigned max_level;
87 gfn_t table_gfn[PT_MAX_FULL_LEVELS];
88 pt_element_t ptes[PT_MAX_FULL_LEVELS];
89 pt_element_t prefetch_ptes[PTE_PREFETCH_NUM];
90 gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
91 pt_element_t __user *ptep_user[PT_MAX_FULL_LEVELS];
92 bool pte_writable[PT_MAX_FULL_LEVELS];
93 unsigned int pt_access[PT_MAX_FULL_LEVELS];
94 unsigned int pte_access;
95 gfn_t gfn;
96 struct x86_exception fault;
97 };
98
gpte_to_gfn_lvl(pt_element_t gpte,int lvl)99 static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl)
100 {
101 return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT;
102 }
103
FNAME(protect_clean_gpte)104 static inline void FNAME(protect_clean_gpte)(struct kvm_mmu *mmu, unsigned *access,
105 unsigned gpte)
106 {
107 unsigned mask;
108
109 /* dirty bit is not supported, so no need to track it */
110 if (!PT_HAVE_ACCESSED_DIRTY(mmu))
111 return;
112
113 BUILD_BUG_ON(PT_WRITABLE_MASK != ACC_WRITE_MASK);
114
115 mask = (unsigned)~ACC_WRITE_MASK;
116 /* Allow write access to dirty gptes */
117 mask |= (gpte >> (PT_GUEST_DIRTY_SHIFT - PT_WRITABLE_SHIFT)) &
118 PT_WRITABLE_MASK;
119 *access &= mask;
120 }
121
FNAME(is_present_gpte)122 static inline int FNAME(is_present_gpte)(unsigned long pte)
123 {
124 #if PTTYPE != PTTYPE_EPT
125 return pte & PT_PRESENT_MASK;
126 #else
127 return pte & 7;
128 #endif
129 }
130
FNAME(is_bad_mt_xwr)131 static bool FNAME(is_bad_mt_xwr)(struct rsvd_bits_validate *rsvd_check, u64 gpte)
132 {
133 #if PTTYPE != PTTYPE_EPT
134 return false;
135 #else
136 return __is_bad_mt_xwr(rsvd_check, gpte);
137 #endif
138 }
139
FNAME(is_rsvd_bits_set)140 static bool FNAME(is_rsvd_bits_set)(struct kvm_mmu *mmu, u64 gpte, int level)
141 {
142 return __is_rsvd_bits_set(&mmu->guest_rsvd_check, gpte, level) ||
143 FNAME(is_bad_mt_xwr)(&mmu->guest_rsvd_check, gpte);
144 }
145
FNAME(cmpxchg_gpte)146 static int FNAME(cmpxchg_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
147 pt_element_t __user *ptep_user, unsigned index,
148 pt_element_t orig_pte, pt_element_t new_pte)
149 {
150 int npages;
151 pt_element_t ret;
152 pt_element_t *table;
153 struct page *page;
154
155 npages = get_user_pages_fast((unsigned long)ptep_user, 1, FOLL_WRITE, &page);
156 if (likely(npages == 1)) {
157 table = kmap_atomic(page);
158 ret = CMPXCHG(&table[index], orig_pte, new_pte);
159 kunmap_atomic(table);
160
161 kvm_release_page_dirty(page);
162 } else {
163 struct vm_area_struct *vma;
164 unsigned long vaddr = (unsigned long)ptep_user & PAGE_MASK;
165 unsigned long pfn;
166 unsigned long paddr;
167
168 mmap_read_lock(current->mm);
169 vma = find_vma_intersection(current->mm, vaddr, vaddr + PAGE_SIZE);
170 if (!vma || !(vma->vm_flags & VM_PFNMAP)) {
171 mmap_read_unlock(current->mm);
172 return -EFAULT;
173 }
174 pfn = ((vaddr - vma->vm_start) >> PAGE_SHIFT) + vma->vm_pgoff;
175 paddr = pfn << PAGE_SHIFT;
176 table = memremap(paddr, PAGE_SIZE, MEMREMAP_WB);
177 if (!table) {
178 mmap_read_unlock(current->mm);
179 return -EFAULT;
180 }
181 ret = CMPXCHG(&table[index], orig_pte, new_pte);
182 memunmap(table);
183 mmap_read_unlock(current->mm);
184 }
185
186 return (ret != orig_pte);
187 }
188
FNAME(prefetch_invalid_gpte)189 static bool FNAME(prefetch_invalid_gpte)(struct kvm_vcpu *vcpu,
190 struct kvm_mmu_page *sp, u64 *spte,
191 u64 gpte)
192 {
193 if (!FNAME(is_present_gpte)(gpte))
194 goto no_present;
195
196 /* if accessed bit is not supported prefetch non accessed gpte */
197 if (PT_HAVE_ACCESSED_DIRTY(vcpu->arch.mmu) &&
198 !(gpte & PT_GUEST_ACCESSED_MASK))
199 goto no_present;
200
201 if (FNAME(is_rsvd_bits_set)(vcpu->arch.mmu, gpte, PG_LEVEL_4K))
202 goto no_present;
203
204 return false;
205
206 no_present:
207 drop_spte(vcpu->kvm, spte);
208 return true;
209 }
210
211 /*
212 * For PTTYPE_EPT, a page table can be executable but not readable
213 * on supported processors. Therefore, set_spte does not automatically
214 * set bit 0 if execute only is supported. Here, we repurpose ACC_USER_MASK
215 * to signify readability since it isn't used in the EPT case
216 */
FNAME(gpte_access)217 static inline unsigned FNAME(gpte_access)(u64 gpte)
218 {
219 unsigned access;
220 #if PTTYPE == PTTYPE_EPT
221 access = ((gpte & VMX_EPT_WRITABLE_MASK) ? ACC_WRITE_MASK : 0) |
222 ((gpte & VMX_EPT_EXECUTABLE_MASK) ? ACC_EXEC_MASK : 0) |
223 ((gpte & VMX_EPT_READABLE_MASK) ? ACC_USER_MASK : 0);
224 #else
225 BUILD_BUG_ON(ACC_EXEC_MASK != PT_PRESENT_MASK);
226 BUILD_BUG_ON(ACC_EXEC_MASK != 1);
227 access = gpte & (PT_WRITABLE_MASK | PT_USER_MASK | PT_PRESENT_MASK);
228 /* Combine NX with P (which is set here) to get ACC_EXEC_MASK. */
229 access ^= (gpte >> PT64_NX_SHIFT);
230 #endif
231
232 return access;
233 }
234
FNAME(update_accessed_dirty_bits)235 static int FNAME(update_accessed_dirty_bits)(struct kvm_vcpu *vcpu,
236 struct kvm_mmu *mmu,
237 struct guest_walker *walker,
238 gpa_t addr, int write_fault)
239 {
240 unsigned level, index;
241 pt_element_t pte, orig_pte;
242 pt_element_t __user *ptep_user;
243 gfn_t table_gfn;
244 int ret;
245
246 /* dirty/accessed bits are not supported, so no need to update them */
247 if (!PT_HAVE_ACCESSED_DIRTY(mmu))
248 return 0;
249
250 for (level = walker->max_level; level >= walker->level; --level) {
251 pte = orig_pte = walker->ptes[level - 1];
252 table_gfn = walker->table_gfn[level - 1];
253 ptep_user = walker->ptep_user[level - 1];
254 index = offset_in_page(ptep_user) / sizeof(pt_element_t);
255 if (!(pte & PT_GUEST_ACCESSED_MASK)) {
256 trace_kvm_mmu_set_accessed_bit(table_gfn, index, sizeof(pte));
257 pte |= PT_GUEST_ACCESSED_MASK;
258 }
259 if (level == walker->level && write_fault &&
260 !(pte & PT_GUEST_DIRTY_MASK)) {
261 trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte));
262 #if PTTYPE == PTTYPE_EPT
263 if (kvm_x86_ops.nested_ops->write_log_dirty(vcpu, addr))
264 return -EINVAL;
265 #endif
266 pte |= PT_GUEST_DIRTY_MASK;
267 }
268 if (pte == orig_pte)
269 continue;
270
271 /*
272 * If the slot is read-only, simply do not process the accessed
273 * and dirty bits. This is the correct thing to do if the slot
274 * is ROM, and page tables in read-as-ROM/write-as-MMIO slots
275 * are only supported if the accessed and dirty bits are already
276 * set in the ROM (so that MMIO writes are never needed).
277 *
278 * Note that NPT does not allow this at all and faults, since
279 * it always wants nested page table entries for the guest
280 * page tables to be writable. And EPT works but will simply
281 * overwrite the read-only memory to set the accessed and dirty
282 * bits.
283 */
284 if (unlikely(!walker->pte_writable[level - 1]))
285 continue;
286
287 ret = FNAME(cmpxchg_gpte)(vcpu, mmu, ptep_user, index, orig_pte, pte);
288 if (ret)
289 return ret;
290
291 kvm_vcpu_mark_page_dirty(vcpu, table_gfn);
292 walker->ptes[level - 1] = pte;
293 }
294 return 0;
295 }
296
FNAME(gpte_pkeys)297 static inline unsigned FNAME(gpte_pkeys)(struct kvm_vcpu *vcpu, u64 gpte)
298 {
299 unsigned pkeys = 0;
300 #if PTTYPE == 64
301 pte_t pte = {.pte = gpte};
302
303 pkeys = pte_flags_pkey(pte_flags(pte));
304 #endif
305 return pkeys;
306 }
307
308 /*
309 * Fetch a guest pte for a guest virtual address, or for an L2's GPA.
310 */
FNAME(walk_addr_generic)311 static int FNAME(walk_addr_generic)(struct guest_walker *walker,
312 struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
313 gpa_t addr, u32 access)
314 {
315 int ret;
316 pt_element_t pte;
317 pt_element_t __user *ptep_user;
318 gfn_t table_gfn;
319 u64 pt_access, pte_access;
320 unsigned index, accessed_dirty, pte_pkey;
321 unsigned nested_access;
322 gpa_t pte_gpa;
323 bool have_ad;
324 int offset;
325 u64 walk_nx_mask = 0;
326 const int write_fault = access & PFERR_WRITE_MASK;
327 const int user_fault = access & PFERR_USER_MASK;
328 const int fetch_fault = access & PFERR_FETCH_MASK;
329 u16 errcode = 0;
330 gpa_t real_gpa;
331 gfn_t gfn;
332
333 trace_kvm_mmu_pagetable_walk(addr, access);
334 retry_walk:
335 walker->level = mmu->root_level;
336 pte = mmu->get_guest_pgd(vcpu);
337 have_ad = PT_HAVE_ACCESSED_DIRTY(mmu);
338
339 #if PTTYPE == 64
340 walk_nx_mask = 1ULL << PT64_NX_SHIFT;
341 if (walker->level == PT32E_ROOT_LEVEL) {
342 pte = mmu->get_pdptr(vcpu, (addr >> 30) & 3);
343 trace_kvm_mmu_paging_element(pte, walker->level);
344 if (!FNAME(is_present_gpte)(pte))
345 goto error;
346 --walker->level;
347 }
348 #endif
349 walker->max_level = walker->level;
350 ASSERT(!(is_long_mode(vcpu) && !is_pae(vcpu)));
351
352 /*
353 * FIXME: on Intel processors, loads of the PDPTE registers for PAE paging
354 * by the MOV to CR instruction are treated as reads and do not cause the
355 * processor to set the dirty flag in any EPT paging-structure entry.
356 */
357 nested_access = (have_ad ? PFERR_WRITE_MASK : 0) | PFERR_USER_MASK;
358
359 pte_access = ~0;
360 ++walker->level;
361
362 do {
363 unsigned long host_addr;
364
365 pt_access = pte_access;
366 --walker->level;
367
368 index = PT_INDEX(addr, walker->level);
369 table_gfn = gpte_to_gfn(pte);
370 offset = index * sizeof(pt_element_t);
371 pte_gpa = gfn_to_gpa(table_gfn) + offset;
372
373 BUG_ON(walker->level < 1);
374 walker->table_gfn[walker->level - 1] = table_gfn;
375 walker->pte_gpa[walker->level - 1] = pte_gpa;
376
377 real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(table_gfn),
378 nested_access,
379 &walker->fault);
380
381 /*
382 * FIXME: This can happen if emulation (for of an INS/OUTS
383 * instruction) triggers a nested page fault. The exit
384 * qualification / exit info field will incorrectly have
385 * "guest page access" as the nested page fault's cause,
386 * instead of "guest page structure access". To fix this,
387 * the x86_exception struct should be augmented with enough
388 * information to fix the exit_qualification or exit_info_1
389 * fields.
390 */
391 if (unlikely(real_gpa == UNMAPPED_GVA))
392 return 0;
393
394 host_addr = kvm_vcpu_gfn_to_hva_prot(vcpu, gpa_to_gfn(real_gpa),
395 &walker->pte_writable[walker->level - 1]);
396 if (unlikely(kvm_is_error_hva(host_addr)))
397 goto error;
398
399 ptep_user = (pt_element_t __user *)((void *)host_addr + offset);
400 if (unlikely(__get_user(pte, ptep_user)))
401 goto error;
402 walker->ptep_user[walker->level - 1] = ptep_user;
403
404 trace_kvm_mmu_paging_element(pte, walker->level);
405
406 /*
407 * Inverting the NX it lets us AND it like other
408 * permission bits.
409 */
410 pte_access = pt_access & (pte ^ walk_nx_mask);
411
412 if (unlikely(!FNAME(is_present_gpte)(pte)))
413 goto error;
414
415 if (unlikely(FNAME(is_rsvd_bits_set)(mmu, pte, walker->level))) {
416 errcode = PFERR_RSVD_MASK | PFERR_PRESENT_MASK;
417 goto error;
418 }
419
420 walker->ptes[walker->level - 1] = pte;
421
422 /* Convert to ACC_*_MASK flags for struct guest_walker. */
423 walker->pt_access[walker->level - 1] = FNAME(gpte_access)(pt_access ^ walk_nx_mask);
424 } while (!is_last_gpte(mmu, walker->level, pte));
425
426 pte_pkey = FNAME(gpte_pkeys)(vcpu, pte);
427 accessed_dirty = have_ad ? pte_access & PT_GUEST_ACCESSED_MASK : 0;
428
429 /* Convert to ACC_*_MASK flags for struct guest_walker. */
430 walker->pte_access = FNAME(gpte_access)(pte_access ^ walk_nx_mask);
431 errcode = permission_fault(vcpu, mmu, walker->pte_access, pte_pkey, access);
432 if (unlikely(errcode))
433 goto error;
434
435 gfn = gpte_to_gfn_lvl(pte, walker->level);
436 gfn += (addr & PT_LVL_OFFSET_MASK(walker->level)) >> PAGE_SHIFT;
437
438 if (PTTYPE == 32 && walker->level > PG_LEVEL_4K && is_cpuid_PSE36())
439 gfn += pse36_gfn_delta(pte);
440
441 real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(gfn), access, &walker->fault);
442 if (real_gpa == UNMAPPED_GVA)
443 return 0;
444
445 walker->gfn = real_gpa >> PAGE_SHIFT;
446
447 if (!write_fault)
448 FNAME(protect_clean_gpte)(mmu, &walker->pte_access, pte);
449 else
450 /*
451 * On a write fault, fold the dirty bit into accessed_dirty.
452 * For modes without A/D bits support accessed_dirty will be
453 * always clear.
454 */
455 accessed_dirty &= pte >>
456 (PT_GUEST_DIRTY_SHIFT - PT_GUEST_ACCESSED_SHIFT);
457
458 if (unlikely(!accessed_dirty)) {
459 ret = FNAME(update_accessed_dirty_bits)(vcpu, mmu, walker,
460 addr, write_fault);
461 if (unlikely(ret < 0))
462 goto error;
463 else if (ret)
464 goto retry_walk;
465 }
466
467 pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
468 __func__, (u64)pte, walker->pte_access,
469 walker->pt_access[walker->level - 1]);
470 return 1;
471
472 error:
473 errcode |= write_fault | user_fault;
474 if (fetch_fault && (mmu->nx || mmu->mmu_role.ext.cr4_smep))
475 errcode |= PFERR_FETCH_MASK;
476
477 walker->fault.vector = PF_VECTOR;
478 walker->fault.error_code_valid = true;
479 walker->fault.error_code = errcode;
480
481 #if PTTYPE == PTTYPE_EPT
482 /*
483 * Use PFERR_RSVD_MASK in error_code to to tell if EPT
484 * misconfiguration requires to be injected. The detection is
485 * done by is_rsvd_bits_set() above.
486 *
487 * We set up the value of exit_qualification to inject:
488 * [2:0] - Derive from the access bits. The exit_qualification might be
489 * out of date if it is serving an EPT misconfiguration.
490 * [5:3] - Calculated by the page walk of the guest EPT page tables
491 * [7:8] - Derived from [7:8] of real exit_qualification
492 *
493 * The other bits are set to 0.
494 */
495 if (!(errcode & PFERR_RSVD_MASK)) {
496 vcpu->arch.exit_qualification &= 0x180;
497 if (write_fault)
498 vcpu->arch.exit_qualification |= EPT_VIOLATION_ACC_WRITE;
499 if (user_fault)
500 vcpu->arch.exit_qualification |= EPT_VIOLATION_ACC_READ;
501 if (fetch_fault)
502 vcpu->arch.exit_qualification |= EPT_VIOLATION_ACC_INSTR;
503 vcpu->arch.exit_qualification |= (pte_access & 0x7) << 3;
504 }
505 #endif
506 walker->fault.address = addr;
507 walker->fault.nested_page_fault = mmu != vcpu->arch.walk_mmu;
508
509 trace_kvm_mmu_walker_error(walker->fault.error_code);
510 return 0;
511 }
512
FNAME(walk_addr)513 static int FNAME(walk_addr)(struct guest_walker *walker,
514 struct kvm_vcpu *vcpu, gpa_t addr, u32 access)
515 {
516 return FNAME(walk_addr_generic)(walker, vcpu, vcpu->arch.mmu, addr,
517 access);
518 }
519
520 #if PTTYPE != PTTYPE_EPT
FNAME(walk_addr_nested)521 static int FNAME(walk_addr_nested)(struct guest_walker *walker,
522 struct kvm_vcpu *vcpu, gva_t addr,
523 u32 access)
524 {
525 return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.nested_mmu,
526 addr, access);
527 }
528 #endif
529
530 static bool
FNAME(prefetch_gpte)531 FNAME(prefetch_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
532 u64 *spte, pt_element_t gpte, bool no_dirty_log)
533 {
534 unsigned pte_access;
535 gfn_t gfn;
536 kvm_pfn_t pfn;
537
538 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte))
539 return false;
540
541 pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte);
542
543 gfn = gpte_to_gfn(gpte);
544 pte_access = sp->role.access & FNAME(gpte_access)(gpte);
545 FNAME(protect_clean_gpte)(vcpu->arch.mmu, &pte_access, gpte);
546 pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn,
547 no_dirty_log && (pte_access & ACC_WRITE_MASK));
548 if (is_error_pfn(pfn))
549 return false;
550
551 /*
552 * we call mmu_set_spte() with host_writable = true because
553 * pte_prefetch_gfn_to_pfn always gets a writable pfn.
554 */
555 mmu_set_spte(vcpu, spte, pte_access, false, PG_LEVEL_4K, gfn, pfn,
556 true, true);
557
558 kvm_release_pfn_clean(pfn);
559 return true;
560 }
561
FNAME(update_pte)562 static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
563 u64 *spte, const void *pte)
564 {
565 pt_element_t gpte = *(const pt_element_t *)pte;
566
567 FNAME(prefetch_gpte)(vcpu, sp, spte, gpte, false);
568 }
569
FNAME(gpte_changed)570 static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu,
571 struct guest_walker *gw, int level)
572 {
573 pt_element_t curr_pte;
574 gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1];
575 u64 mask;
576 int r, index;
577
578 if (level == PG_LEVEL_4K) {
579 mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1;
580 base_gpa = pte_gpa & ~mask;
581 index = (pte_gpa - base_gpa) / sizeof(pt_element_t);
582
583 r = kvm_vcpu_read_guest_atomic(vcpu, base_gpa,
584 gw->prefetch_ptes, sizeof(gw->prefetch_ptes));
585 curr_pte = gw->prefetch_ptes[index];
586 } else
587 r = kvm_vcpu_read_guest_atomic(vcpu, pte_gpa,
588 &curr_pte, sizeof(curr_pte));
589
590 return r || curr_pte != gw->ptes[level - 1];
591 }
592
FNAME(pte_prefetch)593 static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw,
594 u64 *sptep)
595 {
596 struct kvm_mmu_page *sp;
597 pt_element_t *gptep = gw->prefetch_ptes;
598 u64 *spte;
599 int i;
600
601 sp = sptep_to_sp(sptep);
602
603 if (sp->role.level > PG_LEVEL_4K)
604 return;
605
606 if (sp->role.direct)
607 return __direct_pte_prefetch(vcpu, sp, sptep);
608
609 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
610 spte = sp->spt + i;
611
612 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
613 if (spte == sptep)
614 continue;
615
616 if (is_shadow_present_pte(*spte))
617 continue;
618
619 if (!FNAME(prefetch_gpte)(vcpu, sp, spte, gptep[i], true))
620 break;
621 }
622 }
623
624 /*
625 * Fetch a shadow pte for a specific level in the paging hierarchy.
626 * If the guest tries to write a write-protected page, we need to
627 * emulate this operation, return 1 to indicate this case.
628 */
FNAME(fetch)629 static int FNAME(fetch)(struct kvm_vcpu *vcpu, gpa_t addr,
630 struct guest_walker *gw, u32 error_code,
631 int max_level, kvm_pfn_t pfn, bool map_writable,
632 bool prefault)
633 {
634 bool nx_huge_page_workaround_enabled = is_nx_huge_page_enabled();
635 bool write_fault = error_code & PFERR_WRITE_MASK;
636 bool exec = error_code & PFERR_FETCH_MASK;
637 bool huge_page_disallowed = exec && nx_huge_page_workaround_enabled;
638 struct kvm_mmu_page *sp = NULL;
639 struct kvm_shadow_walk_iterator it;
640 unsigned int direct_access, access;
641 int top_level, level, req_level, ret;
642 gfn_t base_gfn = gw->gfn;
643
644 direct_access = gw->pte_access;
645
646 top_level = vcpu->arch.mmu->root_level;
647 if (top_level == PT32E_ROOT_LEVEL)
648 top_level = PT32_ROOT_LEVEL;
649 /*
650 * Verify that the top-level gpte is still there. Since the page
651 * is a root page, it is either write protected (and cannot be
652 * changed from now on) or it is invalid (in which case, we don't
653 * really care if it changes underneath us after this point).
654 */
655 if (FNAME(gpte_changed)(vcpu, gw, top_level))
656 goto out_gpte_changed;
657
658 if (WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa)))
659 goto out_gpte_changed;
660
661 for (shadow_walk_init(&it, vcpu, addr);
662 shadow_walk_okay(&it) && it.level > gw->level;
663 shadow_walk_next(&it)) {
664 gfn_t table_gfn;
665
666 clear_sp_write_flooding_count(it.sptep);
667 drop_large_spte(vcpu, it.sptep);
668
669 sp = NULL;
670 if (!is_shadow_present_pte(*it.sptep)) {
671 table_gfn = gw->table_gfn[it.level - 2];
672 access = gw->pt_access[it.level - 2];
673 sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1,
674 false, access);
675 }
676
677 /*
678 * Verify that the gpte in the page we've just write
679 * protected is still there.
680 */
681 if (FNAME(gpte_changed)(vcpu, gw, it.level - 1))
682 goto out_gpte_changed;
683
684 if (sp)
685 link_shadow_page(vcpu, it.sptep, sp);
686 }
687
688 level = kvm_mmu_hugepage_adjust(vcpu, gw->gfn, max_level, &pfn,
689 huge_page_disallowed, &req_level);
690
691 trace_kvm_mmu_spte_requested(addr, gw->level, pfn);
692
693 for (; shadow_walk_okay(&it); shadow_walk_next(&it)) {
694 clear_sp_write_flooding_count(it.sptep);
695
696 /*
697 * We cannot overwrite existing page tables with an NX
698 * large page, as the leaf could be executable.
699 */
700 if (nx_huge_page_workaround_enabled)
701 disallowed_hugepage_adjust(*it.sptep, gw->gfn, it.level,
702 &pfn, &level);
703
704 base_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1);
705 if (it.level == level)
706 break;
707
708 validate_direct_spte(vcpu, it.sptep, direct_access);
709
710 drop_large_spte(vcpu, it.sptep);
711
712 if (!is_shadow_present_pte(*it.sptep)) {
713 sp = kvm_mmu_get_page(vcpu, base_gfn, addr,
714 it.level - 1, true, direct_access);
715 link_shadow_page(vcpu, it.sptep, sp);
716 if (huge_page_disallowed && req_level >= it.level)
717 account_huge_nx_page(vcpu->kvm, sp);
718 }
719 }
720
721 ret = mmu_set_spte(vcpu, it.sptep, gw->pte_access, write_fault,
722 it.level, base_gfn, pfn, prefault, map_writable);
723 if (ret == RET_PF_SPURIOUS)
724 return ret;
725
726 FNAME(pte_prefetch)(vcpu, gw, it.sptep);
727 ++vcpu->stat.pf_fixed;
728 return ret;
729
730 out_gpte_changed:
731 return RET_PF_RETRY;
732 }
733
734 /*
735 * To see whether the mapped gfn can write its page table in the current
736 * mapping.
737 *
738 * It is the helper function of FNAME(page_fault). When guest uses large page
739 * size to map the writable gfn which is used as current page table, we should
740 * force kvm to use small page size to map it because new shadow page will be
741 * created when kvm establishes shadow page table that stop kvm using large
742 * page size. Do it early can avoid unnecessary #PF and emulation.
743 *
744 * @write_fault_to_shadow_pgtable will return true if the fault gfn is
745 * currently used as its page table.
746 *
747 * Note: the PDPT page table is not checked for PAE-32 bit guest. It is ok
748 * since the PDPT is always shadowed, that means, we can not use large page
749 * size to map the gfn which is used as PDPT.
750 */
751 static bool
FNAME(is_self_change_mapping)752 FNAME(is_self_change_mapping)(struct kvm_vcpu *vcpu,
753 struct guest_walker *walker, bool user_fault,
754 bool *write_fault_to_shadow_pgtable)
755 {
756 int level;
757 gfn_t mask = ~(KVM_PAGES_PER_HPAGE(walker->level) - 1);
758 bool self_changed = false;
759
760 if (!(walker->pte_access & ACC_WRITE_MASK ||
761 (!is_write_protection(vcpu) && !user_fault)))
762 return false;
763
764 for (level = walker->level; level <= walker->max_level; level++) {
765 gfn_t gfn = walker->gfn ^ walker->table_gfn[level - 1];
766
767 self_changed |= !(gfn & mask);
768 *write_fault_to_shadow_pgtable |= !gfn;
769 }
770
771 return self_changed;
772 }
773
774 /*
775 * Page fault handler. There are several causes for a page fault:
776 * - there is no shadow pte for the guest pte
777 * - write access through a shadow pte marked read only so that we can set
778 * the dirty bit
779 * - write access to a shadow pte marked read only so we can update the page
780 * dirty bitmap, when userspace requests it
781 * - mmio access; in this case we will never install a present shadow pte
782 * - normal guest page fault due to the guest pte marked not present, not
783 * writable, or not executable
784 *
785 * Returns: 1 if we need to emulate the instruction, 0 otherwise, or
786 * a negative value on error.
787 */
FNAME(page_fault)788 static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gpa_t addr, u32 error_code,
789 bool prefault)
790 {
791 bool write_fault = error_code & PFERR_WRITE_MASK;
792 bool user_fault = error_code & PFERR_USER_MASK;
793 struct guest_walker walker;
794 int r;
795 kvm_pfn_t pfn;
796 unsigned long mmu_seq;
797 bool map_writable, is_self_change_mapping;
798 int max_level;
799
800 pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code);
801
802 /*
803 * If PFEC.RSVD is set, this is a shadow page fault.
804 * The bit needs to be cleared before walking guest page tables.
805 */
806 error_code &= ~PFERR_RSVD_MASK;
807
808 /*
809 * Look up the guest pte for the faulting address.
810 */
811 r = FNAME(walk_addr)(&walker, vcpu, addr, error_code);
812
813 /*
814 * The page is not mapped by the guest. Let the guest handle it.
815 */
816 if (!r) {
817 pgprintk("%s: guest page fault\n", __func__);
818 if (!prefault)
819 kvm_inject_emulated_page_fault(vcpu, &walker.fault);
820
821 return RET_PF_RETRY;
822 }
823
824 if (page_fault_handle_page_track(vcpu, error_code, walker.gfn)) {
825 shadow_page_table_clear_flood(vcpu, addr);
826 return RET_PF_EMULATE;
827 }
828
829 r = mmu_topup_memory_caches(vcpu, true);
830 if (r)
831 return r;
832
833 vcpu->arch.write_fault_to_shadow_pgtable = false;
834
835 is_self_change_mapping = FNAME(is_self_change_mapping)(vcpu,
836 &walker, user_fault, &vcpu->arch.write_fault_to_shadow_pgtable);
837
838 if (is_self_change_mapping)
839 max_level = PG_LEVEL_4K;
840 else
841 max_level = walker.level;
842
843 mmu_seq = vcpu->kvm->mmu_notifier_seq;
844 smp_rmb();
845
846 if (try_async_pf(vcpu, prefault, walker.gfn, addr, &pfn, write_fault,
847 &map_writable))
848 return RET_PF_RETRY;
849
850 if (handle_abnormal_pfn(vcpu, addr, walker.gfn, pfn, walker.pte_access, &r))
851 return r;
852
853 /*
854 * Do not change pte_access if the pfn is a mmio page, otherwise
855 * we will cache the incorrect access into mmio spte.
856 */
857 if (write_fault && !(walker.pte_access & ACC_WRITE_MASK) &&
858 !is_write_protection(vcpu) && !user_fault &&
859 !is_noslot_pfn(pfn)) {
860 walker.pte_access |= ACC_WRITE_MASK;
861 walker.pte_access &= ~ACC_USER_MASK;
862
863 /*
864 * If we converted a user page to a kernel page,
865 * so that the kernel can write to it when cr0.wp=0,
866 * then we should prevent the kernel from executing it
867 * if SMEP is enabled.
868 */
869 if (kvm_read_cr4_bits(vcpu, X86_CR4_SMEP))
870 walker.pte_access &= ~ACC_EXEC_MASK;
871 }
872
873 r = RET_PF_RETRY;
874 spin_lock(&vcpu->kvm->mmu_lock);
875 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
876 goto out_unlock;
877
878 kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT);
879 r = make_mmu_pages_available(vcpu);
880 if (r)
881 goto out_unlock;
882 r = FNAME(fetch)(vcpu, addr, &walker, error_code, max_level, pfn,
883 map_writable, prefault);
884 kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT);
885
886 out_unlock:
887 spin_unlock(&vcpu->kvm->mmu_lock);
888 kvm_release_pfn_clean(pfn);
889 return r;
890 }
891
FNAME(get_level1_sp_gpa)892 static gpa_t FNAME(get_level1_sp_gpa)(struct kvm_mmu_page *sp)
893 {
894 int offset = 0;
895
896 WARN_ON(sp->role.level != PG_LEVEL_4K);
897
898 if (PTTYPE == 32)
899 offset = sp->role.quadrant << PT64_LEVEL_BITS;
900
901 return gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t);
902 }
903
FNAME(invlpg)904 static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva, hpa_t root_hpa)
905 {
906 struct kvm_shadow_walk_iterator iterator;
907 struct kvm_mmu_page *sp;
908 u64 old_spte;
909 int level;
910 u64 *sptep;
911
912 vcpu_clear_mmio_info(vcpu, gva);
913
914 /*
915 * No need to check return value here, rmap_can_add() can
916 * help us to skip pte prefetch later.
917 */
918 mmu_topup_memory_caches(vcpu, true);
919
920 if (!VALID_PAGE(root_hpa)) {
921 WARN_ON(1);
922 return;
923 }
924
925 spin_lock(&vcpu->kvm->mmu_lock);
926 for_each_shadow_entry_using_root(vcpu, root_hpa, gva, iterator) {
927 level = iterator.level;
928 sptep = iterator.sptep;
929
930 sp = sptep_to_sp(sptep);
931 old_spte = *sptep;
932 if (is_last_spte(old_spte, level)) {
933 pt_element_t gpte;
934 gpa_t pte_gpa;
935
936 if (!sp->unsync)
937 break;
938
939 pte_gpa = FNAME(get_level1_sp_gpa)(sp);
940 pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t);
941
942 mmu_page_zap_pte(vcpu->kvm, sp, sptep, NULL);
943 if (is_shadow_present_pte(old_spte))
944 kvm_flush_remote_tlbs_with_address(vcpu->kvm,
945 sp->gfn, KVM_PAGES_PER_HPAGE(sp->role.level));
946
947 if (!rmap_can_add(vcpu))
948 break;
949
950 if (kvm_vcpu_read_guest_atomic(vcpu, pte_gpa, &gpte,
951 sizeof(pt_element_t)))
952 break;
953
954 FNAME(update_pte)(vcpu, sp, sptep, &gpte);
955 }
956
957 if (!is_shadow_present_pte(*sptep) || !sp->unsync_children)
958 break;
959 }
960 spin_unlock(&vcpu->kvm->mmu_lock);
961 }
962
963 /* Note, @addr is a GPA when gva_to_gpa() translates an L2 GPA to an L1 GPA. */
FNAME(gva_to_gpa)964 static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gpa_t addr, u32 access,
965 struct x86_exception *exception)
966 {
967 struct guest_walker walker;
968 gpa_t gpa = UNMAPPED_GVA;
969 int r;
970
971 r = FNAME(walk_addr)(&walker, vcpu, addr, access);
972
973 if (r) {
974 gpa = gfn_to_gpa(walker.gfn);
975 gpa |= addr & ~PAGE_MASK;
976 } else if (exception)
977 *exception = walker.fault;
978
979 return gpa;
980 }
981
982 #if PTTYPE != PTTYPE_EPT
983 /* Note, gva_to_gpa_nested() is only used to translate L2 GVAs. */
FNAME(gva_to_gpa_nested)984 static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gpa_t vaddr,
985 u32 access,
986 struct x86_exception *exception)
987 {
988 struct guest_walker walker;
989 gpa_t gpa = UNMAPPED_GVA;
990 int r;
991
992 #ifndef CONFIG_X86_64
993 /* A 64-bit GVA should be impossible on 32-bit KVM. */
994 WARN_ON_ONCE(vaddr >> 32);
995 #endif
996
997 r = FNAME(walk_addr_nested)(&walker, vcpu, vaddr, access);
998
999 if (r) {
1000 gpa = gfn_to_gpa(walker.gfn);
1001 gpa |= vaddr & ~PAGE_MASK;
1002 } else if (exception)
1003 *exception = walker.fault;
1004
1005 return gpa;
1006 }
1007 #endif
1008
1009 /*
1010 * Using the cached information from sp->gfns is safe because:
1011 * - The spte has a reference to the struct page, so the pfn for a given gfn
1012 * can't change unless all sptes pointing to it are nuked first.
1013 *
1014 * Note:
1015 * We should flush all tlbs if spte is dropped even though guest is
1016 * responsible for it. Since if we don't, kvm_mmu_notifier_invalidate_page
1017 * and kvm_mmu_notifier_invalidate_range_start detect the mapping page isn't
1018 * used by guest then tlbs are not flushed, so guest is allowed to access the
1019 * freed pages.
1020 * And we increase kvm->tlbs_dirty to delay tlbs flush in this case.
1021 */
FNAME(sync_page)1022 static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
1023 {
1024 int i, nr_present = 0;
1025 bool host_writable;
1026 gpa_t first_pte_gpa;
1027 int set_spte_ret = 0;
1028
1029 /* direct kvm_mmu_page can not be unsync. */
1030 BUG_ON(sp->role.direct);
1031
1032 first_pte_gpa = FNAME(get_level1_sp_gpa)(sp);
1033
1034 for (i = 0; i < PT64_ENT_PER_PAGE; i++) {
1035 unsigned pte_access;
1036 pt_element_t gpte;
1037 gpa_t pte_gpa;
1038 gfn_t gfn;
1039
1040 if (!sp->spt[i])
1041 continue;
1042
1043 pte_gpa = first_pte_gpa + i * sizeof(pt_element_t);
1044
1045 if (kvm_vcpu_read_guest_atomic(vcpu, pte_gpa, &gpte,
1046 sizeof(pt_element_t)))
1047 return 0;
1048
1049 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, &sp->spt[i], gpte)) {
1050 /*
1051 * Update spte before increasing tlbs_dirty to make
1052 * sure no tlb flush is lost after spte is zapped; see
1053 * the comments in kvm_flush_remote_tlbs().
1054 */
1055 smp_wmb();
1056 vcpu->kvm->tlbs_dirty++;
1057 continue;
1058 }
1059
1060 gfn = gpte_to_gfn(gpte);
1061 pte_access = sp->role.access;
1062 pte_access &= FNAME(gpte_access)(gpte);
1063 FNAME(protect_clean_gpte)(vcpu->arch.mmu, &pte_access, gpte);
1064
1065 if (sync_mmio_spte(vcpu, &sp->spt[i], gfn, pte_access,
1066 &nr_present))
1067 continue;
1068
1069 if (gfn != sp->gfns[i]) {
1070 drop_spte(vcpu->kvm, &sp->spt[i]);
1071 /*
1072 * The same as above where we are doing
1073 * prefetch_invalid_gpte().
1074 */
1075 smp_wmb();
1076 vcpu->kvm->tlbs_dirty++;
1077 continue;
1078 }
1079
1080 nr_present++;
1081
1082 host_writable = sp->spt[i] & SPTE_HOST_WRITEABLE;
1083
1084 set_spte_ret |= set_spte(vcpu, &sp->spt[i],
1085 pte_access, PG_LEVEL_4K,
1086 gfn, spte_to_pfn(sp->spt[i]),
1087 true, false, host_writable);
1088 }
1089
1090 if (set_spte_ret & SET_SPTE_NEED_REMOTE_TLB_FLUSH)
1091 kvm_flush_remote_tlbs(vcpu->kvm);
1092
1093 return nr_present;
1094 }
1095
1096 #undef pt_element_t
1097 #undef guest_walker
1098 #undef FNAME
1099 #undef PT_BASE_ADDR_MASK
1100 #undef PT_INDEX
1101 #undef PT_LVL_ADDR_MASK
1102 #undef PT_LVL_OFFSET_MASK
1103 #undef PT_LEVEL_BITS
1104 #undef PT_MAX_FULL_LEVELS
1105 #undef gpte_to_gfn
1106 #undef gpte_to_gfn_lvl
1107 #undef CMPXCHG
1108 #undef PT_GUEST_ACCESSED_MASK
1109 #undef PT_GUEST_DIRTY_MASK
1110 #undef PT_GUEST_DIRTY_SHIFT
1111 #undef PT_GUEST_ACCESSED_SHIFT
1112 #undef PT_HAVE_ACCESSED_DIRTY
1113