1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * ahci.c - AHCI SATA support
4 *
5 * Maintained by: Tejun Heo <tj@kernel.org>
6 * Please ALWAYS copy linux-ide@vger.kernel.org
7 * on emails.
8 *
9 * Copyright 2004-2005 Red Hat, Inc.
10 *
11 * libata documentation is available via 'make {ps|pdf}docs',
12 * as Documentation/driver-api/libata.rst
13 *
14 * AHCI hardware documentation:
15 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
16 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
17 */
18
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/pci.h>
22 #include <linux/blkdev.h>
23 #include <linux/delay.h>
24 #include <linux/interrupt.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/device.h>
27 #include <linux/dmi.h>
28 #include <linux/gfp.h>
29 #include <linux/msi.h>
30 #include <scsi/scsi_host.h>
31 #include <scsi/scsi_cmnd.h>
32 #include <linux/libata.h>
33 #include <linux/ahci-remap.h>
34 #include <linux/io-64-nonatomic-lo-hi.h>
35 #include "ahci.h"
36
37 #define DRV_NAME "ahci"
38 #define DRV_VERSION "3.0"
39
40 enum {
41 AHCI_PCI_BAR_STA2X11 = 0,
42 AHCI_PCI_BAR_CAVIUM = 0,
43 AHCI_PCI_BAR_LOONGSON = 0,
44 AHCI_PCI_BAR_ENMOTUS = 2,
45 AHCI_PCI_BAR_CAVIUM_GEN5 = 4,
46 AHCI_PCI_BAR_STANDARD = 5,
47 };
48
49 enum board_ids {
50 /* board IDs by feature in alphabetical order */
51 board_ahci,
52 board_ahci_ign_iferr,
53 board_ahci_mobile,
54 board_ahci_nomsi,
55 board_ahci_noncq,
56 board_ahci_nosntf,
57 board_ahci_yes_fbs,
58
59 /* board IDs for specific chipsets in alphabetical order */
60 board_ahci_al,
61 board_ahci_avn,
62 board_ahci_mcp65,
63 board_ahci_mcp77,
64 board_ahci_mcp89,
65 board_ahci_mv,
66 board_ahci_sb600,
67 board_ahci_sb700, /* for SB700 and SB800 */
68 board_ahci_vt8251,
69
70 /*
71 * board IDs for Intel chipsets that support more than 6 ports
72 * *and* end up needing the PCS quirk.
73 */
74 board_ahci_pcs7,
75
76 /* aliases */
77 board_ahci_mcp_linux = board_ahci_mcp65,
78 board_ahci_mcp67 = board_ahci_mcp65,
79 board_ahci_mcp73 = board_ahci_mcp65,
80 board_ahci_mcp79 = board_ahci_mcp77,
81 };
82
83 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
84 static void ahci_remove_one(struct pci_dev *dev);
85 static void ahci_shutdown_one(struct pci_dev *dev);
86 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
88 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
89 unsigned long deadline);
90 static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
91 static bool is_mcp89_apple(struct pci_dev *pdev);
92 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
93 unsigned long deadline);
94 #ifdef CONFIG_PM
95 static int ahci_pci_device_runtime_suspend(struct device *dev);
96 static int ahci_pci_device_runtime_resume(struct device *dev);
97 #ifdef CONFIG_PM_SLEEP
98 static int ahci_pci_device_suspend(struct device *dev);
99 static int ahci_pci_device_resume(struct device *dev);
100 #endif
101 #endif /* CONFIG_PM */
102
103 static struct scsi_host_template ahci_sht = {
104 AHCI_SHT("ahci"),
105 };
106
107 static struct ata_port_operations ahci_vt8251_ops = {
108 .inherits = &ahci_ops,
109 .hardreset = ahci_vt8251_hardreset,
110 };
111
112 static struct ata_port_operations ahci_p5wdh_ops = {
113 .inherits = &ahci_ops,
114 .hardreset = ahci_p5wdh_hardreset,
115 };
116
117 static struct ata_port_operations ahci_avn_ops = {
118 .inherits = &ahci_ops,
119 .hardreset = ahci_avn_hardreset,
120 };
121
122 static const struct ata_port_info ahci_port_info[] = {
123 /* by features */
124 [board_ahci] = {
125 .flags = AHCI_FLAG_COMMON,
126 .pio_mask = ATA_PIO4,
127 .udma_mask = ATA_UDMA6,
128 .port_ops = &ahci_ops,
129 },
130 [board_ahci_ign_iferr] = {
131 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
132 .flags = AHCI_FLAG_COMMON,
133 .pio_mask = ATA_PIO4,
134 .udma_mask = ATA_UDMA6,
135 .port_ops = &ahci_ops,
136 },
137 [board_ahci_mobile] = {
138 AHCI_HFLAGS (AHCI_HFLAG_IS_MOBILE),
139 .flags = AHCI_FLAG_COMMON,
140 .pio_mask = ATA_PIO4,
141 .udma_mask = ATA_UDMA6,
142 .port_ops = &ahci_ops,
143 },
144 [board_ahci_nomsi] = {
145 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
146 .flags = AHCI_FLAG_COMMON,
147 .pio_mask = ATA_PIO4,
148 .udma_mask = ATA_UDMA6,
149 .port_ops = &ahci_ops,
150 },
151 [board_ahci_noncq] = {
152 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
153 .flags = AHCI_FLAG_COMMON,
154 .pio_mask = ATA_PIO4,
155 .udma_mask = ATA_UDMA6,
156 .port_ops = &ahci_ops,
157 },
158 [board_ahci_nosntf] = {
159 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
160 .flags = AHCI_FLAG_COMMON,
161 .pio_mask = ATA_PIO4,
162 .udma_mask = ATA_UDMA6,
163 .port_ops = &ahci_ops,
164 },
165 [board_ahci_yes_fbs] = {
166 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
167 .flags = AHCI_FLAG_COMMON,
168 .pio_mask = ATA_PIO4,
169 .udma_mask = ATA_UDMA6,
170 .port_ops = &ahci_ops,
171 },
172 /* by chipsets */
173 [board_ahci_al] = {
174 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP | AHCI_HFLAG_NO_MSI),
175 .flags = AHCI_FLAG_COMMON,
176 .pio_mask = ATA_PIO4,
177 .udma_mask = ATA_UDMA6,
178 .port_ops = &ahci_ops,
179 },
180 [board_ahci_avn] = {
181 .flags = AHCI_FLAG_COMMON,
182 .pio_mask = ATA_PIO4,
183 .udma_mask = ATA_UDMA6,
184 .port_ops = &ahci_avn_ops,
185 },
186 [board_ahci_mcp65] = {
187 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
188 AHCI_HFLAG_YES_NCQ),
189 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
190 .pio_mask = ATA_PIO4,
191 .udma_mask = ATA_UDMA6,
192 .port_ops = &ahci_ops,
193 },
194 [board_ahci_mcp77] = {
195 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
196 .flags = AHCI_FLAG_COMMON,
197 .pio_mask = ATA_PIO4,
198 .udma_mask = ATA_UDMA6,
199 .port_ops = &ahci_ops,
200 },
201 [board_ahci_mcp89] = {
202 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
203 .flags = AHCI_FLAG_COMMON,
204 .pio_mask = ATA_PIO4,
205 .udma_mask = ATA_UDMA6,
206 .port_ops = &ahci_ops,
207 },
208 [board_ahci_mv] = {
209 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
210 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
211 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
212 .pio_mask = ATA_PIO4,
213 .udma_mask = ATA_UDMA6,
214 .port_ops = &ahci_ops,
215 },
216 [board_ahci_sb600] = {
217 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
218 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
219 AHCI_HFLAG_32BIT_ONLY),
220 .flags = AHCI_FLAG_COMMON,
221 .pio_mask = ATA_PIO4,
222 .udma_mask = ATA_UDMA6,
223 .port_ops = &ahci_pmp_retry_srst_ops,
224 },
225 [board_ahci_sb700] = { /* for SB700 and SB800 */
226 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
227 .flags = AHCI_FLAG_COMMON,
228 .pio_mask = ATA_PIO4,
229 .udma_mask = ATA_UDMA6,
230 .port_ops = &ahci_pmp_retry_srst_ops,
231 },
232 [board_ahci_vt8251] = {
233 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
234 .flags = AHCI_FLAG_COMMON,
235 .pio_mask = ATA_PIO4,
236 .udma_mask = ATA_UDMA6,
237 .port_ops = &ahci_vt8251_ops,
238 },
239 [board_ahci_pcs7] = {
240 .flags = AHCI_FLAG_COMMON,
241 .pio_mask = ATA_PIO4,
242 .udma_mask = ATA_UDMA6,
243 .port_ops = &ahci_ops,
244 },
245 };
246
247 static const struct pci_device_id ahci_pci_tbl[] = {
248 /* Intel */
249 { PCI_VDEVICE(INTEL, 0x06d6), board_ahci }, /* Comet Lake PCH-H RAID */
250 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
251 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
252 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
253 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
254 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
255 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
256 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
257 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
258 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
259 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
260 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
261 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
262 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
263 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
264 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
265 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
266 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
267 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
268 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
269 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
270 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_mobile }, /* ICH9M */
271 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_mobile }, /* ICH9M */
272 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_mobile }, /* ICH9M */
273 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_mobile }, /* ICH9M */
274 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_mobile }, /* ICH9M */
275 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
276 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_mobile }, /* ICH9M */
277 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
278 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
279 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
280 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
281 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
282 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
283 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
284 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
285 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
286 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_mobile }, /* PCH M AHCI */
287 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
288 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_mobile }, /* PCH M RAID */
289 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
290 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci_pcs7 }, /* DNV AHCI */
291 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci_pcs7 }, /* DNV AHCI */
292 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci_pcs7 }, /* DNV AHCI */
293 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci_pcs7 }, /* DNV AHCI */
294 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci_pcs7 }, /* DNV AHCI */
295 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci_pcs7 }, /* DNV AHCI */
296 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci_pcs7 }, /* DNV AHCI */
297 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci_pcs7 }, /* DNV AHCI */
298 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci_pcs7 }, /* DNV AHCI */
299 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci_pcs7 }, /* DNV AHCI */
300 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci_pcs7 }, /* DNV AHCI */
301 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci_pcs7 }, /* DNV AHCI */
302 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci_pcs7 }, /* DNV AHCI */
303 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci_pcs7 }, /* DNV AHCI */
304 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci_pcs7 }, /* DNV AHCI */
305 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci_pcs7 }, /* DNV AHCI */
306 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci_pcs7 }, /* DNV AHCI */
307 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci_pcs7 }, /* DNV AHCI */
308 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci_pcs7 }, /* DNV AHCI */
309 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci_pcs7 }, /* DNV AHCI */
310 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
311 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_mobile }, /* CPT M AHCI */
312 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
313 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_mobile }, /* CPT M RAID */
314 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
315 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
316 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
317 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
318 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
319 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
320 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
321 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
322 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_mobile }, /* Panther M AHCI */
323 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
324 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
325 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
326 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_mobile }, /* Panther M RAID */
327 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
328 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
329 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_mobile }, /* Lynx M AHCI */
330 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
331 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_mobile }, /* Lynx M RAID */
332 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
333 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_mobile }, /* Lynx M RAID */
334 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
335 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_mobile }, /* Lynx M RAID */
336 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_mobile }, /* Lynx LP AHCI */
337 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_mobile }, /* Lynx LP AHCI */
338 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_mobile }, /* Lynx LP RAID */
339 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_mobile }, /* Lynx LP RAID */
340 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_mobile }, /* Lynx LP RAID */
341 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_mobile }, /* Lynx LP RAID */
342 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_mobile }, /* Lynx LP RAID */
343 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_mobile }, /* Lynx LP RAID */
344 { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_mobile }, /* Cannon Lake PCH-LP AHCI */
345 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
346 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
347 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
348 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
349 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
350 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
351 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
352 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
353 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
354 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
355 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
356 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
357 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
358 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
359 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
360 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
361 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
362 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
363 { PCI_VDEVICE(INTEL, 0x43d4), board_ahci }, /* Rocket Lake PCH-H RAID */
364 { PCI_VDEVICE(INTEL, 0x43d5), board_ahci }, /* Rocket Lake PCH-H RAID */
365 { PCI_VDEVICE(INTEL, 0x43d6), board_ahci }, /* Rocket Lake PCH-H RAID */
366 { PCI_VDEVICE(INTEL, 0x43d7), board_ahci }, /* Rocket Lake PCH-H RAID */
367 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
368 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
369 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
370 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
371 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
372 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
373 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
374 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
375 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
376 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_mobile }, /* Wildcat LP AHCI */
377 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_mobile }, /* Wildcat LP RAID */
378 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_mobile }, /* Wildcat LP RAID */
379 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_mobile }, /* Wildcat LP RAID */
380 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
381 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_mobile }, /* 9 Series M AHCI */
382 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
383 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_mobile }, /* 9 Series M RAID */
384 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
385 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_mobile }, /* 9 Series M RAID */
386 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
387 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_mobile }, /* 9 Series M RAID */
388 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_mobile }, /* Sunrise LP AHCI */
389 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_mobile }, /* Sunrise LP RAID */
390 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_mobile }, /* Sunrise LP RAID */
391 { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
392 { PCI_VDEVICE(INTEL, 0xa103), board_ahci_mobile }, /* Sunrise M AHCI */
393 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
394 { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
395 { PCI_VDEVICE(INTEL, 0xa107), board_ahci_mobile }, /* Sunrise M RAID */
396 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
397 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/
398 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/
399 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/
400 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Lewisburg RAID*/
401 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
402 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
403 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/
404 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/
405 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
406 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
407 { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/
408 { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
409 { PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */
410 { PCI_VDEVICE(INTEL, 0x06d7), board_ahci }, /* Comet Lake-H RAID */
411 { PCI_VDEVICE(INTEL, 0xa386), board_ahci }, /* Comet Lake PCH-V RAID */
412 { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_mobile }, /* Bay Trail AHCI */
413 { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_mobile }, /* Bay Trail AHCI */
414 { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_mobile }, /* Cherry Tr. AHCI */
415 { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_mobile }, /* ApolloLake AHCI */
416 { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_mobile }, /* Ice Lake LP AHCI */
417 { PCI_VDEVICE(INTEL, 0x02d3), board_ahci_mobile }, /* Comet Lake PCH-U AHCI */
418 { PCI_VDEVICE(INTEL, 0x02d7), board_ahci_mobile }, /* Comet Lake PCH RAID */
419
420 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
421 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
422 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
423 /* JMicron 362B and 362C have an AHCI function with IDE class code */
424 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
425 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
426 /* May need to update quirk_jmicron_async_suspend() for additions */
427
428 /* ATI */
429 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
430 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
431 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
432 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
433 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
434 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
435 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
436
437 /* Amazon's Annapurna Labs support */
438 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031),
439 .class = PCI_CLASS_STORAGE_SATA_AHCI,
440 .class_mask = 0xffffff,
441 board_ahci_al },
442 /* AMD */
443 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
444 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
445 { PCI_VDEVICE(AMD, 0x7901), board_ahci_mobile }, /* AMD Green Sardine */
446 /* AMD is using RAID class only for ahci controllers */
447 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
448 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
449
450 /* VIA */
451 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
452 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
453
454 /* NVIDIA */
455 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
456 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
457 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
458 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
459 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
460 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
461 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
462 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
463 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
464 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
465 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
466 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
467 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
468 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
469 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
470 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
471 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
472 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
473 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
474 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
475 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
476 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
477 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
478 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
479 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
480 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
481 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
482 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
483 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
484 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
485 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
486 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
487 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
488 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
489 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
490 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
491 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
492 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
493 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
494 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
495 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
496 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
497 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
498 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
499 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
500 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
501 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
502 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
503 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
504 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
505 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
506 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
507 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
508 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
509 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
510 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
511 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
512 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
513 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
514 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
515 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
516 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
517 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
518 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
519 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
520 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
521 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
522 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
523 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
524 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
525 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
526 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
527 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
528 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
529 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
530 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
531 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
532 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
533 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
534 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
535 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
536 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
537 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
538 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
539
540 /* SiS */
541 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
542 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
543 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
544
545 /* ST Microelectronics */
546 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
547
548 /* Marvell */
549 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
550 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
551 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
552 .class = PCI_CLASS_STORAGE_SATA_AHCI,
553 .class_mask = 0xffffff,
554 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
555 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
556 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
557 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
558 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
559 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
560 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
561 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
562 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
563 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
564 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
565 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
566 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
567 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
568 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
569 .driver_data = board_ahci_yes_fbs },
570 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */
571 .driver_data = board_ahci_yes_fbs },
572 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
573 .driver_data = board_ahci_yes_fbs },
574 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
575 .driver_data = board_ahci_yes_fbs },
576 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */
577 .driver_data = board_ahci_yes_fbs },
578 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */
579 .driver_data = board_ahci_yes_fbs },
580
581 /* Promise */
582 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
583 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
584
585 /* Asmedia */
586 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
587 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
588 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
589 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
590 { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci }, /* ASM1061R */
591 { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci }, /* ASM1062R */
592
593 /*
594 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
595 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
596 */
597 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
598 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
599
600 /* Enmotus */
601 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
602
603 /* Loongson */
604 { PCI_VDEVICE(LOONGSON, 0x7a08), board_ahci },
605
606 /* Generic, PCI class code for AHCI */
607 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
608 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
609
610 { } /* terminate list */
611 };
612
613 static const struct dev_pm_ops ahci_pci_pm_ops = {
614 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume)
615 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend,
616 ahci_pci_device_runtime_resume, NULL)
617 };
618
619 static struct pci_driver ahci_pci_driver = {
620 .name = DRV_NAME,
621 .id_table = ahci_pci_tbl,
622 .probe = ahci_init_one,
623 .remove = ahci_remove_one,
624 .shutdown = ahci_shutdown_one,
625 .driver = {
626 .pm = &ahci_pci_pm_ops,
627 },
628 };
629
630 #if IS_ENABLED(CONFIG_PATA_MARVELL)
631 static int marvell_enable;
632 #else
633 static int marvell_enable = 1;
634 #endif
635 module_param(marvell_enable, int, 0644);
636 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
637
638 static int mobile_lpm_policy = -1;
639 module_param(mobile_lpm_policy, int, 0644);
640 MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets");
641
ahci_pci_save_initial_config(struct pci_dev * pdev,struct ahci_host_priv * hpriv)642 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
643 struct ahci_host_priv *hpriv)
644 {
645 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
646 dev_info(&pdev->dev, "JMB361 has only one port\n");
647 hpriv->force_port_map = 1;
648 }
649
650 /*
651 * Temporary Marvell 6145 hack: PATA port presence
652 * is asserted through the standard AHCI port
653 * presence register, as bit 4 (counting from 0)
654 */
655 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
656 if (pdev->device == 0x6121)
657 hpriv->mask_port_map = 0x3;
658 else
659 hpriv->mask_port_map = 0xf;
660 dev_info(&pdev->dev,
661 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
662 }
663
664 ahci_save_initial_config(&pdev->dev, hpriv);
665 }
666
ahci_pci_init_controller(struct ata_host * host)667 static void ahci_pci_init_controller(struct ata_host *host)
668 {
669 struct ahci_host_priv *hpriv = host->private_data;
670 struct pci_dev *pdev = to_pci_dev(host->dev);
671 void __iomem *port_mmio;
672 u32 tmp;
673 int mv;
674
675 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
676 if (pdev->device == 0x6121)
677 mv = 2;
678 else
679 mv = 4;
680 port_mmio = __ahci_port_base(host, mv);
681
682 writel(0, port_mmio + PORT_IRQ_MASK);
683
684 /* clear port IRQ */
685 tmp = readl(port_mmio + PORT_IRQ_STAT);
686 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
687 if (tmp)
688 writel(tmp, port_mmio + PORT_IRQ_STAT);
689 }
690
691 ahci_init_controller(host);
692 }
693
ahci_vt8251_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline)694 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
695 unsigned long deadline)
696 {
697 struct ata_port *ap = link->ap;
698 struct ahci_host_priv *hpriv = ap->host->private_data;
699 bool online;
700 int rc;
701
702 DPRINTK("ENTER\n");
703
704 hpriv->stop_engine(ap);
705
706 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
707 deadline, &online, NULL);
708
709 hpriv->start_engine(ap);
710
711 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
712
713 /* vt8251 doesn't clear BSY on signature FIS reception,
714 * request follow-up softreset.
715 */
716 return online ? -EAGAIN : rc;
717 }
718
ahci_p5wdh_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline)719 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
720 unsigned long deadline)
721 {
722 struct ata_port *ap = link->ap;
723 struct ahci_port_priv *pp = ap->private_data;
724 struct ahci_host_priv *hpriv = ap->host->private_data;
725 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
726 struct ata_taskfile tf;
727 bool online;
728 int rc;
729
730 hpriv->stop_engine(ap);
731
732 /* clear D2H reception area to properly wait for D2H FIS */
733 ata_tf_init(link->device, &tf);
734 tf.command = ATA_BUSY;
735 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
736
737 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
738 deadline, &online, NULL);
739
740 hpriv->start_engine(ap);
741
742 /* The pseudo configuration device on SIMG4726 attached to
743 * ASUS P5W-DH Deluxe doesn't send signature FIS after
744 * hardreset if no device is attached to the first downstream
745 * port && the pseudo device locks up on SRST w/ PMP==0. To
746 * work around this, wait for !BSY only briefly. If BSY isn't
747 * cleared, perform CLO and proceed to IDENTIFY (achieved by
748 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
749 *
750 * Wait for two seconds. Devices attached to downstream port
751 * which can't process the following IDENTIFY after this will
752 * have to be reset again. For most cases, this should
753 * suffice while making probing snappish enough.
754 */
755 if (online) {
756 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
757 ahci_check_ready);
758 if (rc)
759 ahci_kick_engine(ap);
760 }
761 return rc;
762 }
763
764 /*
765 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
766 *
767 * It has been observed with some SSDs that the timing of events in the
768 * link synchronization phase can leave the port in a state that can not
769 * be recovered by a SATA-hard-reset alone. The failing signature is
770 * SStatus.DET stuck at 1 ("Device presence detected but Phy
771 * communication not established"). It was found that unloading and
772 * reloading the driver when this problem occurs allows the drive
773 * connection to be recovered (DET advanced to 0x3). The critical
774 * component of reloading the driver is that the port state machines are
775 * reset by bouncing "port enable" in the AHCI PCS configuration
776 * register. So, reproduce that effect by bouncing a port whenever we
777 * see DET==1 after a reset.
778 */
ahci_avn_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline)779 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
780 unsigned long deadline)
781 {
782 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
783 struct ata_port *ap = link->ap;
784 struct ahci_port_priv *pp = ap->private_data;
785 struct ahci_host_priv *hpriv = ap->host->private_data;
786 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
787 unsigned long tmo = deadline - jiffies;
788 struct ata_taskfile tf;
789 bool online;
790 int rc, i;
791
792 DPRINTK("ENTER\n");
793
794 hpriv->stop_engine(ap);
795
796 for (i = 0; i < 2; i++) {
797 u16 val;
798 u32 sstatus;
799 int port = ap->port_no;
800 struct ata_host *host = ap->host;
801 struct pci_dev *pdev = to_pci_dev(host->dev);
802
803 /* clear D2H reception area to properly wait for D2H FIS */
804 ata_tf_init(link->device, &tf);
805 tf.command = ATA_BUSY;
806 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
807
808 rc = sata_link_hardreset(link, timing, deadline, &online,
809 ahci_check_ready);
810
811 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
812 (sstatus & 0xf) != 1)
813 break;
814
815 ata_link_info(link, "avn bounce port%d\n", port);
816
817 pci_read_config_word(pdev, 0x92, &val);
818 val &= ~(1 << port);
819 pci_write_config_word(pdev, 0x92, val);
820 ata_msleep(ap, 1000);
821 val |= 1 << port;
822 pci_write_config_word(pdev, 0x92, val);
823 deadline += tmo;
824 }
825
826 hpriv->start_engine(ap);
827
828 if (online)
829 *class = ahci_dev_classify(ap);
830
831 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
832 return rc;
833 }
834
835
836 #ifdef CONFIG_PM
ahci_pci_disable_interrupts(struct ata_host * host)837 static void ahci_pci_disable_interrupts(struct ata_host *host)
838 {
839 struct ahci_host_priv *hpriv = host->private_data;
840 void __iomem *mmio = hpriv->mmio;
841 u32 ctl;
842
843 /* AHCI spec rev1.1 section 8.3.3:
844 * Software must disable interrupts prior to requesting a
845 * transition of the HBA to D3 state.
846 */
847 ctl = readl(mmio + HOST_CTL);
848 ctl &= ~HOST_IRQ_EN;
849 writel(ctl, mmio + HOST_CTL);
850 readl(mmio + HOST_CTL); /* flush */
851 }
852
ahci_pci_device_runtime_suspend(struct device * dev)853 static int ahci_pci_device_runtime_suspend(struct device *dev)
854 {
855 struct pci_dev *pdev = to_pci_dev(dev);
856 struct ata_host *host = pci_get_drvdata(pdev);
857
858 ahci_pci_disable_interrupts(host);
859 return 0;
860 }
861
ahci_pci_device_runtime_resume(struct device * dev)862 static int ahci_pci_device_runtime_resume(struct device *dev)
863 {
864 struct pci_dev *pdev = to_pci_dev(dev);
865 struct ata_host *host = pci_get_drvdata(pdev);
866 int rc;
867
868 rc = ahci_reset_controller(host);
869 if (rc)
870 return rc;
871 ahci_pci_init_controller(host);
872 return 0;
873 }
874
875 #ifdef CONFIG_PM_SLEEP
ahci_pci_device_suspend(struct device * dev)876 static int ahci_pci_device_suspend(struct device *dev)
877 {
878 struct pci_dev *pdev = to_pci_dev(dev);
879 struct ata_host *host = pci_get_drvdata(pdev);
880 struct ahci_host_priv *hpriv = host->private_data;
881
882 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
883 dev_err(&pdev->dev,
884 "BIOS update required for suspend/resume\n");
885 return -EIO;
886 }
887
888 ahci_pci_disable_interrupts(host);
889 return ata_host_suspend(host, PMSG_SUSPEND);
890 }
891
ahci_pci_device_resume(struct device * dev)892 static int ahci_pci_device_resume(struct device *dev)
893 {
894 struct pci_dev *pdev = to_pci_dev(dev);
895 struct ata_host *host = pci_get_drvdata(pdev);
896 int rc;
897
898 /* Apple BIOS helpfully mangles the registers on resume */
899 if (is_mcp89_apple(pdev))
900 ahci_mcp89_apple_enable(pdev);
901
902 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
903 rc = ahci_reset_controller(host);
904 if (rc)
905 return rc;
906
907 ahci_pci_init_controller(host);
908 }
909
910 ata_host_resume(host);
911
912 return 0;
913 }
914 #endif
915
916 #endif /* CONFIG_PM */
917
ahci_configure_dma_masks(struct pci_dev * pdev,int using_dac)918 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
919 {
920 const int dma_bits = using_dac ? 64 : 32;
921 int rc;
922
923 /*
924 * If the device fixup already set the dma_mask to some non-standard
925 * value, don't extend it here. This happens on STA2X11, for example.
926 *
927 * XXX: manipulating the DMA mask from platform code is completely
928 * bogus, platform code should use dev->bus_dma_limit instead..
929 */
930 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
931 return 0;
932
933 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits));
934 if (rc)
935 dev_err(&pdev->dev, "DMA enable failed\n");
936 return rc;
937 }
938
ahci_pci_print_info(struct ata_host * host)939 static void ahci_pci_print_info(struct ata_host *host)
940 {
941 struct pci_dev *pdev = to_pci_dev(host->dev);
942 u16 cc;
943 const char *scc_s;
944
945 pci_read_config_word(pdev, 0x0a, &cc);
946 if (cc == PCI_CLASS_STORAGE_IDE)
947 scc_s = "IDE";
948 else if (cc == PCI_CLASS_STORAGE_SATA)
949 scc_s = "SATA";
950 else if (cc == PCI_CLASS_STORAGE_RAID)
951 scc_s = "RAID";
952 else
953 scc_s = "unknown";
954
955 ahci_print_info(host, scc_s);
956 }
957
958 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
959 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
960 * support PMP and the 4726 either directly exports the device
961 * attached to the first downstream port or acts as a hardware storage
962 * controller and emulate a single ATA device (can be RAID 0/1 or some
963 * other configuration).
964 *
965 * When there's no device attached to the first downstream port of the
966 * 4726, "Config Disk" appears, which is a pseudo ATA device to
967 * configure the 4726. However, ATA emulation of the device is very
968 * lame. It doesn't send signature D2H Reg FIS after the initial
969 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
970 *
971 * The following function works around the problem by always using
972 * hardreset on the port and not depending on receiving signature FIS
973 * afterward. If signature FIS isn't received soon, ATA class is
974 * assumed without follow-up softreset.
975 */
ahci_p5wdh_workaround(struct ata_host * host)976 static void ahci_p5wdh_workaround(struct ata_host *host)
977 {
978 static const struct dmi_system_id sysids[] = {
979 {
980 .ident = "P5W DH Deluxe",
981 .matches = {
982 DMI_MATCH(DMI_SYS_VENDOR,
983 "ASUSTEK COMPUTER INC"),
984 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
985 },
986 },
987 { }
988 };
989 struct pci_dev *pdev = to_pci_dev(host->dev);
990
991 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
992 dmi_check_system(sysids)) {
993 struct ata_port *ap = host->ports[1];
994
995 dev_info(&pdev->dev,
996 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
997
998 ap->ops = &ahci_p5wdh_ops;
999 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
1000 }
1001 }
1002
1003 /*
1004 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
1005 * booting in BIOS compatibility mode. We restore the registers but not ID.
1006 */
ahci_mcp89_apple_enable(struct pci_dev * pdev)1007 static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
1008 {
1009 u32 val;
1010
1011 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
1012
1013 pci_read_config_dword(pdev, 0xf8, &val);
1014 val |= 1 << 0x1b;
1015 /* the following changes the device ID, but appears not to affect function */
1016 /* val = (val & ~0xf0000000) | 0x80000000; */
1017 pci_write_config_dword(pdev, 0xf8, val);
1018
1019 pci_read_config_dword(pdev, 0x54c, &val);
1020 val |= 1 << 0xc;
1021 pci_write_config_dword(pdev, 0x54c, val);
1022
1023 pci_read_config_dword(pdev, 0x4a4, &val);
1024 val &= 0xff;
1025 val |= 0x01060100;
1026 pci_write_config_dword(pdev, 0x4a4, val);
1027
1028 pci_read_config_dword(pdev, 0x54c, &val);
1029 val &= ~(1 << 0xc);
1030 pci_write_config_dword(pdev, 0x54c, val);
1031
1032 pci_read_config_dword(pdev, 0xf8, &val);
1033 val &= ~(1 << 0x1b);
1034 pci_write_config_dword(pdev, 0xf8, val);
1035 }
1036
is_mcp89_apple(struct pci_dev * pdev)1037 static bool is_mcp89_apple(struct pci_dev *pdev)
1038 {
1039 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1040 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1041 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1042 pdev->subsystem_device == 0xcb89;
1043 }
1044
1045 /* only some SB600 ahci controllers can do 64bit DMA */
ahci_sb600_enable_64bit(struct pci_dev * pdev)1046 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
1047 {
1048 static const struct dmi_system_id sysids[] = {
1049 /*
1050 * The oldest version known to be broken is 0901 and
1051 * working is 1501 which was released on 2007-10-26.
1052 * Enable 64bit DMA on 1501 and anything newer.
1053 *
1054 * Please read bko#9412 for more info.
1055 */
1056 {
1057 .ident = "ASUS M2A-VM",
1058 .matches = {
1059 DMI_MATCH(DMI_BOARD_VENDOR,
1060 "ASUSTeK Computer INC."),
1061 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
1062 },
1063 .driver_data = "20071026", /* yyyymmdd */
1064 },
1065 /*
1066 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
1067 * support 64bit DMA.
1068 *
1069 * BIOS versions earlier than 1.5 had the Manufacturer DMI
1070 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
1071 * This spelling mistake was fixed in BIOS version 1.5, so
1072 * 1.5 and later have the Manufacturer as
1073 * "MICRO-STAR INTERNATIONAL CO.,LTD".
1074 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
1075 *
1076 * BIOS versions earlier than 1.9 had a Board Product Name
1077 * DMI field of "MS-7376". This was changed to be
1078 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
1079 * match on DMI_BOARD_NAME of "MS-7376".
1080 */
1081 {
1082 .ident = "MSI K9A2 Platinum",
1083 .matches = {
1084 DMI_MATCH(DMI_BOARD_VENDOR,
1085 "MICRO-STAR INTER"),
1086 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1087 },
1088 },
1089 /*
1090 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1091 * 64bit DMA.
1092 *
1093 * This board also had the typo mentioned above in the
1094 * Manufacturer DMI field (fixed in BIOS version 1.5), so
1095 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1096 */
1097 {
1098 .ident = "MSI K9AGM2",
1099 .matches = {
1100 DMI_MATCH(DMI_BOARD_VENDOR,
1101 "MICRO-STAR INTER"),
1102 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1103 },
1104 },
1105 /*
1106 * All BIOS versions for the Asus M3A support 64bit DMA.
1107 * (all release versions from 0301 to 1206 were tested)
1108 */
1109 {
1110 .ident = "ASUS M3A",
1111 .matches = {
1112 DMI_MATCH(DMI_BOARD_VENDOR,
1113 "ASUSTeK Computer INC."),
1114 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1115 },
1116 },
1117 { }
1118 };
1119 const struct dmi_system_id *match;
1120 int year, month, date;
1121 char buf[9];
1122
1123 match = dmi_first_match(sysids);
1124 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
1125 !match)
1126 return false;
1127
1128 if (!match->driver_data)
1129 goto enable_64bit;
1130
1131 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1132 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1133
1134 if (strcmp(buf, match->driver_data) >= 0)
1135 goto enable_64bit;
1136 else {
1137 dev_warn(&pdev->dev,
1138 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1139 match->ident);
1140 return false;
1141 }
1142
1143 enable_64bit:
1144 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
1145 return true;
1146 }
1147
ahci_broken_system_poweroff(struct pci_dev * pdev)1148 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1149 {
1150 static const struct dmi_system_id broken_systems[] = {
1151 {
1152 .ident = "HP Compaq nx6310",
1153 .matches = {
1154 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1155 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1156 },
1157 /* PCI slot number of the controller */
1158 .driver_data = (void *)0x1FUL,
1159 },
1160 {
1161 .ident = "HP Compaq 6720s",
1162 .matches = {
1163 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1164 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1165 },
1166 /* PCI slot number of the controller */
1167 .driver_data = (void *)0x1FUL,
1168 },
1169
1170 { } /* terminate list */
1171 };
1172 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1173
1174 if (dmi) {
1175 unsigned long slot = (unsigned long)dmi->driver_data;
1176 /* apply the quirk only to on-board controllers */
1177 return slot == PCI_SLOT(pdev->devfn);
1178 }
1179
1180 return false;
1181 }
1182
ahci_broken_suspend(struct pci_dev * pdev)1183 static bool ahci_broken_suspend(struct pci_dev *pdev)
1184 {
1185 static const struct dmi_system_id sysids[] = {
1186 /*
1187 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1188 * to the harddisk doesn't become online after
1189 * resuming from STR. Warn and fail suspend.
1190 *
1191 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1192 *
1193 * Use dates instead of versions to match as HP is
1194 * apparently recycling both product and version
1195 * strings.
1196 *
1197 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1198 */
1199 {
1200 .ident = "dv4",
1201 .matches = {
1202 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1203 DMI_MATCH(DMI_PRODUCT_NAME,
1204 "HP Pavilion dv4 Notebook PC"),
1205 },
1206 .driver_data = "20090105", /* F.30 */
1207 },
1208 {
1209 .ident = "dv5",
1210 .matches = {
1211 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1212 DMI_MATCH(DMI_PRODUCT_NAME,
1213 "HP Pavilion dv5 Notebook PC"),
1214 },
1215 .driver_data = "20090506", /* F.16 */
1216 },
1217 {
1218 .ident = "dv6",
1219 .matches = {
1220 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1221 DMI_MATCH(DMI_PRODUCT_NAME,
1222 "HP Pavilion dv6 Notebook PC"),
1223 },
1224 .driver_data = "20090423", /* F.21 */
1225 },
1226 {
1227 .ident = "HDX18",
1228 .matches = {
1229 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1230 DMI_MATCH(DMI_PRODUCT_NAME,
1231 "HP HDX18 Notebook PC"),
1232 },
1233 .driver_data = "20090430", /* F.23 */
1234 },
1235 /*
1236 * Acer eMachines G725 has the same problem. BIOS
1237 * V1.03 is known to be broken. V3.04 is known to
1238 * work. Between, there are V1.06, V2.06 and V3.03
1239 * that we don't have much idea about. For now,
1240 * blacklist anything older than V3.04.
1241 *
1242 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1243 */
1244 {
1245 .ident = "G725",
1246 .matches = {
1247 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1248 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1249 },
1250 .driver_data = "20091216", /* V3.04 */
1251 },
1252 { } /* terminate list */
1253 };
1254 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1255 int year, month, date;
1256 char buf[9];
1257
1258 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1259 return false;
1260
1261 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1262 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1263
1264 return strcmp(buf, dmi->driver_data) < 0;
1265 }
1266
ahci_broken_lpm(struct pci_dev * pdev)1267 static bool ahci_broken_lpm(struct pci_dev *pdev)
1268 {
1269 static const struct dmi_system_id sysids[] = {
1270 /* Various Lenovo 50 series have LPM issues with older BIOSen */
1271 {
1272 .matches = {
1273 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1274 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"),
1275 },
1276 .driver_data = "20180406", /* 1.31 */
1277 },
1278 {
1279 .matches = {
1280 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1281 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"),
1282 },
1283 .driver_data = "20180420", /* 1.28 */
1284 },
1285 {
1286 .matches = {
1287 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1288 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"),
1289 },
1290 .driver_data = "20180315", /* 1.33 */
1291 },
1292 {
1293 .matches = {
1294 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1295 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"),
1296 },
1297 /*
1298 * Note date based on release notes, 2.35 has been
1299 * reported to be good, but I've been unable to get
1300 * a hold of the reporter to get the DMI BIOS date.
1301 * TODO: fix this.
1302 */
1303 .driver_data = "20180310", /* 2.35 */
1304 },
1305 { } /* terminate list */
1306 };
1307 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1308 int year, month, date;
1309 char buf[9];
1310
1311 if (!dmi)
1312 return false;
1313
1314 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1315 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1316
1317 return strcmp(buf, dmi->driver_data) < 0;
1318 }
1319
ahci_broken_online(struct pci_dev * pdev)1320 static bool ahci_broken_online(struct pci_dev *pdev)
1321 {
1322 #define ENCODE_BUSDEVFN(bus, slot, func) \
1323 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1324 static const struct dmi_system_id sysids[] = {
1325 /*
1326 * There are several gigabyte boards which use
1327 * SIMG5723s configured as hardware RAID. Certain
1328 * 5723 firmware revisions shipped there keep the link
1329 * online but fail to answer properly to SRST or
1330 * IDENTIFY when no device is attached downstream
1331 * causing libata to retry quite a few times leading
1332 * to excessive detection delay.
1333 *
1334 * As these firmwares respond to the second reset try
1335 * with invalid device signature, considering unknown
1336 * sig as offline works around the problem acceptably.
1337 */
1338 {
1339 .ident = "EP45-DQ6",
1340 .matches = {
1341 DMI_MATCH(DMI_BOARD_VENDOR,
1342 "Gigabyte Technology Co., Ltd."),
1343 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1344 },
1345 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1346 },
1347 {
1348 .ident = "EP45-DS5",
1349 .matches = {
1350 DMI_MATCH(DMI_BOARD_VENDOR,
1351 "Gigabyte Technology Co., Ltd."),
1352 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1353 },
1354 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1355 },
1356 { } /* terminate list */
1357 };
1358 #undef ENCODE_BUSDEVFN
1359 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1360 unsigned int val;
1361
1362 if (!dmi)
1363 return false;
1364
1365 val = (unsigned long)dmi->driver_data;
1366
1367 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1368 }
1369
ahci_broken_devslp(struct pci_dev * pdev)1370 static bool ahci_broken_devslp(struct pci_dev *pdev)
1371 {
1372 /* device with broken DEVSLP but still showing SDS capability */
1373 static const struct pci_device_id ids[] = {
1374 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1375 {}
1376 };
1377
1378 return pci_match_id(ids, pdev);
1379 }
1380
1381 #ifdef CONFIG_ATA_ACPI
ahci_gtf_filter_workaround(struct ata_host * host)1382 static void ahci_gtf_filter_workaround(struct ata_host *host)
1383 {
1384 static const struct dmi_system_id sysids[] = {
1385 /*
1386 * Aspire 3810T issues a bunch of SATA enable commands
1387 * via _GTF including an invalid one and one which is
1388 * rejected by the device. Among the successful ones
1389 * is FPDMA non-zero offset enable which when enabled
1390 * only on the drive side leads to NCQ command
1391 * failures. Filter it out.
1392 */
1393 {
1394 .ident = "Aspire 3810T",
1395 .matches = {
1396 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1397 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1398 },
1399 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1400 },
1401 { }
1402 };
1403 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1404 unsigned int filter;
1405 int i;
1406
1407 if (!dmi)
1408 return;
1409
1410 filter = (unsigned long)dmi->driver_data;
1411 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1412 filter, dmi->ident);
1413
1414 for (i = 0; i < host->n_ports; i++) {
1415 struct ata_port *ap = host->ports[i];
1416 struct ata_link *link;
1417 struct ata_device *dev;
1418
1419 ata_for_each_link(link, ap, EDGE)
1420 ata_for_each_dev(dev, link, ALL)
1421 dev->gtf_filter |= filter;
1422 }
1423 }
1424 #else
ahci_gtf_filter_workaround(struct ata_host * host)1425 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1426 {}
1427 #endif
1428
1429 /*
1430 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected
1431 * as DUMMY, or detected but eventually get a "link down" and never get up
1432 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the
1433 * port_map may hold a value of 0x00.
1434 *
1435 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports
1436 * and can significantly reduce the occurrence of the problem.
1437 *
1438 * https://bugzilla.kernel.org/show_bug.cgi?id=189471
1439 */
acer_sa5_271_workaround(struct ahci_host_priv * hpriv,struct pci_dev * pdev)1440 static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv,
1441 struct pci_dev *pdev)
1442 {
1443 static const struct dmi_system_id sysids[] = {
1444 {
1445 .ident = "Acer Switch Alpha 12",
1446 .matches = {
1447 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1448 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271")
1449 },
1450 },
1451 { }
1452 };
1453
1454 if (dmi_check_system(sysids)) {
1455 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n");
1456 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) {
1457 hpriv->port_map = 0x7;
1458 hpriv->cap = 0xC734FF02;
1459 }
1460 }
1461 }
1462
1463 #ifdef CONFIG_ARM64
1464 /*
1465 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently.
1466 * Workaround is to make sure all pending IRQs are served before leaving
1467 * handler.
1468 */
ahci_thunderx_irq_handler(int irq,void * dev_instance)1469 static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
1470 {
1471 struct ata_host *host = dev_instance;
1472 struct ahci_host_priv *hpriv;
1473 unsigned int rc = 0;
1474 void __iomem *mmio;
1475 u32 irq_stat, irq_masked;
1476 unsigned int handled = 1;
1477
1478 VPRINTK("ENTER\n");
1479 hpriv = host->private_data;
1480 mmio = hpriv->mmio;
1481 irq_stat = readl(mmio + HOST_IRQ_STAT);
1482 if (!irq_stat)
1483 return IRQ_NONE;
1484
1485 do {
1486 irq_masked = irq_stat & hpriv->port_map;
1487 spin_lock(&host->lock);
1488 rc = ahci_handle_port_intr(host, irq_masked);
1489 if (!rc)
1490 handled = 0;
1491 writel(irq_stat, mmio + HOST_IRQ_STAT);
1492 irq_stat = readl(mmio + HOST_IRQ_STAT);
1493 spin_unlock(&host->lock);
1494 } while (irq_stat);
1495 VPRINTK("EXIT\n");
1496
1497 return IRQ_RETVAL(handled);
1498 }
1499 #endif
1500
ahci_remap_check(struct pci_dev * pdev,int bar,struct ahci_host_priv * hpriv)1501 static void ahci_remap_check(struct pci_dev *pdev, int bar,
1502 struct ahci_host_priv *hpriv)
1503 {
1504 int i;
1505 u32 cap;
1506
1507 /*
1508 * Check if this device might have remapped nvme devices.
1509 */
1510 if (pdev->vendor != PCI_VENDOR_ID_INTEL ||
1511 pci_resource_len(pdev, bar) < SZ_512K ||
1512 bar != AHCI_PCI_BAR_STANDARD ||
1513 !(readl(hpriv->mmio + AHCI_VSCAP) & 1))
1514 return;
1515
1516 cap = readq(hpriv->mmio + AHCI_REMAP_CAP);
1517 for (i = 0; i < AHCI_MAX_REMAP; i++) {
1518 if ((cap & (1 << i)) == 0)
1519 continue;
1520 if (readl(hpriv->mmio + ahci_remap_dcc(i))
1521 != PCI_CLASS_STORAGE_EXPRESS)
1522 continue;
1523
1524 /* We've found a remapped device */
1525 hpriv->remapped_nvme++;
1526 }
1527
1528 if (!hpriv->remapped_nvme)
1529 return;
1530
1531 dev_warn(&pdev->dev, "Found %u remapped NVMe devices.\n",
1532 hpriv->remapped_nvme);
1533 dev_warn(&pdev->dev,
1534 "Switch your BIOS from RAID to AHCI mode to use them.\n");
1535
1536 /*
1537 * Don't rely on the msi-x capability in the remap case,
1538 * share the legacy interrupt across ahci and remapped devices.
1539 */
1540 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1541 }
1542
ahci_get_irq_vector(struct ata_host * host,int port)1543 static int ahci_get_irq_vector(struct ata_host *host, int port)
1544 {
1545 return pci_irq_vector(to_pci_dev(host->dev), port);
1546 }
1547
ahci_init_msi(struct pci_dev * pdev,unsigned int n_ports,struct ahci_host_priv * hpriv)1548 static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
1549 struct ahci_host_priv *hpriv)
1550 {
1551 int nvec;
1552
1553 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1554 return -ENODEV;
1555
1556 /*
1557 * If number of MSIs is less than number of ports then Sharing Last
1558 * Message mode could be enforced. In this case assume that advantage
1559 * of multipe MSIs is negated and use single MSI mode instead.
1560 */
1561 if (n_ports > 1) {
1562 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX,
1563 PCI_IRQ_MSIX | PCI_IRQ_MSI);
1564 if (nvec > 0) {
1565 if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) {
1566 hpriv->get_irq_vector = ahci_get_irq_vector;
1567 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1568 return nvec;
1569 }
1570
1571 /*
1572 * Fallback to single MSI mode if the controller
1573 * enforced MRSM mode.
1574 */
1575 printk(KERN_INFO
1576 "ahci: MRSM is on, fallback to single MSI\n");
1577 pci_free_irq_vectors(pdev);
1578 }
1579 }
1580
1581 /*
1582 * If the host is not capable of supporting per-port vectors, fall
1583 * back to single MSI before finally attempting single MSI-X.
1584 */
1585 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1586 if (nvec == 1)
1587 return nvec;
1588 return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX);
1589 }
1590
ahci_update_initial_lpm_policy(struct ata_port * ap,struct ahci_host_priv * hpriv)1591 static void ahci_update_initial_lpm_policy(struct ata_port *ap,
1592 struct ahci_host_priv *hpriv)
1593 {
1594 int policy = CONFIG_SATA_MOBILE_LPM_POLICY;
1595
1596
1597 /* Ignore processing for non mobile platforms */
1598 if (!(hpriv->flags & AHCI_HFLAG_IS_MOBILE))
1599 return;
1600
1601 /* user modified policy via module param */
1602 if (mobile_lpm_policy != -1) {
1603 policy = mobile_lpm_policy;
1604 goto update_policy;
1605 }
1606
1607 #ifdef CONFIG_ACPI
1608 if (policy > ATA_LPM_MED_POWER &&
1609 (acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0)) {
1610 if (hpriv->cap & HOST_CAP_PART)
1611 policy = ATA_LPM_MIN_POWER_WITH_PARTIAL;
1612 else if (hpriv->cap & HOST_CAP_SSC)
1613 policy = ATA_LPM_MIN_POWER;
1614 }
1615 #endif
1616
1617 update_policy:
1618 if (policy >= ATA_LPM_UNKNOWN && policy <= ATA_LPM_MIN_POWER)
1619 ap->target_lpm_policy = policy;
1620 }
1621
ahci_intel_pcs_quirk(struct pci_dev * pdev,struct ahci_host_priv * hpriv)1622 static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
1623 {
1624 const struct pci_device_id *id = pci_match_id(ahci_pci_tbl, pdev);
1625 u16 tmp16;
1626
1627 /*
1628 * Only apply the 6-port PCS quirk for known legacy platforms.
1629 */
1630 if (!id || id->vendor != PCI_VENDOR_ID_INTEL)
1631 return;
1632
1633 /* Skip applying the quirk on Denverton and beyond */
1634 if (((enum board_ids) id->driver_data) >= board_ahci_pcs7)
1635 return;
1636
1637 /*
1638 * port_map is determined from PORTS_IMPL PCI register which is
1639 * implemented as write or write-once register. If the register
1640 * isn't programmed, ahci automatically generates it from number
1641 * of ports, which is good enough for PCS programming. It is
1642 * otherwise expected that platform firmware enables the ports
1643 * before the OS boots.
1644 */
1645 pci_read_config_word(pdev, PCS_6, &tmp16);
1646 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1647 tmp16 |= hpriv->port_map;
1648 pci_write_config_word(pdev, PCS_6, tmp16);
1649 }
1650 }
1651
remapped_nvme_show(struct device * dev,struct device_attribute * attr,char * buf)1652 static ssize_t remapped_nvme_show(struct device *dev,
1653 struct device_attribute *attr,
1654 char *buf)
1655 {
1656 struct ata_host *host = dev_get_drvdata(dev);
1657 struct ahci_host_priv *hpriv = host->private_data;
1658
1659 return sprintf(buf, "%u\n", hpriv->remapped_nvme);
1660 }
1661
1662 static DEVICE_ATTR_RO(remapped_nvme);
1663
ahci_init_one(struct pci_dev * pdev,const struct pci_device_id * ent)1664 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1665 {
1666 unsigned int board_id = ent->driver_data;
1667 struct ata_port_info pi = ahci_port_info[board_id];
1668 const struct ata_port_info *ppi[] = { &pi, NULL };
1669 struct device *dev = &pdev->dev;
1670 struct ahci_host_priv *hpriv;
1671 struct ata_host *host;
1672 int n_ports, i, rc;
1673 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1674
1675 VPRINTK("ENTER\n");
1676
1677 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1678
1679 ata_print_version_once(&pdev->dev, DRV_VERSION);
1680
1681 /* The AHCI driver can only drive the SATA ports, the PATA driver
1682 can drive them all so if both drivers are selected make sure
1683 AHCI stays out of the way */
1684 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1685 return -ENODEV;
1686
1687 /* Apple BIOS on MCP89 prevents us using AHCI */
1688 if (is_mcp89_apple(pdev))
1689 ahci_mcp89_apple_enable(pdev);
1690
1691 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1692 * At the moment, we can only use the AHCI mode. Let the users know
1693 * that for SAS drives they're out of luck.
1694 */
1695 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1696 dev_info(&pdev->dev,
1697 "PDC42819 can only drive SATA devices with this driver\n");
1698
1699 /* Some devices use non-standard BARs */
1700 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1701 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1702 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1703 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1704 else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) {
1705 if (pdev->device == 0xa01c)
1706 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
1707 if (pdev->device == 0xa084)
1708 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5;
1709 } else if (pdev->vendor == PCI_VENDOR_ID_LOONGSON) {
1710 if (pdev->device == 0x7a08)
1711 ahci_pci_bar = AHCI_PCI_BAR_LOONGSON;
1712 }
1713
1714 /* acquire resources */
1715 rc = pcim_enable_device(pdev);
1716 if (rc)
1717 return rc;
1718
1719 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1720 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1721 u8 map;
1722
1723 /* ICH6s share the same PCI ID for both piix and ahci
1724 * modes. Enabling ahci mode while MAP indicates
1725 * combined mode is a bad idea. Yield to ata_piix.
1726 */
1727 pci_read_config_byte(pdev, ICH_MAP, &map);
1728 if (map & 0x3) {
1729 dev_info(&pdev->dev,
1730 "controller is in combined mode, can't enable AHCI mode\n");
1731 return -ENODEV;
1732 }
1733 }
1734
1735 /* AHCI controllers often implement SFF compatible interface.
1736 * Grab all PCI BARs just in case.
1737 */
1738 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1739 if (rc == -EBUSY)
1740 pcim_pin_device(pdev);
1741 if (rc)
1742 return rc;
1743
1744 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1745 if (!hpriv)
1746 return -ENOMEM;
1747 hpriv->flags |= (unsigned long)pi.private_data;
1748
1749 /* MCP65 revision A1 and A2 can't do MSI */
1750 if (board_id == board_ahci_mcp65 &&
1751 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1752 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1753
1754 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1755 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1756 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1757
1758 /* only some SB600s can do 64bit DMA */
1759 if (ahci_sb600_enable_64bit(pdev))
1760 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1761
1762 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1763
1764 /* detect remapped nvme devices */
1765 ahci_remap_check(pdev, ahci_pci_bar, hpriv);
1766
1767 sysfs_add_file_to_group(&pdev->dev.kobj,
1768 &dev_attr_remapped_nvme.attr,
1769 NULL);
1770
1771 /* must set flag prior to save config in order to take effect */
1772 if (ahci_broken_devslp(pdev))
1773 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1774
1775 #ifdef CONFIG_ARM64
1776 if (pdev->vendor == PCI_VENDOR_ID_HUAWEI &&
1777 pdev->device == 0xa235 &&
1778 pdev->revision < 0x30)
1779 hpriv->flags |= AHCI_HFLAG_NO_SXS;
1780
1781 if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1782 hpriv->irq_handler = ahci_thunderx_irq_handler;
1783 #endif
1784
1785 /* save initial config */
1786 ahci_pci_save_initial_config(pdev, hpriv);
1787
1788 /*
1789 * If platform firmware failed to enable ports, try to enable
1790 * them here.
1791 */
1792 ahci_intel_pcs_quirk(pdev, hpriv);
1793
1794 /* prepare host */
1795 if (hpriv->cap & HOST_CAP_NCQ) {
1796 pi.flags |= ATA_FLAG_NCQ;
1797 /*
1798 * Auto-activate optimization is supposed to be
1799 * supported on all AHCI controllers indicating NCQ
1800 * capability, but it seems to be broken on some
1801 * chipsets including NVIDIAs.
1802 */
1803 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1804 pi.flags |= ATA_FLAG_FPDMA_AA;
1805
1806 /*
1807 * All AHCI controllers should be forward-compatible
1808 * with the new auxiliary field. This code should be
1809 * conditionalized if any buggy AHCI controllers are
1810 * encountered.
1811 */
1812 pi.flags |= ATA_FLAG_FPDMA_AUX;
1813 }
1814
1815 if (hpriv->cap & HOST_CAP_PMP)
1816 pi.flags |= ATA_FLAG_PMP;
1817
1818 ahci_set_em_messages(hpriv, &pi);
1819
1820 if (ahci_broken_system_poweroff(pdev)) {
1821 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1822 dev_info(&pdev->dev,
1823 "quirky BIOS, skipping spindown on poweroff\n");
1824 }
1825
1826 if (ahci_broken_lpm(pdev)) {
1827 pi.flags |= ATA_FLAG_NO_LPM;
1828 dev_warn(&pdev->dev,
1829 "BIOS update required for Link Power Management support\n");
1830 }
1831
1832 if (ahci_broken_suspend(pdev)) {
1833 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1834 dev_warn(&pdev->dev,
1835 "BIOS update required for suspend/resume\n");
1836 }
1837
1838 if (ahci_broken_online(pdev)) {
1839 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1840 dev_info(&pdev->dev,
1841 "online status unreliable, applying workaround\n");
1842 }
1843
1844
1845 /* Acer SA5-271 workaround modifies private_data */
1846 acer_sa5_271_workaround(hpriv, pdev);
1847
1848 /* CAP.NP sometimes indicate the index of the last enabled
1849 * port, at other times, that of the last possible port, so
1850 * determining the maximum port number requires looking at
1851 * both CAP.NP and port_map.
1852 */
1853 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1854
1855 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1856 if (!host)
1857 return -ENOMEM;
1858 host->private_data = hpriv;
1859
1860 if (ahci_init_msi(pdev, n_ports, hpriv) < 0) {
1861 /* legacy intx interrupts */
1862 pci_intx(pdev, 1);
1863 }
1864 hpriv->irq = pci_irq_vector(pdev, 0);
1865
1866 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1867 host->flags |= ATA_HOST_PARALLEL_SCAN;
1868 else
1869 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1870
1871 if (pi.flags & ATA_FLAG_EM)
1872 ahci_reset_em(host);
1873
1874 for (i = 0; i < host->n_ports; i++) {
1875 struct ata_port *ap = host->ports[i];
1876
1877 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1878 ata_port_pbar_desc(ap, ahci_pci_bar,
1879 0x100 + ap->port_no * 0x80, "port");
1880
1881 /* set enclosure management message type */
1882 if (ap->flags & ATA_FLAG_EM)
1883 ap->em_message_type = hpriv->em_msg_type;
1884
1885 ahci_update_initial_lpm_policy(ap, hpriv);
1886
1887 /* disabled/not-implemented port */
1888 if (!(hpriv->port_map & (1 << i)))
1889 ap->ops = &ata_dummy_port_ops;
1890 }
1891
1892 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1893 ahci_p5wdh_workaround(host);
1894
1895 /* apply gtf filter quirk */
1896 ahci_gtf_filter_workaround(host);
1897
1898 /* initialize adapter */
1899 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1900 if (rc)
1901 return rc;
1902
1903 rc = ahci_reset_controller(host);
1904 if (rc)
1905 return rc;
1906
1907 ahci_pci_init_controller(host);
1908 ahci_pci_print_info(host);
1909
1910 pci_set_master(pdev);
1911
1912 rc = ahci_host_activate(host, &ahci_sht);
1913 if (rc)
1914 return rc;
1915
1916 pm_runtime_put_noidle(&pdev->dev);
1917 return 0;
1918 }
1919
ahci_shutdown_one(struct pci_dev * pdev)1920 static void ahci_shutdown_one(struct pci_dev *pdev)
1921 {
1922 ata_pci_shutdown_one(pdev);
1923 }
1924
ahci_remove_one(struct pci_dev * pdev)1925 static void ahci_remove_one(struct pci_dev *pdev)
1926 {
1927 sysfs_remove_file_from_group(&pdev->dev.kobj,
1928 &dev_attr_remapped_nvme.attr,
1929 NULL);
1930 pm_runtime_get_noresume(&pdev->dev);
1931 ata_pci_remove_one(pdev);
1932 }
1933
1934 module_pci_driver(ahci_pci_driver);
1935
1936 MODULE_AUTHOR("Jeff Garzik");
1937 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1938 MODULE_LICENSE("GPL");
1939 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1940 MODULE_VERSION(DRV_VERSION);
1941