1 /*
2 * GPIO driver for Marvell SoCs
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 * Andrew Lunn <andrew@lunn.ch>
8 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 *
14 * This driver is a fairly straightforward GPIO driver for the
15 * complete family of Marvell EBU SoC platforms (Orion, Dove,
16 * Kirkwood, Discovery, Armada 370/XP). The only complexity of this
17 * driver is the different register layout that exists between the
18 * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP
19 * platforms (MV78200 from the Discovery family and the Armada
20 * XP). Therefore, this driver handles three variants of the GPIO
21 * block:
22 * - the basic variant, called "orion-gpio", with the simplest
23 * register set. Used on Orion, Dove, Kirkwoord, Armada 370 and
24 * non-SMP Discovery systems
25 * - the mv78200 variant for MV78200 Discovery systems. This variant
26 * turns the edge mask and level mask registers into CPU0 edge
27 * mask/level mask registers, and adds CPU1 edge mask/level mask
28 * registers.
29 * - the armadaxp variant for Armada XP systems. This variant keeps
30 * the normal cause/edge mask/level mask registers when the global
31 * interrupts are used, but adds per-CPU cause/edge mask/level mask
32 * registers n a separate memory area for the per-CPU GPIO
33 * interrupts.
34 */
35
36 #include <linux/bitops.h>
37 #include <linux/clk.h>
38 #include <linux/err.h>
39 #include <linux/gpio/driver.h>
40 #include <linux/gpio/consumer.h>
41 #include <linux/gpio/machine.h>
42 #include <linux/init.h>
43 #include <linux/io.h>
44 #include <linux/irq.h>
45 #include <linux/irqchip/chained_irq.h>
46 #include <linux/irqdomain.h>
47 #include <linux/mfd/syscon.h>
48 #include <linux/of_device.h>
49 #include <linux/pinctrl/consumer.h>
50 #include <linux/platform_device.h>
51 #include <linux/pwm.h>
52 #include <linux/regmap.h>
53 #include <linux/slab.h>
54
55 /*
56 * GPIO unit register offsets.
57 */
58 #define GPIO_OUT_OFF 0x0000
59 #define GPIO_IO_CONF_OFF 0x0004
60 #define GPIO_BLINK_EN_OFF 0x0008
61 #define GPIO_IN_POL_OFF 0x000c
62 #define GPIO_DATA_IN_OFF 0x0010
63 #define GPIO_EDGE_CAUSE_OFF 0x0014
64 #define GPIO_EDGE_MASK_OFF 0x0018
65 #define GPIO_LEVEL_MASK_OFF 0x001c
66 #define GPIO_BLINK_CNT_SELECT_OFF 0x0020
67
68 /*
69 * PWM register offsets.
70 */
71 #define PWM_BLINK_ON_DURATION_OFF 0x0
72 #define PWM_BLINK_OFF_DURATION_OFF 0x4
73
74
75 /* The MV78200 has per-CPU registers for edge mask and level mask */
76 #define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18)
77 #define GPIO_LEVEL_MASK_MV78200_OFF(cpu) ((cpu) ? 0x34 : 0x1C)
78
79 /*
80 * The Armada XP has per-CPU registers for interrupt cause, interrupt
81 * mask and interrupt level mask. Those are relative to the
82 * percpu_membase.
83 */
84 #define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4)
85 #define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu) (0x10 + (cpu) * 0x4)
86 #define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4)
87
88 #define MVEBU_GPIO_SOC_VARIANT_ORION 0x1
89 #define MVEBU_GPIO_SOC_VARIANT_MV78200 0x2
90 #define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3
91 #define MVEBU_GPIO_SOC_VARIANT_A8K 0x4
92
93 #define MVEBU_MAX_GPIO_PER_BANK 32
94
95 struct mvebu_pwm {
96 void __iomem *membase;
97 unsigned long clk_rate;
98 struct gpio_desc *gpiod;
99 struct pwm_chip chip;
100 spinlock_t lock;
101 struct mvebu_gpio_chip *mvchip;
102
103 /* Used to preserve GPIO/PWM registers across suspend/resume */
104 u32 blink_select;
105 u32 blink_on_duration;
106 u32 blink_off_duration;
107 };
108
109 struct mvebu_gpio_chip {
110 struct gpio_chip chip;
111 struct regmap *regs;
112 u32 offset;
113 struct regmap *percpu_regs;
114 int irqbase;
115 struct irq_domain *domain;
116 int soc_variant;
117
118 /* Used for PWM support */
119 struct clk *clk;
120 struct mvebu_pwm *mvpwm;
121
122 /* Used to preserve GPIO registers across suspend/resume */
123 u32 out_reg;
124 u32 io_conf_reg;
125 u32 blink_en_reg;
126 u32 in_pol_reg;
127 u32 edge_mask_regs[4];
128 u32 level_mask_regs[4];
129 };
130
131 /*
132 * Functions returning addresses of individual registers for a given
133 * GPIO controller.
134 */
135
mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip * mvchip,struct regmap ** map,unsigned int * offset)136 static void mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip,
137 struct regmap **map, unsigned int *offset)
138 {
139 int cpu;
140
141 switch (mvchip->soc_variant) {
142 case MVEBU_GPIO_SOC_VARIANT_ORION:
143 case MVEBU_GPIO_SOC_VARIANT_MV78200:
144 case MVEBU_GPIO_SOC_VARIANT_A8K:
145 *map = mvchip->regs;
146 *offset = GPIO_EDGE_CAUSE_OFF + mvchip->offset;
147 break;
148 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
149 cpu = smp_processor_id();
150 *map = mvchip->percpu_regs;
151 *offset = GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu);
152 break;
153 default:
154 BUG();
155 }
156 }
157
158 static u32
mvebu_gpio_read_edge_cause(struct mvebu_gpio_chip * mvchip)159 mvebu_gpio_read_edge_cause(struct mvebu_gpio_chip *mvchip)
160 {
161 struct regmap *map;
162 unsigned int offset;
163 u32 val;
164
165 mvebu_gpioreg_edge_cause(mvchip, &map, &offset);
166 regmap_read(map, offset, &val);
167
168 return val;
169 }
170
171 static void
mvebu_gpio_write_edge_cause(struct mvebu_gpio_chip * mvchip,u32 val)172 mvebu_gpio_write_edge_cause(struct mvebu_gpio_chip *mvchip, u32 val)
173 {
174 struct regmap *map;
175 unsigned int offset;
176
177 mvebu_gpioreg_edge_cause(mvchip, &map, &offset);
178 regmap_write(map, offset, val);
179 }
180
181 static inline void
mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip * mvchip,struct regmap ** map,unsigned int * offset)182 mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip,
183 struct regmap **map, unsigned int *offset)
184 {
185 int cpu;
186
187 switch (mvchip->soc_variant) {
188 case MVEBU_GPIO_SOC_VARIANT_ORION:
189 case MVEBU_GPIO_SOC_VARIANT_A8K:
190 *map = mvchip->regs;
191 *offset = GPIO_EDGE_MASK_OFF + mvchip->offset;
192 break;
193 case MVEBU_GPIO_SOC_VARIANT_MV78200:
194 cpu = smp_processor_id();
195 *map = mvchip->regs;
196 *offset = GPIO_EDGE_MASK_MV78200_OFF(cpu);
197 break;
198 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
199 cpu = smp_processor_id();
200 *map = mvchip->percpu_regs;
201 *offset = GPIO_EDGE_MASK_ARMADAXP_OFF(cpu);
202 break;
203 default:
204 BUG();
205 }
206 }
207
208 static u32
mvebu_gpio_read_edge_mask(struct mvebu_gpio_chip * mvchip)209 mvebu_gpio_read_edge_mask(struct mvebu_gpio_chip *mvchip)
210 {
211 struct regmap *map;
212 unsigned int offset;
213 u32 val;
214
215 mvebu_gpioreg_edge_mask(mvchip, &map, &offset);
216 regmap_read(map, offset, &val);
217
218 return val;
219 }
220
221 static void
mvebu_gpio_write_edge_mask(struct mvebu_gpio_chip * mvchip,u32 val)222 mvebu_gpio_write_edge_mask(struct mvebu_gpio_chip *mvchip, u32 val)
223 {
224 struct regmap *map;
225 unsigned int offset;
226
227 mvebu_gpioreg_edge_mask(mvchip, &map, &offset);
228 regmap_write(map, offset, val);
229 }
230
231 static void
mvebu_gpioreg_level_mask(struct mvebu_gpio_chip * mvchip,struct regmap ** map,unsigned int * offset)232 mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip,
233 struct regmap **map, unsigned int *offset)
234 {
235 int cpu;
236
237 switch (mvchip->soc_variant) {
238 case MVEBU_GPIO_SOC_VARIANT_ORION:
239 case MVEBU_GPIO_SOC_VARIANT_A8K:
240 *map = mvchip->regs;
241 *offset = GPIO_LEVEL_MASK_OFF + mvchip->offset;
242 break;
243 case MVEBU_GPIO_SOC_VARIANT_MV78200:
244 cpu = smp_processor_id();
245 *map = mvchip->regs;
246 *offset = GPIO_LEVEL_MASK_MV78200_OFF(cpu);
247 break;
248 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
249 cpu = smp_processor_id();
250 *map = mvchip->percpu_regs;
251 *offset = GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu);
252 break;
253 default:
254 BUG();
255 }
256 }
257
258 static u32
mvebu_gpio_read_level_mask(struct mvebu_gpio_chip * mvchip)259 mvebu_gpio_read_level_mask(struct mvebu_gpio_chip *mvchip)
260 {
261 struct regmap *map;
262 unsigned int offset;
263 u32 val;
264
265 mvebu_gpioreg_level_mask(mvchip, &map, &offset);
266 regmap_read(map, offset, &val);
267
268 return val;
269 }
270
271 static void
mvebu_gpio_write_level_mask(struct mvebu_gpio_chip * mvchip,u32 val)272 mvebu_gpio_write_level_mask(struct mvebu_gpio_chip *mvchip, u32 val)
273 {
274 struct regmap *map;
275 unsigned int offset;
276
277 mvebu_gpioreg_level_mask(mvchip, &map, &offset);
278 regmap_write(map, offset, val);
279 }
280
281 /*
282 * Functions returning addresses of individual registers for a given
283 * PWM controller.
284 */
mvebu_pwmreg_blink_on_duration(struct mvebu_pwm * mvpwm)285 static void __iomem *mvebu_pwmreg_blink_on_duration(struct mvebu_pwm *mvpwm)
286 {
287 return mvpwm->membase + PWM_BLINK_ON_DURATION_OFF;
288 }
289
mvebu_pwmreg_blink_off_duration(struct mvebu_pwm * mvpwm)290 static void __iomem *mvebu_pwmreg_blink_off_duration(struct mvebu_pwm *mvpwm)
291 {
292 return mvpwm->membase + PWM_BLINK_OFF_DURATION_OFF;
293 }
294
295 /*
296 * Functions implementing the gpio_chip methods
297 */
mvebu_gpio_set(struct gpio_chip * chip,unsigned int pin,int value)298 static void mvebu_gpio_set(struct gpio_chip *chip, unsigned int pin, int value)
299 {
300 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
301
302 regmap_update_bits(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
303 BIT(pin), value ? BIT(pin) : 0);
304 }
305
mvebu_gpio_get(struct gpio_chip * chip,unsigned int pin)306 static int mvebu_gpio_get(struct gpio_chip *chip, unsigned int pin)
307 {
308 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
309 u32 u;
310
311 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u);
312
313 if (u & BIT(pin)) {
314 u32 data_in, in_pol;
315
316 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset,
317 &data_in);
318 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
319 &in_pol);
320 u = data_in ^ in_pol;
321 } else {
322 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &u);
323 }
324
325 return (u >> pin) & 1;
326 }
327
mvebu_gpio_blink(struct gpio_chip * chip,unsigned int pin,int value)328 static void mvebu_gpio_blink(struct gpio_chip *chip, unsigned int pin,
329 int value)
330 {
331 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
332
333 regmap_update_bits(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
334 BIT(pin), value ? BIT(pin) : 0);
335 }
336
mvebu_gpio_direction_input(struct gpio_chip * chip,unsigned int pin)337 static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned int pin)
338 {
339 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
340 int ret;
341
342 /*
343 * Check with the pinctrl driver whether this pin is usable as
344 * an input GPIO
345 */
346 ret = pinctrl_gpio_direction_input(chip->base + pin);
347 if (ret)
348 return ret;
349
350 regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
351 BIT(pin), BIT(pin));
352
353 return 0;
354 }
355
mvebu_gpio_direction_output(struct gpio_chip * chip,unsigned int pin,int value)356 static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned int pin,
357 int value)
358 {
359 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
360 int ret;
361
362 /*
363 * Check with the pinctrl driver whether this pin is usable as
364 * an output GPIO
365 */
366 ret = pinctrl_gpio_direction_output(chip->base + pin);
367 if (ret)
368 return ret;
369
370 mvebu_gpio_blink(chip, pin, 0);
371 mvebu_gpio_set(chip, pin, value);
372
373 regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
374 BIT(pin), 0);
375
376 return 0;
377 }
378
mvebu_gpio_get_direction(struct gpio_chip * chip,unsigned int pin)379 static int mvebu_gpio_get_direction(struct gpio_chip *chip, unsigned int pin)
380 {
381 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
382 u32 u;
383
384 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u);
385
386 if (u & BIT(pin))
387 return GPIO_LINE_DIRECTION_IN;
388
389 return GPIO_LINE_DIRECTION_OUT;
390 }
391
mvebu_gpio_to_irq(struct gpio_chip * chip,unsigned int pin)392 static int mvebu_gpio_to_irq(struct gpio_chip *chip, unsigned int pin)
393 {
394 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
395
396 return irq_create_mapping(mvchip->domain, pin);
397 }
398
399 /*
400 * Functions implementing the irq_chip methods
401 */
mvebu_gpio_irq_ack(struct irq_data * d)402 static void mvebu_gpio_irq_ack(struct irq_data *d)
403 {
404 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
405 struct mvebu_gpio_chip *mvchip = gc->private;
406 u32 mask = d->mask;
407
408 irq_gc_lock(gc);
409 mvebu_gpio_write_edge_cause(mvchip, ~mask);
410 irq_gc_unlock(gc);
411 }
412
mvebu_gpio_edge_irq_mask(struct irq_data * d)413 static void mvebu_gpio_edge_irq_mask(struct irq_data *d)
414 {
415 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
416 struct mvebu_gpio_chip *mvchip = gc->private;
417 struct irq_chip_type *ct = irq_data_get_chip_type(d);
418 u32 mask = d->mask;
419
420 irq_gc_lock(gc);
421 ct->mask_cache_priv &= ~mask;
422 mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv);
423 irq_gc_unlock(gc);
424 }
425
mvebu_gpio_edge_irq_unmask(struct irq_data * d)426 static void mvebu_gpio_edge_irq_unmask(struct irq_data *d)
427 {
428 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
429 struct mvebu_gpio_chip *mvchip = gc->private;
430 struct irq_chip_type *ct = irq_data_get_chip_type(d);
431 u32 mask = d->mask;
432
433 irq_gc_lock(gc);
434 mvebu_gpio_write_edge_cause(mvchip, ~mask);
435 ct->mask_cache_priv |= mask;
436 mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv);
437 irq_gc_unlock(gc);
438 }
439
mvebu_gpio_level_irq_mask(struct irq_data * d)440 static void mvebu_gpio_level_irq_mask(struct irq_data *d)
441 {
442 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
443 struct mvebu_gpio_chip *mvchip = gc->private;
444 struct irq_chip_type *ct = irq_data_get_chip_type(d);
445 u32 mask = d->mask;
446
447 irq_gc_lock(gc);
448 ct->mask_cache_priv &= ~mask;
449 mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv);
450 irq_gc_unlock(gc);
451 }
452
mvebu_gpio_level_irq_unmask(struct irq_data * d)453 static void mvebu_gpio_level_irq_unmask(struct irq_data *d)
454 {
455 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
456 struct mvebu_gpio_chip *mvchip = gc->private;
457 struct irq_chip_type *ct = irq_data_get_chip_type(d);
458 u32 mask = d->mask;
459
460 irq_gc_lock(gc);
461 ct->mask_cache_priv |= mask;
462 mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv);
463 irq_gc_unlock(gc);
464 }
465
466 /*****************************************************************************
467 * MVEBU GPIO IRQ
468 *
469 * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same
470 * value of the line or the opposite value.
471 *
472 * Level IRQ handlers: DATA_IN is used directly as cause register.
473 * Interrupt are masked by LEVEL_MASK registers.
474 * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE.
475 * Interrupt are masked by EDGE_MASK registers.
476 * Both-edge handlers: Similar to regular Edge handlers, but also swaps
477 * the polarity to catch the next line transaction.
478 * This is a race condition that might not perfectly
479 * work on some use cases.
480 *
481 * Every eight GPIO lines are grouped (OR'ed) before going up to main
482 * cause register.
483 *
484 * EDGE cause mask
485 * data-in /--------| |-----| |----\
486 * -----| |----- ---- to main cause reg
487 * X \----------------| |----/
488 * polarity LEVEL mask
489 *
490 ****************************************************************************/
491
mvebu_gpio_irq_set_type(struct irq_data * d,unsigned int type)492 static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type)
493 {
494 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
495 struct irq_chip_type *ct = irq_data_get_chip_type(d);
496 struct mvebu_gpio_chip *mvchip = gc->private;
497 int pin;
498 u32 u;
499
500 pin = d->hwirq;
501
502 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u);
503 if ((u & BIT(pin)) == 0)
504 return -EINVAL;
505
506 type &= IRQ_TYPE_SENSE_MASK;
507 if (type == IRQ_TYPE_NONE)
508 return -EINVAL;
509
510 /* Check if we need to change chip and handler */
511 if (!(ct->type & type))
512 if (irq_setup_alt_chip(d, type))
513 return -EINVAL;
514
515 /*
516 * Configure interrupt polarity.
517 */
518 switch (type) {
519 case IRQ_TYPE_EDGE_RISING:
520 case IRQ_TYPE_LEVEL_HIGH:
521 regmap_update_bits(mvchip->regs,
522 GPIO_IN_POL_OFF + mvchip->offset,
523 BIT(pin), 0);
524 break;
525 case IRQ_TYPE_EDGE_FALLING:
526 case IRQ_TYPE_LEVEL_LOW:
527 regmap_update_bits(mvchip->regs,
528 GPIO_IN_POL_OFF + mvchip->offset,
529 BIT(pin), BIT(pin));
530 break;
531 case IRQ_TYPE_EDGE_BOTH: {
532 u32 data_in, in_pol, val;
533
534 regmap_read(mvchip->regs,
535 GPIO_IN_POL_OFF + mvchip->offset, &in_pol);
536 regmap_read(mvchip->regs,
537 GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
538
539 /*
540 * set initial polarity based on current input level
541 */
542 if ((data_in ^ in_pol) & BIT(pin))
543 val = BIT(pin); /* falling */
544 else
545 val = 0; /* raising */
546
547 regmap_update_bits(mvchip->regs,
548 GPIO_IN_POL_OFF + mvchip->offset,
549 BIT(pin), val);
550 break;
551 }
552 }
553 return 0;
554 }
555
mvebu_gpio_irq_handler(struct irq_desc * desc)556 static void mvebu_gpio_irq_handler(struct irq_desc *desc)
557 {
558 struct mvebu_gpio_chip *mvchip = irq_desc_get_handler_data(desc);
559 struct irq_chip *chip = irq_desc_get_chip(desc);
560 u32 cause, type, data_in, level_mask, edge_cause, edge_mask;
561 int i;
562
563 if (mvchip == NULL)
564 return;
565
566 chained_irq_enter(chip, desc);
567
568 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
569 level_mask = mvebu_gpio_read_level_mask(mvchip);
570 edge_cause = mvebu_gpio_read_edge_cause(mvchip);
571 edge_mask = mvebu_gpio_read_edge_mask(mvchip);
572
573 cause = (data_in & level_mask) | (edge_cause & edge_mask);
574
575 for (i = 0; i < mvchip->chip.ngpio; i++) {
576 int irq;
577
578 irq = irq_find_mapping(mvchip->domain, i);
579
580 if (!(cause & BIT(i)))
581 continue;
582
583 type = irq_get_trigger_type(irq);
584 if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
585 /* Swap polarity (race with GPIO line) */
586 u32 polarity;
587
588 regmap_read(mvchip->regs,
589 GPIO_IN_POL_OFF + mvchip->offset,
590 &polarity);
591 polarity ^= BIT(i);
592 regmap_write(mvchip->regs,
593 GPIO_IN_POL_OFF + mvchip->offset,
594 polarity);
595 }
596
597 generic_handle_irq(irq);
598 }
599
600 chained_irq_exit(chip, desc);
601 }
602
603 /*
604 * Functions implementing the pwm_chip methods
605 */
to_mvebu_pwm(struct pwm_chip * chip)606 static struct mvebu_pwm *to_mvebu_pwm(struct pwm_chip *chip)
607 {
608 return container_of(chip, struct mvebu_pwm, chip);
609 }
610
mvebu_pwm_request(struct pwm_chip * chip,struct pwm_device * pwm)611 static int mvebu_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
612 {
613 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
614 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
615 struct gpio_desc *desc;
616 unsigned long flags;
617 int ret = 0;
618
619 spin_lock_irqsave(&mvpwm->lock, flags);
620
621 if (mvpwm->gpiod) {
622 ret = -EBUSY;
623 } else {
624 desc = gpiochip_request_own_desc(&mvchip->chip,
625 pwm->hwpwm, "mvebu-pwm",
626 GPIO_ACTIVE_HIGH,
627 GPIOD_OUT_LOW);
628 if (IS_ERR(desc)) {
629 ret = PTR_ERR(desc);
630 goto out;
631 }
632
633 mvpwm->gpiod = desc;
634 }
635 out:
636 spin_unlock_irqrestore(&mvpwm->lock, flags);
637 return ret;
638 }
639
mvebu_pwm_free(struct pwm_chip * chip,struct pwm_device * pwm)640 static void mvebu_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
641 {
642 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
643 unsigned long flags;
644
645 spin_lock_irqsave(&mvpwm->lock, flags);
646 gpiochip_free_own_desc(mvpwm->gpiod);
647 mvpwm->gpiod = NULL;
648 spin_unlock_irqrestore(&mvpwm->lock, flags);
649 }
650
mvebu_pwm_get_state(struct pwm_chip * chip,struct pwm_device * pwm,struct pwm_state * state)651 static void mvebu_pwm_get_state(struct pwm_chip *chip,
652 struct pwm_device *pwm,
653 struct pwm_state *state) {
654
655 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
656 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
657 unsigned long long val;
658 unsigned long flags;
659 u32 u;
660
661 spin_lock_irqsave(&mvpwm->lock, flags);
662
663 u = readl_relaxed(mvebu_pwmreg_blink_on_duration(mvpwm));
664 val = (unsigned long long) u * NSEC_PER_SEC;
665 do_div(val, mvpwm->clk_rate);
666 if (val > UINT_MAX)
667 state->duty_cycle = UINT_MAX;
668 else if (val)
669 state->duty_cycle = val;
670 else
671 state->duty_cycle = 1;
672
673 val = (unsigned long long) u; /* on duration */
674 /* period = on + off duration */
675 val += readl_relaxed(mvebu_pwmreg_blink_off_duration(mvpwm));
676 val *= NSEC_PER_SEC;
677 do_div(val, mvpwm->clk_rate);
678 if (val > UINT_MAX)
679 state->period = UINT_MAX;
680 else if (val)
681 state->period = val;
682 else
683 state->period = 1;
684
685 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &u);
686 if (u)
687 state->enabled = true;
688 else
689 state->enabled = false;
690
691 spin_unlock_irqrestore(&mvpwm->lock, flags);
692 }
693
mvebu_pwm_apply(struct pwm_chip * chip,struct pwm_device * pwm,const struct pwm_state * state)694 static int mvebu_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
695 const struct pwm_state *state)
696 {
697 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
698 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
699 unsigned long long val;
700 unsigned long flags;
701 unsigned int on, off;
702
703 val = (unsigned long long) mvpwm->clk_rate * state->duty_cycle;
704 do_div(val, NSEC_PER_SEC);
705 if (val > UINT_MAX)
706 return -EINVAL;
707 if (val)
708 on = val;
709 else
710 on = 1;
711
712 val = (unsigned long long) mvpwm->clk_rate *
713 (state->period - state->duty_cycle);
714 do_div(val, NSEC_PER_SEC);
715 if (val > UINT_MAX)
716 return -EINVAL;
717 if (val)
718 off = val;
719 else
720 off = 1;
721
722 spin_lock_irqsave(&mvpwm->lock, flags);
723
724 writel_relaxed(on, mvebu_pwmreg_blink_on_duration(mvpwm));
725 writel_relaxed(off, mvebu_pwmreg_blink_off_duration(mvpwm));
726 if (state->enabled)
727 mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 1);
728 else
729 mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 0);
730
731 spin_unlock_irqrestore(&mvpwm->lock, flags);
732
733 return 0;
734 }
735
736 static const struct pwm_ops mvebu_pwm_ops = {
737 .request = mvebu_pwm_request,
738 .free = mvebu_pwm_free,
739 .get_state = mvebu_pwm_get_state,
740 .apply = mvebu_pwm_apply,
741 .owner = THIS_MODULE,
742 };
743
mvebu_pwm_suspend(struct mvebu_gpio_chip * mvchip)744 static void __maybe_unused mvebu_pwm_suspend(struct mvebu_gpio_chip *mvchip)
745 {
746 struct mvebu_pwm *mvpwm = mvchip->mvpwm;
747
748 regmap_read(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset,
749 &mvpwm->blink_select);
750 mvpwm->blink_on_duration =
751 readl_relaxed(mvebu_pwmreg_blink_on_duration(mvpwm));
752 mvpwm->blink_off_duration =
753 readl_relaxed(mvebu_pwmreg_blink_off_duration(mvpwm));
754 }
755
mvebu_pwm_resume(struct mvebu_gpio_chip * mvchip)756 static void __maybe_unused mvebu_pwm_resume(struct mvebu_gpio_chip *mvchip)
757 {
758 struct mvebu_pwm *mvpwm = mvchip->mvpwm;
759
760 regmap_write(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset,
761 mvpwm->blink_select);
762 writel_relaxed(mvpwm->blink_on_duration,
763 mvebu_pwmreg_blink_on_duration(mvpwm));
764 writel_relaxed(mvpwm->blink_off_duration,
765 mvebu_pwmreg_blink_off_duration(mvpwm));
766 }
767
mvebu_pwm_probe(struct platform_device * pdev,struct mvebu_gpio_chip * mvchip,int id)768 static int mvebu_pwm_probe(struct platform_device *pdev,
769 struct mvebu_gpio_chip *mvchip,
770 int id)
771 {
772 struct device *dev = &pdev->dev;
773 struct mvebu_pwm *mvpwm;
774 u32 set;
775
776 if (!of_device_is_compatible(mvchip->chip.of_node,
777 "marvell,armada-370-gpio"))
778 return 0;
779
780 /*
781 * There are only two sets of PWM configuration registers for
782 * all the GPIO lines on those SoCs which this driver reserves
783 * for the first two GPIO chips. So if the resource is missing
784 * we can't treat it as an error.
785 */
786 if (!platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwm"))
787 return 0;
788
789 if (IS_ERR(mvchip->clk))
790 return PTR_ERR(mvchip->clk);
791
792 /*
793 * Use set A for lines of GPIO chip with id 0, B for GPIO chip
794 * with id 1. Don't allow further GPIO chips to be used for PWM.
795 */
796 if (id == 0)
797 set = 0;
798 else if (id == 1)
799 set = U32_MAX;
800 else
801 return -EINVAL;
802 regmap_write(mvchip->regs,
803 GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, set);
804
805 mvpwm = devm_kzalloc(dev, sizeof(struct mvebu_pwm), GFP_KERNEL);
806 if (!mvpwm)
807 return -ENOMEM;
808 mvchip->mvpwm = mvpwm;
809 mvpwm->mvchip = mvchip;
810
811 mvpwm->membase = devm_platform_ioremap_resource_byname(pdev, "pwm");
812 if (IS_ERR(mvpwm->membase))
813 return PTR_ERR(mvpwm->membase);
814
815 mvpwm->clk_rate = clk_get_rate(mvchip->clk);
816 if (!mvpwm->clk_rate) {
817 dev_err(dev, "failed to get clock rate\n");
818 return -EINVAL;
819 }
820
821 mvpwm->chip.dev = dev;
822 mvpwm->chip.ops = &mvebu_pwm_ops;
823 mvpwm->chip.npwm = mvchip->chip.ngpio;
824 /*
825 * There may already be some PWM allocated, so we can't force
826 * mvpwm->chip.base to a fixed point like mvchip->chip.base.
827 * So, we let pwmchip_add() do the numbering and take the next free
828 * region.
829 */
830 mvpwm->chip.base = -1;
831
832 spin_lock_init(&mvpwm->lock);
833
834 return pwmchip_add(&mvpwm->chip);
835 }
836
837 #ifdef CONFIG_DEBUG_FS
838 #include <linux/seq_file.h>
839
mvebu_gpio_dbg_show(struct seq_file * s,struct gpio_chip * chip)840 static void mvebu_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
841 {
842 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
843 u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk;
844 const char *label;
845 int i;
846
847 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &out);
848 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &io_conf);
849 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &blink);
850 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, &in_pol);
851 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
852 cause = mvebu_gpio_read_edge_cause(mvchip);
853 edg_msk = mvebu_gpio_read_edge_mask(mvchip);
854 lvl_msk = mvebu_gpio_read_level_mask(mvchip);
855
856 for_each_requested_gpio(chip, i, label) {
857 u32 msk;
858 bool is_out;
859
860 msk = BIT(i);
861 is_out = !(io_conf & msk);
862
863 seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label);
864
865 if (is_out) {
866 seq_printf(s, " out %s %s\n",
867 out & msk ? "hi" : "lo",
868 blink & msk ? "(blink )" : "");
869 continue;
870 }
871
872 seq_printf(s, " in %s (act %s) - IRQ",
873 (data_in ^ in_pol) & msk ? "hi" : "lo",
874 in_pol & msk ? "lo" : "hi");
875 if (!((edg_msk | lvl_msk) & msk)) {
876 seq_puts(s, " disabled\n");
877 continue;
878 }
879 if (edg_msk & msk)
880 seq_puts(s, " edge ");
881 if (lvl_msk & msk)
882 seq_puts(s, " level");
883 seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear ");
884 }
885 }
886 #else
887 #define mvebu_gpio_dbg_show NULL
888 #endif
889
890 static const struct of_device_id mvebu_gpio_of_match[] = {
891 {
892 .compatible = "marvell,orion-gpio",
893 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION,
894 },
895 {
896 .compatible = "marvell,mv78200-gpio",
897 .data = (void *) MVEBU_GPIO_SOC_VARIANT_MV78200,
898 },
899 {
900 .compatible = "marvell,armadaxp-gpio",
901 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ARMADAXP,
902 },
903 {
904 .compatible = "marvell,armada-370-gpio",
905 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION,
906 },
907 {
908 .compatible = "marvell,armada-8k-gpio",
909 .data = (void *) MVEBU_GPIO_SOC_VARIANT_A8K,
910 },
911 {
912 /* sentinel */
913 },
914 };
915
mvebu_gpio_suspend(struct platform_device * pdev,pm_message_t state)916 static int mvebu_gpio_suspend(struct platform_device *pdev, pm_message_t state)
917 {
918 struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev);
919 int i;
920
921 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
922 &mvchip->out_reg);
923 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
924 &mvchip->io_conf_reg);
925 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
926 &mvchip->blink_en_reg);
927 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
928 &mvchip->in_pol_reg);
929
930 switch (mvchip->soc_variant) {
931 case MVEBU_GPIO_SOC_VARIANT_ORION:
932 case MVEBU_GPIO_SOC_VARIANT_A8K:
933 regmap_read(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset,
934 &mvchip->edge_mask_regs[0]);
935 regmap_read(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset,
936 &mvchip->level_mask_regs[0]);
937 break;
938 case MVEBU_GPIO_SOC_VARIANT_MV78200:
939 for (i = 0; i < 2; i++) {
940 regmap_read(mvchip->regs,
941 GPIO_EDGE_MASK_MV78200_OFF(i),
942 &mvchip->edge_mask_regs[i]);
943 regmap_read(mvchip->regs,
944 GPIO_LEVEL_MASK_MV78200_OFF(i),
945 &mvchip->level_mask_regs[i]);
946 }
947 break;
948 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
949 for (i = 0; i < 4; i++) {
950 regmap_read(mvchip->regs,
951 GPIO_EDGE_MASK_ARMADAXP_OFF(i),
952 &mvchip->edge_mask_regs[i]);
953 regmap_read(mvchip->regs,
954 GPIO_LEVEL_MASK_ARMADAXP_OFF(i),
955 &mvchip->level_mask_regs[i]);
956 }
957 break;
958 default:
959 BUG();
960 }
961
962 if (IS_ENABLED(CONFIG_PWM))
963 mvebu_pwm_suspend(mvchip);
964
965 return 0;
966 }
967
mvebu_gpio_resume(struct platform_device * pdev)968 static int mvebu_gpio_resume(struct platform_device *pdev)
969 {
970 struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev);
971 int i;
972
973 regmap_write(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
974 mvchip->out_reg);
975 regmap_write(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
976 mvchip->io_conf_reg);
977 regmap_write(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
978 mvchip->blink_en_reg);
979 regmap_write(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
980 mvchip->in_pol_reg);
981
982 switch (mvchip->soc_variant) {
983 case MVEBU_GPIO_SOC_VARIANT_ORION:
984 case MVEBU_GPIO_SOC_VARIANT_A8K:
985 regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset,
986 mvchip->edge_mask_regs[0]);
987 regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset,
988 mvchip->level_mask_regs[0]);
989 break;
990 case MVEBU_GPIO_SOC_VARIANT_MV78200:
991 for (i = 0; i < 2; i++) {
992 regmap_write(mvchip->regs,
993 GPIO_EDGE_MASK_MV78200_OFF(i),
994 mvchip->edge_mask_regs[i]);
995 regmap_write(mvchip->regs,
996 GPIO_LEVEL_MASK_MV78200_OFF(i),
997 mvchip->level_mask_regs[i]);
998 }
999 break;
1000 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
1001 for (i = 0; i < 4; i++) {
1002 regmap_write(mvchip->regs,
1003 GPIO_EDGE_MASK_ARMADAXP_OFF(i),
1004 mvchip->edge_mask_regs[i]);
1005 regmap_write(mvchip->regs,
1006 GPIO_LEVEL_MASK_ARMADAXP_OFF(i),
1007 mvchip->level_mask_regs[i]);
1008 }
1009 break;
1010 default:
1011 BUG();
1012 }
1013
1014 if (IS_ENABLED(CONFIG_PWM))
1015 mvebu_pwm_resume(mvchip);
1016
1017 return 0;
1018 }
1019
1020 static const struct regmap_config mvebu_gpio_regmap_config = {
1021 .reg_bits = 32,
1022 .reg_stride = 4,
1023 .val_bits = 32,
1024 .fast_io = true,
1025 };
1026
mvebu_gpio_probe_raw(struct platform_device * pdev,struct mvebu_gpio_chip * mvchip)1027 static int mvebu_gpio_probe_raw(struct platform_device *pdev,
1028 struct mvebu_gpio_chip *mvchip)
1029 {
1030 void __iomem *base;
1031
1032 base = devm_platform_ioremap_resource(pdev, 0);
1033 if (IS_ERR(base))
1034 return PTR_ERR(base);
1035
1036 mvchip->regs = devm_regmap_init_mmio(&pdev->dev, base,
1037 &mvebu_gpio_regmap_config);
1038 if (IS_ERR(mvchip->regs))
1039 return PTR_ERR(mvchip->regs);
1040
1041 /*
1042 * For the legacy SoCs, the regmap directly maps to the GPIO
1043 * registers, so no offset is needed.
1044 */
1045 mvchip->offset = 0;
1046
1047 /*
1048 * The Armada XP has a second range of registers for the
1049 * per-CPU registers
1050 */
1051 if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) {
1052 base = devm_platform_ioremap_resource(pdev, 1);
1053 if (IS_ERR(base))
1054 return PTR_ERR(base);
1055
1056 mvchip->percpu_regs =
1057 devm_regmap_init_mmio(&pdev->dev, base,
1058 &mvebu_gpio_regmap_config);
1059 if (IS_ERR(mvchip->percpu_regs))
1060 return PTR_ERR(mvchip->percpu_regs);
1061 }
1062
1063 return 0;
1064 }
1065
mvebu_gpio_probe_syscon(struct platform_device * pdev,struct mvebu_gpio_chip * mvchip)1066 static int mvebu_gpio_probe_syscon(struct platform_device *pdev,
1067 struct mvebu_gpio_chip *mvchip)
1068 {
1069 mvchip->regs = syscon_node_to_regmap(pdev->dev.parent->of_node);
1070 if (IS_ERR(mvchip->regs))
1071 return PTR_ERR(mvchip->regs);
1072
1073 if (of_property_read_u32(pdev->dev.of_node, "offset", &mvchip->offset))
1074 return -EINVAL;
1075
1076 return 0;
1077 }
1078
mvebu_gpio_probe(struct platform_device * pdev)1079 static int mvebu_gpio_probe(struct platform_device *pdev)
1080 {
1081 struct mvebu_gpio_chip *mvchip;
1082 const struct of_device_id *match;
1083 struct device_node *np = pdev->dev.of_node;
1084 struct irq_chip_generic *gc;
1085 struct irq_chip_type *ct;
1086 unsigned int ngpios;
1087 bool have_irqs;
1088 int soc_variant;
1089 int i, cpu, id;
1090 int err;
1091
1092 match = of_match_device(mvebu_gpio_of_match, &pdev->dev);
1093 if (match)
1094 soc_variant = (unsigned long) match->data;
1095 else
1096 soc_variant = MVEBU_GPIO_SOC_VARIANT_ORION;
1097
1098 /* Some gpio controllers do not provide irq support */
1099 err = platform_irq_count(pdev);
1100 if (err < 0)
1101 return err;
1102
1103 have_irqs = err != 0;
1104
1105 mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip),
1106 GFP_KERNEL);
1107 if (!mvchip)
1108 return -ENOMEM;
1109
1110 platform_set_drvdata(pdev, mvchip);
1111
1112 if (of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios)) {
1113 dev_err(&pdev->dev, "Missing ngpios OF property\n");
1114 return -ENODEV;
1115 }
1116
1117 id = of_alias_get_id(pdev->dev.of_node, "gpio");
1118 if (id < 0) {
1119 dev_err(&pdev->dev, "Couldn't get OF id\n");
1120 return id;
1121 }
1122
1123 mvchip->clk = devm_clk_get(&pdev->dev, NULL);
1124 /* Not all SoCs require a clock.*/
1125 if (!IS_ERR(mvchip->clk))
1126 clk_prepare_enable(mvchip->clk);
1127
1128 mvchip->soc_variant = soc_variant;
1129 mvchip->chip.label = dev_name(&pdev->dev);
1130 mvchip->chip.parent = &pdev->dev;
1131 mvchip->chip.request = gpiochip_generic_request;
1132 mvchip->chip.free = gpiochip_generic_free;
1133 mvchip->chip.get_direction = mvebu_gpio_get_direction;
1134 mvchip->chip.direction_input = mvebu_gpio_direction_input;
1135 mvchip->chip.get = mvebu_gpio_get;
1136 mvchip->chip.direction_output = mvebu_gpio_direction_output;
1137 mvchip->chip.set = mvebu_gpio_set;
1138 if (have_irqs)
1139 mvchip->chip.to_irq = mvebu_gpio_to_irq;
1140 mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK;
1141 mvchip->chip.ngpio = ngpios;
1142 mvchip->chip.can_sleep = false;
1143 mvchip->chip.of_node = np;
1144 mvchip->chip.dbg_show = mvebu_gpio_dbg_show;
1145
1146 if (soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K)
1147 err = mvebu_gpio_probe_syscon(pdev, mvchip);
1148 else
1149 err = mvebu_gpio_probe_raw(pdev, mvchip);
1150
1151 if (err)
1152 return err;
1153
1154 /*
1155 * Mask and clear GPIO interrupts.
1156 */
1157 switch (soc_variant) {
1158 case MVEBU_GPIO_SOC_VARIANT_ORION:
1159 case MVEBU_GPIO_SOC_VARIANT_A8K:
1160 regmap_write(mvchip->regs,
1161 GPIO_EDGE_CAUSE_OFF + mvchip->offset, 0);
1162 regmap_write(mvchip->regs,
1163 GPIO_EDGE_MASK_OFF + mvchip->offset, 0);
1164 regmap_write(mvchip->regs,
1165 GPIO_LEVEL_MASK_OFF + mvchip->offset, 0);
1166 break;
1167 case MVEBU_GPIO_SOC_VARIANT_MV78200:
1168 regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0);
1169 for (cpu = 0; cpu < 2; cpu++) {
1170 regmap_write(mvchip->regs,
1171 GPIO_EDGE_MASK_MV78200_OFF(cpu), 0);
1172 regmap_write(mvchip->regs,
1173 GPIO_LEVEL_MASK_MV78200_OFF(cpu), 0);
1174 }
1175 break;
1176 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
1177 regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0);
1178 regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF, 0);
1179 regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF, 0);
1180 for (cpu = 0; cpu < 4; cpu++) {
1181 regmap_write(mvchip->percpu_regs,
1182 GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu), 0);
1183 regmap_write(mvchip->percpu_regs,
1184 GPIO_EDGE_MASK_ARMADAXP_OFF(cpu), 0);
1185 regmap_write(mvchip->percpu_regs,
1186 GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu), 0);
1187 }
1188 break;
1189 default:
1190 BUG();
1191 }
1192
1193 devm_gpiochip_add_data(&pdev->dev, &mvchip->chip, mvchip);
1194
1195 /* Some MVEBU SoCs have simple PWM support for GPIO lines */
1196 if (IS_ENABLED(CONFIG_PWM)) {
1197 err = mvebu_pwm_probe(pdev, mvchip, id);
1198 if (err)
1199 return err;
1200 }
1201
1202 /* Some gpio controllers do not provide irq support */
1203 if (!have_irqs)
1204 return 0;
1205
1206 mvchip->domain =
1207 irq_domain_add_linear(np, ngpios, &irq_generic_chip_ops, NULL);
1208 if (!mvchip->domain) {
1209 dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n",
1210 mvchip->chip.label);
1211 err = -ENODEV;
1212 goto err_pwm;
1213 }
1214
1215 err = irq_alloc_domain_generic_chips(
1216 mvchip->domain, ngpios, 2, np->name, handle_level_irq,
1217 IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_LEVEL, 0, 0);
1218 if (err) {
1219 dev_err(&pdev->dev, "couldn't allocate irq chips %s (DT).\n",
1220 mvchip->chip.label);
1221 goto err_domain;
1222 }
1223
1224 /*
1225 * NOTE: The common accessors cannot be used because of the percpu
1226 * access to the mask registers
1227 */
1228 gc = irq_get_domain_generic_chip(mvchip->domain, 0);
1229 gc->private = mvchip;
1230 ct = &gc->chip_types[0];
1231 ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
1232 ct->chip.irq_mask = mvebu_gpio_level_irq_mask;
1233 ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask;
1234 ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
1235 ct->chip.name = mvchip->chip.label;
1236
1237 ct = &gc->chip_types[1];
1238 ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
1239 ct->chip.irq_ack = mvebu_gpio_irq_ack;
1240 ct->chip.irq_mask = mvebu_gpio_edge_irq_mask;
1241 ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask;
1242 ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
1243 ct->handler = handle_edge_irq;
1244 ct->chip.name = mvchip->chip.label;
1245
1246 /*
1247 * Setup the interrupt handlers. Each chip can have up to 4
1248 * interrupt handlers, with each handler dealing with 8 GPIO
1249 * pins.
1250 */
1251 for (i = 0; i < 4; i++) {
1252 int irq = platform_get_irq_optional(pdev, i);
1253
1254 if (irq < 0)
1255 continue;
1256 irq_set_chained_handler_and_data(irq, mvebu_gpio_irq_handler,
1257 mvchip);
1258 }
1259
1260 return 0;
1261
1262 err_domain:
1263 irq_domain_remove(mvchip->domain);
1264 err_pwm:
1265 pwmchip_remove(&mvchip->mvpwm->chip);
1266
1267 return err;
1268 }
1269
1270 static struct platform_driver mvebu_gpio_driver = {
1271 .driver = {
1272 .name = "mvebu-gpio",
1273 .of_match_table = mvebu_gpio_of_match,
1274 },
1275 .probe = mvebu_gpio_probe,
1276 .suspend = mvebu_gpio_suspend,
1277 .resume = mvebu_gpio_resume,
1278 };
1279 builtin_platform_driver(mvebu_gpio_driver);
1280