1 /*
2 * Copyright 2015-2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <linux/pci.h>
24 #include <linux/acpi.h>
25 #include "kfd_crat.h"
26 #include "kfd_priv.h"
27 #include "kfd_topology.h"
28 #include "kfd_iommu.h"
29 #include "amdgpu_amdkfd.h"
30
31 /* GPU Processor ID base for dGPUs for which VCRAT needs to be created.
32 * GPU processor ID are expressed with Bit[31]=1.
33 * The base is set to 0x8000_0000 + 0x1000 to avoid collision with GPU IDs
34 * used in the CRAT.
35 */
36 static uint32_t gpu_processor_id_low = 0x80001000;
37
38 /* Return the next available gpu_processor_id and increment it for next GPU
39 * @total_cu_count - Total CUs present in the GPU including ones
40 * masked off
41 */
get_and_inc_gpu_processor_id(unsigned int total_cu_count)42 static inline unsigned int get_and_inc_gpu_processor_id(
43 unsigned int total_cu_count)
44 {
45 int current_id = gpu_processor_id_low;
46
47 gpu_processor_id_low += total_cu_count;
48 return current_id;
49 }
50
51 /* Static table to describe GPU Cache information */
52 struct kfd_gpu_cache_info {
53 uint32_t cache_size;
54 uint32_t cache_level;
55 uint32_t flags;
56 /* Indicates how many Compute Units share this cache
57 * Value = 1 indicates the cache is not shared
58 */
59 uint32_t num_cu_shared;
60 };
61
62 static struct kfd_gpu_cache_info kaveri_cache_info[] = {
63 {
64 /* TCP L1 Cache per CU */
65 .cache_size = 16,
66 .cache_level = 1,
67 .flags = (CRAT_CACHE_FLAGS_ENABLED |
68 CRAT_CACHE_FLAGS_DATA_CACHE |
69 CRAT_CACHE_FLAGS_SIMD_CACHE),
70 .num_cu_shared = 1,
71
72 },
73 {
74 /* Scalar L1 Instruction Cache (in SQC module) per bank */
75 .cache_size = 16,
76 .cache_level = 1,
77 .flags = (CRAT_CACHE_FLAGS_ENABLED |
78 CRAT_CACHE_FLAGS_INST_CACHE |
79 CRAT_CACHE_FLAGS_SIMD_CACHE),
80 .num_cu_shared = 2,
81 },
82 {
83 /* Scalar L1 Data Cache (in SQC module) per bank */
84 .cache_size = 8,
85 .cache_level = 1,
86 .flags = (CRAT_CACHE_FLAGS_ENABLED |
87 CRAT_CACHE_FLAGS_DATA_CACHE |
88 CRAT_CACHE_FLAGS_SIMD_CACHE),
89 .num_cu_shared = 2,
90 },
91
92 /* TODO: Add L2 Cache information */
93 };
94
95
96 static struct kfd_gpu_cache_info carrizo_cache_info[] = {
97 {
98 /* TCP L1 Cache per CU */
99 .cache_size = 16,
100 .cache_level = 1,
101 .flags = (CRAT_CACHE_FLAGS_ENABLED |
102 CRAT_CACHE_FLAGS_DATA_CACHE |
103 CRAT_CACHE_FLAGS_SIMD_CACHE),
104 .num_cu_shared = 1,
105 },
106 {
107 /* Scalar L1 Instruction Cache (in SQC module) per bank */
108 .cache_size = 8,
109 .cache_level = 1,
110 .flags = (CRAT_CACHE_FLAGS_ENABLED |
111 CRAT_CACHE_FLAGS_INST_CACHE |
112 CRAT_CACHE_FLAGS_SIMD_CACHE),
113 .num_cu_shared = 4,
114 },
115 {
116 /* Scalar L1 Data Cache (in SQC module) per bank. */
117 .cache_size = 4,
118 .cache_level = 1,
119 .flags = (CRAT_CACHE_FLAGS_ENABLED |
120 CRAT_CACHE_FLAGS_DATA_CACHE |
121 CRAT_CACHE_FLAGS_SIMD_CACHE),
122 .num_cu_shared = 4,
123 },
124
125 /* TODO: Add L2 Cache information */
126 };
127
128 /* NOTE: In future if more information is added to struct kfd_gpu_cache_info
129 * the following ASICs may need a separate table.
130 */
131 #define hawaii_cache_info kaveri_cache_info
132 #define tonga_cache_info carrizo_cache_info
133 #define fiji_cache_info carrizo_cache_info
134 #define polaris10_cache_info carrizo_cache_info
135 #define polaris11_cache_info carrizo_cache_info
136 #define polaris12_cache_info carrizo_cache_info
137 #define vegam_cache_info carrizo_cache_info
138 /* TODO - check & update Vega10 cache details */
139 #define vega10_cache_info carrizo_cache_info
140 #define raven_cache_info carrizo_cache_info
141 #define renoir_cache_info carrizo_cache_info
142 /* TODO - check & update Navi10 cache details */
143 #define navi10_cache_info carrizo_cache_info
144
kfd_populated_cu_info_cpu(struct kfd_topology_device * dev,struct crat_subtype_computeunit * cu)145 static void kfd_populated_cu_info_cpu(struct kfd_topology_device *dev,
146 struct crat_subtype_computeunit *cu)
147 {
148 dev->node_props.cpu_cores_count = cu->num_cpu_cores;
149 dev->node_props.cpu_core_id_base = cu->processor_id_low;
150 if (cu->hsa_capability & CRAT_CU_FLAGS_IOMMU_PRESENT)
151 dev->node_props.capability |= HSA_CAP_ATS_PRESENT;
152
153 pr_debug("CU CPU: cores=%d id_base=%d\n", cu->num_cpu_cores,
154 cu->processor_id_low);
155 }
156
kfd_populated_cu_info_gpu(struct kfd_topology_device * dev,struct crat_subtype_computeunit * cu)157 static void kfd_populated_cu_info_gpu(struct kfd_topology_device *dev,
158 struct crat_subtype_computeunit *cu)
159 {
160 dev->node_props.simd_id_base = cu->processor_id_low;
161 dev->node_props.simd_count = cu->num_simd_cores;
162 dev->node_props.lds_size_in_kb = cu->lds_size_in_kb;
163 dev->node_props.max_waves_per_simd = cu->max_waves_simd;
164 dev->node_props.wave_front_size = cu->wave_front_size;
165 dev->node_props.array_count = cu->array_count;
166 dev->node_props.cu_per_simd_array = cu->num_cu_per_array;
167 dev->node_props.simd_per_cu = cu->num_simd_per_cu;
168 dev->node_props.max_slots_scratch_cu = cu->max_slots_scatch_cu;
169 if (cu->hsa_capability & CRAT_CU_FLAGS_HOT_PLUGGABLE)
170 dev->node_props.capability |= HSA_CAP_HOT_PLUGGABLE;
171 pr_debug("CU GPU: id_base=%d\n", cu->processor_id_low);
172 }
173
174 /* kfd_parse_subtype_cu - parse compute unit subtypes and attach it to correct
175 * topology device present in the device_list
176 */
kfd_parse_subtype_cu(struct crat_subtype_computeunit * cu,struct list_head * device_list)177 static int kfd_parse_subtype_cu(struct crat_subtype_computeunit *cu,
178 struct list_head *device_list)
179 {
180 struct kfd_topology_device *dev;
181
182 pr_debug("Found CU entry in CRAT table with proximity_domain=%d caps=%x\n",
183 cu->proximity_domain, cu->hsa_capability);
184 list_for_each_entry(dev, device_list, list) {
185 if (cu->proximity_domain == dev->proximity_domain) {
186 if (cu->flags & CRAT_CU_FLAGS_CPU_PRESENT)
187 kfd_populated_cu_info_cpu(dev, cu);
188
189 if (cu->flags & CRAT_CU_FLAGS_GPU_PRESENT)
190 kfd_populated_cu_info_gpu(dev, cu);
191 break;
192 }
193 }
194
195 return 0;
196 }
197
198 static struct kfd_mem_properties *
find_subtype_mem(uint32_t heap_type,uint32_t flags,uint32_t width,struct kfd_topology_device * dev)199 find_subtype_mem(uint32_t heap_type, uint32_t flags, uint32_t width,
200 struct kfd_topology_device *dev)
201 {
202 struct kfd_mem_properties *props;
203
204 list_for_each_entry(props, &dev->mem_props, list) {
205 if (props->heap_type == heap_type
206 && props->flags == flags
207 && props->width == width)
208 return props;
209 }
210
211 return NULL;
212 }
213 /* kfd_parse_subtype_mem - parse memory subtypes and attach it to correct
214 * topology device present in the device_list
215 */
kfd_parse_subtype_mem(struct crat_subtype_memory * mem,struct list_head * device_list)216 static int kfd_parse_subtype_mem(struct crat_subtype_memory *mem,
217 struct list_head *device_list)
218 {
219 struct kfd_mem_properties *props;
220 struct kfd_topology_device *dev;
221 uint32_t heap_type;
222 uint64_t size_in_bytes;
223 uint32_t flags = 0;
224 uint32_t width;
225
226 pr_debug("Found memory entry in CRAT table with proximity_domain=%d\n",
227 mem->proximity_domain);
228 list_for_each_entry(dev, device_list, list) {
229 if (mem->proximity_domain == dev->proximity_domain) {
230 /* We're on GPU node */
231 if (dev->node_props.cpu_cores_count == 0) {
232 /* APU */
233 if (mem->visibility_type == 0)
234 heap_type =
235 HSA_MEM_HEAP_TYPE_FB_PRIVATE;
236 /* dGPU */
237 else
238 heap_type = mem->visibility_type;
239 } else
240 heap_type = HSA_MEM_HEAP_TYPE_SYSTEM;
241
242 if (mem->flags & CRAT_MEM_FLAGS_HOT_PLUGGABLE)
243 flags |= HSA_MEM_FLAGS_HOT_PLUGGABLE;
244 if (mem->flags & CRAT_MEM_FLAGS_NON_VOLATILE)
245 flags |= HSA_MEM_FLAGS_NON_VOLATILE;
246
247 size_in_bytes =
248 ((uint64_t)mem->length_high << 32) +
249 mem->length_low;
250 width = mem->width;
251
252 /* Multiple banks of the same type are aggregated into
253 * one. User mode doesn't care about multiple physical
254 * memory segments. It's managed as a single virtual
255 * heap for user mode.
256 */
257 props = find_subtype_mem(heap_type, flags, width, dev);
258 if (props) {
259 props->size_in_bytes += size_in_bytes;
260 break;
261 }
262
263 props = kfd_alloc_struct(props);
264 if (!props)
265 return -ENOMEM;
266
267 props->heap_type = heap_type;
268 props->flags = flags;
269 props->size_in_bytes = size_in_bytes;
270 props->width = width;
271
272 dev->node_props.mem_banks_count++;
273 list_add_tail(&props->list, &dev->mem_props);
274
275 break;
276 }
277 }
278
279 return 0;
280 }
281
282 /* kfd_parse_subtype_cache - parse cache subtypes and attach it to correct
283 * topology device present in the device_list
284 */
kfd_parse_subtype_cache(struct crat_subtype_cache * cache,struct list_head * device_list)285 static int kfd_parse_subtype_cache(struct crat_subtype_cache *cache,
286 struct list_head *device_list)
287 {
288 struct kfd_cache_properties *props;
289 struct kfd_topology_device *dev;
290 uint32_t id;
291 uint32_t total_num_of_cu;
292
293 id = cache->processor_id_low;
294
295 pr_debug("Found cache entry in CRAT table with processor_id=%d\n", id);
296 list_for_each_entry(dev, device_list, list) {
297 total_num_of_cu = (dev->node_props.array_count *
298 dev->node_props.cu_per_simd_array);
299
300 /* Cache infomration in CRAT doesn't have proximity_domain
301 * information as it is associated with a CPU core or GPU
302 * Compute Unit. So map the cache using CPU core Id or SIMD
303 * (GPU) ID.
304 * TODO: This works because currently we can safely assume that
305 * Compute Units are parsed before caches are parsed. In
306 * future, remove this dependency
307 */
308 if ((id >= dev->node_props.cpu_core_id_base &&
309 id <= dev->node_props.cpu_core_id_base +
310 dev->node_props.cpu_cores_count) ||
311 (id >= dev->node_props.simd_id_base &&
312 id < dev->node_props.simd_id_base +
313 total_num_of_cu)) {
314 props = kfd_alloc_struct(props);
315 if (!props)
316 return -ENOMEM;
317
318 props->processor_id_low = id;
319 props->cache_level = cache->cache_level;
320 props->cache_size = cache->cache_size;
321 props->cacheline_size = cache->cache_line_size;
322 props->cachelines_per_tag = cache->lines_per_tag;
323 props->cache_assoc = cache->associativity;
324 props->cache_latency = cache->cache_latency;
325 memcpy(props->sibling_map, cache->sibling_map,
326 sizeof(props->sibling_map));
327
328 if (cache->flags & CRAT_CACHE_FLAGS_DATA_CACHE)
329 props->cache_type |= HSA_CACHE_TYPE_DATA;
330 if (cache->flags & CRAT_CACHE_FLAGS_INST_CACHE)
331 props->cache_type |= HSA_CACHE_TYPE_INSTRUCTION;
332 if (cache->flags & CRAT_CACHE_FLAGS_CPU_CACHE)
333 props->cache_type |= HSA_CACHE_TYPE_CPU;
334 if (cache->flags & CRAT_CACHE_FLAGS_SIMD_CACHE)
335 props->cache_type |= HSA_CACHE_TYPE_HSACU;
336
337 dev->cache_count++;
338 dev->node_props.caches_count++;
339 list_add_tail(&props->list, &dev->cache_props);
340
341 break;
342 }
343 }
344
345 return 0;
346 }
347
348 /* kfd_parse_subtype_iolink - parse iolink subtypes and attach it to correct
349 * topology device present in the device_list
350 */
kfd_parse_subtype_iolink(struct crat_subtype_iolink * iolink,struct list_head * device_list)351 static int kfd_parse_subtype_iolink(struct crat_subtype_iolink *iolink,
352 struct list_head *device_list)
353 {
354 struct kfd_iolink_properties *props = NULL, *props2;
355 struct kfd_topology_device *dev, *to_dev;
356 uint32_t id_from;
357 uint32_t id_to;
358
359 id_from = iolink->proximity_domain_from;
360 id_to = iolink->proximity_domain_to;
361
362 pr_debug("Found IO link entry in CRAT table with id_from=%d, id_to %d\n",
363 id_from, id_to);
364 list_for_each_entry(dev, device_list, list) {
365 if (id_from == dev->proximity_domain) {
366 props = kfd_alloc_struct(props);
367 if (!props)
368 return -ENOMEM;
369
370 props->node_from = id_from;
371 props->node_to = id_to;
372 props->ver_maj = iolink->version_major;
373 props->ver_min = iolink->version_minor;
374 props->iolink_type = iolink->io_interface_type;
375
376 if (props->iolink_type == CRAT_IOLINK_TYPE_PCIEXPRESS)
377 props->weight = 20;
378 else if (props->iolink_type == CRAT_IOLINK_TYPE_XGMI)
379 props->weight = 15 * iolink->num_hops_xgmi;
380 else
381 props->weight = node_distance(id_from, id_to);
382
383 props->min_latency = iolink->minimum_latency;
384 props->max_latency = iolink->maximum_latency;
385 props->min_bandwidth = iolink->minimum_bandwidth_mbs;
386 props->max_bandwidth = iolink->maximum_bandwidth_mbs;
387 props->rec_transfer_size =
388 iolink->recommended_transfer_size;
389
390 dev->io_link_count++;
391 dev->node_props.io_links_count++;
392 list_add_tail(&props->list, &dev->io_link_props);
393 break;
394 }
395 }
396
397 /* CPU topology is created before GPUs are detected, so CPU->GPU
398 * links are not built at that time. If a PCIe type is discovered, it
399 * means a GPU is detected and we are adding GPU->CPU to the topology.
400 * At this time, also add the corresponded CPU->GPU link if GPU
401 * is large bar.
402 * For xGMI, we only added the link with one direction in the crat
403 * table, add corresponded reversed direction link now.
404 */
405 if (props && (iolink->flags & CRAT_IOLINK_FLAGS_BI_DIRECTIONAL)) {
406 to_dev = kfd_topology_device_by_proximity_domain(id_to);
407 if (!to_dev)
408 return -ENODEV;
409 /* same everything but the other direction */
410 props2 = kmemdup(props, sizeof(*props2), GFP_KERNEL);
411 if (!props2)
412 return -ENOMEM;
413
414 props2->node_from = id_to;
415 props2->node_to = id_from;
416 props2->kobj = NULL;
417 to_dev->io_link_count++;
418 to_dev->node_props.io_links_count++;
419 list_add_tail(&props2->list, &to_dev->io_link_props);
420 }
421
422 return 0;
423 }
424
425 /* kfd_parse_subtype - parse subtypes and attach it to correct topology device
426 * present in the device_list
427 * @sub_type_hdr - subtype section of crat_image
428 * @device_list - list of topology devices present in this crat_image
429 */
kfd_parse_subtype(struct crat_subtype_generic * sub_type_hdr,struct list_head * device_list)430 static int kfd_parse_subtype(struct crat_subtype_generic *sub_type_hdr,
431 struct list_head *device_list)
432 {
433 struct crat_subtype_computeunit *cu;
434 struct crat_subtype_memory *mem;
435 struct crat_subtype_cache *cache;
436 struct crat_subtype_iolink *iolink;
437 int ret = 0;
438
439 switch (sub_type_hdr->type) {
440 case CRAT_SUBTYPE_COMPUTEUNIT_AFFINITY:
441 cu = (struct crat_subtype_computeunit *)sub_type_hdr;
442 ret = kfd_parse_subtype_cu(cu, device_list);
443 break;
444 case CRAT_SUBTYPE_MEMORY_AFFINITY:
445 mem = (struct crat_subtype_memory *)sub_type_hdr;
446 ret = kfd_parse_subtype_mem(mem, device_list);
447 break;
448 case CRAT_SUBTYPE_CACHE_AFFINITY:
449 cache = (struct crat_subtype_cache *)sub_type_hdr;
450 ret = kfd_parse_subtype_cache(cache, device_list);
451 break;
452 case CRAT_SUBTYPE_TLB_AFFINITY:
453 /*
454 * For now, nothing to do here
455 */
456 pr_debug("Found TLB entry in CRAT table (not processing)\n");
457 break;
458 case CRAT_SUBTYPE_CCOMPUTE_AFFINITY:
459 /*
460 * For now, nothing to do here
461 */
462 pr_debug("Found CCOMPUTE entry in CRAT table (not processing)\n");
463 break;
464 case CRAT_SUBTYPE_IOLINK_AFFINITY:
465 iolink = (struct crat_subtype_iolink *)sub_type_hdr;
466 ret = kfd_parse_subtype_iolink(iolink, device_list);
467 break;
468 default:
469 pr_warn("Unknown subtype %d in CRAT\n",
470 sub_type_hdr->type);
471 }
472
473 return ret;
474 }
475
476 /* kfd_parse_crat_table - parse CRAT table. For each node present in CRAT
477 * create a kfd_topology_device and add in to device_list. Also parse
478 * CRAT subtypes and attach it to appropriate kfd_topology_device
479 * @crat_image - input image containing CRAT
480 * @device_list - [OUT] list of kfd_topology_device generated after
481 * parsing crat_image
482 * @proximity_domain - Proximity domain of the first device in the table
483 *
484 * Return - 0 if successful else -ve value
485 */
kfd_parse_crat_table(void * crat_image,struct list_head * device_list,uint32_t proximity_domain)486 int kfd_parse_crat_table(void *crat_image, struct list_head *device_list,
487 uint32_t proximity_domain)
488 {
489 struct kfd_topology_device *top_dev = NULL;
490 struct crat_subtype_generic *sub_type_hdr;
491 uint16_t node_id;
492 int ret = 0;
493 struct crat_header *crat_table = (struct crat_header *)crat_image;
494 uint16_t num_nodes;
495 uint32_t image_len;
496
497 if (!crat_image)
498 return -EINVAL;
499
500 if (!list_empty(device_list)) {
501 pr_warn("Error device list should be empty\n");
502 return -EINVAL;
503 }
504
505 num_nodes = crat_table->num_domains;
506 image_len = crat_table->length;
507
508 pr_debug("Parsing CRAT table with %d nodes\n", num_nodes);
509
510 for (node_id = 0; node_id < num_nodes; node_id++) {
511 top_dev = kfd_create_topology_device(device_list);
512 if (!top_dev)
513 break;
514 top_dev->proximity_domain = proximity_domain++;
515 }
516
517 if (!top_dev) {
518 ret = -ENOMEM;
519 goto err;
520 }
521
522 memcpy(top_dev->oem_id, crat_table->oem_id, CRAT_OEMID_LENGTH);
523 memcpy(top_dev->oem_table_id, crat_table->oem_table_id,
524 CRAT_OEMTABLEID_LENGTH);
525 top_dev->oem_revision = crat_table->oem_revision;
526
527 sub_type_hdr = (struct crat_subtype_generic *)(crat_table+1);
528 while ((char *)sub_type_hdr + sizeof(struct crat_subtype_generic) <
529 ((char *)crat_image) + image_len) {
530 if (sub_type_hdr->flags & CRAT_SUBTYPE_FLAGS_ENABLED) {
531 ret = kfd_parse_subtype(sub_type_hdr, device_list);
532 if (ret)
533 break;
534 }
535
536 sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr +
537 sub_type_hdr->length);
538 }
539
540 err:
541 if (ret)
542 kfd_release_topology_device_list(device_list);
543
544 return ret;
545 }
546
547 /* Helper function. See kfd_fill_gpu_cache_info for parameter description */
fill_in_pcache(struct crat_subtype_cache * pcache,struct kfd_gpu_cache_info * pcache_info,struct kfd_cu_info * cu_info,int mem_available,int cu_bitmask,int cache_type,unsigned int cu_processor_id,int cu_block)548 static int fill_in_pcache(struct crat_subtype_cache *pcache,
549 struct kfd_gpu_cache_info *pcache_info,
550 struct kfd_cu_info *cu_info,
551 int mem_available,
552 int cu_bitmask,
553 int cache_type, unsigned int cu_processor_id,
554 int cu_block)
555 {
556 unsigned int cu_sibling_map_mask;
557 int first_active_cu;
558
559 /* First check if enough memory is available */
560 if (sizeof(struct crat_subtype_cache) > mem_available)
561 return -ENOMEM;
562
563 cu_sibling_map_mask = cu_bitmask;
564 cu_sibling_map_mask >>= cu_block;
565 cu_sibling_map_mask &=
566 ((1 << pcache_info[cache_type].num_cu_shared) - 1);
567 first_active_cu = ffs(cu_sibling_map_mask);
568
569 /* CU could be inactive. In case of shared cache find the first active
570 * CU. and incase of non-shared cache check if the CU is inactive. If
571 * inactive active skip it
572 */
573 if (first_active_cu) {
574 memset(pcache, 0, sizeof(struct crat_subtype_cache));
575 pcache->type = CRAT_SUBTYPE_CACHE_AFFINITY;
576 pcache->length = sizeof(struct crat_subtype_cache);
577 pcache->flags = pcache_info[cache_type].flags;
578 pcache->processor_id_low = cu_processor_id
579 + (first_active_cu - 1);
580 pcache->cache_level = pcache_info[cache_type].cache_level;
581 pcache->cache_size = pcache_info[cache_type].cache_size;
582
583 /* Sibling map is w.r.t processor_id_low, so shift out
584 * inactive CU
585 */
586 cu_sibling_map_mask =
587 cu_sibling_map_mask >> (first_active_cu - 1);
588
589 pcache->sibling_map[0] = (uint8_t)(cu_sibling_map_mask & 0xFF);
590 pcache->sibling_map[1] =
591 (uint8_t)((cu_sibling_map_mask >> 8) & 0xFF);
592 pcache->sibling_map[2] =
593 (uint8_t)((cu_sibling_map_mask >> 16) & 0xFF);
594 pcache->sibling_map[3] =
595 (uint8_t)((cu_sibling_map_mask >> 24) & 0xFF);
596 return 0;
597 }
598 return 1;
599 }
600
601 /* kfd_fill_gpu_cache_info - Fill GPU cache info using kfd_gpu_cache_info
602 * tables
603 *
604 * @kdev - [IN] GPU device
605 * @gpu_processor_id - [IN] GPU processor ID to which these caches
606 * associate
607 * @available_size - [IN] Amount of memory available in pcache
608 * @cu_info - [IN] Compute Unit info obtained from KGD
609 * @pcache - [OUT] memory into which cache data is to be filled in.
610 * @size_filled - [OUT] amount of data used up in pcache.
611 * @num_of_entries - [OUT] number of caches added
612 */
kfd_fill_gpu_cache_info(struct kfd_dev * kdev,int gpu_processor_id,int available_size,struct kfd_cu_info * cu_info,struct crat_subtype_cache * pcache,int * size_filled,int * num_of_entries)613 static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev,
614 int gpu_processor_id,
615 int available_size,
616 struct kfd_cu_info *cu_info,
617 struct crat_subtype_cache *pcache,
618 int *size_filled,
619 int *num_of_entries)
620 {
621 struct kfd_gpu_cache_info *pcache_info;
622 int num_of_cache_types = 0;
623 int i, j, k;
624 int ct = 0;
625 int mem_available = available_size;
626 unsigned int cu_processor_id;
627 int ret;
628
629 switch (kdev->device_info->asic_family) {
630 case CHIP_KAVERI:
631 pcache_info = kaveri_cache_info;
632 num_of_cache_types = ARRAY_SIZE(kaveri_cache_info);
633 break;
634 case CHIP_HAWAII:
635 pcache_info = hawaii_cache_info;
636 num_of_cache_types = ARRAY_SIZE(hawaii_cache_info);
637 break;
638 case CHIP_CARRIZO:
639 pcache_info = carrizo_cache_info;
640 num_of_cache_types = ARRAY_SIZE(carrizo_cache_info);
641 break;
642 case CHIP_TONGA:
643 pcache_info = tonga_cache_info;
644 num_of_cache_types = ARRAY_SIZE(tonga_cache_info);
645 break;
646 case CHIP_FIJI:
647 pcache_info = fiji_cache_info;
648 num_of_cache_types = ARRAY_SIZE(fiji_cache_info);
649 break;
650 case CHIP_POLARIS10:
651 pcache_info = polaris10_cache_info;
652 num_of_cache_types = ARRAY_SIZE(polaris10_cache_info);
653 break;
654 case CHIP_POLARIS11:
655 pcache_info = polaris11_cache_info;
656 num_of_cache_types = ARRAY_SIZE(polaris11_cache_info);
657 break;
658 case CHIP_POLARIS12:
659 pcache_info = polaris12_cache_info;
660 num_of_cache_types = ARRAY_SIZE(polaris12_cache_info);
661 break;
662 case CHIP_VEGAM:
663 pcache_info = vegam_cache_info;
664 num_of_cache_types = ARRAY_SIZE(vegam_cache_info);
665 break;
666 case CHIP_VEGA10:
667 case CHIP_VEGA12:
668 case CHIP_VEGA20:
669 case CHIP_ARCTURUS:
670 pcache_info = vega10_cache_info;
671 num_of_cache_types = ARRAY_SIZE(vega10_cache_info);
672 break;
673 case CHIP_RAVEN:
674 pcache_info = raven_cache_info;
675 num_of_cache_types = ARRAY_SIZE(raven_cache_info);
676 break;
677 case CHIP_RENOIR:
678 pcache_info = renoir_cache_info;
679 num_of_cache_types = ARRAY_SIZE(renoir_cache_info);
680 break;
681 case CHIP_NAVI10:
682 case CHIP_NAVI12:
683 case CHIP_NAVI14:
684 case CHIP_SIENNA_CICHLID:
685 case CHIP_NAVY_FLOUNDER:
686 pcache_info = navi10_cache_info;
687 num_of_cache_types = ARRAY_SIZE(navi10_cache_info);
688 break;
689 default:
690 return -EINVAL;
691 }
692
693 *size_filled = 0;
694 *num_of_entries = 0;
695
696 /* For each type of cache listed in the kfd_gpu_cache_info table,
697 * go through all available Compute Units.
698 * The [i,j,k] loop will
699 * if kfd_gpu_cache_info.num_cu_shared = 1
700 * will parse through all available CU
701 * If (kfd_gpu_cache_info.num_cu_shared != 1)
702 * then it will consider only one CU from
703 * the shared unit
704 */
705
706 for (ct = 0; ct < num_of_cache_types; ct++) {
707 cu_processor_id = gpu_processor_id;
708 for (i = 0; i < cu_info->num_shader_engines; i++) {
709 for (j = 0; j < cu_info->num_shader_arrays_per_engine;
710 j++) {
711 for (k = 0; k < cu_info->num_cu_per_sh;
712 k += pcache_info[ct].num_cu_shared) {
713
714 ret = fill_in_pcache(pcache,
715 pcache_info,
716 cu_info,
717 mem_available,
718 cu_info->cu_bitmap[i % 4][j + i / 4],
719 ct,
720 cu_processor_id,
721 k);
722
723 if (ret < 0)
724 break;
725
726 if (!ret) {
727 pcache++;
728 (*num_of_entries)++;
729 mem_available -=
730 sizeof(*pcache);
731 (*size_filled) +=
732 sizeof(*pcache);
733 }
734
735 /* Move to next CU block */
736 cu_processor_id +=
737 pcache_info[ct].num_cu_shared;
738 }
739 }
740 }
741 }
742
743 pr_debug("Added [%d] GPU cache entries\n", *num_of_entries);
744
745 return 0;
746 }
747
kfd_ignore_crat(void)748 static bool kfd_ignore_crat(void)
749 {
750 bool ret;
751
752 if (ignore_crat)
753 return true;
754
755 #ifndef KFD_SUPPORT_IOMMU_V2
756 ret = true;
757 #else
758 ret = false;
759 #endif
760
761 return ret;
762 }
763
764 /*
765 * kfd_create_crat_image_acpi - Allocates memory for CRAT image and
766 * copies CRAT from ACPI (if available).
767 * NOTE: Call kfd_destroy_crat_image to free CRAT image memory
768 *
769 * @crat_image: CRAT read from ACPI. If no CRAT in ACPI then
770 * crat_image will be NULL
771 * @size: [OUT] size of crat_image
772 *
773 * Return 0 if successful else return error code
774 */
kfd_create_crat_image_acpi(void ** crat_image,size_t * size)775 int kfd_create_crat_image_acpi(void **crat_image, size_t *size)
776 {
777 struct acpi_table_header *crat_table;
778 acpi_status status;
779 void *pcrat_image;
780 int rc = 0;
781
782 if (!crat_image)
783 return -EINVAL;
784
785 *crat_image = NULL;
786
787 /* Fetch the CRAT table from ACPI */
788 status = acpi_get_table(CRAT_SIGNATURE, 0, &crat_table);
789 if (status == AE_NOT_FOUND) {
790 pr_warn("CRAT table not found\n");
791 return -ENODATA;
792 } else if (ACPI_FAILURE(status)) {
793 const char *err = acpi_format_exception(status);
794
795 pr_err("CRAT table error: %s\n", err);
796 return -EINVAL;
797 }
798
799 if (kfd_ignore_crat()) {
800 pr_info("CRAT table disabled by module option\n");
801 return -ENODATA;
802 }
803
804 pcrat_image = kvmalloc(crat_table->length, GFP_KERNEL);
805 if (!pcrat_image) {
806 rc = -ENOMEM;
807 goto out;
808 }
809
810 memcpy(pcrat_image, crat_table, crat_table->length);
811 *crat_image = pcrat_image;
812 *size = crat_table->length;
813 out:
814 acpi_put_table(crat_table);
815 return rc;
816 }
817
818 /* Memory required to create Virtual CRAT.
819 * Since there is no easy way to predict the amount of memory required, the
820 * following amount is allocated for GPU Virtual CRAT. This is
821 * expected to cover all known conditions. But to be safe additional check
822 * is put in the code to ensure we don't overwrite.
823 */
824 #define VCRAT_SIZE_FOR_GPU (4 * PAGE_SIZE)
825
826 /* kfd_fill_cu_for_cpu - Fill in Compute info for the given CPU NUMA node
827 *
828 * @numa_node_id: CPU NUMA node id
829 * @avail_size: Available size in the memory
830 * @sub_type_hdr: Memory into which compute info will be filled in
831 *
832 * Return 0 if successful else return -ve value
833 */
kfd_fill_cu_for_cpu(int numa_node_id,int * avail_size,int proximity_domain,struct crat_subtype_computeunit * sub_type_hdr)834 static int kfd_fill_cu_for_cpu(int numa_node_id, int *avail_size,
835 int proximity_domain,
836 struct crat_subtype_computeunit *sub_type_hdr)
837 {
838 const struct cpumask *cpumask;
839
840 *avail_size -= sizeof(struct crat_subtype_computeunit);
841 if (*avail_size < 0)
842 return -ENOMEM;
843
844 memset(sub_type_hdr, 0, sizeof(struct crat_subtype_computeunit));
845
846 /* Fill in subtype header data */
847 sub_type_hdr->type = CRAT_SUBTYPE_COMPUTEUNIT_AFFINITY;
848 sub_type_hdr->length = sizeof(struct crat_subtype_computeunit);
849 sub_type_hdr->flags = CRAT_SUBTYPE_FLAGS_ENABLED;
850
851 cpumask = cpumask_of_node(numa_node_id);
852
853 /* Fill in CU data */
854 sub_type_hdr->flags |= CRAT_CU_FLAGS_CPU_PRESENT;
855 sub_type_hdr->proximity_domain = proximity_domain;
856 sub_type_hdr->processor_id_low = kfd_numa_node_to_apic_id(numa_node_id);
857 if (sub_type_hdr->processor_id_low == -1)
858 return -EINVAL;
859
860 sub_type_hdr->num_cpu_cores = cpumask_weight(cpumask);
861
862 return 0;
863 }
864
865 /* kfd_fill_mem_info_for_cpu - Fill in Memory info for the given CPU NUMA node
866 *
867 * @numa_node_id: CPU NUMA node id
868 * @avail_size: Available size in the memory
869 * @sub_type_hdr: Memory into which compute info will be filled in
870 *
871 * Return 0 if successful else return -ve value
872 */
kfd_fill_mem_info_for_cpu(int numa_node_id,int * avail_size,int proximity_domain,struct crat_subtype_memory * sub_type_hdr)873 static int kfd_fill_mem_info_for_cpu(int numa_node_id, int *avail_size,
874 int proximity_domain,
875 struct crat_subtype_memory *sub_type_hdr)
876 {
877 uint64_t mem_in_bytes = 0;
878 pg_data_t *pgdat;
879 int zone_type;
880
881 *avail_size -= sizeof(struct crat_subtype_memory);
882 if (*avail_size < 0)
883 return -ENOMEM;
884
885 memset(sub_type_hdr, 0, sizeof(struct crat_subtype_memory));
886
887 /* Fill in subtype header data */
888 sub_type_hdr->type = CRAT_SUBTYPE_MEMORY_AFFINITY;
889 sub_type_hdr->length = sizeof(struct crat_subtype_memory);
890 sub_type_hdr->flags = CRAT_SUBTYPE_FLAGS_ENABLED;
891
892 /* Fill in Memory Subunit data */
893
894 /* Unlike si_meminfo, si_meminfo_node is not exported. So
895 * the following lines are duplicated from si_meminfo_node
896 * function
897 */
898 pgdat = NODE_DATA(numa_node_id);
899 for (zone_type = 0; zone_type < MAX_NR_ZONES; zone_type++)
900 mem_in_bytes += zone_managed_pages(&pgdat->node_zones[zone_type]);
901 mem_in_bytes <<= PAGE_SHIFT;
902
903 sub_type_hdr->length_low = lower_32_bits(mem_in_bytes);
904 sub_type_hdr->length_high = upper_32_bits(mem_in_bytes);
905 sub_type_hdr->proximity_domain = proximity_domain;
906
907 return 0;
908 }
909
910 #ifdef CONFIG_X86_64
kfd_fill_iolink_info_for_cpu(int numa_node_id,int * avail_size,uint32_t * num_entries,struct crat_subtype_iolink * sub_type_hdr)911 static int kfd_fill_iolink_info_for_cpu(int numa_node_id, int *avail_size,
912 uint32_t *num_entries,
913 struct crat_subtype_iolink *sub_type_hdr)
914 {
915 int nid;
916 struct cpuinfo_x86 *c = &cpu_data(0);
917 uint8_t link_type;
918
919 if (c->x86_vendor == X86_VENDOR_AMD)
920 link_type = CRAT_IOLINK_TYPE_HYPERTRANSPORT;
921 else
922 link_type = CRAT_IOLINK_TYPE_QPI_1_1;
923
924 *num_entries = 0;
925
926 /* Create IO links from this node to other CPU nodes */
927 for_each_online_node(nid) {
928 if (nid == numa_node_id) /* node itself */
929 continue;
930
931 *avail_size -= sizeof(struct crat_subtype_iolink);
932 if (*avail_size < 0)
933 return -ENOMEM;
934
935 memset(sub_type_hdr, 0, sizeof(struct crat_subtype_iolink));
936
937 /* Fill in subtype header data */
938 sub_type_hdr->type = CRAT_SUBTYPE_IOLINK_AFFINITY;
939 sub_type_hdr->length = sizeof(struct crat_subtype_iolink);
940 sub_type_hdr->flags = CRAT_SUBTYPE_FLAGS_ENABLED;
941
942 /* Fill in IO link data */
943 sub_type_hdr->proximity_domain_from = numa_node_id;
944 sub_type_hdr->proximity_domain_to = nid;
945 sub_type_hdr->io_interface_type = link_type;
946
947 (*num_entries)++;
948 sub_type_hdr++;
949 }
950
951 return 0;
952 }
953 #endif
954
955 /* kfd_create_vcrat_image_cpu - Create Virtual CRAT for CPU
956 *
957 * @pcrat_image: Fill in VCRAT for CPU
958 * @size: [IN] allocated size of crat_image.
959 * [OUT] actual size of data filled in crat_image
960 */
kfd_create_vcrat_image_cpu(void * pcrat_image,size_t * size)961 static int kfd_create_vcrat_image_cpu(void *pcrat_image, size_t *size)
962 {
963 struct crat_header *crat_table = (struct crat_header *)pcrat_image;
964 struct acpi_table_header *acpi_table;
965 acpi_status status;
966 struct crat_subtype_generic *sub_type_hdr;
967 int avail_size = *size;
968 int numa_node_id;
969 #ifdef CONFIG_X86_64
970 uint32_t entries = 0;
971 #endif
972 int ret = 0;
973
974 if (!pcrat_image)
975 return -EINVAL;
976
977 /* Fill in CRAT Header.
978 * Modify length and total_entries as subunits are added.
979 */
980 avail_size -= sizeof(struct crat_header);
981 if (avail_size < 0)
982 return -ENOMEM;
983
984 memset(crat_table, 0, sizeof(struct crat_header));
985 memcpy(&crat_table->signature, CRAT_SIGNATURE,
986 sizeof(crat_table->signature));
987 crat_table->length = sizeof(struct crat_header);
988
989 status = acpi_get_table("DSDT", 0, &acpi_table);
990 if (status != AE_OK)
991 pr_warn("DSDT table not found for OEM information\n");
992 else {
993 crat_table->oem_revision = acpi_table->revision;
994 memcpy(crat_table->oem_id, acpi_table->oem_id,
995 CRAT_OEMID_LENGTH);
996 memcpy(crat_table->oem_table_id, acpi_table->oem_table_id,
997 CRAT_OEMTABLEID_LENGTH);
998 acpi_put_table(acpi_table);
999 }
1000 crat_table->total_entries = 0;
1001 crat_table->num_domains = 0;
1002
1003 sub_type_hdr = (struct crat_subtype_generic *)(crat_table+1);
1004
1005 for_each_online_node(numa_node_id) {
1006 if (kfd_numa_node_to_apic_id(numa_node_id) == -1)
1007 continue;
1008
1009 /* Fill in Subtype: Compute Unit */
1010 ret = kfd_fill_cu_for_cpu(numa_node_id, &avail_size,
1011 crat_table->num_domains,
1012 (struct crat_subtype_computeunit *)sub_type_hdr);
1013 if (ret < 0)
1014 return ret;
1015 crat_table->length += sub_type_hdr->length;
1016 crat_table->total_entries++;
1017
1018 sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr +
1019 sub_type_hdr->length);
1020
1021 /* Fill in Subtype: Memory */
1022 ret = kfd_fill_mem_info_for_cpu(numa_node_id, &avail_size,
1023 crat_table->num_domains,
1024 (struct crat_subtype_memory *)sub_type_hdr);
1025 if (ret < 0)
1026 return ret;
1027 crat_table->length += sub_type_hdr->length;
1028 crat_table->total_entries++;
1029
1030 sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr +
1031 sub_type_hdr->length);
1032
1033 /* Fill in Subtype: IO Link */
1034 #ifdef CONFIG_X86_64
1035 ret = kfd_fill_iolink_info_for_cpu(numa_node_id, &avail_size,
1036 &entries,
1037 (struct crat_subtype_iolink *)sub_type_hdr);
1038 if (ret < 0)
1039 return ret;
1040
1041 if (entries) {
1042 crat_table->length += (sub_type_hdr->length * entries);
1043 crat_table->total_entries += entries;
1044
1045 sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr +
1046 sub_type_hdr->length * entries);
1047 }
1048 #else
1049 pr_info("IO link not available for non x86 platforms\n");
1050 #endif
1051
1052 crat_table->num_domains++;
1053 }
1054
1055 /* TODO: Add cache Subtype for CPU.
1056 * Currently, CPU cache information is available in function
1057 * detect_cache_attributes(cpu) defined in the file
1058 * ./arch/x86/kernel/cpu/intel_cacheinfo.c. This function is not
1059 * exported and to get the same information the code needs to be
1060 * duplicated.
1061 */
1062
1063 *size = crat_table->length;
1064 pr_info("Virtual CRAT table created for CPU\n");
1065
1066 return 0;
1067 }
1068
kfd_fill_gpu_memory_affinity(int * avail_size,struct kfd_dev * kdev,uint8_t type,uint64_t size,struct crat_subtype_memory * sub_type_hdr,uint32_t proximity_domain,const struct kfd_local_mem_info * local_mem_info)1069 static int kfd_fill_gpu_memory_affinity(int *avail_size,
1070 struct kfd_dev *kdev, uint8_t type, uint64_t size,
1071 struct crat_subtype_memory *sub_type_hdr,
1072 uint32_t proximity_domain,
1073 const struct kfd_local_mem_info *local_mem_info)
1074 {
1075 *avail_size -= sizeof(struct crat_subtype_memory);
1076 if (*avail_size < 0)
1077 return -ENOMEM;
1078
1079 memset((void *)sub_type_hdr, 0, sizeof(struct crat_subtype_memory));
1080 sub_type_hdr->type = CRAT_SUBTYPE_MEMORY_AFFINITY;
1081 sub_type_hdr->length = sizeof(struct crat_subtype_memory);
1082 sub_type_hdr->flags |= CRAT_SUBTYPE_FLAGS_ENABLED;
1083
1084 sub_type_hdr->proximity_domain = proximity_domain;
1085
1086 pr_debug("Fill gpu memory affinity - type 0x%x size 0x%llx\n",
1087 type, size);
1088
1089 sub_type_hdr->length_low = lower_32_bits(size);
1090 sub_type_hdr->length_high = upper_32_bits(size);
1091
1092 sub_type_hdr->width = local_mem_info->vram_width;
1093 sub_type_hdr->visibility_type = type;
1094
1095 return 0;
1096 }
1097
1098 /* kfd_fill_gpu_direct_io_link - Fill in direct io link from GPU
1099 * to its NUMA node
1100 * @avail_size: Available size in the memory
1101 * @kdev - [IN] GPU device
1102 * @sub_type_hdr: Memory into which io link info will be filled in
1103 * @proximity_domain - proximity domain of the GPU node
1104 *
1105 * Return 0 if successful else return -ve value
1106 */
kfd_fill_gpu_direct_io_link_to_cpu(int * avail_size,struct kfd_dev * kdev,struct crat_subtype_iolink * sub_type_hdr,uint32_t proximity_domain)1107 static int kfd_fill_gpu_direct_io_link_to_cpu(int *avail_size,
1108 struct kfd_dev *kdev,
1109 struct crat_subtype_iolink *sub_type_hdr,
1110 uint32_t proximity_domain)
1111 {
1112 *avail_size -= sizeof(struct crat_subtype_iolink);
1113 if (*avail_size < 0)
1114 return -ENOMEM;
1115
1116 memset((void *)sub_type_hdr, 0, sizeof(struct crat_subtype_iolink));
1117
1118 /* Fill in subtype header data */
1119 sub_type_hdr->type = CRAT_SUBTYPE_IOLINK_AFFINITY;
1120 sub_type_hdr->length = sizeof(struct crat_subtype_iolink);
1121 sub_type_hdr->flags |= CRAT_SUBTYPE_FLAGS_ENABLED;
1122 if (kfd_dev_is_large_bar(kdev))
1123 sub_type_hdr->flags |= CRAT_IOLINK_FLAGS_BI_DIRECTIONAL;
1124
1125 /* Fill in IOLINK subtype.
1126 * TODO: Fill-in other fields of iolink subtype
1127 */
1128 sub_type_hdr->io_interface_type = CRAT_IOLINK_TYPE_PCIEXPRESS;
1129 sub_type_hdr->proximity_domain_from = proximity_domain;
1130 #ifdef CONFIG_NUMA
1131 if (kdev->pdev->dev.numa_node == NUMA_NO_NODE)
1132 sub_type_hdr->proximity_domain_to = 0;
1133 else
1134 sub_type_hdr->proximity_domain_to = kdev->pdev->dev.numa_node;
1135 #else
1136 sub_type_hdr->proximity_domain_to = 0;
1137 #endif
1138 return 0;
1139 }
1140
kfd_fill_gpu_xgmi_link_to_gpu(int * avail_size,struct kfd_dev * kdev,struct kfd_dev * peer_kdev,struct crat_subtype_iolink * sub_type_hdr,uint32_t proximity_domain_from,uint32_t proximity_domain_to)1141 static int kfd_fill_gpu_xgmi_link_to_gpu(int *avail_size,
1142 struct kfd_dev *kdev,
1143 struct kfd_dev *peer_kdev,
1144 struct crat_subtype_iolink *sub_type_hdr,
1145 uint32_t proximity_domain_from,
1146 uint32_t proximity_domain_to)
1147 {
1148 *avail_size -= sizeof(struct crat_subtype_iolink);
1149 if (*avail_size < 0)
1150 return -ENOMEM;
1151
1152 memset((void *)sub_type_hdr, 0, sizeof(struct crat_subtype_iolink));
1153
1154 sub_type_hdr->type = CRAT_SUBTYPE_IOLINK_AFFINITY;
1155 sub_type_hdr->length = sizeof(struct crat_subtype_iolink);
1156 sub_type_hdr->flags |= CRAT_SUBTYPE_FLAGS_ENABLED |
1157 CRAT_IOLINK_FLAGS_BI_DIRECTIONAL;
1158
1159 sub_type_hdr->io_interface_type = CRAT_IOLINK_TYPE_XGMI;
1160 sub_type_hdr->proximity_domain_from = proximity_domain_from;
1161 sub_type_hdr->proximity_domain_to = proximity_domain_to;
1162 sub_type_hdr->num_hops_xgmi =
1163 amdgpu_amdkfd_get_xgmi_hops_count(kdev->kgd, peer_kdev->kgd);
1164 return 0;
1165 }
1166
1167 /* kfd_create_vcrat_image_gpu - Create Virtual CRAT for CPU
1168 *
1169 * @pcrat_image: Fill in VCRAT for GPU
1170 * @size: [IN] allocated size of crat_image.
1171 * [OUT] actual size of data filled in crat_image
1172 */
kfd_create_vcrat_image_gpu(void * pcrat_image,size_t * size,struct kfd_dev * kdev,uint32_t proximity_domain)1173 static int kfd_create_vcrat_image_gpu(void *pcrat_image,
1174 size_t *size, struct kfd_dev *kdev,
1175 uint32_t proximity_domain)
1176 {
1177 struct crat_header *crat_table = (struct crat_header *)pcrat_image;
1178 struct crat_subtype_generic *sub_type_hdr;
1179 struct kfd_local_mem_info local_mem_info;
1180 struct kfd_topology_device *peer_dev;
1181 struct crat_subtype_computeunit *cu;
1182 struct kfd_cu_info cu_info;
1183 int avail_size = *size;
1184 uint32_t total_num_of_cu;
1185 int num_of_cache_entries = 0;
1186 int cache_mem_filled = 0;
1187 uint32_t nid = 0;
1188 int ret = 0;
1189
1190 if (!pcrat_image || avail_size < VCRAT_SIZE_FOR_GPU)
1191 return -EINVAL;
1192
1193 /* Fill the CRAT Header.
1194 * Modify length and total_entries as subunits are added.
1195 */
1196 avail_size -= sizeof(struct crat_header);
1197 if (avail_size < 0)
1198 return -ENOMEM;
1199
1200 memset(crat_table, 0, sizeof(struct crat_header));
1201
1202 memcpy(&crat_table->signature, CRAT_SIGNATURE,
1203 sizeof(crat_table->signature));
1204 /* Change length as we add more subtypes*/
1205 crat_table->length = sizeof(struct crat_header);
1206 crat_table->num_domains = 1;
1207 crat_table->total_entries = 0;
1208
1209 /* Fill in Subtype: Compute Unit
1210 * First fill in the sub type header and then sub type data
1211 */
1212 avail_size -= sizeof(struct crat_subtype_computeunit);
1213 if (avail_size < 0)
1214 return -ENOMEM;
1215
1216 sub_type_hdr = (struct crat_subtype_generic *)(crat_table + 1);
1217 memset(sub_type_hdr, 0, sizeof(struct crat_subtype_computeunit));
1218
1219 sub_type_hdr->type = CRAT_SUBTYPE_COMPUTEUNIT_AFFINITY;
1220 sub_type_hdr->length = sizeof(struct crat_subtype_computeunit);
1221 sub_type_hdr->flags = CRAT_SUBTYPE_FLAGS_ENABLED;
1222
1223 /* Fill CU subtype data */
1224 cu = (struct crat_subtype_computeunit *)sub_type_hdr;
1225 cu->flags |= CRAT_CU_FLAGS_GPU_PRESENT;
1226 cu->proximity_domain = proximity_domain;
1227
1228 amdgpu_amdkfd_get_cu_info(kdev->kgd, &cu_info);
1229 cu->num_simd_per_cu = cu_info.simd_per_cu;
1230 cu->num_simd_cores = cu_info.simd_per_cu * cu_info.cu_active_number;
1231 cu->max_waves_simd = cu_info.max_waves_per_simd;
1232
1233 cu->wave_front_size = cu_info.wave_front_size;
1234 cu->array_count = cu_info.num_shader_arrays_per_engine *
1235 cu_info.num_shader_engines;
1236 total_num_of_cu = (cu->array_count * cu_info.num_cu_per_sh);
1237 cu->processor_id_low = get_and_inc_gpu_processor_id(total_num_of_cu);
1238 cu->num_cu_per_array = cu_info.num_cu_per_sh;
1239 cu->max_slots_scatch_cu = cu_info.max_scratch_slots_per_cu;
1240 cu->num_banks = cu_info.num_shader_engines;
1241 cu->lds_size_in_kb = cu_info.lds_size;
1242
1243 cu->hsa_capability = 0;
1244
1245 /* Check if this node supports IOMMU. During parsing this flag will
1246 * translate to HSA_CAP_ATS_PRESENT
1247 */
1248 if (!kfd_iommu_check_device(kdev))
1249 cu->hsa_capability |= CRAT_CU_FLAGS_IOMMU_PRESENT;
1250
1251 crat_table->length += sub_type_hdr->length;
1252 crat_table->total_entries++;
1253
1254 /* Fill in Subtype: Memory. Only on systems with large BAR (no
1255 * private FB), report memory as public. On other systems
1256 * report the total FB size (public+private) as a single
1257 * private heap.
1258 */
1259 amdgpu_amdkfd_get_local_mem_info(kdev->kgd, &local_mem_info);
1260 sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr +
1261 sub_type_hdr->length);
1262
1263 if (debug_largebar)
1264 local_mem_info.local_mem_size_private = 0;
1265
1266 if (local_mem_info.local_mem_size_private == 0)
1267 ret = kfd_fill_gpu_memory_affinity(&avail_size,
1268 kdev, HSA_MEM_HEAP_TYPE_FB_PUBLIC,
1269 local_mem_info.local_mem_size_public,
1270 (struct crat_subtype_memory *)sub_type_hdr,
1271 proximity_domain,
1272 &local_mem_info);
1273 else
1274 ret = kfd_fill_gpu_memory_affinity(&avail_size,
1275 kdev, HSA_MEM_HEAP_TYPE_FB_PRIVATE,
1276 local_mem_info.local_mem_size_public +
1277 local_mem_info.local_mem_size_private,
1278 (struct crat_subtype_memory *)sub_type_hdr,
1279 proximity_domain,
1280 &local_mem_info);
1281 if (ret < 0)
1282 return ret;
1283
1284 crat_table->length += sizeof(struct crat_subtype_memory);
1285 crat_table->total_entries++;
1286
1287 /* TODO: Fill in cache information. This information is NOT readily
1288 * available in KGD
1289 */
1290 sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr +
1291 sub_type_hdr->length);
1292 ret = kfd_fill_gpu_cache_info(kdev, cu->processor_id_low,
1293 avail_size,
1294 &cu_info,
1295 (struct crat_subtype_cache *)sub_type_hdr,
1296 &cache_mem_filled,
1297 &num_of_cache_entries);
1298
1299 if (ret < 0)
1300 return ret;
1301
1302 crat_table->length += cache_mem_filled;
1303 crat_table->total_entries += num_of_cache_entries;
1304 avail_size -= cache_mem_filled;
1305
1306 /* Fill in Subtype: IO_LINKS
1307 * Only direct links are added here which is Link from GPU to
1308 * to its NUMA node. Indirect links are added by userspace.
1309 */
1310 sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr +
1311 cache_mem_filled);
1312 ret = kfd_fill_gpu_direct_io_link_to_cpu(&avail_size, kdev,
1313 (struct crat_subtype_iolink *)sub_type_hdr, proximity_domain);
1314
1315 if (ret < 0)
1316 return ret;
1317
1318 crat_table->length += sub_type_hdr->length;
1319 crat_table->total_entries++;
1320
1321
1322 /* Fill in Subtype: IO_LINKS
1323 * Direct links from GPU to other GPUs through xGMI.
1324 * We will loop GPUs that already be processed (with lower value
1325 * of proximity_domain), add the link for the GPUs with same
1326 * hive id (from this GPU to other GPU) . The reversed iolink
1327 * (from other GPU to this GPU) will be added
1328 * in kfd_parse_subtype_iolink.
1329 */
1330 if (kdev->hive_id) {
1331 for (nid = 0; nid < proximity_domain; ++nid) {
1332 peer_dev = kfd_topology_device_by_proximity_domain(nid);
1333 if (!peer_dev->gpu)
1334 continue;
1335 if (peer_dev->gpu->hive_id != kdev->hive_id)
1336 continue;
1337 sub_type_hdr = (typeof(sub_type_hdr))(
1338 (char *)sub_type_hdr +
1339 sizeof(struct crat_subtype_iolink));
1340 ret = kfd_fill_gpu_xgmi_link_to_gpu(
1341 &avail_size, kdev, peer_dev->gpu,
1342 (struct crat_subtype_iolink *)sub_type_hdr,
1343 proximity_domain, nid);
1344 if (ret < 0)
1345 return ret;
1346 crat_table->length += sub_type_hdr->length;
1347 crat_table->total_entries++;
1348 }
1349 }
1350 *size = crat_table->length;
1351 pr_info("Virtual CRAT table created for GPU\n");
1352
1353 return ret;
1354 }
1355
1356 /* kfd_create_crat_image_virtual - Allocates memory for CRAT image and
1357 * creates a Virtual CRAT (VCRAT) image
1358 *
1359 * NOTE: Call kfd_destroy_crat_image to free CRAT image memory
1360 *
1361 * @crat_image: VCRAT image created because ACPI does not have a
1362 * CRAT for this device
1363 * @size: [OUT] size of virtual crat_image
1364 * @flags: COMPUTE_UNIT_CPU - Create VCRAT for CPU device
1365 * COMPUTE_UNIT_GPU - Create VCRAT for GPU
1366 * (COMPUTE_UNIT_CPU | COMPUTE_UNIT_GPU) - Create VCRAT for APU
1367 * -- this option is not currently implemented.
1368 * The assumption is that all AMD APUs will have CRAT
1369 * @kdev: Valid kfd_device required if flags contain COMPUTE_UNIT_GPU
1370 *
1371 * Return 0 if successful else return -ve value
1372 */
kfd_create_crat_image_virtual(void ** crat_image,size_t * size,int flags,struct kfd_dev * kdev,uint32_t proximity_domain)1373 int kfd_create_crat_image_virtual(void **crat_image, size_t *size,
1374 int flags, struct kfd_dev *kdev,
1375 uint32_t proximity_domain)
1376 {
1377 void *pcrat_image = NULL;
1378 int ret = 0, num_nodes;
1379 size_t dyn_size;
1380
1381 if (!crat_image)
1382 return -EINVAL;
1383
1384 *crat_image = NULL;
1385
1386 /* Allocate the CPU Virtual CRAT size based on the number of online
1387 * nodes. Allocate VCRAT_SIZE_FOR_GPU for GPU virtual CRAT image.
1388 * This should cover all the current conditions. A check is put not
1389 * to overwrite beyond allocated size for GPUs
1390 */
1391 switch (flags) {
1392 case COMPUTE_UNIT_CPU:
1393 num_nodes = num_online_nodes();
1394 dyn_size = sizeof(struct crat_header) +
1395 num_nodes * (sizeof(struct crat_subtype_computeunit) +
1396 sizeof(struct crat_subtype_memory) +
1397 (num_nodes - 1) * sizeof(struct crat_subtype_iolink));
1398 pcrat_image = kvmalloc(dyn_size, GFP_KERNEL);
1399 if (!pcrat_image)
1400 return -ENOMEM;
1401 *size = dyn_size;
1402 pr_debug("CRAT size is %ld", dyn_size);
1403 ret = kfd_create_vcrat_image_cpu(pcrat_image, size);
1404 break;
1405 case COMPUTE_UNIT_GPU:
1406 if (!kdev)
1407 return -EINVAL;
1408 pcrat_image = kvmalloc(VCRAT_SIZE_FOR_GPU, GFP_KERNEL);
1409 if (!pcrat_image)
1410 return -ENOMEM;
1411 *size = VCRAT_SIZE_FOR_GPU;
1412 ret = kfd_create_vcrat_image_gpu(pcrat_image, size, kdev,
1413 proximity_domain);
1414 break;
1415 case (COMPUTE_UNIT_CPU | COMPUTE_UNIT_GPU):
1416 /* TODO: */
1417 ret = -EINVAL;
1418 pr_err("VCRAT not implemented for APU\n");
1419 break;
1420 default:
1421 ret = -EINVAL;
1422 }
1423
1424 if (!ret)
1425 *crat_image = pcrat_image;
1426 else
1427 kvfree(pcrat_image);
1428
1429 return ret;
1430 }
1431
1432
1433 /* kfd_destroy_crat_image
1434 *
1435 * @crat_image: [IN] - crat_image from kfd_create_crat_image_xxx(..)
1436 *
1437 */
kfd_destroy_crat_image(void * crat_image)1438 void kfd_destroy_crat_image(void *crat_image)
1439 {
1440 kvfree(crat_image);
1441 }
1442