1 /*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 * Copyright 2019 Raptor Engineering, LLC
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27 #include <linux/slab.h>
28
29 #include "dm_services.h"
30 #include "dc.h"
31
32 #include "dcn21_init.h"
33
34 #include "resource.h"
35 #include "include/irq_service_interface.h"
36 #include "dcn20/dcn20_resource.h"
37
38 #include "clk_mgr.h"
39 #include "dcn10/dcn10_hubp.h"
40 #include "dcn10/dcn10_ipp.h"
41 #include "dcn20/dcn20_hubbub.h"
42 #include "dcn20/dcn20_mpc.h"
43 #include "dcn20/dcn20_hubp.h"
44 #include "dcn21_hubp.h"
45 #include "irq/dcn21/irq_service_dcn21.h"
46 #include "dcn20/dcn20_dpp.h"
47 #include "dcn20/dcn20_optc.h"
48 #include "dcn21/dcn21_hwseq.h"
49 #include "dce110/dce110_hw_sequencer.h"
50 #include "dcn20/dcn20_opp.h"
51 #include "dcn20/dcn20_dsc.h"
52 #include "dcn21/dcn21_link_encoder.h"
53 #include "dcn20/dcn20_stream_encoder.h"
54 #include "dce/dce_clock_source.h"
55 #include "dce/dce_audio.h"
56 #include "dce/dce_hwseq.h"
57 #include "virtual/virtual_stream_encoder.h"
58 #include "dce110/dce110_resource.h"
59 #include "dml/display_mode_vba.h"
60 #include "dcn20/dcn20_dccg.h"
61 #include "dcn21_hubbub.h"
62 #include "dcn10/dcn10_resource.h"
63 #include "dce110/dce110_resource.h"
64 #include "dce/dce_panel_cntl.h"
65
66 #include "dcn20/dcn20_dwb.h"
67 #include "dcn20/dcn20_mmhubbub.h"
68 #include "dpcs/dpcs_2_1_0_offset.h"
69 #include "dpcs/dpcs_2_1_0_sh_mask.h"
70
71 #include "renoir_ip_offset.h"
72 #include "dcn/dcn_2_1_0_offset.h"
73 #include "dcn/dcn_2_1_0_sh_mask.h"
74
75 #include "nbio/nbio_7_0_offset.h"
76
77 #include "mmhub/mmhub_2_0_0_offset.h"
78 #include "mmhub/mmhub_2_0_0_sh_mask.h"
79
80 #include "reg_helper.h"
81 #include "dce/dce_abm.h"
82 #include "dce/dce_dmcu.h"
83 #include "dce/dce_aux.h"
84 #include "dce/dce_i2c.h"
85 #include "dcn21_resource.h"
86 #include "vm_helper.h"
87 #include "dcn20/dcn20_vmid.h"
88 #include "dce/dmub_psr.h"
89 #include "dce/dmub_abm.h"
90
91 #define DC_LOGGER_INIT(logger)
92
93
94 struct _vcs_dpi_ip_params_st dcn2_1_ip = {
95 .odm_capable = 1,
96 .gpuvm_enable = 1,
97 .hostvm_enable = 1,
98 .gpuvm_max_page_table_levels = 1,
99 .hostvm_max_page_table_levels = 4,
100 .hostvm_cached_page_table_levels = 2,
101 .num_dsc = 3,
102 .rob_buffer_size_kbytes = 168,
103 .det_buffer_size_kbytes = 164,
104 .dpte_buffer_size_in_pte_reqs_luma = 44,
105 .dpte_buffer_size_in_pte_reqs_chroma = 42,//todo
106 .dpp_output_buffer_pixels = 2560,
107 .opp_output_buffer_lines = 1,
108 .pixel_chunk_size_kbytes = 8,
109 .pte_enable = 1,
110 .max_page_table_levels = 4,
111 .pte_chunk_size_kbytes = 2,
112 .meta_chunk_size_kbytes = 2,
113 .writeback_chunk_size_kbytes = 2,
114 .line_buffer_size_bits = 789504,
115 .is_line_buffer_bpp_fixed = 0,
116 .line_buffer_fixed_bpp = 0,
117 .dcc_supported = true,
118 .max_line_buffer_lines = 12,
119 .writeback_luma_buffer_size_kbytes = 12,
120 .writeback_chroma_buffer_size_kbytes = 8,
121 .writeback_chroma_line_buffer_width_pixels = 4,
122 .writeback_max_hscl_ratio = 1,
123 .writeback_max_vscl_ratio = 1,
124 .writeback_min_hscl_ratio = 1,
125 .writeback_min_vscl_ratio = 1,
126 .writeback_max_hscl_taps = 12,
127 .writeback_max_vscl_taps = 12,
128 .writeback_line_buffer_luma_buffer_size = 0,
129 .writeback_line_buffer_chroma_buffer_size = 14643,
130 .cursor_buffer_size = 8,
131 .cursor_chunk_size = 2,
132 .max_num_otg = 4,
133 .max_num_dpp = 4,
134 .max_num_wb = 1,
135 .max_dchub_pscl_bw_pix_per_clk = 4,
136 .max_pscl_lb_bw_pix_per_clk = 2,
137 .max_lb_vscl_bw_pix_per_clk = 4,
138 .max_vscl_hscl_bw_pix_per_clk = 4,
139 .max_hscl_ratio = 4,
140 .max_vscl_ratio = 4,
141 .hscl_mults = 4,
142 .vscl_mults = 4,
143 .max_hscl_taps = 8,
144 .max_vscl_taps = 8,
145 .dispclk_ramp_margin_percent = 1,
146 .underscan_factor = 1.10,
147 .min_vblank_lines = 32, //
148 .dppclk_delay_subtotal = 77, //
149 .dppclk_delay_scl_lb_only = 16,
150 .dppclk_delay_scl = 50,
151 .dppclk_delay_cnvc_formatter = 8,
152 .dppclk_delay_cnvc_cursor = 6,
153 .dispclk_delay_subtotal = 87, //
154 .dcfclk_cstate_latency = 10, // SRExitTime
155 .max_inter_dcn_tile_repeaters = 8,
156
157 .xfc_supported = false,
158 .xfc_fill_bw_overhead_percent = 10.0,
159 .xfc_fill_constant_bytes = 0,
160 .ptoi_supported = 0,
161 .number_of_cursors = 1,
162 };
163
164 struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = {
165 .clock_limits = {
166 {
167 .state = 0,
168 .dcfclk_mhz = 400.0,
169 .fabricclk_mhz = 400.0,
170 .dispclk_mhz = 600.0,
171 .dppclk_mhz = 400.00,
172 .phyclk_mhz = 600.0,
173 .socclk_mhz = 278.0,
174 .dscclk_mhz = 205.67,
175 .dram_speed_mts = 1600.0,
176 },
177 {
178 .state = 1,
179 .dcfclk_mhz = 464.52,
180 .fabricclk_mhz = 800.0,
181 .dispclk_mhz = 654.55,
182 .dppclk_mhz = 626.09,
183 .phyclk_mhz = 600.0,
184 .socclk_mhz = 278.0,
185 .dscclk_mhz = 205.67,
186 .dram_speed_mts = 1600.0,
187 },
188 {
189 .state = 2,
190 .dcfclk_mhz = 514.29,
191 .fabricclk_mhz = 933.0,
192 .dispclk_mhz = 757.89,
193 .dppclk_mhz = 685.71,
194 .phyclk_mhz = 600.0,
195 .socclk_mhz = 278.0,
196 .dscclk_mhz = 287.67,
197 .dram_speed_mts = 1866.0,
198 },
199 {
200 .state = 3,
201 .dcfclk_mhz = 576.00,
202 .fabricclk_mhz = 1067.0,
203 .dispclk_mhz = 847.06,
204 .dppclk_mhz = 757.89,
205 .phyclk_mhz = 600.0,
206 .socclk_mhz = 715.0,
207 .dscclk_mhz = 318.334,
208 .dram_speed_mts = 2134.0,
209 },
210 {
211 .state = 4,
212 .dcfclk_mhz = 626.09,
213 .fabricclk_mhz = 1200.0,
214 .dispclk_mhz = 900.00,
215 .dppclk_mhz = 847.06,
216 .phyclk_mhz = 810.0,
217 .socclk_mhz = 953.0,
218 .dscclk_mhz = 489.0,
219 .dram_speed_mts = 2400.0,
220 },
221 {
222 .state = 5,
223 .dcfclk_mhz = 685.71,
224 .fabricclk_mhz = 1333.0,
225 .dispclk_mhz = 1028.57,
226 .dppclk_mhz = 960.00,
227 .phyclk_mhz = 810.0,
228 .socclk_mhz = 278.0,
229 .dscclk_mhz = 287.67,
230 .dram_speed_mts = 2666.0,
231 },
232 {
233 .state = 6,
234 .dcfclk_mhz = 757.89,
235 .fabricclk_mhz = 1467.0,
236 .dispclk_mhz = 1107.69,
237 .dppclk_mhz = 1028.57,
238 .phyclk_mhz = 810.0,
239 .socclk_mhz = 715.0,
240 .dscclk_mhz = 318.334,
241 .dram_speed_mts = 3200.0,
242 },
243 {
244 .state = 7,
245 .dcfclk_mhz = 847.06,
246 .fabricclk_mhz = 1600.0,
247 .dispclk_mhz = 1395.0,
248 .dppclk_mhz = 1285.00,
249 .phyclk_mhz = 1325.0,
250 .socclk_mhz = 953.0,
251 .dscclk_mhz = 489.0,
252 .dram_speed_mts = 4266.0,
253 },
254 /*Extra state, no dispclk ramping*/
255 {
256 .state = 8,
257 .dcfclk_mhz = 847.06,
258 .fabricclk_mhz = 1600.0,
259 .dispclk_mhz = 1395.0,
260 .dppclk_mhz = 1285.0,
261 .phyclk_mhz = 1325.0,
262 .socclk_mhz = 953.0,
263 .dscclk_mhz = 489.0,
264 .dram_speed_mts = 4266.0,
265 },
266
267 },
268
269 .sr_exit_time_us = 12.5,
270 .sr_enter_plus_exit_time_us = 17.0,
271 .urgent_latency_us = 4.0,
272 .urgent_latency_pixel_data_only_us = 4.0,
273 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
274 .urgent_latency_vm_data_only_us = 4.0,
275 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
276 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
277 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
278 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0,
279 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 75.0,
280 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
281 .max_avg_sdp_bw_use_normal_percent = 60.0,
282 .max_avg_dram_bw_use_normal_percent = 100.0,
283 .writeback_latency_us = 12.0,
284 .max_request_size_bytes = 256,
285 .dram_channel_width_bytes = 4,
286 .fabric_datapath_to_dcn_data_return_bytes = 32,
287 .dcn_downspread_percent = 0.5,
288 .downspread_percent = 0.38,
289 .dram_page_open_time_ns = 50.0,
290 .dram_rw_turnaround_time_ns = 17.5,
291 .dram_return_buffer_per_channel_bytes = 8192,
292 .round_trip_ping_latency_dcfclk_cycles = 128,
293 .urgent_out_of_order_return_per_channel_bytes = 4096,
294 .channel_interleave_bytes = 256,
295 .num_banks = 8,
296 .num_chans = 4,
297 .vmm_page_size_bytes = 4096,
298 .dram_clock_change_latency_us = 23.84,
299 .return_bus_width_bytes = 64,
300 .dispclk_dppclk_vco_speed_mhz = 3600,
301 .xfc_bus_transport_time_us = 4,
302 .xfc_xbuf_latency_tolerance_us = 4,
303 .use_urgent_burst_bw = 1,
304 .num_states = 8
305 };
306
307 #ifndef MAX
308 #define MAX(X, Y) ((X) > (Y) ? (X) : (Y))
309 #endif
310 #ifndef MIN
311 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
312 #endif
313
314 /* begin *********************
315 * macros to expend register list macro defined in HW object header file */
316
317 /* DCN */
318 /* TODO awful hack. fixup dcn20_dwb.h */
319 #undef BASE_INNER
320 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
321
322 #define BASE(seg) BASE_INNER(seg)
323
324 #define SR(reg_name)\
325 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
326 mm ## reg_name
327
328 #define SRI(reg_name, block, id)\
329 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
330 mm ## block ## id ## _ ## reg_name
331
332 #define SRIR(var_name, reg_name, block, id)\
333 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
334 mm ## block ## id ## _ ## reg_name
335
336 #define SRII(reg_name, block, id)\
337 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
338 mm ## block ## id ## _ ## reg_name
339
340 #define DCCG_SRII(reg_name, block, id)\
341 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
342 mm ## block ## id ## _ ## reg_name
343
344 #define VUPDATE_SRII(reg_name, block, id)\
345 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
346 mm ## reg_name ## _ ## block ## id
347
348 /* NBIO */
349 #define NBIO_BASE_INNER(seg) \
350 NBIF0_BASE__INST0_SEG ## seg
351
352 #define NBIO_BASE(seg) \
353 NBIO_BASE_INNER(seg)
354
355 #define NBIO_SR(reg_name)\
356 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
357 mm ## reg_name
358
359 /* MMHUB */
360 #define MMHUB_BASE_INNER(seg) \
361 MMHUB_BASE__INST0_SEG ## seg
362
363 #define MMHUB_BASE(seg) \
364 MMHUB_BASE_INNER(seg)
365
366 #define MMHUB_SR(reg_name)\
367 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
368 mmMM ## reg_name
369
370 #define clk_src_regs(index, pllid)\
371 [index] = {\
372 CS_COMMON_REG_LIST_DCN2_1(index, pllid),\
373 }
374
375 static const struct dce110_clk_src_regs clk_src_regs[] = {
376 clk_src_regs(0, A),
377 clk_src_regs(1, B),
378 clk_src_regs(2, C),
379 clk_src_regs(3, D),
380 clk_src_regs(4, E),
381 };
382
383 static const struct dce110_clk_src_shift cs_shift = {
384 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
385 };
386
387 static const struct dce110_clk_src_mask cs_mask = {
388 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
389 };
390
391 static const struct bios_registers bios_regs = {
392 NBIO_SR(BIOS_SCRATCH_3),
393 NBIO_SR(BIOS_SCRATCH_6)
394 };
395
396 static const struct dce_dmcu_registers dmcu_regs = {
397 DMCU_DCN20_REG_LIST()
398 };
399
400 static const struct dce_dmcu_shift dmcu_shift = {
401 DMCU_MASK_SH_LIST_DCN10(__SHIFT)
402 };
403
404 static const struct dce_dmcu_mask dmcu_mask = {
405 DMCU_MASK_SH_LIST_DCN10(_MASK)
406 };
407
408 static const struct dce_abm_registers abm_regs = {
409 ABM_DCN20_REG_LIST()
410 };
411
412 static const struct dce_abm_shift abm_shift = {
413 ABM_MASK_SH_LIST_DCN20(__SHIFT)
414 };
415
416 static const struct dce_abm_mask abm_mask = {
417 ABM_MASK_SH_LIST_DCN20(_MASK)
418 };
419
420 #define audio_regs(id)\
421 [id] = {\
422 AUD_COMMON_REG_LIST(id)\
423 }
424
425 static const struct dce_audio_registers audio_regs[] = {
426 audio_regs(0),
427 audio_regs(1),
428 audio_regs(2),
429 audio_regs(3),
430 audio_regs(4),
431 audio_regs(5),
432 };
433
434 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
435 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
436 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
437 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
438
439 static const struct dce_audio_shift audio_shift = {
440 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
441 };
442
443 static const struct dce_audio_mask audio_mask = {
444 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
445 };
446
447 static const struct dccg_registers dccg_regs = {
448 DCCG_COMMON_REG_LIST_DCN_BASE()
449 };
450
451 static const struct dccg_shift dccg_shift = {
452 DCCG_MASK_SH_LIST_DCN2(__SHIFT)
453 };
454
455 static const struct dccg_mask dccg_mask = {
456 DCCG_MASK_SH_LIST_DCN2(_MASK)
457 };
458
459 #define opp_regs(id)\
460 [id] = {\
461 OPP_REG_LIST_DCN20(id),\
462 }
463
464 static const struct dcn20_opp_registers opp_regs[] = {
465 opp_regs(0),
466 opp_regs(1),
467 opp_regs(2),
468 opp_regs(3),
469 opp_regs(4),
470 opp_regs(5),
471 };
472
473 static const struct dcn20_opp_shift opp_shift = {
474 OPP_MASK_SH_LIST_DCN20(__SHIFT)
475 };
476
477 static const struct dcn20_opp_mask opp_mask = {
478 OPP_MASK_SH_LIST_DCN20(_MASK)
479 };
480
481 #define tg_regs(id)\
482 [id] = {TG_COMMON_REG_LIST_DCN2_0(id)}
483
484 static const struct dcn_optc_registers tg_regs[] = {
485 tg_regs(0),
486 tg_regs(1),
487 tg_regs(2),
488 tg_regs(3)
489 };
490
491 static const struct dcn_optc_shift tg_shift = {
492 TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
493 };
494
495 static const struct dcn_optc_mask tg_mask = {
496 TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
497 };
498
499 static const struct dcn20_mpc_registers mpc_regs = {
500 MPC_REG_LIST_DCN2_0(0),
501 MPC_REG_LIST_DCN2_0(1),
502 MPC_REG_LIST_DCN2_0(2),
503 MPC_REG_LIST_DCN2_0(3),
504 MPC_REG_LIST_DCN2_0(4),
505 MPC_REG_LIST_DCN2_0(5),
506 MPC_OUT_MUX_REG_LIST_DCN2_0(0),
507 MPC_OUT_MUX_REG_LIST_DCN2_0(1),
508 MPC_OUT_MUX_REG_LIST_DCN2_0(2),
509 MPC_OUT_MUX_REG_LIST_DCN2_0(3),
510 MPC_DBG_REG_LIST_DCN2_0()
511 };
512
513 static const struct dcn20_mpc_shift mpc_shift = {
514 MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT),
515 MPC_DEBUG_REG_LIST_SH_DCN20
516 };
517
518 static const struct dcn20_mpc_mask mpc_mask = {
519 MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK),
520 MPC_DEBUG_REG_LIST_MASK_DCN20
521 };
522
523 #define hubp_regs(id)\
524 [id] = {\
525 HUBP_REG_LIST_DCN21(id)\
526 }
527
528 static const struct dcn_hubp2_registers hubp_regs[] = {
529 hubp_regs(0),
530 hubp_regs(1),
531 hubp_regs(2),
532 hubp_regs(3)
533 };
534
535 static const struct dcn_hubp2_shift hubp_shift = {
536 HUBP_MASK_SH_LIST_DCN21(__SHIFT)
537 };
538
539 static const struct dcn_hubp2_mask hubp_mask = {
540 HUBP_MASK_SH_LIST_DCN21(_MASK)
541 };
542
543 static const struct dcn_hubbub_registers hubbub_reg = {
544 HUBBUB_REG_LIST_DCN21()
545 };
546
547 static const struct dcn_hubbub_shift hubbub_shift = {
548 HUBBUB_MASK_SH_LIST_DCN21(__SHIFT)
549 };
550
551 static const struct dcn_hubbub_mask hubbub_mask = {
552 HUBBUB_MASK_SH_LIST_DCN21(_MASK)
553 };
554
555
556 #define vmid_regs(id)\
557 [id] = {\
558 DCN20_VMID_REG_LIST(id)\
559 }
560
561 static const struct dcn_vmid_registers vmid_regs[] = {
562 vmid_regs(0),
563 vmid_regs(1),
564 vmid_regs(2),
565 vmid_regs(3),
566 vmid_regs(4),
567 vmid_regs(5),
568 vmid_regs(6),
569 vmid_regs(7),
570 vmid_regs(8),
571 vmid_regs(9),
572 vmid_regs(10),
573 vmid_regs(11),
574 vmid_regs(12),
575 vmid_regs(13),
576 vmid_regs(14),
577 vmid_regs(15)
578 };
579
580 static const struct dcn20_vmid_shift vmid_shifts = {
581 DCN20_VMID_MASK_SH_LIST(__SHIFT)
582 };
583
584 static const struct dcn20_vmid_mask vmid_masks = {
585 DCN20_VMID_MASK_SH_LIST(_MASK)
586 };
587
588 #define dsc_regsDCN20(id)\
589 [id] = {\
590 DSC_REG_LIST_DCN20(id)\
591 }
592
593 static const struct dcn20_dsc_registers dsc_regs[] = {
594 dsc_regsDCN20(0),
595 dsc_regsDCN20(1),
596 dsc_regsDCN20(2),
597 dsc_regsDCN20(3),
598 dsc_regsDCN20(4),
599 dsc_regsDCN20(5)
600 };
601
602 static const struct dcn20_dsc_shift dsc_shift = {
603 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
604 };
605
606 static const struct dcn20_dsc_mask dsc_mask = {
607 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
608 };
609
610 #define ipp_regs(id)\
611 [id] = {\
612 IPP_REG_LIST_DCN20(id),\
613 }
614
615 static const struct dcn10_ipp_registers ipp_regs[] = {
616 ipp_regs(0),
617 ipp_regs(1),
618 ipp_regs(2),
619 ipp_regs(3),
620 };
621
622 static const struct dcn10_ipp_shift ipp_shift = {
623 IPP_MASK_SH_LIST_DCN20(__SHIFT)
624 };
625
626 static const struct dcn10_ipp_mask ipp_mask = {
627 IPP_MASK_SH_LIST_DCN20(_MASK),
628 };
629
630 #define opp_regs(id)\
631 [id] = {\
632 OPP_REG_LIST_DCN20(id),\
633 }
634
635
636 #define aux_engine_regs(id)\
637 [id] = {\
638 AUX_COMMON_REG_LIST0(id), \
639 .AUXN_IMPCAL = 0, \
640 .AUXP_IMPCAL = 0, \
641 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
642 }
643
644 static const struct dce110_aux_registers aux_engine_regs[] = {
645 aux_engine_regs(0),
646 aux_engine_regs(1),
647 aux_engine_regs(2),
648 aux_engine_regs(3),
649 aux_engine_regs(4),
650 };
651
652 #define tf_regs(id)\
653 [id] = {\
654 TF_REG_LIST_DCN20(id),\
655 TF_REG_LIST_DCN20_COMMON_APPEND(id),\
656 }
657
658 static const struct dcn2_dpp_registers tf_regs[] = {
659 tf_regs(0),
660 tf_regs(1),
661 tf_regs(2),
662 tf_regs(3),
663 };
664
665 static const struct dcn2_dpp_shift tf_shift = {
666 TF_REG_LIST_SH_MASK_DCN20(__SHIFT),
667 TF_DEBUG_REG_LIST_SH_DCN20
668 };
669
670 static const struct dcn2_dpp_mask tf_mask = {
671 TF_REG_LIST_SH_MASK_DCN20(_MASK),
672 TF_DEBUG_REG_LIST_MASK_DCN20
673 };
674
675 #define stream_enc_regs(id)\
676 [id] = {\
677 SE_DCN2_REG_LIST(id)\
678 }
679
680 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
681 stream_enc_regs(0),
682 stream_enc_regs(1),
683 stream_enc_regs(2),
684 stream_enc_regs(3),
685 stream_enc_regs(4),
686 };
687
688 static const struct dce110_aux_registers_shift aux_shift = {
689 DCN_AUX_MASK_SH_LIST(__SHIFT)
690 };
691
692 static const struct dce110_aux_registers_mask aux_mask = {
693 DCN_AUX_MASK_SH_LIST(_MASK)
694 };
695
696 static const struct dcn10_stream_encoder_shift se_shift = {
697 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)
698 };
699
700 static const struct dcn10_stream_encoder_mask se_mask = {
701 SE_COMMON_MASK_SH_LIST_DCN20(_MASK)
702 };
703
704 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
705
706 static int dcn21_populate_dml_pipes_from_context(
707 struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes);
708
dcn21_ipp_create(struct dc_context * ctx,uint32_t inst)709 static struct input_pixel_processor *dcn21_ipp_create(
710 struct dc_context *ctx, uint32_t inst)
711 {
712 struct dcn10_ipp *ipp =
713 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);
714
715 if (!ipp) {
716 BREAK_TO_DEBUGGER();
717 return NULL;
718 }
719
720 dcn20_ipp_construct(ipp, ctx, inst,
721 &ipp_regs[inst], &ipp_shift, &ipp_mask);
722 return &ipp->base;
723 }
724
dcn21_dpp_create(struct dc_context * ctx,uint32_t inst)725 static struct dpp *dcn21_dpp_create(
726 struct dc_context *ctx,
727 uint32_t inst)
728 {
729 struct dcn20_dpp *dpp =
730 kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL);
731
732 if (!dpp)
733 return NULL;
734
735 if (dpp2_construct(dpp, ctx, inst,
736 &tf_regs[inst], &tf_shift, &tf_mask))
737 return &dpp->base;
738
739 BREAK_TO_DEBUGGER();
740 kfree(dpp);
741 return NULL;
742 }
743
dcn21_aux_engine_create(struct dc_context * ctx,uint32_t inst)744 static struct dce_aux *dcn21_aux_engine_create(
745 struct dc_context *ctx,
746 uint32_t inst)
747 {
748 struct aux_engine_dce110 *aux_engine =
749 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
750
751 if (!aux_engine)
752 return NULL;
753
754 dce110_aux_engine_construct(aux_engine, ctx, inst,
755 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
756 &aux_engine_regs[inst],
757 &aux_mask,
758 &aux_shift,
759 ctx->dc->caps.extended_aux_timeout_support);
760
761 return &aux_engine->base;
762 }
763
764 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
765
766 static const struct dce_i2c_registers i2c_hw_regs[] = {
767 i2c_inst_regs(1),
768 i2c_inst_regs(2),
769 i2c_inst_regs(3),
770 i2c_inst_regs(4),
771 i2c_inst_regs(5),
772 };
773
774 static const struct dce_i2c_shift i2c_shifts = {
775 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
776 };
777
778 static const struct dce_i2c_mask i2c_masks = {
779 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
780 };
781
dcn21_i2c_hw_create(struct dc_context * ctx,uint32_t inst)782 struct dce_i2c_hw *dcn21_i2c_hw_create(
783 struct dc_context *ctx,
784 uint32_t inst)
785 {
786 struct dce_i2c_hw *dce_i2c_hw =
787 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
788
789 if (!dce_i2c_hw)
790 return NULL;
791
792 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
793 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
794
795 return dce_i2c_hw;
796 }
797
798 static const struct resource_caps res_cap_rn = {
799 .num_timing_generator = 4,
800 .num_opp = 4,
801 .num_video_plane = 4,
802 .num_audio = 4, // 4 audio endpoints. 4 audio streams
803 .num_stream_encoder = 5,
804 .num_pll = 5, // maybe 3 because the last two used for USB-c
805 .num_dwb = 1,
806 .num_ddc = 5,
807 .num_vmid = 16,
808 .num_dsc = 3,
809 };
810
811 #ifdef DIAGS_BUILD
812 static const struct resource_caps res_cap_rn_FPGA_4pipe = {
813 .num_timing_generator = 4,
814 .num_opp = 4,
815 .num_video_plane = 4,
816 .num_audio = 7,
817 .num_stream_encoder = 4,
818 .num_pll = 4,
819 .num_dwb = 1,
820 .num_ddc = 4,
821 .num_dsc = 0,
822 };
823
824 static const struct resource_caps res_cap_rn_FPGA_2pipe_dsc = {
825 .num_timing_generator = 2,
826 .num_opp = 2,
827 .num_video_plane = 2,
828 .num_audio = 7,
829 .num_stream_encoder = 2,
830 .num_pll = 4,
831 .num_dwb = 1,
832 .num_ddc = 4,
833 .num_dsc = 2,
834 };
835 #endif
836
837 static const struct dc_plane_cap plane_cap = {
838 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
839 .blends_with_above = true,
840 .blends_with_below = true,
841 .per_pixel_alpha = true,
842
843 .pixel_format_support = {
844 .argb8888 = true,
845 .nv12 = true,
846 .fp16 = true,
847 .p010 = true
848 },
849
850 .max_upscale_factor = {
851 .argb8888 = 16000,
852 .nv12 = 16000,
853 .fp16 = 16000
854 },
855
856 .max_downscale_factor = {
857 .argb8888 = 250,
858 .nv12 = 250,
859 .fp16 = 250
860 },
861 64,
862 64
863 };
864
865 static const struct dc_debug_options debug_defaults_drv = {
866 .disable_dmcu = false,
867 .force_abm_enable = false,
868 .timing_trace = false,
869 .clock_trace = true,
870 .disable_pplib_clock_request = true,
871 .min_disp_clk_khz = 100000,
872 .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
873 .force_single_disp_pipe_split = false,
874 .disable_dcc = DCC_ENABLE,
875 .vsr_support = true,
876 .performance_trace = false,
877 .max_downscale_src_width = 4096,
878 .disable_pplib_wm_range = false,
879 .scl_reset_length10 = true,
880 .sanity_checks = true,
881 .disable_48mhz_pwrdwn = false,
882 .usbc_combo_phy_reset_wa = true
883 };
884
885 static const struct dc_debug_options debug_defaults_diags = {
886 .disable_dmcu = false,
887 .force_abm_enable = false,
888 .timing_trace = true,
889 .clock_trace = true,
890 .disable_dpp_power_gate = true,
891 .disable_hubp_power_gate = true,
892 .disable_clock_gate = true,
893 .disable_pplib_clock_request = true,
894 .disable_pplib_wm_range = true,
895 .disable_stutter = true,
896 .disable_48mhz_pwrdwn = true,
897 .disable_psr = true,
898 .enable_tri_buf = true
899 };
900
901 enum dcn20_clk_src_array_id {
902 DCN20_CLK_SRC_PLL0,
903 DCN20_CLK_SRC_PLL1,
904 DCN20_CLK_SRC_PLL2,
905 DCN20_CLK_SRC_PLL3,
906 DCN20_CLK_SRC_PLL4,
907 DCN20_CLK_SRC_TOTAL_DCN21
908 };
909
dcn21_resource_destruct(struct dcn21_resource_pool * pool)910 static void dcn21_resource_destruct(struct dcn21_resource_pool *pool)
911 {
912 unsigned int i;
913
914 for (i = 0; i < pool->base.stream_enc_count; i++) {
915 if (pool->base.stream_enc[i] != NULL) {
916 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
917 pool->base.stream_enc[i] = NULL;
918 }
919 }
920
921 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
922 if (pool->base.dscs[i] != NULL)
923 dcn20_dsc_destroy(&pool->base.dscs[i]);
924 }
925
926 if (pool->base.mpc != NULL) {
927 kfree(TO_DCN20_MPC(pool->base.mpc));
928 pool->base.mpc = NULL;
929 }
930 if (pool->base.hubbub != NULL) {
931 kfree(pool->base.hubbub);
932 pool->base.hubbub = NULL;
933 }
934 for (i = 0; i < pool->base.pipe_count; i++) {
935 if (pool->base.dpps[i] != NULL)
936 dcn20_dpp_destroy(&pool->base.dpps[i]);
937
938 if (pool->base.ipps[i] != NULL)
939 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
940
941 if (pool->base.hubps[i] != NULL) {
942 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
943 pool->base.hubps[i] = NULL;
944 }
945
946 if (pool->base.irqs != NULL) {
947 dal_irq_service_destroy(&pool->base.irqs);
948 }
949 }
950
951 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
952 if (pool->base.engines[i] != NULL)
953 dce110_engine_destroy(&pool->base.engines[i]);
954 if (pool->base.hw_i2cs[i] != NULL) {
955 kfree(pool->base.hw_i2cs[i]);
956 pool->base.hw_i2cs[i] = NULL;
957 }
958 if (pool->base.sw_i2cs[i] != NULL) {
959 kfree(pool->base.sw_i2cs[i]);
960 pool->base.sw_i2cs[i] = NULL;
961 }
962 }
963
964 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
965 if (pool->base.opps[i] != NULL)
966 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
967 }
968
969 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
970 if (pool->base.timing_generators[i] != NULL) {
971 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
972 pool->base.timing_generators[i] = NULL;
973 }
974 }
975
976 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
977 if (pool->base.dwbc[i] != NULL) {
978 kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
979 pool->base.dwbc[i] = NULL;
980 }
981 if (pool->base.mcif_wb[i] != NULL) {
982 kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));
983 pool->base.mcif_wb[i] = NULL;
984 }
985 }
986
987 for (i = 0; i < pool->base.audio_count; i++) {
988 if (pool->base.audios[i])
989 dce_aud_destroy(&pool->base.audios[i]);
990 }
991
992 for (i = 0; i < pool->base.clk_src_count; i++) {
993 if (pool->base.clock_sources[i] != NULL) {
994 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
995 pool->base.clock_sources[i] = NULL;
996 }
997 }
998
999 if (pool->base.dp_clock_source != NULL) {
1000 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1001 pool->base.dp_clock_source = NULL;
1002 }
1003
1004 if (pool->base.abm != NULL) {
1005 if (pool->base.abm->ctx->dc->config.disable_dmcu)
1006 dmub_abm_destroy(&pool->base.abm);
1007 else
1008 dce_abm_destroy(&pool->base.abm);
1009 }
1010
1011 if (pool->base.dmcu != NULL)
1012 dce_dmcu_destroy(&pool->base.dmcu);
1013
1014 if (pool->base.psr != NULL)
1015 dmub_psr_destroy(&pool->base.psr);
1016
1017 if (pool->base.dccg != NULL)
1018 dcn_dccg_destroy(&pool->base.dccg);
1019
1020 if (pool->base.pp_smu != NULL)
1021 dcn21_pp_smu_destroy(&pool->base.pp_smu);
1022 }
1023
1024
calculate_wm_set_for_vlevel(int vlevel,struct wm_range_table_entry * table_entry,struct dcn_watermarks * wm_set,struct display_mode_lib * dml,display_e2e_pipe_params_st * pipes,int pipe_cnt)1025 static void calculate_wm_set_for_vlevel(
1026 int vlevel,
1027 struct wm_range_table_entry *table_entry,
1028 struct dcn_watermarks *wm_set,
1029 struct display_mode_lib *dml,
1030 display_e2e_pipe_params_st *pipes,
1031 int pipe_cnt)
1032 {
1033 double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us;
1034
1035 ASSERT(vlevel < dml->soc.num_states);
1036 /* only pipe 0 is read for voltage and dcf/soc clocks */
1037 pipes[0].clks_cfg.voltage = vlevel;
1038 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz;
1039 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz;
1040
1041 dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us;
1042 dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us;
1043 dml->soc.sr_enter_plus_exit_time_us = table_entry->sr_enter_plus_exit_time_us;
1044
1045 wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000;
1046 wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000;
1047 wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000;
1048 wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000;
1049 wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000;
1050 wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000;
1051 wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000;
1052 wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) * 1000;
1053 dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached;
1054
1055 }
1056
patch_bounding_box(struct dc * dc,struct _vcs_dpi_soc_bounding_box_st * bb)1057 static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
1058 {
1059 int i;
1060
1061 if (dc->bb_overrides.sr_exit_time_ns) {
1062 for (i = 0; i < WM_SET_COUNT; i++) {
1063 dc->clk_mgr->bw_params->wm_table.entries[i].sr_exit_time_us =
1064 dc->bb_overrides.sr_exit_time_ns / 1000.0;
1065 }
1066 }
1067
1068 if (dc->bb_overrides.sr_enter_plus_exit_time_ns) {
1069 for (i = 0; i < WM_SET_COUNT; i++) {
1070 dc->clk_mgr->bw_params->wm_table.entries[i].sr_enter_plus_exit_time_us =
1071 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
1072 }
1073 }
1074
1075 if (dc->bb_overrides.urgent_latency_ns) {
1076 bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
1077 }
1078
1079 if (dc->bb_overrides.dram_clock_change_latency_ns) {
1080 for (i = 0; i < WM_SET_COUNT; i++) {
1081 dc->clk_mgr->bw_params->wm_table.entries[i].pstate_latency_us =
1082 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
1083 }
1084 }
1085 }
1086
dcn21_calculate_wm(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int * out_pipe_cnt,int * pipe_split_from,int vlevel_req)1087 void dcn21_calculate_wm(
1088 struct dc *dc, struct dc_state *context,
1089 display_e2e_pipe_params_st *pipes,
1090 int *out_pipe_cnt,
1091 int *pipe_split_from,
1092 int vlevel_req)
1093 {
1094 int pipe_cnt, i, pipe_idx;
1095 int vlevel, vlevel_max;
1096 struct wm_range_table_entry *table_entry;
1097 struct clk_bw_params *bw_params = dc->clk_mgr->bw_params;
1098
1099 ASSERT(bw_params);
1100
1101 patch_bounding_box(dc, &context->bw_ctx.dml.soc);
1102
1103 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1104 if (!context->res_ctx.pipe_ctx[i].stream)
1105 continue;
1106
1107 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
1108 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb];
1109
1110 if (pipe_split_from[i] < 0) {
1111 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
1112 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
1113 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
1114 pipes[pipe_cnt].pipe.dest.odm_combine =
1115 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_idx];
1116 else
1117 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
1118 pipe_idx++;
1119 } else {
1120 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
1121 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
1122 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])
1123 pipes[pipe_cnt].pipe.dest.odm_combine =
1124 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_split_from[i]];
1125 else
1126 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
1127 }
1128 pipe_cnt++;
1129 }
1130
1131 if (pipe_cnt != pipe_idx) {
1132 if (dc->res_pool->funcs->populate_dml_pipes)
1133 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
1134 context, pipes);
1135 else
1136 pipe_cnt = dcn21_populate_dml_pipes_from_context(dc,
1137 context, pipes);
1138 }
1139
1140 *out_pipe_cnt = pipe_cnt;
1141
1142 vlevel_max = bw_params->clk_table.num_entries - 1;
1143
1144
1145 /* WM Set D */
1146 table_entry = &bw_params->wm_table.entries[WM_D];
1147 if (table_entry->wm_type == WM_TYPE_RETRAINING)
1148 vlevel = 0;
1149 else
1150 vlevel = vlevel_max;
1151 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d,
1152 &context->bw_ctx.dml, pipes, pipe_cnt);
1153 /* WM Set C */
1154 table_entry = &bw_params->wm_table.entries[WM_C];
1155 vlevel = MIN(MAX(vlevel_req, 2), vlevel_max);
1156 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c,
1157 &context->bw_ctx.dml, pipes, pipe_cnt);
1158 /* WM Set B */
1159 table_entry = &bw_params->wm_table.entries[WM_B];
1160 vlevel = MIN(MAX(vlevel_req, 1), vlevel_max);
1161 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b,
1162 &context->bw_ctx.dml, pipes, pipe_cnt);
1163
1164 /* WM Set A */
1165 table_entry = &bw_params->wm_table.entries[WM_A];
1166 vlevel = MIN(vlevel_req, vlevel_max);
1167 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a,
1168 &context->bw_ctx.dml, pipes, pipe_cnt);
1169 }
1170
1171
dcn21_validate_bandwidth_fp(struct dc * dc,struct dc_state * context,bool fast_validate)1172 static noinline bool dcn21_validate_bandwidth_fp(struct dc *dc,
1173 struct dc_state *context, bool fast_validate)
1174 {
1175 bool out = false;
1176
1177 BW_VAL_TRACE_SETUP();
1178
1179 int vlevel = 0;
1180 int pipe_split_from[MAX_PIPES];
1181 int pipe_cnt = 0;
1182 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_ATOMIC);
1183 DC_LOGGER_INIT(dc->ctx->logger);
1184
1185 BW_VAL_TRACE_COUNT();
1186
1187 /*Unsafe due to current pipe merge and split logic*/
1188 ASSERT(context != dc->current_state);
1189
1190 out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel);
1191
1192 if (pipe_cnt == 0)
1193 goto validate_out;
1194
1195 if (!out)
1196 goto validate_fail;
1197
1198 BW_VAL_TRACE_END_VOLTAGE_LEVEL();
1199
1200 if (fast_validate) {
1201 BW_VAL_TRACE_SKIP(fast);
1202 goto validate_out;
1203 }
1204
1205 dcn21_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel);
1206 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
1207
1208 BW_VAL_TRACE_END_WATERMARKS();
1209
1210 goto validate_out;
1211
1212 validate_fail:
1213 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
1214 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
1215
1216 BW_VAL_TRACE_SKIP(fail);
1217 out = false;
1218
1219 validate_out:
1220 kfree(pipes);
1221
1222 BW_VAL_TRACE_FINISH();
1223
1224 return out;
1225 }
1226
1227 /*
1228 * Some of the functions further below use the FPU, so we need to wrap this
1229 * with DC_FP_START()/DC_FP_END(). Use the same approach as for
1230 * dcn20_validate_bandwidth in dcn20_resource.c.
1231 */
dcn21_validate_bandwidth(struct dc * dc,struct dc_state * context,bool fast_validate)1232 bool dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context,
1233 bool fast_validate)
1234 {
1235 bool voltage_supported;
1236 DC_FP_START();
1237 voltage_supported = dcn21_validate_bandwidth_fp(dc, context, fast_validate);
1238 DC_FP_END();
1239 return voltage_supported;
1240 }
1241
dcn21_destroy_resource_pool(struct resource_pool ** pool)1242 static void dcn21_destroy_resource_pool(struct resource_pool **pool)
1243 {
1244 struct dcn21_resource_pool *dcn21_pool = TO_DCN21_RES_POOL(*pool);
1245
1246 dcn21_resource_destruct(dcn21_pool);
1247 kfree(dcn21_pool);
1248 *pool = NULL;
1249 }
1250
dcn21_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)1251 static struct clock_source *dcn21_clock_source_create(
1252 struct dc_context *ctx,
1253 struct dc_bios *bios,
1254 enum clock_source_id id,
1255 const struct dce110_clk_src_regs *regs,
1256 bool dp_clk_src)
1257 {
1258 struct dce110_clk_src *clk_src =
1259 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1260
1261 if (!clk_src)
1262 return NULL;
1263
1264 if (dcn20_clk_src_construct(clk_src, ctx, bios, id,
1265 regs, &cs_shift, &cs_mask)) {
1266 clk_src->base.dp_clk_src = dp_clk_src;
1267 return &clk_src->base;
1268 }
1269
1270 BREAK_TO_DEBUGGER();
1271 return NULL;
1272 }
1273
dcn21_hubp_create(struct dc_context * ctx,uint32_t inst)1274 static struct hubp *dcn21_hubp_create(
1275 struct dc_context *ctx,
1276 uint32_t inst)
1277 {
1278 struct dcn21_hubp *hubp21 =
1279 kzalloc(sizeof(struct dcn21_hubp), GFP_KERNEL);
1280
1281 if (!hubp21)
1282 return NULL;
1283
1284 if (hubp21_construct(hubp21, ctx, inst,
1285 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1286 return &hubp21->base;
1287
1288 BREAK_TO_DEBUGGER();
1289 kfree(hubp21);
1290 return NULL;
1291 }
1292
dcn21_hubbub_create(struct dc_context * ctx)1293 static struct hubbub *dcn21_hubbub_create(struct dc_context *ctx)
1294 {
1295 int i;
1296
1297 struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub),
1298 GFP_KERNEL);
1299
1300 if (!hubbub)
1301 return NULL;
1302
1303 hubbub21_construct(hubbub, ctx,
1304 &hubbub_reg,
1305 &hubbub_shift,
1306 &hubbub_mask);
1307
1308 for (i = 0; i < res_cap_rn.num_vmid; i++) {
1309 struct dcn20_vmid *vmid = &hubbub->vmid[i];
1310
1311 vmid->ctx = ctx;
1312
1313 vmid->regs = &vmid_regs[i];
1314 vmid->shifts = &vmid_shifts;
1315 vmid->masks = &vmid_masks;
1316 }
1317 hubbub->num_vmid = res_cap_rn.num_vmid;
1318
1319 return &hubbub->base;
1320 }
1321
dcn21_opp_create(struct dc_context * ctx,uint32_t inst)1322 struct output_pixel_processor *dcn21_opp_create(
1323 struct dc_context *ctx, uint32_t inst)
1324 {
1325 struct dcn20_opp *opp =
1326 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
1327
1328 if (!opp) {
1329 BREAK_TO_DEBUGGER();
1330 return NULL;
1331 }
1332
1333 dcn20_opp_construct(opp, ctx, inst,
1334 &opp_regs[inst], &opp_shift, &opp_mask);
1335 return &opp->base;
1336 }
1337
dcn21_timing_generator_create(struct dc_context * ctx,uint32_t instance)1338 struct timing_generator *dcn21_timing_generator_create(
1339 struct dc_context *ctx,
1340 uint32_t instance)
1341 {
1342 struct optc *tgn10 =
1343 kzalloc(sizeof(struct optc), GFP_KERNEL);
1344
1345 if (!tgn10)
1346 return NULL;
1347
1348 tgn10->base.inst = instance;
1349 tgn10->base.ctx = ctx;
1350
1351 tgn10->tg_regs = &tg_regs[instance];
1352 tgn10->tg_shift = &tg_shift;
1353 tgn10->tg_mask = &tg_mask;
1354
1355 dcn20_timing_generator_init(tgn10);
1356
1357 return &tgn10->base;
1358 }
1359
dcn21_mpc_create(struct dc_context * ctx)1360 struct mpc *dcn21_mpc_create(struct dc_context *ctx)
1361 {
1362 struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc),
1363 GFP_KERNEL);
1364
1365 if (!mpc20)
1366 return NULL;
1367
1368 dcn20_mpc_construct(mpc20, ctx,
1369 &mpc_regs,
1370 &mpc_shift,
1371 &mpc_mask,
1372 6);
1373
1374 return &mpc20->base;
1375 }
1376
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)1377 static void read_dce_straps(
1378 struct dc_context *ctx,
1379 struct resource_straps *straps)
1380 {
1381 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
1382 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1383
1384 }
1385
1386
dcn21_dsc_create(struct dc_context * ctx,uint32_t inst)1387 struct display_stream_compressor *dcn21_dsc_create(
1388 struct dc_context *ctx, uint32_t inst)
1389 {
1390 struct dcn20_dsc *dsc =
1391 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1392
1393 if (!dsc) {
1394 BREAK_TO_DEBUGGER();
1395 return NULL;
1396 }
1397
1398 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1399 return &dsc->base;
1400 }
1401
update_bw_bounding_box(struct dc * dc,struct clk_bw_params * bw_params)1402 static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1403 {
1404 struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool);
1405 struct clk_limit_table *clk_table = &bw_params->clk_table;
1406 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
1407 unsigned int i, closest_clk_lvl;
1408 int j;
1409
1410 // Default clock levels are used for diags, which may lead to overclocking.
1411 if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
1412 dcn2_1_ip.max_num_otg = pool->base.res_cap->num_timing_generator;
1413 dcn2_1_ip.max_num_dpp = pool->base.pipe_count;
1414 dcn2_1_soc.num_chans = bw_params->num_channels;
1415
1416 ASSERT(clk_table->num_entries);
1417 for (i = 0; i < clk_table->num_entries; i++) {
1418 /* loop backwards*/
1419 for (closest_clk_lvl = 0, j = dcn2_1_soc.num_states - 1; j >= 0; j--) {
1420 if ((unsigned int) dcn2_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) {
1421 closest_clk_lvl = j;
1422 break;
1423 }
1424 }
1425
1426 clock_limits[i].state = i;
1427 clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
1428 clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
1429 clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
1430 clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;
1431
1432 clock_limits[i].dispclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
1433 clock_limits[i].dppclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
1434 clock_limits[i].dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
1435 clock_limits[i].dscclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
1436 clock_limits[i].dtbclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
1437 clock_limits[i].phyclk_d18_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
1438 clock_limits[i].phyclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
1439 }
1440 for (i = 0; i < clk_table->num_entries; i++)
1441 dcn2_1_soc.clock_limits[i] = clock_limits[i];
1442 if (clk_table->num_entries) {
1443 dcn2_1_soc.num_states = clk_table->num_entries;
1444 /* duplicate last level */
1445 dcn2_1_soc.clock_limits[dcn2_1_soc.num_states] = dcn2_1_soc.clock_limits[dcn2_1_soc.num_states - 1];
1446 dcn2_1_soc.clock_limits[dcn2_1_soc.num_states].state = dcn2_1_soc.num_states;
1447 }
1448 }
1449
1450 dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);
1451 }
1452
1453 /* Temporary Place holder until we can get them from fuse */
1454 static struct dpm_clocks dummy_clocks = {
1455 .DcfClocks = {
1456 {.Freq = 400, .Vol = 1},
1457 {.Freq = 483, .Vol = 1},
1458 {.Freq = 602, .Vol = 1},
1459 {.Freq = 738, .Vol = 1} },
1460 .SocClocks = {
1461 {.Freq = 300, .Vol = 1},
1462 {.Freq = 400, .Vol = 1},
1463 {.Freq = 400, .Vol = 1},
1464 {.Freq = 400, .Vol = 1} },
1465 .FClocks = {
1466 {.Freq = 400, .Vol = 1},
1467 {.Freq = 800, .Vol = 1},
1468 {.Freq = 1067, .Vol = 1},
1469 {.Freq = 1600, .Vol = 1} },
1470 .MemClocks = {
1471 {.Freq = 800, .Vol = 1},
1472 {.Freq = 1600, .Vol = 1},
1473 {.Freq = 1067, .Vol = 1},
1474 {.Freq = 1600, .Vol = 1} },
1475
1476 };
1477
dummy_set_wm_ranges(struct pp_smu * pp,struct pp_smu_wm_range_sets * ranges)1478 static enum pp_smu_status dummy_set_wm_ranges(struct pp_smu *pp,
1479 struct pp_smu_wm_range_sets *ranges)
1480 {
1481 return PP_SMU_RESULT_OK;
1482 }
1483
dummy_get_dpm_clock_table(struct pp_smu * pp,struct dpm_clocks * clock_table)1484 static enum pp_smu_status dummy_get_dpm_clock_table(struct pp_smu *pp,
1485 struct dpm_clocks *clock_table)
1486 {
1487 *clock_table = dummy_clocks;
1488 return PP_SMU_RESULT_OK;
1489 }
1490
dcn21_pp_smu_create(struct dc_context * ctx)1491 static struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx)
1492 {
1493 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
1494
1495 if (!pp_smu)
1496 return pp_smu;
1497
1498 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment) || IS_DIAG_DC(ctx->dce_environment)) {
1499 pp_smu->ctx.ver = PP_SMU_VER_RN;
1500 pp_smu->rn_funcs.get_dpm_clock_table = dummy_get_dpm_clock_table;
1501 pp_smu->rn_funcs.set_wm_ranges = dummy_set_wm_ranges;
1502 } else {
1503
1504 dm_pp_get_funcs(ctx, pp_smu);
1505
1506 if (pp_smu->ctx.ver != PP_SMU_VER_RN)
1507 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs));
1508 }
1509
1510 return pp_smu;
1511 }
1512
dcn21_pp_smu_destroy(struct pp_smu_funcs ** pp_smu)1513 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
1514 {
1515 if (pp_smu && *pp_smu) {
1516 kfree(*pp_smu);
1517 *pp_smu = NULL;
1518 }
1519 }
1520
dcn21_create_audio(struct dc_context * ctx,unsigned int inst)1521 static struct audio *dcn21_create_audio(
1522 struct dc_context *ctx, unsigned int inst)
1523 {
1524 return dce_audio_create(ctx, inst,
1525 &audio_regs[inst], &audio_shift, &audio_mask);
1526 }
1527
1528 static struct dc_cap_funcs cap_funcs = {
1529 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1530 };
1531
dcn21_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1532 struct stream_encoder *dcn21_stream_encoder_create(
1533 enum engine_id eng_id,
1534 struct dc_context *ctx)
1535 {
1536 struct dcn10_stream_encoder *enc1 =
1537 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1538
1539 if (!enc1)
1540 return NULL;
1541
1542 dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
1543 &stream_enc_regs[eng_id],
1544 &se_shift, &se_mask);
1545
1546 return &enc1->base;
1547 }
1548
1549 static const struct dce_hwseq_registers hwseq_reg = {
1550 HWSEQ_DCN21_REG_LIST()
1551 };
1552
1553 static const struct dce_hwseq_shift hwseq_shift = {
1554 HWSEQ_DCN21_MASK_SH_LIST(__SHIFT)
1555 };
1556
1557 static const struct dce_hwseq_mask hwseq_mask = {
1558 HWSEQ_DCN21_MASK_SH_LIST(_MASK)
1559 };
1560
dcn21_hwseq_create(struct dc_context * ctx)1561 static struct dce_hwseq *dcn21_hwseq_create(
1562 struct dc_context *ctx)
1563 {
1564 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1565
1566 if (hws) {
1567 hws->ctx = ctx;
1568 hws->regs = &hwseq_reg;
1569 hws->shifts = &hwseq_shift;
1570 hws->masks = &hwseq_mask;
1571 hws->wa.DEGVIDCN21 = true;
1572 hws->wa.disallow_self_refresh_during_multi_plane_transition = true;
1573 }
1574 return hws;
1575 }
1576
1577 static const struct resource_create_funcs res_create_funcs = {
1578 .read_dce_straps = read_dce_straps,
1579 .create_audio = dcn21_create_audio,
1580 .create_stream_encoder = dcn21_stream_encoder_create,
1581 .create_hwseq = dcn21_hwseq_create,
1582 };
1583
1584 static const struct resource_create_funcs res_create_maximus_funcs = {
1585 .read_dce_straps = NULL,
1586 .create_audio = NULL,
1587 .create_stream_encoder = NULL,
1588 .create_hwseq = dcn21_hwseq_create,
1589 };
1590
1591 static const struct encoder_feature_support link_enc_feature = {
1592 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1593 .max_hdmi_pixel_clock = 600000,
1594 .hdmi_ycbcr420_supported = true,
1595 .dp_ycbcr420_supported = true,
1596 .fec_supported = true,
1597 .flags.bits.IS_HBR2_CAPABLE = true,
1598 .flags.bits.IS_HBR3_CAPABLE = true,
1599 .flags.bits.IS_TPS3_CAPABLE = true,
1600 .flags.bits.IS_TPS4_CAPABLE = true
1601 };
1602
1603
1604 #define link_regs(id, phyid)\
1605 [id] = {\
1606 LE_DCN2_REG_LIST(id), \
1607 UNIPHY_DCN2_REG_LIST(phyid), \
1608 DPCS_DCN21_REG_LIST(id), \
1609 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
1610 }
1611
1612 static const struct dcn10_link_enc_registers link_enc_regs[] = {
1613 link_regs(0, A),
1614 link_regs(1, B),
1615 link_regs(2, C),
1616 link_regs(3, D),
1617 link_regs(4, E),
1618 };
1619
1620 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
1621 { DCN_PANEL_CNTL_REG_LIST() }
1622 };
1623
1624 static const struct dce_panel_cntl_shift panel_cntl_shift = {
1625 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
1626 };
1627
1628 static const struct dce_panel_cntl_mask panel_cntl_mask = {
1629 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
1630 };
1631
1632 #define aux_regs(id)\
1633 [id] = {\
1634 DCN2_AUX_REG_LIST(id)\
1635 }
1636
1637 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
1638 aux_regs(0),
1639 aux_regs(1),
1640 aux_regs(2),
1641 aux_regs(3),
1642 aux_regs(4)
1643 };
1644
1645 #define hpd_regs(id)\
1646 [id] = {\
1647 HPD_REG_LIST(id)\
1648 }
1649
1650 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
1651 hpd_regs(0),
1652 hpd_regs(1),
1653 hpd_regs(2),
1654 hpd_regs(3),
1655 hpd_regs(4)
1656 };
1657
1658 static const struct dcn10_link_enc_shift le_shift = {
1659 LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT),\
1660 DPCS_DCN21_MASK_SH_LIST(__SHIFT)
1661 };
1662
1663 static const struct dcn10_link_enc_mask le_mask = {
1664 LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\
1665 DPCS_DCN21_MASK_SH_LIST(_MASK)
1666 };
1667
map_transmitter_id_to_phy_instance(enum transmitter transmitter)1668 static int map_transmitter_id_to_phy_instance(
1669 enum transmitter transmitter)
1670 {
1671 switch (transmitter) {
1672 case TRANSMITTER_UNIPHY_A:
1673 return 0;
1674 break;
1675 case TRANSMITTER_UNIPHY_B:
1676 return 1;
1677 break;
1678 case TRANSMITTER_UNIPHY_C:
1679 return 2;
1680 break;
1681 case TRANSMITTER_UNIPHY_D:
1682 return 3;
1683 break;
1684 case TRANSMITTER_UNIPHY_E:
1685 return 4;
1686 break;
1687 default:
1688 ASSERT(0);
1689 return 0;
1690 }
1691 }
1692
dcn21_link_encoder_create(const struct encoder_init_data * enc_init_data)1693 static struct link_encoder *dcn21_link_encoder_create(
1694 const struct encoder_init_data *enc_init_data)
1695 {
1696 struct dcn21_link_encoder *enc21 =
1697 kzalloc(sizeof(struct dcn21_link_encoder), GFP_KERNEL);
1698 int link_regs_id;
1699
1700 if (!enc21)
1701 return NULL;
1702
1703 link_regs_id =
1704 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
1705
1706 dcn21_link_encoder_construct(enc21,
1707 enc_init_data,
1708 &link_enc_feature,
1709 &link_enc_regs[link_regs_id],
1710 &link_enc_aux_regs[enc_init_data->channel - 1],
1711 &link_enc_hpd_regs[enc_init_data->hpd_source],
1712 &le_shift,
1713 &le_mask);
1714
1715 return &enc21->enc10.base;
1716 }
1717
dcn21_panel_cntl_create(const struct panel_cntl_init_data * init_data)1718 static struct panel_cntl *dcn21_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1719 {
1720 struct dce_panel_cntl *panel_cntl =
1721 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
1722
1723 if (!panel_cntl)
1724 return NULL;
1725
1726 dce_panel_cntl_construct(panel_cntl,
1727 init_data,
1728 &panel_cntl_regs[init_data->inst],
1729 &panel_cntl_shift,
1730 &panel_cntl_mask);
1731
1732 return &panel_cntl->base;
1733 }
1734
1735 #define CTX ctx
1736
1737 #define REG(reg_name) \
1738 (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
1739
read_pipe_fuses(struct dc_context * ctx)1740 static uint32_t read_pipe_fuses(struct dc_context *ctx)
1741 {
1742 uint32_t value = REG_READ(CC_DC_PIPE_DIS);
1743 /* RV1 support max 4 pipes */
1744 value = value & 0xf;
1745 return value;
1746 }
1747
dcn21_populate_dml_pipes_from_context(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes)1748 static int dcn21_populate_dml_pipes_from_context(
1749 struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes)
1750 {
1751 uint32_t pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes);
1752 int i;
1753
1754 for (i = 0; i < pipe_cnt; i++) {
1755
1756 pipes[i].pipe.src.hostvm = 1;
1757 pipes[i].pipe.src.gpuvm = 1;
1758 }
1759
1760 return pipe_cnt;
1761 }
1762
dcn21_patch_unknown_plane_state(struct dc_plane_state * plane_state)1763 enum dc_status dcn21_patch_unknown_plane_state(struct dc_plane_state *plane_state)
1764 {
1765 enum dc_status result = DC_OK;
1766
1767 if (plane_state->ctx->dc->debug.disable_dcc == DCC_ENABLE) {
1768 plane_state->dcc.enable = 1;
1769 /* align to our worst case block width */
1770 plane_state->dcc.meta_pitch = ((plane_state->src_rect.width + 1023) / 1024) * 1024;
1771 }
1772 result = dcn20_patch_unknown_plane_state(plane_state);
1773 return result;
1774 }
1775
1776 static const struct resource_funcs dcn21_res_pool_funcs = {
1777 .destroy = dcn21_destroy_resource_pool,
1778 .link_enc_create = dcn21_link_encoder_create,
1779 .panel_cntl_create = dcn21_panel_cntl_create,
1780 .validate_bandwidth = dcn21_validate_bandwidth,
1781 .populate_dml_pipes = dcn21_populate_dml_pipes_from_context,
1782 .add_stream_to_ctx = dcn20_add_stream_to_ctx,
1783 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1784 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1785 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
1786 .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context,
1787 .patch_unknown_plane_state = dcn21_patch_unknown_plane_state,
1788 .set_mcif_arb_params = dcn20_set_mcif_arb_params,
1789 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1790 .update_bw_bounding_box = update_bw_bounding_box
1791 };
1792
dcn21_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dcn21_resource_pool * pool)1793 static bool dcn21_resource_construct(
1794 uint8_t num_virtual_links,
1795 struct dc *dc,
1796 struct dcn21_resource_pool *pool)
1797 {
1798 int i, j;
1799 struct dc_context *ctx = dc->ctx;
1800 struct irq_service_init_data init_data;
1801 uint32_t pipe_fuses = read_pipe_fuses(ctx);
1802 uint32_t num_pipes;
1803
1804 ctx->dc_bios->regs = &bios_regs;
1805
1806 pool->base.res_cap = &res_cap_rn;
1807 #ifdef DIAGS_BUILD
1808 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
1809 //pool->base.res_cap = &res_cap_nv10_FPGA_2pipe_dsc;
1810 pool->base.res_cap = &res_cap_rn_FPGA_4pipe;
1811 #endif
1812
1813 pool->base.funcs = &dcn21_res_pool_funcs;
1814
1815 /*************************************************
1816 * Resource + asic cap harcoding *
1817 *************************************************/
1818 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1819
1820 /* max pipe num for ASIC before check pipe fuses */
1821 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1822
1823 dc->caps.max_downscale_ratio = 200;
1824 dc->caps.i2c_speed_in_khz = 100;
1825 dc->caps.max_cursor_size = 256;
1826 dc->caps.dmdata_alloc_size = 2048;
1827
1828 dc->caps.max_slave_planes = 1;
1829 dc->caps.post_blend_color_processing = true;
1830 dc->caps.force_dp_tps4_for_cp2520 = true;
1831 dc->caps.extended_aux_timeout_support = true;
1832 dc->caps.dmcub_support = true;
1833 dc->caps.is_apu = true;
1834
1835 /* Color pipeline capabilities */
1836 dc->caps.color.dpp.dcn_arch = 1;
1837 dc->caps.color.dpp.input_lut_shared = 0;
1838 dc->caps.color.dpp.icsc = 1;
1839 dc->caps.color.dpp.dgam_ram = 1;
1840 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1841 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1842 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;
1843 dc->caps.color.dpp.dgam_rom_caps.pq = 0;
1844 dc->caps.color.dpp.dgam_rom_caps.hlg = 0;
1845 dc->caps.color.dpp.post_csc = 0;
1846 dc->caps.color.dpp.gamma_corr = 0;
1847
1848 dc->caps.color.dpp.hw_3d_lut = 1;
1849 dc->caps.color.dpp.ogam_ram = 1;
1850 // no OGAM ROM on DCN2
1851 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1852 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1853 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1854 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1855 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1856 dc->caps.color.dpp.ocsc = 0;
1857
1858 dc->caps.color.mpc.gamut_remap = 0;
1859 dc->caps.color.mpc.num_3dluts = 0;
1860 dc->caps.color.mpc.shared_3d_lut = 0;
1861 dc->caps.color.mpc.ogam_ram = 1;
1862 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1863 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1864 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1865 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1866 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1867 dc->caps.color.mpc.ocsc = 1;
1868
1869 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1870 dc->debug = debug_defaults_drv;
1871 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
1872 pool->base.pipe_count = 4;
1873 dc->debug = debug_defaults_diags;
1874 } else
1875 dc->debug = debug_defaults_diags;
1876
1877 // Init the vm_helper
1878 if (dc->vm_helper)
1879 vm_helper_init(dc->vm_helper, 16);
1880
1881 /*************************************************
1882 * Create resources *
1883 *************************************************/
1884
1885 pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =
1886 dcn21_clock_source_create(ctx, ctx->dc_bios,
1887 CLOCK_SOURCE_COMBO_PHY_PLL0,
1888 &clk_src_regs[0], false);
1889 pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =
1890 dcn21_clock_source_create(ctx, ctx->dc_bios,
1891 CLOCK_SOURCE_COMBO_PHY_PLL1,
1892 &clk_src_regs[1], false);
1893 pool->base.clock_sources[DCN20_CLK_SRC_PLL2] =
1894 dcn21_clock_source_create(ctx, ctx->dc_bios,
1895 CLOCK_SOURCE_COMBO_PHY_PLL2,
1896 &clk_src_regs[2], false);
1897 pool->base.clock_sources[DCN20_CLK_SRC_PLL3] =
1898 dcn21_clock_source_create(ctx, ctx->dc_bios,
1899 CLOCK_SOURCE_COMBO_PHY_PLL3,
1900 &clk_src_regs[3], false);
1901 pool->base.clock_sources[DCN20_CLK_SRC_PLL4] =
1902 dcn21_clock_source_create(ctx, ctx->dc_bios,
1903 CLOCK_SOURCE_COMBO_PHY_PLL4,
1904 &clk_src_regs[4], false);
1905
1906 pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN21;
1907
1908 /* todo: not reuse phy_pll registers */
1909 pool->base.dp_clock_source =
1910 dcn21_clock_source_create(ctx, ctx->dc_bios,
1911 CLOCK_SOURCE_ID_DP_DTO,
1912 &clk_src_regs[0], true);
1913
1914 for (i = 0; i < pool->base.clk_src_count; i++) {
1915 if (pool->base.clock_sources[i] == NULL) {
1916 dm_error("DC: failed to create clock sources!\n");
1917 BREAK_TO_DEBUGGER();
1918 goto create_fail;
1919 }
1920 }
1921
1922 pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1923 if (pool->base.dccg == NULL) {
1924 dm_error("DC: failed to create dccg!\n");
1925 BREAK_TO_DEBUGGER();
1926 goto create_fail;
1927 }
1928
1929 if (!dc->config.disable_dmcu) {
1930 pool->base.dmcu = dcn21_dmcu_create(ctx,
1931 &dmcu_regs,
1932 &dmcu_shift,
1933 &dmcu_mask);
1934 if (pool->base.dmcu == NULL) {
1935 dm_error("DC: failed to create dmcu!\n");
1936 BREAK_TO_DEBUGGER();
1937 goto create_fail;
1938 }
1939
1940 dc->debug.dmub_command_table = false;
1941 }
1942
1943 if (dc->config.disable_dmcu) {
1944 pool->base.psr = dmub_psr_create(ctx);
1945
1946 if (pool->base.psr == NULL) {
1947 dm_error("DC: failed to create psr obj!\n");
1948 BREAK_TO_DEBUGGER();
1949 goto create_fail;
1950 }
1951 }
1952
1953 if (dc->config.disable_dmcu)
1954 pool->base.abm = dmub_abm_create(ctx,
1955 &abm_regs,
1956 &abm_shift,
1957 &abm_mask);
1958 else
1959 pool->base.abm = dce_abm_create(ctx,
1960 &abm_regs,
1961 &abm_shift,
1962 &abm_mask);
1963
1964 pool->base.pp_smu = dcn21_pp_smu_create(ctx);
1965
1966 num_pipes = dcn2_1_ip.max_num_dpp;
1967
1968 for (i = 0; i < dcn2_1_ip.max_num_dpp; i++)
1969 if (pipe_fuses & 1 << i)
1970 num_pipes--;
1971 dcn2_1_ip.max_num_dpp = num_pipes;
1972 dcn2_1_ip.max_num_otg = num_pipes;
1973
1974 dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);
1975
1976 init_data.ctx = dc->ctx;
1977 pool->base.irqs = dal_irq_service_dcn21_create(&init_data);
1978 if (!pool->base.irqs)
1979 goto create_fail;
1980
1981 j = 0;
1982 /* mem input -> ipp -> dpp -> opp -> TG */
1983 for (i = 0; i < pool->base.pipe_count; i++) {
1984 /* if pipe is disabled, skip instance of HW pipe,
1985 * i.e, skip ASIC register instance
1986 */
1987 if ((pipe_fuses & (1 << i)) != 0)
1988 continue;
1989
1990 pool->base.hubps[j] = dcn21_hubp_create(ctx, i);
1991 if (pool->base.hubps[j] == NULL) {
1992 BREAK_TO_DEBUGGER();
1993 dm_error(
1994 "DC: failed to create memory input!\n");
1995 goto create_fail;
1996 }
1997
1998 pool->base.ipps[j] = dcn21_ipp_create(ctx, i);
1999 if (pool->base.ipps[j] == NULL) {
2000 BREAK_TO_DEBUGGER();
2001 dm_error(
2002 "DC: failed to create input pixel processor!\n");
2003 goto create_fail;
2004 }
2005
2006 pool->base.dpps[j] = dcn21_dpp_create(ctx, i);
2007 if (pool->base.dpps[j] == NULL) {
2008 BREAK_TO_DEBUGGER();
2009 dm_error(
2010 "DC: failed to create dpps!\n");
2011 goto create_fail;
2012 }
2013
2014 pool->base.opps[j] = dcn21_opp_create(ctx, i);
2015 if (pool->base.opps[j] == NULL) {
2016 BREAK_TO_DEBUGGER();
2017 dm_error(
2018 "DC: failed to create output pixel processor!\n");
2019 goto create_fail;
2020 }
2021
2022 pool->base.timing_generators[j] = dcn21_timing_generator_create(
2023 ctx, i);
2024 if (pool->base.timing_generators[j] == NULL) {
2025 BREAK_TO_DEBUGGER();
2026 dm_error("DC: failed to create tg!\n");
2027 goto create_fail;
2028 }
2029 j++;
2030 }
2031
2032 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2033 pool->base.engines[i] = dcn21_aux_engine_create(ctx, i);
2034 if (pool->base.engines[i] == NULL) {
2035 BREAK_TO_DEBUGGER();
2036 dm_error(
2037 "DC:failed to create aux engine!!\n");
2038 goto create_fail;
2039 }
2040 pool->base.hw_i2cs[i] = dcn21_i2c_hw_create(ctx, i);
2041 if (pool->base.hw_i2cs[i] == NULL) {
2042 BREAK_TO_DEBUGGER();
2043 dm_error(
2044 "DC:failed to create hw i2c!!\n");
2045 goto create_fail;
2046 }
2047 pool->base.sw_i2cs[i] = NULL;
2048 }
2049
2050 pool->base.timing_generator_count = j;
2051 pool->base.pipe_count = j;
2052 pool->base.mpcc_count = j;
2053
2054 pool->base.mpc = dcn21_mpc_create(ctx);
2055 if (pool->base.mpc == NULL) {
2056 BREAK_TO_DEBUGGER();
2057 dm_error("DC: failed to create mpc!\n");
2058 goto create_fail;
2059 }
2060
2061 pool->base.hubbub = dcn21_hubbub_create(ctx);
2062 if (pool->base.hubbub == NULL) {
2063 BREAK_TO_DEBUGGER();
2064 dm_error("DC: failed to create hubbub!\n");
2065 goto create_fail;
2066 }
2067
2068 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2069 pool->base.dscs[i] = dcn21_dsc_create(ctx, i);
2070 if (pool->base.dscs[i] == NULL) {
2071 BREAK_TO_DEBUGGER();
2072 dm_error("DC: failed to create display stream compressor %d!\n", i);
2073 goto create_fail;
2074 }
2075 }
2076
2077 if (!dcn20_dwbc_create(ctx, &pool->base)) {
2078 BREAK_TO_DEBUGGER();
2079 dm_error("DC: failed to create dwbc!\n");
2080 goto create_fail;
2081 }
2082 if (!dcn20_mmhubbub_create(ctx, &pool->base)) {
2083 BREAK_TO_DEBUGGER();
2084 dm_error("DC: failed to create mcif_wb!\n");
2085 goto create_fail;
2086 }
2087
2088 if (!resource_construct(num_virtual_links, dc, &pool->base,
2089 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
2090 &res_create_funcs : &res_create_maximus_funcs)))
2091 goto create_fail;
2092
2093 dcn21_hw_sequencer_construct(dc);
2094
2095 dc->caps.max_planes = pool->base.pipe_count;
2096
2097 for (i = 0; i < dc->caps.max_planes; ++i)
2098 dc->caps.planes[i] = plane_cap;
2099
2100 dc->cap_funcs = cap_funcs;
2101
2102 return true;
2103
2104 create_fail:
2105
2106 dcn21_resource_destruct(pool);
2107
2108 return false;
2109 }
2110
dcn21_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)2111 struct resource_pool *dcn21_create_resource_pool(
2112 const struct dc_init_data *init_data,
2113 struct dc *dc)
2114 {
2115 struct dcn21_resource_pool *pool =
2116 kzalloc(sizeof(struct dcn21_resource_pool), GFP_KERNEL);
2117
2118 if (!pool)
2119 return NULL;
2120
2121 if (dcn21_resource_construct(init_data->num_virtual_links, dc, pool))
2122 return &pool->base;
2123
2124 BREAK_TO_DEBUGGER();
2125 kfree(pool);
2126 return NULL;
2127 }
2128