1 /*
2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
4 *
5 * Copyright(c) 2012 Intel Corporation. All rights reserved.
6 *
7 * GPL LICENSE SUMMARY
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 * The full GNU General Public License is included in this distribution
18 * in the file called LICENSE.GPL.
19 *
20 * BSD LICENSE
21 *
22 * Redistribution and use in source and binary forms, with or without
23 * modification, are permitted provided that the following conditions
24 * are met:
25 *
26 * * Redistributions of source code must retain the above copyright
27 * notice, this list of conditions and the following disclaimer.
28 * * Redistributions in binary form must reproduce the above copyright
29 * notice, this list of conditions and the following disclaimer in
30 * the documentation and/or other materials provided with the
31 * distribution.
32 * * Neither the name of Intel Corporation nor the names of its
33 * contributors may be used to endorse or promote products derived
34 * from this software without specific prior written permission.
35 *
36 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
37 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
38 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
39 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
40 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
41 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
42 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
43 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
44 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
45 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
46 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
47 */
48
49 /*
50 * Supports the SMBus Message Transport (SMT) in the Intel Atom Processor
51 * S12xx Product Family.
52 *
53 * Features supported by this driver:
54 * Hardware PEC yes
55 * Block buffer yes
56 * Block process call transaction no
57 * Slave mode no
58 */
59
60 #include <linux/module.h>
61 #include <linux/pci.h>
62 #include <linux/kernel.h>
63 #include <linux/stddef.h>
64 #include <linux/completion.h>
65 #include <linux/dma-mapping.h>
66 #include <linux/i2c.h>
67 #include <linux/acpi.h>
68 #include <linux/interrupt.h>
69
70 #include <linux/io-64-nonatomic-lo-hi.h>
71
72 /* PCI Address Constants */
73 #define SMBBAR 0
74
75 /* PCI DIDs for the Intel SMBus Message Transport (SMT) Devices */
76 #define PCI_DEVICE_ID_INTEL_S1200_SMT0 0x0c59
77 #define PCI_DEVICE_ID_INTEL_S1200_SMT1 0x0c5a
78 #define PCI_DEVICE_ID_INTEL_CDF_SMT 0x18ac
79 #define PCI_DEVICE_ID_INTEL_DNV_SMT 0x19ac
80 #define PCI_DEVICE_ID_INTEL_EBG_SMT 0x1bff
81 #define PCI_DEVICE_ID_INTEL_AVOTON_SMT 0x1f15
82
83 #define ISMT_DESC_ENTRIES 2 /* number of descriptor entries */
84 #define ISMT_MAX_RETRIES 3 /* number of SMBus retries to attempt */
85
86 /* Hardware Descriptor Constants - Control Field */
87 #define ISMT_DESC_CWRL 0x01 /* Command/Write Length */
88 #define ISMT_DESC_BLK 0X04 /* Perform Block Transaction */
89 #define ISMT_DESC_FAIR 0x08 /* Set fairness flag upon successful arbit. */
90 #define ISMT_DESC_PEC 0x10 /* Packet Error Code */
91 #define ISMT_DESC_I2C 0x20 /* I2C Enable */
92 #define ISMT_DESC_INT 0x40 /* Interrupt */
93 #define ISMT_DESC_SOE 0x80 /* Stop On Error */
94
95 /* Hardware Descriptor Constants - Status Field */
96 #define ISMT_DESC_SCS 0x01 /* Success */
97 #define ISMT_DESC_DLTO 0x04 /* Data Low Time Out */
98 #define ISMT_DESC_NAK 0x08 /* NAK Received */
99 #define ISMT_DESC_CRC 0x10 /* CRC Error */
100 #define ISMT_DESC_CLTO 0x20 /* Clock Low Time Out */
101 #define ISMT_DESC_COL 0x40 /* Collisions */
102 #define ISMT_DESC_LPR 0x80 /* Large Packet Received */
103
104 /* Macros */
105 #define ISMT_DESC_ADDR_RW(addr, rw) (((addr) << 1) | (rw))
106
107 /* iSMT General Register address offsets (SMBBAR + <addr>) */
108 #define ISMT_GR_GCTRL 0x000 /* General Control */
109 #define ISMT_GR_SMTICL 0x008 /* SMT Interrupt Cause Location */
110 #define ISMT_GR_ERRINTMSK 0x010 /* Error Interrupt Mask */
111 #define ISMT_GR_ERRAERMSK 0x014 /* Error AER Mask */
112 #define ISMT_GR_ERRSTS 0x018 /* Error Status */
113 #define ISMT_GR_ERRINFO 0x01c /* Error Information */
114
115 /* iSMT Master Registers */
116 #define ISMT_MSTR_MDBA 0x100 /* Master Descriptor Base Address */
117 #define ISMT_MSTR_MCTRL 0x108 /* Master Control */
118 #define ISMT_MSTR_MSTS 0x10c /* Master Status */
119 #define ISMT_MSTR_MDS 0x110 /* Master Descriptor Size */
120 #define ISMT_MSTR_RPOLICY 0x114 /* Retry Policy */
121
122 /* iSMT Miscellaneous Registers */
123 #define ISMT_SPGT 0x300 /* SMBus PHY Global Timing */
124
125 /* General Control Register (GCTRL) bit definitions */
126 #define ISMT_GCTRL_TRST 0x04 /* Target Reset */
127 #define ISMT_GCTRL_KILL 0x08 /* Kill */
128 #define ISMT_GCTRL_SRST 0x40 /* Soft Reset */
129
130 /* Master Control Register (MCTRL) bit definitions */
131 #define ISMT_MCTRL_SS 0x01 /* Start/Stop */
132 #define ISMT_MCTRL_MEIE 0x10 /* Master Error Interrupt Enable */
133 #define ISMT_MCTRL_FMHP 0x00ff0000 /* Firmware Master Head Ptr (FMHP) */
134
135 /* Master Status Register (MSTS) bit definitions */
136 #define ISMT_MSTS_HMTP 0xff0000 /* HW Master Tail Pointer (HMTP) */
137 #define ISMT_MSTS_MIS 0x20 /* Master Interrupt Status (MIS) */
138 #define ISMT_MSTS_MEIS 0x10 /* Master Error Int Status (MEIS) */
139 #define ISMT_MSTS_IP 0x01 /* In Progress */
140
141 /* Master Descriptor Size (MDS) bit definitions */
142 #define ISMT_MDS_MASK 0xff /* Master Descriptor Size mask (MDS) */
143
144 /* SMBus PHY Global Timing Register (SPGT) bit definitions */
145 #define ISMT_SPGT_SPD_MASK 0xc0000000 /* SMBus Speed mask */
146 #define ISMT_SPGT_SPD_80K 0x00 /* 80 kHz */
147 #define ISMT_SPGT_SPD_100K (0x1 << 30) /* 100 kHz */
148 #define ISMT_SPGT_SPD_400K (0x2 << 30) /* 400 kHz */
149 #define ISMT_SPGT_SPD_1M (0x3 << 30) /* 1 MHz */
150
151
152 /* MSI Control Register (MSICTL) bit definitions */
153 #define ISMT_MSICTL_MSIE 0x01 /* MSI Enable */
154
155 /* iSMT Hardware Descriptor */
156 struct ismt_desc {
157 u8 tgtaddr_rw; /* target address & r/w bit */
158 u8 wr_len_cmd; /* write length in bytes or a command */
159 u8 rd_len; /* read length */
160 u8 control; /* control bits */
161 u8 status; /* status bits */
162 u8 retry; /* collision retry and retry count */
163 u8 rxbytes; /* received bytes */
164 u8 txbytes; /* transmitted bytes */
165 u32 dptr_low; /* lower 32 bit of the data pointer */
166 u32 dptr_high; /* upper 32 bit of the data pointer */
167 } __packed;
168
169 struct ismt_priv {
170 struct i2c_adapter adapter;
171 void __iomem *smba; /* PCI BAR */
172 struct pci_dev *pci_dev;
173 struct ismt_desc *hw; /* descriptor virt base addr */
174 dma_addr_t io_rng_dma; /* descriptor HW base addr */
175 u8 head; /* ring buffer head pointer */
176 struct completion cmp; /* interrupt completion */
177 u8 buffer[I2C_SMBUS_BLOCK_MAX + 16]; /* temp R/W data buffer */
178 };
179
180 static const struct pci_device_id ismt_ids[] = {
181 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_S1200_SMT0) },
182 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_S1200_SMT1) },
183 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CDF_SMT) },
184 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMT) },
185 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EBG_SMT) },
186 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMT) },
187 { 0, }
188 };
189
190 MODULE_DEVICE_TABLE(pci, ismt_ids);
191
192 /* Bus speed control bits for slow debuggers - refer to the docs for usage */
193 static unsigned int bus_speed;
194 module_param(bus_speed, uint, S_IRUGO);
195 MODULE_PARM_DESC(bus_speed, "Bus Speed in kHz (0 = BIOS default)");
196
197 /**
198 * __ismt_desc_dump() - dump the contents of a specific descriptor
199 * @dev: the iSMT device
200 * @desc: the iSMT hardware descriptor
201 */
__ismt_desc_dump(struct device * dev,const struct ismt_desc * desc)202 static void __ismt_desc_dump(struct device *dev, const struct ismt_desc *desc)
203 {
204
205 dev_dbg(dev, "Descriptor struct: %p\n", desc);
206 dev_dbg(dev, "\ttgtaddr_rw=0x%02X\n", desc->tgtaddr_rw);
207 dev_dbg(dev, "\twr_len_cmd=0x%02X\n", desc->wr_len_cmd);
208 dev_dbg(dev, "\trd_len= 0x%02X\n", desc->rd_len);
209 dev_dbg(dev, "\tcontrol= 0x%02X\n", desc->control);
210 dev_dbg(dev, "\tstatus= 0x%02X\n", desc->status);
211 dev_dbg(dev, "\tretry= 0x%02X\n", desc->retry);
212 dev_dbg(dev, "\trxbytes= 0x%02X\n", desc->rxbytes);
213 dev_dbg(dev, "\ttxbytes= 0x%02X\n", desc->txbytes);
214 dev_dbg(dev, "\tdptr_low= 0x%08X\n", desc->dptr_low);
215 dev_dbg(dev, "\tdptr_high= 0x%08X\n", desc->dptr_high);
216 }
217 /**
218 * ismt_desc_dump() - dump the contents of a descriptor for debug purposes
219 * @priv: iSMT private data
220 */
ismt_desc_dump(struct ismt_priv * priv)221 static void ismt_desc_dump(struct ismt_priv *priv)
222 {
223 struct device *dev = &priv->pci_dev->dev;
224 struct ismt_desc *desc = &priv->hw[priv->head];
225
226 dev_dbg(dev, "Dump of the descriptor struct: 0x%X\n", priv->head);
227 __ismt_desc_dump(dev, desc);
228 }
229
230 /**
231 * ismt_gen_reg_dump() - dump the iSMT General Registers
232 * @priv: iSMT private data
233 */
ismt_gen_reg_dump(struct ismt_priv * priv)234 static void ismt_gen_reg_dump(struct ismt_priv *priv)
235 {
236 struct device *dev = &priv->pci_dev->dev;
237
238 dev_dbg(dev, "Dump of the iSMT General Registers\n");
239 dev_dbg(dev, " GCTRL.... : (0x%p)=0x%X\n",
240 priv->smba + ISMT_GR_GCTRL,
241 readl(priv->smba + ISMT_GR_GCTRL));
242 dev_dbg(dev, " SMTICL... : (0x%p)=0x%016llX\n",
243 priv->smba + ISMT_GR_SMTICL,
244 (long long unsigned int)readq(priv->smba + ISMT_GR_SMTICL));
245 dev_dbg(dev, " ERRINTMSK : (0x%p)=0x%X\n",
246 priv->smba + ISMT_GR_ERRINTMSK,
247 readl(priv->smba + ISMT_GR_ERRINTMSK));
248 dev_dbg(dev, " ERRAERMSK : (0x%p)=0x%X\n",
249 priv->smba + ISMT_GR_ERRAERMSK,
250 readl(priv->smba + ISMT_GR_ERRAERMSK));
251 dev_dbg(dev, " ERRSTS... : (0x%p)=0x%X\n",
252 priv->smba + ISMT_GR_ERRSTS,
253 readl(priv->smba + ISMT_GR_ERRSTS));
254 dev_dbg(dev, " ERRINFO.. : (0x%p)=0x%X\n",
255 priv->smba + ISMT_GR_ERRINFO,
256 readl(priv->smba + ISMT_GR_ERRINFO));
257 }
258
259 /**
260 * ismt_mstr_reg_dump() - dump the iSMT Master Registers
261 * @priv: iSMT private data
262 */
ismt_mstr_reg_dump(struct ismt_priv * priv)263 static void ismt_mstr_reg_dump(struct ismt_priv *priv)
264 {
265 struct device *dev = &priv->pci_dev->dev;
266
267 dev_dbg(dev, "Dump of the iSMT Master Registers\n");
268 dev_dbg(dev, " MDBA..... : (0x%p)=0x%016llX\n",
269 priv->smba + ISMT_MSTR_MDBA,
270 (long long unsigned int)readq(priv->smba + ISMT_MSTR_MDBA));
271 dev_dbg(dev, " MCTRL.... : (0x%p)=0x%X\n",
272 priv->smba + ISMT_MSTR_MCTRL,
273 readl(priv->smba + ISMT_MSTR_MCTRL));
274 dev_dbg(dev, " MSTS..... : (0x%p)=0x%X\n",
275 priv->smba + ISMT_MSTR_MSTS,
276 readl(priv->smba + ISMT_MSTR_MSTS));
277 dev_dbg(dev, " MDS...... : (0x%p)=0x%X\n",
278 priv->smba + ISMT_MSTR_MDS,
279 readl(priv->smba + ISMT_MSTR_MDS));
280 dev_dbg(dev, " RPOLICY.. : (0x%p)=0x%X\n",
281 priv->smba + ISMT_MSTR_RPOLICY,
282 readl(priv->smba + ISMT_MSTR_RPOLICY));
283 dev_dbg(dev, " SPGT..... : (0x%p)=0x%X\n",
284 priv->smba + ISMT_SPGT,
285 readl(priv->smba + ISMT_SPGT));
286 }
287
288 /**
289 * ismt_submit_desc() - add a descriptor to the ring
290 * @priv: iSMT private data
291 */
ismt_submit_desc(struct ismt_priv * priv)292 static void ismt_submit_desc(struct ismt_priv *priv)
293 {
294 uint fmhp;
295 uint val;
296
297 ismt_desc_dump(priv);
298 ismt_gen_reg_dump(priv);
299 ismt_mstr_reg_dump(priv);
300
301 /* Set the FMHP (Firmware Master Head Pointer)*/
302 fmhp = ((priv->head + 1) % ISMT_DESC_ENTRIES) << 16;
303 val = readl(priv->smba + ISMT_MSTR_MCTRL);
304 writel((val & ~ISMT_MCTRL_FMHP) | fmhp,
305 priv->smba + ISMT_MSTR_MCTRL);
306
307 /* Set the start bit */
308 val = readl(priv->smba + ISMT_MSTR_MCTRL);
309 writel(val | ISMT_MCTRL_SS,
310 priv->smba + ISMT_MSTR_MCTRL);
311 }
312
313 /**
314 * ismt_process_desc() - handle the completion of the descriptor
315 * @desc: the iSMT hardware descriptor
316 * @data: data buffer from the upper layer
317 * @priv: ismt_priv struct holding our dma buffer
318 * @size: SMBus transaction type
319 * @read_write: flag to indicate if this is a read or write
320 */
ismt_process_desc(const struct ismt_desc * desc,union i2c_smbus_data * data,struct ismt_priv * priv,int size,char read_write)321 static int ismt_process_desc(const struct ismt_desc *desc,
322 union i2c_smbus_data *data,
323 struct ismt_priv *priv, int size,
324 char read_write)
325 {
326 u8 *dma_buffer = PTR_ALIGN(&priv->buffer[0], 16);
327
328 dev_dbg(&priv->pci_dev->dev, "Processing completed descriptor\n");
329 __ismt_desc_dump(&priv->pci_dev->dev, desc);
330 ismt_gen_reg_dump(priv);
331 ismt_mstr_reg_dump(priv);
332
333 if (desc->status & ISMT_DESC_SCS) {
334 if (read_write == I2C_SMBUS_WRITE &&
335 size != I2C_SMBUS_PROC_CALL)
336 return 0;
337
338 switch (size) {
339 case I2C_SMBUS_BYTE:
340 case I2C_SMBUS_BYTE_DATA:
341 data->byte = dma_buffer[0];
342 break;
343 case I2C_SMBUS_WORD_DATA:
344 case I2C_SMBUS_PROC_CALL:
345 data->word = dma_buffer[0] | (dma_buffer[1] << 8);
346 break;
347 case I2C_SMBUS_BLOCK_DATA:
348 if (desc->rxbytes != dma_buffer[0] + 1)
349 return -EMSGSIZE;
350
351 memcpy(data->block, dma_buffer, desc->rxbytes);
352 break;
353 case I2C_SMBUS_I2C_BLOCK_DATA:
354 memcpy(&data->block[1], dma_buffer, desc->rxbytes);
355 data->block[0] = desc->rxbytes;
356 break;
357 }
358 return 0;
359 }
360
361 if (likely(desc->status & ISMT_DESC_NAK))
362 return -ENXIO;
363
364 if (desc->status & ISMT_DESC_CRC)
365 return -EBADMSG;
366
367 if (desc->status & ISMT_DESC_COL)
368 return -EAGAIN;
369
370 if (desc->status & ISMT_DESC_LPR)
371 return -EPROTO;
372
373 if (desc->status & (ISMT_DESC_DLTO | ISMT_DESC_CLTO))
374 return -ETIMEDOUT;
375
376 return -EIO;
377 }
378
379 /**
380 * ismt_access() - process an SMBus command
381 * @adap: the i2c host adapter
382 * @addr: address of the i2c/SMBus target
383 * @flags: command options
384 * @read_write: read from or write to device
385 * @command: the i2c/SMBus command to issue
386 * @size: SMBus transaction type
387 * @data: read/write data buffer
388 */
ismt_access(struct i2c_adapter * adap,u16 addr,unsigned short flags,char read_write,u8 command,int size,union i2c_smbus_data * data)389 static int ismt_access(struct i2c_adapter *adap, u16 addr,
390 unsigned short flags, char read_write, u8 command,
391 int size, union i2c_smbus_data *data)
392 {
393 int ret;
394 unsigned long time_left;
395 dma_addr_t dma_addr = 0; /* address of the data buffer */
396 u8 dma_size = 0;
397 enum dma_data_direction dma_direction = 0;
398 struct ismt_desc *desc;
399 struct ismt_priv *priv = i2c_get_adapdata(adap);
400 struct device *dev = &priv->pci_dev->dev;
401 u8 *dma_buffer = PTR_ALIGN(&priv->buffer[0], 16);
402
403 desc = &priv->hw[priv->head];
404
405 /* Initialize the DMA buffer */
406 memset(priv->buffer, 0, sizeof(priv->buffer));
407
408 /* Initialize the descriptor */
409 memset(desc, 0, sizeof(struct ismt_desc));
410 desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(addr, read_write);
411
412 /* Initialize common control bits */
413 if (likely(pci_dev_msi_enabled(priv->pci_dev)))
414 desc->control = ISMT_DESC_INT | ISMT_DESC_FAIR;
415 else
416 desc->control = ISMT_DESC_FAIR;
417
418 if ((flags & I2C_CLIENT_PEC) && (size != I2C_SMBUS_QUICK)
419 && (size != I2C_SMBUS_I2C_BLOCK_DATA))
420 desc->control |= ISMT_DESC_PEC;
421
422 switch (size) {
423 case I2C_SMBUS_QUICK:
424 dev_dbg(dev, "I2C_SMBUS_QUICK\n");
425 break;
426
427 case I2C_SMBUS_BYTE:
428 if (read_write == I2C_SMBUS_WRITE) {
429 /*
430 * Send Byte
431 * The command field contains the write data
432 */
433 dev_dbg(dev, "I2C_SMBUS_BYTE: WRITE\n");
434 desc->control |= ISMT_DESC_CWRL;
435 desc->wr_len_cmd = command;
436 } else {
437 /* Receive Byte */
438 dev_dbg(dev, "I2C_SMBUS_BYTE: READ\n");
439 dma_size = 1;
440 dma_direction = DMA_FROM_DEVICE;
441 desc->rd_len = 1;
442 }
443 break;
444
445 case I2C_SMBUS_BYTE_DATA:
446 if (read_write == I2C_SMBUS_WRITE) {
447 /*
448 * Write Byte
449 * Command plus 1 data byte
450 */
451 dev_dbg(dev, "I2C_SMBUS_BYTE_DATA: WRITE\n");
452 desc->wr_len_cmd = 2;
453 dma_size = 2;
454 dma_direction = DMA_TO_DEVICE;
455 dma_buffer[0] = command;
456 dma_buffer[1] = data->byte;
457 } else {
458 /* Read Byte */
459 dev_dbg(dev, "I2C_SMBUS_BYTE_DATA: READ\n");
460 desc->control |= ISMT_DESC_CWRL;
461 desc->wr_len_cmd = command;
462 desc->rd_len = 1;
463 dma_size = 1;
464 dma_direction = DMA_FROM_DEVICE;
465 }
466 break;
467
468 case I2C_SMBUS_WORD_DATA:
469 if (read_write == I2C_SMBUS_WRITE) {
470 /* Write Word */
471 dev_dbg(dev, "I2C_SMBUS_WORD_DATA: WRITE\n");
472 desc->wr_len_cmd = 3;
473 dma_size = 3;
474 dma_direction = DMA_TO_DEVICE;
475 dma_buffer[0] = command;
476 dma_buffer[1] = data->word & 0xff;
477 dma_buffer[2] = data->word >> 8;
478 } else {
479 /* Read Word */
480 dev_dbg(dev, "I2C_SMBUS_WORD_DATA: READ\n");
481 desc->wr_len_cmd = command;
482 desc->control |= ISMT_DESC_CWRL;
483 desc->rd_len = 2;
484 dma_size = 2;
485 dma_direction = DMA_FROM_DEVICE;
486 }
487 break;
488
489 case I2C_SMBUS_PROC_CALL:
490 dev_dbg(dev, "I2C_SMBUS_PROC_CALL\n");
491 desc->wr_len_cmd = 3;
492 desc->rd_len = 2;
493 dma_size = 3;
494 dma_direction = DMA_BIDIRECTIONAL;
495 dma_buffer[0] = command;
496 dma_buffer[1] = data->word & 0xff;
497 dma_buffer[2] = data->word >> 8;
498 break;
499
500 case I2C_SMBUS_BLOCK_DATA:
501 if (read_write == I2C_SMBUS_WRITE) {
502 /* Block Write */
503 dev_dbg(dev, "I2C_SMBUS_BLOCK_DATA: WRITE\n");
504 if (data->block[0] < 1 || data->block[0] > I2C_SMBUS_BLOCK_MAX)
505 return -EINVAL;
506
507 dma_size = data->block[0] + 1;
508 dma_direction = DMA_TO_DEVICE;
509 desc->wr_len_cmd = dma_size;
510 desc->control |= ISMT_DESC_BLK;
511 dma_buffer[0] = command;
512 memcpy(&dma_buffer[1], &data->block[1], dma_size - 1);
513 } else {
514 /* Block Read */
515 dev_dbg(dev, "I2C_SMBUS_BLOCK_DATA: READ\n");
516 dma_size = I2C_SMBUS_BLOCK_MAX;
517 dma_direction = DMA_FROM_DEVICE;
518 desc->rd_len = dma_size;
519 desc->wr_len_cmd = command;
520 desc->control |= (ISMT_DESC_BLK | ISMT_DESC_CWRL);
521 }
522 break;
523
524 case I2C_SMBUS_I2C_BLOCK_DATA:
525 /* Make sure the length is valid */
526 if (data->block[0] < 1)
527 data->block[0] = 1;
528
529 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
530 data->block[0] = I2C_SMBUS_BLOCK_MAX;
531
532 if (read_write == I2C_SMBUS_WRITE) {
533 /* i2c Block Write */
534 dev_dbg(dev, "I2C_SMBUS_I2C_BLOCK_DATA: WRITE\n");
535 dma_size = data->block[0] + 1;
536 dma_direction = DMA_TO_DEVICE;
537 desc->wr_len_cmd = dma_size;
538 desc->control |= ISMT_DESC_I2C;
539 dma_buffer[0] = command;
540 memcpy(&dma_buffer[1], &data->block[1], dma_size - 1);
541 } else {
542 /* i2c Block Read */
543 dev_dbg(dev, "I2C_SMBUS_I2C_BLOCK_DATA: READ\n");
544 dma_size = data->block[0];
545 dma_direction = DMA_FROM_DEVICE;
546 desc->rd_len = dma_size;
547 desc->wr_len_cmd = command;
548 desc->control |= (ISMT_DESC_I2C | ISMT_DESC_CWRL);
549 /*
550 * Per the "Table 15-15. I2C Commands",
551 * in the External Design Specification (EDS),
552 * (Document Number: 508084, Revision: 2.0),
553 * the _rw bit must be 0
554 */
555 desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(addr, 0);
556 }
557 break;
558
559 default:
560 dev_err(dev, "Unsupported transaction %d\n",
561 size);
562 return -EOPNOTSUPP;
563 }
564
565 /* map the data buffer */
566 if (dma_size != 0) {
567 dev_dbg(dev, " dev=%p\n", dev);
568 dev_dbg(dev, " data=%p\n", data);
569 dev_dbg(dev, " dma_buffer=%p\n", dma_buffer);
570 dev_dbg(dev, " dma_size=%d\n", dma_size);
571 dev_dbg(dev, " dma_direction=%d\n", dma_direction);
572
573 dma_addr = dma_map_single(dev,
574 dma_buffer,
575 dma_size,
576 dma_direction);
577
578 if (dma_mapping_error(dev, dma_addr)) {
579 dev_err(dev, "Error in mapping dma buffer %p\n",
580 dma_buffer);
581 return -EIO;
582 }
583
584 dev_dbg(dev, " dma_addr = %pad\n", &dma_addr);
585
586 desc->dptr_low = lower_32_bits(dma_addr);
587 desc->dptr_high = upper_32_bits(dma_addr);
588 }
589
590 reinit_completion(&priv->cmp);
591
592 /* Add the descriptor */
593 ismt_submit_desc(priv);
594
595 /* Now we wait for interrupt completion, 1s */
596 time_left = wait_for_completion_timeout(&priv->cmp, HZ*1);
597
598 /* unmap the data buffer */
599 if (dma_size != 0)
600 dma_unmap_single(dev, dma_addr, dma_size, dma_direction);
601
602 if (unlikely(!time_left)) {
603 dev_err(dev, "completion wait timed out\n");
604 ret = -ETIMEDOUT;
605 goto out;
606 }
607
608 /* do any post processing of the descriptor here */
609 ret = ismt_process_desc(desc, data, priv, size, read_write);
610
611 out:
612 /* Update the ring pointer */
613 priv->head++;
614 priv->head %= ISMT_DESC_ENTRIES;
615
616 return ret;
617 }
618
619 /**
620 * ismt_func() - report which i2c commands are supported by this adapter
621 * @adap: the i2c host adapter
622 */
ismt_func(struct i2c_adapter * adap)623 static u32 ismt_func(struct i2c_adapter *adap)
624 {
625 return I2C_FUNC_SMBUS_QUICK |
626 I2C_FUNC_SMBUS_BYTE |
627 I2C_FUNC_SMBUS_BYTE_DATA |
628 I2C_FUNC_SMBUS_WORD_DATA |
629 I2C_FUNC_SMBUS_PROC_CALL |
630 I2C_FUNC_SMBUS_BLOCK_DATA |
631 I2C_FUNC_SMBUS_I2C_BLOCK |
632 I2C_FUNC_SMBUS_PEC;
633 }
634
635 static const struct i2c_algorithm smbus_algorithm = {
636 .smbus_xfer = ismt_access,
637 .functionality = ismt_func,
638 };
639
640 /**
641 * ismt_handle_isr() - interrupt handler bottom half
642 * @priv: iSMT private data
643 */
ismt_handle_isr(struct ismt_priv * priv)644 static irqreturn_t ismt_handle_isr(struct ismt_priv *priv)
645 {
646 complete(&priv->cmp);
647
648 return IRQ_HANDLED;
649 }
650
651
652 /**
653 * ismt_do_interrupt() - IRQ interrupt handler
654 * @vec: interrupt vector
655 * @data: iSMT private data
656 */
ismt_do_interrupt(int vec,void * data)657 static irqreturn_t ismt_do_interrupt(int vec, void *data)
658 {
659 u32 val;
660 struct ismt_priv *priv = data;
661
662 /*
663 * check to see it's our interrupt, return IRQ_NONE if not ours
664 * since we are sharing interrupt
665 */
666 val = readl(priv->smba + ISMT_MSTR_MSTS);
667
668 if (!(val & (ISMT_MSTS_MIS | ISMT_MSTS_MEIS)))
669 return IRQ_NONE;
670 else
671 writel(val | ISMT_MSTS_MIS | ISMT_MSTS_MEIS,
672 priv->smba + ISMT_MSTR_MSTS);
673
674 return ismt_handle_isr(priv);
675 }
676
677 /**
678 * ismt_do_msi_interrupt() - MSI interrupt handler
679 * @vec: interrupt vector
680 * @data: iSMT private data
681 */
ismt_do_msi_interrupt(int vec,void * data)682 static irqreturn_t ismt_do_msi_interrupt(int vec, void *data)
683 {
684 return ismt_handle_isr(data);
685 }
686
687 /**
688 * ismt_hw_init() - initialize the iSMT hardware
689 * @priv: iSMT private data
690 */
ismt_hw_init(struct ismt_priv * priv)691 static void ismt_hw_init(struct ismt_priv *priv)
692 {
693 u32 val;
694 struct device *dev = &priv->pci_dev->dev;
695
696 /* initialize the Master Descriptor Base Address (MDBA) */
697 writeq(priv->io_rng_dma, priv->smba + ISMT_MSTR_MDBA);
698
699 /* initialize the Master Control Register (MCTRL) */
700 writel(ISMT_MCTRL_MEIE, priv->smba + ISMT_MSTR_MCTRL);
701
702 /* initialize the Master Status Register (MSTS) */
703 writel(0, priv->smba + ISMT_MSTR_MSTS);
704
705 /* initialize the Master Descriptor Size (MDS) */
706 val = readl(priv->smba + ISMT_MSTR_MDS);
707 writel((val & ~ISMT_MDS_MASK) | (ISMT_DESC_ENTRIES - 1),
708 priv->smba + ISMT_MSTR_MDS);
709
710 /*
711 * Set the SMBus speed (could use this for slow HW debuggers)
712 */
713
714 val = readl(priv->smba + ISMT_SPGT);
715
716 switch (bus_speed) {
717 case 0:
718 break;
719
720 case 80:
721 dev_dbg(dev, "Setting SMBus clock to 80 kHz\n");
722 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_80K),
723 priv->smba + ISMT_SPGT);
724 break;
725
726 case 100:
727 dev_dbg(dev, "Setting SMBus clock to 100 kHz\n");
728 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_100K),
729 priv->smba + ISMT_SPGT);
730 break;
731
732 case 400:
733 dev_dbg(dev, "Setting SMBus clock to 400 kHz\n");
734 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_400K),
735 priv->smba + ISMT_SPGT);
736 break;
737
738 case 1000:
739 dev_dbg(dev, "Setting SMBus clock to 1000 kHz\n");
740 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_1M),
741 priv->smba + ISMT_SPGT);
742 break;
743
744 default:
745 dev_warn(dev, "Invalid SMBus clock speed, only 0, 80, 100, 400, and 1000 are valid\n");
746 break;
747 }
748
749 val = readl(priv->smba + ISMT_SPGT);
750
751 switch (val & ISMT_SPGT_SPD_MASK) {
752 case ISMT_SPGT_SPD_80K:
753 bus_speed = 80;
754 break;
755 case ISMT_SPGT_SPD_100K:
756 bus_speed = 100;
757 break;
758 case ISMT_SPGT_SPD_400K:
759 bus_speed = 400;
760 break;
761 case ISMT_SPGT_SPD_1M:
762 bus_speed = 1000;
763 break;
764 }
765 dev_dbg(dev, "SMBus clock is running at %d kHz\n", bus_speed);
766 }
767
768 /**
769 * ismt_dev_init() - initialize the iSMT data structures
770 * @priv: iSMT private data
771 */
ismt_dev_init(struct ismt_priv * priv)772 static int ismt_dev_init(struct ismt_priv *priv)
773 {
774 /* allocate memory for the descriptor */
775 priv->hw = dmam_alloc_coherent(&priv->pci_dev->dev,
776 (ISMT_DESC_ENTRIES
777 * sizeof(struct ismt_desc)),
778 &priv->io_rng_dma,
779 GFP_KERNEL);
780 if (!priv->hw)
781 return -ENOMEM;
782
783 priv->head = 0;
784 init_completion(&priv->cmp);
785
786 return 0;
787 }
788
789 /**
790 * ismt_int_init() - initialize interrupts
791 * @priv: iSMT private data
792 */
ismt_int_init(struct ismt_priv * priv)793 static int ismt_int_init(struct ismt_priv *priv)
794 {
795 int err;
796
797 /* Try using MSI interrupts */
798 err = pci_enable_msi(priv->pci_dev);
799 if (err)
800 goto intx;
801
802 err = devm_request_irq(&priv->pci_dev->dev,
803 priv->pci_dev->irq,
804 ismt_do_msi_interrupt,
805 0,
806 "ismt-msi",
807 priv);
808 if (err) {
809 pci_disable_msi(priv->pci_dev);
810 goto intx;
811 }
812
813 return 0;
814
815 /* Try using legacy interrupts */
816 intx:
817 dev_warn(&priv->pci_dev->dev,
818 "Unable to use MSI interrupts, falling back to legacy\n");
819
820 err = devm_request_irq(&priv->pci_dev->dev,
821 priv->pci_dev->irq,
822 ismt_do_interrupt,
823 IRQF_SHARED,
824 "ismt-intx",
825 priv);
826 if (err) {
827 dev_err(&priv->pci_dev->dev, "no usable interrupts\n");
828 return err;
829 }
830
831 return 0;
832 }
833
834 static struct pci_driver ismt_driver;
835
836 /**
837 * ismt_probe() - probe for iSMT devices
838 * @pdev: PCI-Express device
839 * @id: PCI-Express device ID
840 */
841 static int
ismt_probe(struct pci_dev * pdev,const struct pci_device_id * id)842 ismt_probe(struct pci_dev *pdev, const struct pci_device_id *id)
843 {
844 int err;
845 struct ismt_priv *priv;
846 unsigned long start, len;
847
848 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
849 if (!priv)
850 return -ENOMEM;
851
852 pci_set_drvdata(pdev, priv);
853
854 i2c_set_adapdata(&priv->adapter, priv);
855 priv->adapter.owner = THIS_MODULE;
856 priv->adapter.class = I2C_CLASS_HWMON;
857 priv->adapter.algo = &smbus_algorithm;
858 priv->adapter.dev.parent = &pdev->dev;
859 ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&pdev->dev));
860 priv->adapter.retries = ISMT_MAX_RETRIES;
861
862 priv->pci_dev = pdev;
863
864 err = pcim_enable_device(pdev);
865 if (err) {
866 dev_err(&pdev->dev, "Failed to enable SMBus PCI device (%d)\n",
867 err);
868 return err;
869 }
870
871 /* enable bus mastering */
872 pci_set_master(pdev);
873
874 /* Determine the address of the SMBus area */
875 start = pci_resource_start(pdev, SMBBAR);
876 len = pci_resource_len(pdev, SMBBAR);
877 if (!start || !len) {
878 dev_err(&pdev->dev,
879 "SMBus base address uninitialized, upgrade BIOS\n");
880 return -ENODEV;
881 }
882
883 snprintf(priv->adapter.name, sizeof(priv->adapter.name),
884 "SMBus iSMT adapter at %lx", start);
885
886 dev_dbg(&priv->pci_dev->dev, " start=0x%lX\n", start);
887 dev_dbg(&priv->pci_dev->dev, " len=0x%lX\n", len);
888
889 err = acpi_check_resource_conflict(&pdev->resource[SMBBAR]);
890 if (err) {
891 dev_err(&pdev->dev, "ACPI resource conflict!\n");
892 return err;
893 }
894
895 err = pci_request_region(pdev, SMBBAR, ismt_driver.name);
896 if (err) {
897 dev_err(&pdev->dev,
898 "Failed to request SMBus region 0x%lx-0x%lx\n",
899 start, start + len);
900 return err;
901 }
902
903 priv->smba = pcim_iomap(pdev, SMBBAR, len);
904 if (!priv->smba) {
905 dev_err(&pdev->dev, "Unable to ioremap SMBus BAR\n");
906 return -ENODEV;
907 }
908
909 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) ||
910 (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0)) {
911 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) ||
912 (pci_set_consistent_dma_mask(pdev,
913 DMA_BIT_MASK(32)) != 0)) {
914 dev_err(&pdev->dev, "pci_set_dma_mask fail %p\n",
915 pdev);
916 return -ENODEV;
917 }
918 }
919
920 err = ismt_dev_init(priv);
921 if (err)
922 return err;
923
924 ismt_hw_init(priv);
925
926 err = ismt_int_init(priv);
927 if (err)
928 return err;
929
930 err = i2c_add_adapter(&priv->adapter);
931 if (err)
932 return -ENODEV;
933 return 0;
934 }
935
936 /**
937 * ismt_remove() - release driver resources
938 * @pdev: PCI-Express device
939 */
ismt_remove(struct pci_dev * pdev)940 static void ismt_remove(struct pci_dev *pdev)
941 {
942 struct ismt_priv *priv = pci_get_drvdata(pdev);
943
944 i2c_del_adapter(&priv->adapter);
945 }
946
947 static struct pci_driver ismt_driver = {
948 .name = "ismt_smbus",
949 .id_table = ismt_ids,
950 .probe = ismt_probe,
951 .remove = ismt_remove,
952 };
953
954 module_pci_driver(ismt_driver);
955
956 MODULE_LICENSE("Dual BSD/GPL");
957 MODULE_AUTHOR("Bill E. Brown <bill.e.brown@intel.com>");
958 MODULE_DESCRIPTION("Intel SMBus Message Transport (iSMT) driver");
959