1 /*
2 * Broadcom NetXtreme-E RoCE driver.
3 *
4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term
5 * Broadcom refers to Broadcom Limited and/or its subsidiaries.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 *
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in
21 * the documentation and/or other materials provided with the
22 * distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 *
36 * Description: IB Verbs interpreter
37 */
38
39 #include <linux/interrupt.h>
40 #include <linux/types.h>
41 #include <linux/pci.h>
42 #include <linux/netdevice.h>
43 #include <linux/if_ether.h>
44
45 #include <rdma/ib_verbs.h>
46 #include <rdma/ib_user_verbs.h>
47 #include <rdma/ib_umem.h>
48 #include <rdma/ib_addr.h>
49 #include <rdma/ib_mad.h>
50 #include <rdma/ib_cache.h>
51 #include <rdma/uverbs_ioctl.h>
52
53 #include "bnxt_ulp.h"
54
55 #include "roce_hsi.h"
56 #include "qplib_res.h"
57 #include "qplib_sp.h"
58 #include "qplib_fp.h"
59 #include "qplib_rcfw.h"
60
61 #include "bnxt_re.h"
62 #include "ib_verbs.h"
63 #include <rdma/bnxt_re-abi.h>
64
__from_ib_access_flags(int iflags)65 static int __from_ib_access_flags(int iflags)
66 {
67 int qflags = 0;
68
69 if (iflags & IB_ACCESS_LOCAL_WRITE)
70 qflags |= BNXT_QPLIB_ACCESS_LOCAL_WRITE;
71 if (iflags & IB_ACCESS_REMOTE_READ)
72 qflags |= BNXT_QPLIB_ACCESS_REMOTE_READ;
73 if (iflags & IB_ACCESS_REMOTE_WRITE)
74 qflags |= BNXT_QPLIB_ACCESS_REMOTE_WRITE;
75 if (iflags & IB_ACCESS_REMOTE_ATOMIC)
76 qflags |= BNXT_QPLIB_ACCESS_REMOTE_ATOMIC;
77 if (iflags & IB_ACCESS_MW_BIND)
78 qflags |= BNXT_QPLIB_ACCESS_MW_BIND;
79 if (iflags & IB_ZERO_BASED)
80 qflags |= BNXT_QPLIB_ACCESS_ZERO_BASED;
81 if (iflags & IB_ACCESS_ON_DEMAND)
82 qflags |= BNXT_QPLIB_ACCESS_ON_DEMAND;
83 return qflags;
84 };
85
__to_ib_access_flags(int qflags)86 static enum ib_access_flags __to_ib_access_flags(int qflags)
87 {
88 enum ib_access_flags iflags = 0;
89
90 if (qflags & BNXT_QPLIB_ACCESS_LOCAL_WRITE)
91 iflags |= IB_ACCESS_LOCAL_WRITE;
92 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_WRITE)
93 iflags |= IB_ACCESS_REMOTE_WRITE;
94 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_READ)
95 iflags |= IB_ACCESS_REMOTE_READ;
96 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_ATOMIC)
97 iflags |= IB_ACCESS_REMOTE_ATOMIC;
98 if (qflags & BNXT_QPLIB_ACCESS_MW_BIND)
99 iflags |= IB_ACCESS_MW_BIND;
100 if (qflags & BNXT_QPLIB_ACCESS_ZERO_BASED)
101 iflags |= IB_ZERO_BASED;
102 if (qflags & BNXT_QPLIB_ACCESS_ON_DEMAND)
103 iflags |= IB_ACCESS_ON_DEMAND;
104 return iflags;
105 };
106
bnxt_re_build_sgl(struct ib_sge * ib_sg_list,struct bnxt_qplib_sge * sg_list,int num)107 static int bnxt_re_build_sgl(struct ib_sge *ib_sg_list,
108 struct bnxt_qplib_sge *sg_list, int num)
109 {
110 int i, total = 0;
111
112 for (i = 0; i < num; i++) {
113 sg_list[i].addr = ib_sg_list[i].addr;
114 sg_list[i].lkey = ib_sg_list[i].lkey;
115 sg_list[i].size = ib_sg_list[i].length;
116 total += sg_list[i].size;
117 }
118 return total;
119 }
120
121 /* Device */
bnxt_re_query_device(struct ib_device * ibdev,struct ib_device_attr * ib_attr,struct ib_udata * udata)122 int bnxt_re_query_device(struct ib_device *ibdev,
123 struct ib_device_attr *ib_attr,
124 struct ib_udata *udata)
125 {
126 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
127 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
128
129 memset(ib_attr, 0, sizeof(*ib_attr));
130 memcpy(&ib_attr->fw_ver, dev_attr->fw_ver,
131 min(sizeof(dev_attr->fw_ver),
132 sizeof(ib_attr->fw_ver)));
133 bnxt_qplib_get_guid(rdev->netdev->dev_addr,
134 (u8 *)&ib_attr->sys_image_guid);
135 ib_attr->max_mr_size = BNXT_RE_MAX_MR_SIZE;
136 ib_attr->page_size_cap = BNXT_RE_PAGE_SIZE_4K | BNXT_RE_PAGE_SIZE_2M;
137
138 ib_attr->vendor_id = rdev->en_dev->pdev->vendor;
139 ib_attr->vendor_part_id = rdev->en_dev->pdev->device;
140 ib_attr->hw_ver = rdev->en_dev->pdev->subsystem_device;
141 ib_attr->max_qp = dev_attr->max_qp;
142 ib_attr->max_qp_wr = dev_attr->max_qp_wqes;
143 ib_attr->device_cap_flags =
144 IB_DEVICE_CURR_QP_STATE_MOD
145 | IB_DEVICE_RC_RNR_NAK_GEN
146 | IB_DEVICE_SHUTDOWN_PORT
147 | IB_DEVICE_SYS_IMAGE_GUID
148 | IB_DEVICE_LOCAL_DMA_LKEY
149 | IB_DEVICE_RESIZE_MAX_WR
150 | IB_DEVICE_PORT_ACTIVE_EVENT
151 | IB_DEVICE_N_NOTIFY_CQ
152 | IB_DEVICE_MEM_WINDOW
153 | IB_DEVICE_MEM_WINDOW_TYPE_2B
154 | IB_DEVICE_MEM_MGT_EXTENSIONS;
155 ib_attr->max_send_sge = dev_attr->max_qp_sges;
156 ib_attr->max_recv_sge = dev_attr->max_qp_sges;
157 ib_attr->max_sge_rd = dev_attr->max_qp_sges;
158 ib_attr->max_cq = dev_attr->max_cq;
159 ib_attr->max_cqe = dev_attr->max_cq_wqes;
160 ib_attr->max_mr = dev_attr->max_mr;
161 ib_attr->max_pd = dev_attr->max_pd;
162 ib_attr->max_qp_rd_atom = dev_attr->max_qp_rd_atom;
163 ib_attr->max_qp_init_rd_atom = dev_attr->max_qp_init_rd_atom;
164 ib_attr->atomic_cap = IB_ATOMIC_NONE;
165 ib_attr->masked_atomic_cap = IB_ATOMIC_NONE;
166
167 ib_attr->max_ee_rd_atom = 0;
168 ib_attr->max_res_rd_atom = 0;
169 ib_attr->max_ee_init_rd_atom = 0;
170 ib_attr->max_ee = 0;
171 ib_attr->max_rdd = 0;
172 ib_attr->max_mw = dev_attr->max_mw;
173 ib_attr->max_raw_ipv6_qp = 0;
174 ib_attr->max_raw_ethy_qp = dev_attr->max_raw_ethy_qp;
175 ib_attr->max_mcast_grp = 0;
176 ib_attr->max_mcast_qp_attach = 0;
177 ib_attr->max_total_mcast_qp_attach = 0;
178 ib_attr->max_ah = dev_attr->max_ah;
179
180 ib_attr->max_srq = dev_attr->max_srq;
181 ib_attr->max_srq_wr = dev_attr->max_srq_wqes;
182 ib_attr->max_srq_sge = dev_attr->max_srq_sges;
183
184 ib_attr->max_fast_reg_page_list_len = MAX_PBL_LVL_1_PGS;
185
186 ib_attr->max_pkeys = 1;
187 ib_attr->local_ca_ack_delay = BNXT_RE_DEFAULT_ACK_DELAY;
188 return 0;
189 }
190
191 /* Port */
bnxt_re_query_port(struct ib_device * ibdev,u8 port_num,struct ib_port_attr * port_attr)192 int bnxt_re_query_port(struct ib_device *ibdev, u8 port_num,
193 struct ib_port_attr *port_attr)
194 {
195 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
196 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
197
198 memset(port_attr, 0, sizeof(*port_attr));
199
200 if (netif_running(rdev->netdev) && netif_carrier_ok(rdev->netdev)) {
201 port_attr->state = IB_PORT_ACTIVE;
202 port_attr->phys_state = IB_PORT_PHYS_STATE_LINK_UP;
203 } else {
204 port_attr->state = IB_PORT_DOWN;
205 port_attr->phys_state = IB_PORT_PHYS_STATE_DISABLED;
206 }
207 port_attr->max_mtu = IB_MTU_4096;
208 port_attr->active_mtu = iboe_get_mtu(rdev->netdev->mtu);
209 port_attr->gid_tbl_len = dev_attr->max_sgid;
210 port_attr->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP |
211 IB_PORT_DEVICE_MGMT_SUP |
212 IB_PORT_VENDOR_CLASS_SUP;
213 port_attr->ip_gids = true;
214
215 port_attr->max_msg_sz = (u32)BNXT_RE_MAX_MR_SIZE_LOW;
216 port_attr->bad_pkey_cntr = 0;
217 port_attr->qkey_viol_cntr = 0;
218 port_attr->pkey_tbl_len = dev_attr->max_pkey;
219 port_attr->lid = 0;
220 port_attr->sm_lid = 0;
221 port_attr->lmc = 0;
222 port_attr->max_vl_num = 4;
223 port_attr->sm_sl = 0;
224 port_attr->subnet_timeout = 0;
225 port_attr->init_type_reply = 0;
226 port_attr->active_speed = rdev->active_speed;
227 port_attr->active_width = rdev->active_width;
228
229 return 0;
230 }
231
bnxt_re_get_port_immutable(struct ib_device * ibdev,u8 port_num,struct ib_port_immutable * immutable)232 int bnxt_re_get_port_immutable(struct ib_device *ibdev, u8 port_num,
233 struct ib_port_immutable *immutable)
234 {
235 struct ib_port_attr port_attr;
236
237 if (bnxt_re_query_port(ibdev, port_num, &port_attr))
238 return -EINVAL;
239
240 immutable->pkey_tbl_len = port_attr.pkey_tbl_len;
241 immutable->gid_tbl_len = port_attr.gid_tbl_len;
242 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
243 immutable->core_cap_flags |= RDMA_CORE_CAP_PROT_ROCE_UDP_ENCAP;
244 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
245 return 0;
246 }
247
bnxt_re_query_fw_str(struct ib_device * ibdev,char * str)248 void bnxt_re_query_fw_str(struct ib_device *ibdev, char *str)
249 {
250 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
251
252 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%d.%d",
253 rdev->dev_attr.fw_ver[0], rdev->dev_attr.fw_ver[1],
254 rdev->dev_attr.fw_ver[2], rdev->dev_attr.fw_ver[3]);
255 }
256
bnxt_re_query_pkey(struct ib_device * ibdev,u8 port_num,u16 index,u16 * pkey)257 int bnxt_re_query_pkey(struct ib_device *ibdev, u8 port_num,
258 u16 index, u16 *pkey)
259 {
260 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
261
262 /* Ignore port_num */
263
264 memset(pkey, 0, sizeof(*pkey));
265 return bnxt_qplib_get_pkey(&rdev->qplib_res,
266 &rdev->qplib_res.pkey_tbl, index, pkey);
267 }
268
bnxt_re_query_gid(struct ib_device * ibdev,u8 port_num,int index,union ib_gid * gid)269 int bnxt_re_query_gid(struct ib_device *ibdev, u8 port_num,
270 int index, union ib_gid *gid)
271 {
272 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
273 int rc = 0;
274
275 /* Ignore port_num */
276 memset(gid, 0, sizeof(*gid));
277 rc = bnxt_qplib_get_sgid(&rdev->qplib_res,
278 &rdev->qplib_res.sgid_tbl, index,
279 (struct bnxt_qplib_gid *)gid);
280 return rc;
281 }
282
bnxt_re_del_gid(const struct ib_gid_attr * attr,void ** context)283 int bnxt_re_del_gid(const struct ib_gid_attr *attr, void **context)
284 {
285 int rc = 0;
286 struct bnxt_re_gid_ctx *ctx, **ctx_tbl;
287 struct bnxt_re_dev *rdev = to_bnxt_re_dev(attr->device, ibdev);
288 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl;
289 struct bnxt_qplib_gid *gid_to_del;
290 u16 vlan_id = 0xFFFF;
291
292 /* Delete the entry from the hardware */
293 ctx = *context;
294 if (!ctx)
295 return -EINVAL;
296
297 if (sgid_tbl && sgid_tbl->active) {
298 if (ctx->idx >= sgid_tbl->max)
299 return -EINVAL;
300 gid_to_del = &sgid_tbl->tbl[ctx->idx].gid;
301 vlan_id = sgid_tbl->tbl[ctx->idx].vlan_id;
302 /* DEL_GID is called in WQ context(netdevice_event_work_handler)
303 * or via the ib_unregister_device path. In the former case QP1
304 * may not be destroyed yet, in which case just return as FW
305 * needs that entry to be present and will fail it's deletion.
306 * We could get invoked again after QP1 is destroyed OR get an
307 * ADD_GID call with a different GID value for the same index
308 * where we issue MODIFY_GID cmd to update the GID entry -- TBD
309 */
310 if (ctx->idx == 0 &&
311 rdma_link_local_addr((struct in6_addr *)gid_to_del) &&
312 ctx->refcnt == 1 && rdev->gsi_ctx.gsi_sqp) {
313 ibdev_dbg(&rdev->ibdev,
314 "Trying to delete GID0 while QP1 is alive\n");
315 return -EFAULT;
316 }
317 ctx->refcnt--;
318 if (!ctx->refcnt) {
319 rc = bnxt_qplib_del_sgid(sgid_tbl, gid_to_del,
320 vlan_id, true);
321 if (rc) {
322 ibdev_err(&rdev->ibdev,
323 "Failed to remove GID: %#x", rc);
324 } else {
325 ctx_tbl = sgid_tbl->ctx;
326 ctx_tbl[ctx->idx] = NULL;
327 kfree(ctx);
328 }
329 }
330 } else {
331 return -EINVAL;
332 }
333 return rc;
334 }
335
bnxt_re_add_gid(const struct ib_gid_attr * attr,void ** context)336 int bnxt_re_add_gid(const struct ib_gid_attr *attr, void **context)
337 {
338 int rc;
339 u32 tbl_idx = 0;
340 u16 vlan_id = 0xFFFF;
341 struct bnxt_re_gid_ctx *ctx, **ctx_tbl;
342 struct bnxt_re_dev *rdev = to_bnxt_re_dev(attr->device, ibdev);
343 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl;
344
345 rc = rdma_read_gid_l2_fields(attr, &vlan_id, NULL);
346 if (rc)
347 return rc;
348
349 rc = bnxt_qplib_add_sgid(sgid_tbl, (struct bnxt_qplib_gid *)&attr->gid,
350 rdev->qplib_res.netdev->dev_addr,
351 vlan_id, true, &tbl_idx);
352 if (rc == -EALREADY) {
353 ctx_tbl = sgid_tbl->ctx;
354 ctx_tbl[tbl_idx]->refcnt++;
355 *context = ctx_tbl[tbl_idx];
356 return 0;
357 }
358
359 if (rc < 0) {
360 ibdev_err(&rdev->ibdev, "Failed to add GID: %#x", rc);
361 return rc;
362 }
363
364 ctx = kmalloc(sizeof(*ctx), GFP_KERNEL);
365 if (!ctx)
366 return -ENOMEM;
367 ctx_tbl = sgid_tbl->ctx;
368 ctx->idx = tbl_idx;
369 ctx->refcnt = 1;
370 ctx_tbl[tbl_idx] = ctx;
371 *context = ctx;
372
373 return rc;
374 }
375
bnxt_re_get_link_layer(struct ib_device * ibdev,u8 port_num)376 enum rdma_link_layer bnxt_re_get_link_layer(struct ib_device *ibdev,
377 u8 port_num)
378 {
379 return IB_LINK_LAYER_ETHERNET;
380 }
381
382 #define BNXT_RE_FENCE_PBL_SIZE DIV_ROUND_UP(BNXT_RE_FENCE_BYTES, PAGE_SIZE)
383
bnxt_re_create_fence_wqe(struct bnxt_re_pd * pd)384 static void bnxt_re_create_fence_wqe(struct bnxt_re_pd *pd)
385 {
386 struct bnxt_re_fence_data *fence = &pd->fence;
387 struct ib_mr *ib_mr = &fence->mr->ib_mr;
388 struct bnxt_qplib_swqe *wqe = &fence->bind_wqe;
389
390 memset(wqe, 0, sizeof(*wqe));
391 wqe->type = BNXT_QPLIB_SWQE_TYPE_BIND_MW;
392 wqe->wr_id = BNXT_QPLIB_FENCE_WRID;
393 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
394 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
395 wqe->bind.zero_based = false;
396 wqe->bind.parent_l_key = ib_mr->lkey;
397 wqe->bind.va = (u64)(unsigned long)fence->va;
398 wqe->bind.length = fence->size;
399 wqe->bind.access_cntl = __from_ib_access_flags(IB_ACCESS_REMOTE_READ);
400 wqe->bind.mw_type = SQ_BIND_MW_TYPE_TYPE1;
401
402 /* Save the initial rkey in fence structure for now;
403 * wqe->bind.r_key will be set at (re)bind time.
404 */
405 fence->bind_rkey = ib_inc_rkey(fence->mw->rkey);
406 }
407
bnxt_re_bind_fence_mw(struct bnxt_qplib_qp * qplib_qp)408 static int bnxt_re_bind_fence_mw(struct bnxt_qplib_qp *qplib_qp)
409 {
410 struct bnxt_re_qp *qp = container_of(qplib_qp, struct bnxt_re_qp,
411 qplib_qp);
412 struct ib_pd *ib_pd = qp->ib_qp.pd;
413 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
414 struct bnxt_re_fence_data *fence = &pd->fence;
415 struct bnxt_qplib_swqe *fence_wqe = &fence->bind_wqe;
416 struct bnxt_qplib_swqe wqe;
417 int rc;
418
419 memcpy(&wqe, fence_wqe, sizeof(wqe));
420 wqe.bind.r_key = fence->bind_rkey;
421 fence->bind_rkey = ib_inc_rkey(fence->bind_rkey);
422
423 ibdev_dbg(&qp->rdev->ibdev,
424 "Posting bind fence-WQE: rkey: %#x QP: %d PD: %p\n",
425 wqe.bind.r_key, qp->qplib_qp.id, pd);
426 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe);
427 if (rc) {
428 ibdev_err(&qp->rdev->ibdev, "Failed to bind fence-WQE\n");
429 return rc;
430 }
431 bnxt_qplib_post_send_db(&qp->qplib_qp);
432
433 return rc;
434 }
435
bnxt_re_destroy_fence_mr(struct bnxt_re_pd * pd)436 static void bnxt_re_destroy_fence_mr(struct bnxt_re_pd *pd)
437 {
438 struct bnxt_re_fence_data *fence = &pd->fence;
439 struct bnxt_re_dev *rdev = pd->rdev;
440 struct device *dev = &rdev->en_dev->pdev->dev;
441 struct bnxt_re_mr *mr = fence->mr;
442
443 if (fence->mw) {
444 bnxt_re_dealloc_mw(fence->mw);
445 fence->mw = NULL;
446 }
447 if (mr) {
448 if (mr->ib_mr.rkey)
449 bnxt_qplib_dereg_mrw(&rdev->qplib_res, &mr->qplib_mr,
450 true);
451 if (mr->ib_mr.lkey)
452 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
453 kfree(mr);
454 fence->mr = NULL;
455 }
456 if (fence->dma_addr) {
457 dma_unmap_single(dev, fence->dma_addr, BNXT_RE_FENCE_BYTES,
458 DMA_BIDIRECTIONAL);
459 fence->dma_addr = 0;
460 }
461 }
462
bnxt_re_create_fence_mr(struct bnxt_re_pd * pd)463 static int bnxt_re_create_fence_mr(struct bnxt_re_pd *pd)
464 {
465 int mr_access_flags = IB_ACCESS_LOCAL_WRITE | IB_ACCESS_MW_BIND;
466 struct bnxt_re_fence_data *fence = &pd->fence;
467 struct bnxt_re_dev *rdev = pd->rdev;
468 struct device *dev = &rdev->en_dev->pdev->dev;
469 struct bnxt_re_mr *mr = NULL;
470 dma_addr_t dma_addr = 0;
471 struct ib_mw *mw;
472 u64 pbl_tbl;
473 int rc;
474
475 dma_addr = dma_map_single(dev, fence->va, BNXT_RE_FENCE_BYTES,
476 DMA_BIDIRECTIONAL);
477 rc = dma_mapping_error(dev, dma_addr);
478 if (rc) {
479 ibdev_err(&rdev->ibdev, "Failed to dma-map fence-MR-mem\n");
480 rc = -EIO;
481 fence->dma_addr = 0;
482 goto fail;
483 }
484 fence->dma_addr = dma_addr;
485
486 /* Allocate a MR */
487 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
488 if (!mr) {
489 rc = -ENOMEM;
490 goto fail;
491 }
492 fence->mr = mr;
493 mr->rdev = rdev;
494 mr->qplib_mr.pd = &pd->qplib_pd;
495 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR;
496 mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags);
497 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
498 if (rc) {
499 ibdev_err(&rdev->ibdev, "Failed to alloc fence-HW-MR\n");
500 goto fail;
501 }
502
503 /* Register MR */
504 mr->ib_mr.lkey = mr->qplib_mr.lkey;
505 mr->qplib_mr.va = (u64)(unsigned long)fence->va;
506 mr->qplib_mr.total_size = BNXT_RE_FENCE_BYTES;
507 pbl_tbl = dma_addr;
508 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, &pbl_tbl,
509 BNXT_RE_FENCE_PBL_SIZE, false, PAGE_SIZE);
510 if (rc) {
511 ibdev_err(&rdev->ibdev, "Failed to register fence-MR\n");
512 goto fail;
513 }
514 mr->ib_mr.rkey = mr->qplib_mr.rkey;
515
516 /* Create a fence MW only for kernel consumers */
517 mw = bnxt_re_alloc_mw(&pd->ib_pd, IB_MW_TYPE_1, NULL);
518 if (IS_ERR(mw)) {
519 ibdev_err(&rdev->ibdev,
520 "Failed to create fence-MW for PD: %p\n", pd);
521 rc = PTR_ERR(mw);
522 goto fail;
523 }
524 fence->mw = mw;
525
526 bnxt_re_create_fence_wqe(pd);
527 return 0;
528
529 fail:
530 bnxt_re_destroy_fence_mr(pd);
531 return rc;
532 }
533
534 /* Protection Domains */
bnxt_re_dealloc_pd(struct ib_pd * ib_pd,struct ib_udata * udata)535 int bnxt_re_dealloc_pd(struct ib_pd *ib_pd, struct ib_udata *udata)
536 {
537 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
538 struct bnxt_re_dev *rdev = pd->rdev;
539
540 bnxt_re_destroy_fence_mr(pd);
541
542 if (pd->qplib_pd.id)
543 bnxt_qplib_dealloc_pd(&rdev->qplib_res, &rdev->qplib_res.pd_tbl,
544 &pd->qplib_pd);
545 return 0;
546 }
547
bnxt_re_alloc_pd(struct ib_pd * ibpd,struct ib_udata * udata)548 int bnxt_re_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata)
549 {
550 struct ib_device *ibdev = ibpd->device;
551 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
552 struct bnxt_re_ucontext *ucntx = rdma_udata_to_drv_context(
553 udata, struct bnxt_re_ucontext, ib_uctx);
554 struct bnxt_re_pd *pd = container_of(ibpd, struct bnxt_re_pd, ib_pd);
555 int rc;
556
557 pd->rdev = rdev;
558 if (bnxt_qplib_alloc_pd(&rdev->qplib_res.pd_tbl, &pd->qplib_pd)) {
559 ibdev_err(&rdev->ibdev, "Failed to allocate HW PD");
560 rc = -ENOMEM;
561 goto fail;
562 }
563
564 if (udata) {
565 struct bnxt_re_pd_resp resp;
566
567 if (!ucntx->dpi.dbr) {
568 /* Allocate DPI in alloc_pd to avoid failing of
569 * ibv_devinfo and family of application when DPIs
570 * are depleted.
571 */
572 if (bnxt_qplib_alloc_dpi(&rdev->qplib_res.dpi_tbl,
573 &ucntx->dpi, ucntx)) {
574 rc = -ENOMEM;
575 goto dbfail;
576 }
577 }
578
579 resp.pdid = pd->qplib_pd.id;
580 /* Still allow mapping this DBR to the new user PD. */
581 resp.dpi = ucntx->dpi.dpi;
582 resp.dbr = (u64)ucntx->dpi.umdbr;
583
584 rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
585 if (rc) {
586 ibdev_err(&rdev->ibdev,
587 "Failed to copy user response\n");
588 goto dbfail;
589 }
590 }
591
592 if (!udata)
593 if (bnxt_re_create_fence_mr(pd))
594 ibdev_warn(&rdev->ibdev,
595 "Failed to create Fence-MR\n");
596 return 0;
597 dbfail:
598 bnxt_qplib_dealloc_pd(&rdev->qplib_res, &rdev->qplib_res.pd_tbl,
599 &pd->qplib_pd);
600 fail:
601 return rc;
602 }
603
604 /* Address Handles */
bnxt_re_destroy_ah(struct ib_ah * ib_ah,u32 flags)605 int bnxt_re_destroy_ah(struct ib_ah *ib_ah, u32 flags)
606 {
607 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah);
608 struct bnxt_re_dev *rdev = ah->rdev;
609
610 bnxt_qplib_destroy_ah(&rdev->qplib_res, &ah->qplib_ah,
611 !(flags & RDMA_DESTROY_AH_SLEEPABLE));
612 return 0;
613 }
614
bnxt_re_stack_to_dev_nw_type(enum rdma_network_type ntype)615 static u8 bnxt_re_stack_to_dev_nw_type(enum rdma_network_type ntype)
616 {
617 u8 nw_type;
618
619 switch (ntype) {
620 case RDMA_NETWORK_IPV4:
621 nw_type = CMDQ_CREATE_AH_TYPE_V2IPV4;
622 break;
623 case RDMA_NETWORK_IPV6:
624 nw_type = CMDQ_CREATE_AH_TYPE_V2IPV6;
625 break;
626 default:
627 nw_type = CMDQ_CREATE_AH_TYPE_V1;
628 break;
629 }
630 return nw_type;
631 }
632
bnxt_re_create_ah(struct ib_ah * ib_ah,struct rdma_ah_init_attr * init_attr,struct ib_udata * udata)633 int bnxt_re_create_ah(struct ib_ah *ib_ah, struct rdma_ah_init_attr *init_attr,
634 struct ib_udata *udata)
635 {
636 struct ib_pd *ib_pd = ib_ah->pd;
637 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
638 struct rdma_ah_attr *ah_attr = init_attr->ah_attr;
639 const struct ib_global_route *grh = rdma_ah_read_grh(ah_attr);
640 struct bnxt_re_dev *rdev = pd->rdev;
641 const struct ib_gid_attr *sgid_attr;
642 struct bnxt_re_gid_ctx *ctx;
643 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah);
644 u8 nw_type;
645 int rc;
646
647 if (!(rdma_ah_get_ah_flags(ah_attr) & IB_AH_GRH)) {
648 ibdev_err(&rdev->ibdev, "Failed to alloc AH: GRH not set");
649 return -EINVAL;
650 }
651
652 ah->rdev = rdev;
653 ah->qplib_ah.pd = &pd->qplib_pd;
654
655 /* Supply the configuration for the HW */
656 memcpy(ah->qplib_ah.dgid.data, grh->dgid.raw,
657 sizeof(union ib_gid));
658 sgid_attr = grh->sgid_attr;
659 /* Get the HW context of the GID. The reference
660 * of GID table entry is already taken by the caller.
661 */
662 ctx = rdma_read_gid_hw_context(sgid_attr);
663 ah->qplib_ah.sgid_index = ctx->idx;
664 ah->qplib_ah.host_sgid_index = grh->sgid_index;
665 ah->qplib_ah.traffic_class = grh->traffic_class;
666 ah->qplib_ah.flow_label = grh->flow_label;
667 ah->qplib_ah.hop_limit = grh->hop_limit;
668 ah->qplib_ah.sl = rdma_ah_get_sl(ah_attr);
669
670 /* Get network header type for this GID */
671 nw_type = rdma_gid_attr_network_type(sgid_attr);
672 ah->qplib_ah.nw_type = bnxt_re_stack_to_dev_nw_type(nw_type);
673
674 memcpy(ah->qplib_ah.dmac, ah_attr->roce.dmac, ETH_ALEN);
675 rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah,
676 !(init_attr->flags &
677 RDMA_CREATE_AH_SLEEPABLE));
678 if (rc) {
679 ibdev_err(&rdev->ibdev, "Failed to allocate HW AH");
680 return rc;
681 }
682
683 /* Write AVID to shared page. */
684 if (udata) {
685 struct bnxt_re_ucontext *uctx = rdma_udata_to_drv_context(
686 udata, struct bnxt_re_ucontext, ib_uctx);
687 unsigned long flag;
688 u32 *wrptr;
689
690 spin_lock_irqsave(&uctx->sh_lock, flag);
691 wrptr = (u32 *)(uctx->shpg + BNXT_RE_AVID_OFFT);
692 *wrptr = ah->qplib_ah.id;
693 wmb(); /* make sure cache is updated. */
694 spin_unlock_irqrestore(&uctx->sh_lock, flag);
695 }
696
697 return 0;
698 }
699
bnxt_re_modify_ah(struct ib_ah * ib_ah,struct rdma_ah_attr * ah_attr)700 int bnxt_re_modify_ah(struct ib_ah *ib_ah, struct rdma_ah_attr *ah_attr)
701 {
702 return 0;
703 }
704
bnxt_re_query_ah(struct ib_ah * ib_ah,struct rdma_ah_attr * ah_attr)705 int bnxt_re_query_ah(struct ib_ah *ib_ah, struct rdma_ah_attr *ah_attr)
706 {
707 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah);
708
709 ah_attr->type = ib_ah->type;
710 rdma_ah_set_sl(ah_attr, ah->qplib_ah.sl);
711 memcpy(ah_attr->roce.dmac, ah->qplib_ah.dmac, ETH_ALEN);
712 rdma_ah_set_grh(ah_attr, NULL, 0,
713 ah->qplib_ah.host_sgid_index,
714 0, ah->qplib_ah.traffic_class);
715 rdma_ah_set_dgid_raw(ah_attr, ah->qplib_ah.dgid.data);
716 rdma_ah_set_port_num(ah_attr, 1);
717 rdma_ah_set_static_rate(ah_attr, 0);
718 return 0;
719 }
720
bnxt_re_lock_cqs(struct bnxt_re_qp * qp)721 unsigned long bnxt_re_lock_cqs(struct bnxt_re_qp *qp)
722 __acquires(&qp->scq->cq_lock) __acquires(&qp->rcq->cq_lock)
723 {
724 unsigned long flags;
725
726 spin_lock_irqsave(&qp->scq->cq_lock, flags);
727 if (qp->rcq != qp->scq)
728 spin_lock(&qp->rcq->cq_lock);
729 else
730 __acquire(&qp->rcq->cq_lock);
731
732 return flags;
733 }
734
bnxt_re_unlock_cqs(struct bnxt_re_qp * qp,unsigned long flags)735 void bnxt_re_unlock_cqs(struct bnxt_re_qp *qp,
736 unsigned long flags)
737 __releases(&qp->scq->cq_lock) __releases(&qp->rcq->cq_lock)
738 {
739 if (qp->rcq != qp->scq)
740 spin_unlock(&qp->rcq->cq_lock);
741 else
742 __release(&qp->rcq->cq_lock);
743 spin_unlock_irqrestore(&qp->scq->cq_lock, flags);
744 }
745
bnxt_re_destroy_gsi_sqp(struct bnxt_re_qp * qp)746 static int bnxt_re_destroy_gsi_sqp(struct bnxt_re_qp *qp)
747 {
748 struct bnxt_re_qp *gsi_sqp;
749 struct bnxt_re_ah *gsi_sah;
750 struct bnxt_re_dev *rdev;
751 int rc = 0;
752
753 rdev = qp->rdev;
754 gsi_sqp = rdev->gsi_ctx.gsi_sqp;
755 gsi_sah = rdev->gsi_ctx.gsi_sah;
756
757 ibdev_dbg(&rdev->ibdev, "Destroy the shadow AH\n");
758 bnxt_qplib_destroy_ah(&rdev->qplib_res,
759 &gsi_sah->qplib_ah,
760 true);
761 bnxt_qplib_clean_qp(&qp->qplib_qp);
762
763 ibdev_dbg(&rdev->ibdev, "Destroy the shadow QP\n");
764 rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, &gsi_sqp->qplib_qp);
765 if (rc) {
766 ibdev_err(&rdev->ibdev, "Destroy Shadow QP failed");
767 goto fail;
768 }
769 bnxt_qplib_free_qp_res(&rdev->qplib_res, &gsi_sqp->qplib_qp);
770
771 /* remove from active qp list */
772 mutex_lock(&rdev->qp_lock);
773 list_del(&gsi_sqp->list);
774 mutex_unlock(&rdev->qp_lock);
775 atomic_dec(&rdev->qp_count);
776
777 kfree(rdev->gsi_ctx.sqp_tbl);
778 kfree(gsi_sah);
779 kfree(gsi_sqp);
780 rdev->gsi_ctx.gsi_sqp = NULL;
781 rdev->gsi_ctx.gsi_sah = NULL;
782 rdev->gsi_ctx.sqp_tbl = NULL;
783
784 return 0;
785 fail:
786 return rc;
787 }
788
789 /* Queue Pairs */
bnxt_re_destroy_qp(struct ib_qp * ib_qp,struct ib_udata * udata)790 int bnxt_re_destroy_qp(struct ib_qp *ib_qp, struct ib_udata *udata)
791 {
792 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
793 struct bnxt_re_dev *rdev = qp->rdev;
794 unsigned int flags;
795 int rc;
796
797 bnxt_qplib_flush_cqn_wq(&qp->qplib_qp);
798
799 rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp);
800 if (rc) {
801 ibdev_err(&rdev->ibdev, "Failed to destroy HW QP");
802 return rc;
803 }
804
805 if (rdma_is_kernel_res(&qp->ib_qp.res)) {
806 flags = bnxt_re_lock_cqs(qp);
807 bnxt_qplib_clean_qp(&qp->qplib_qp);
808 bnxt_re_unlock_cqs(qp, flags);
809 }
810
811 bnxt_qplib_free_qp_res(&rdev->qplib_res, &qp->qplib_qp);
812
813 if (ib_qp->qp_type == IB_QPT_GSI && rdev->gsi_ctx.gsi_sqp) {
814 rc = bnxt_re_destroy_gsi_sqp(qp);
815 if (rc)
816 goto sh_fail;
817 }
818
819 mutex_lock(&rdev->qp_lock);
820 list_del(&qp->list);
821 mutex_unlock(&rdev->qp_lock);
822 atomic_dec(&rdev->qp_count);
823
824 ib_umem_release(qp->rumem);
825 ib_umem_release(qp->sumem);
826
827 kfree(qp);
828 return 0;
829 sh_fail:
830 return rc;
831 }
832
__from_ib_qp_type(enum ib_qp_type type)833 static u8 __from_ib_qp_type(enum ib_qp_type type)
834 {
835 switch (type) {
836 case IB_QPT_GSI:
837 return CMDQ_CREATE_QP1_TYPE_GSI;
838 case IB_QPT_RC:
839 return CMDQ_CREATE_QP_TYPE_RC;
840 case IB_QPT_UD:
841 return CMDQ_CREATE_QP_TYPE_UD;
842 default:
843 return IB_QPT_MAX;
844 }
845 }
846
bnxt_re_setup_rwqe_size(struct bnxt_qplib_qp * qplqp,int rsge,int max)847 static u16 bnxt_re_setup_rwqe_size(struct bnxt_qplib_qp *qplqp,
848 int rsge, int max)
849 {
850 if (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC)
851 rsge = max;
852 return bnxt_re_get_rwqe_size(rsge);
853 }
854
bnxt_re_get_wqe_size(int ilsize,int nsge)855 static u16 bnxt_re_get_wqe_size(int ilsize, int nsge)
856 {
857 u16 wqe_size, calc_ils;
858
859 wqe_size = bnxt_re_get_swqe_size(nsge);
860 if (ilsize) {
861 calc_ils = sizeof(struct sq_send_hdr) + ilsize;
862 wqe_size = max_t(u16, calc_ils, wqe_size);
863 wqe_size = ALIGN(wqe_size, sizeof(struct sq_send_hdr));
864 }
865 return wqe_size;
866 }
867
bnxt_re_setup_swqe_size(struct bnxt_re_qp * qp,struct ib_qp_init_attr * init_attr)868 static int bnxt_re_setup_swqe_size(struct bnxt_re_qp *qp,
869 struct ib_qp_init_attr *init_attr)
870 {
871 struct bnxt_qplib_dev_attr *dev_attr;
872 struct bnxt_qplib_qp *qplqp;
873 struct bnxt_re_dev *rdev;
874 struct bnxt_qplib_q *sq;
875 int align, ilsize;
876
877 rdev = qp->rdev;
878 qplqp = &qp->qplib_qp;
879 sq = &qplqp->sq;
880 dev_attr = &rdev->dev_attr;
881
882 align = sizeof(struct sq_send_hdr);
883 ilsize = ALIGN(init_attr->cap.max_inline_data, align);
884
885 sq->wqe_size = bnxt_re_get_wqe_size(ilsize, sq->max_sge);
886 if (sq->wqe_size > bnxt_re_get_swqe_size(dev_attr->max_qp_sges))
887 return -EINVAL;
888 /* For gen p4 and gen p5 backward compatibility mode
889 * wqe size is fixed to 128 bytes
890 */
891 if (sq->wqe_size < bnxt_re_get_swqe_size(dev_attr->max_qp_sges) &&
892 qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC)
893 sq->wqe_size = bnxt_re_get_swqe_size(dev_attr->max_qp_sges);
894
895 if (init_attr->cap.max_inline_data) {
896 qplqp->max_inline_data = sq->wqe_size -
897 sizeof(struct sq_send_hdr);
898 init_attr->cap.max_inline_data = qplqp->max_inline_data;
899 if (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC)
900 sq->max_sge = qplqp->max_inline_data /
901 sizeof(struct sq_sge);
902 }
903
904 return 0;
905 }
906
bnxt_re_init_user_qp(struct bnxt_re_dev * rdev,struct bnxt_re_pd * pd,struct bnxt_re_qp * qp,struct ib_udata * udata)907 static int bnxt_re_init_user_qp(struct bnxt_re_dev *rdev, struct bnxt_re_pd *pd,
908 struct bnxt_re_qp *qp, struct ib_udata *udata)
909 {
910 struct bnxt_qplib_qp *qplib_qp;
911 struct bnxt_re_ucontext *cntx;
912 struct bnxt_re_qp_req ureq;
913 int bytes = 0, psn_sz;
914 struct ib_umem *umem;
915 int psn_nume;
916
917 qplib_qp = &qp->qplib_qp;
918 cntx = rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext,
919 ib_uctx);
920 if (ib_copy_from_udata(&ureq, udata, sizeof(ureq)))
921 return -EFAULT;
922
923 bytes = (qplib_qp->sq.max_wqe * qplib_qp->sq.wqe_size);
924 /* Consider mapping PSN search memory only for RC QPs. */
925 if (qplib_qp->type == CMDQ_CREATE_QP_TYPE_RC) {
926 psn_sz = bnxt_qplib_is_chip_gen_p5(rdev->chip_ctx) ?
927 sizeof(struct sq_psn_search_ext) :
928 sizeof(struct sq_psn_search);
929 psn_nume = (qplib_qp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC) ?
930 qplib_qp->sq.max_wqe :
931 ((qplib_qp->sq.max_wqe * qplib_qp->sq.wqe_size) /
932 sizeof(struct bnxt_qplib_sge));
933 bytes += (psn_nume * psn_sz);
934 }
935
936 bytes = PAGE_ALIGN(bytes);
937 umem = ib_umem_get(&rdev->ibdev, ureq.qpsva, bytes,
938 IB_ACCESS_LOCAL_WRITE);
939 if (IS_ERR(umem))
940 return PTR_ERR(umem);
941
942 qp->sumem = umem;
943 qplib_qp->sq.sg_info.umem = umem;
944 qplib_qp->sq.sg_info.pgsize = PAGE_SIZE;
945 qplib_qp->sq.sg_info.pgshft = PAGE_SHIFT;
946 qplib_qp->qp_handle = ureq.qp_handle;
947
948 if (!qp->qplib_qp.srq) {
949 bytes = (qplib_qp->rq.max_wqe * qplib_qp->rq.wqe_size);
950 bytes = PAGE_ALIGN(bytes);
951 umem = ib_umem_get(&rdev->ibdev, ureq.qprva, bytes,
952 IB_ACCESS_LOCAL_WRITE);
953 if (IS_ERR(umem))
954 goto rqfail;
955 qp->rumem = umem;
956 qplib_qp->rq.sg_info.umem = umem;
957 qplib_qp->rq.sg_info.pgsize = PAGE_SIZE;
958 qplib_qp->rq.sg_info.pgshft = PAGE_SHIFT;
959 }
960
961 qplib_qp->dpi = &cntx->dpi;
962 return 0;
963 rqfail:
964 ib_umem_release(qp->sumem);
965 qp->sumem = NULL;
966 memset(&qplib_qp->sq.sg_info, 0, sizeof(qplib_qp->sq.sg_info));
967
968 return PTR_ERR(umem);
969 }
970
bnxt_re_create_shadow_qp_ah(struct bnxt_re_pd * pd,struct bnxt_qplib_res * qp1_res,struct bnxt_qplib_qp * qp1_qp)971 static struct bnxt_re_ah *bnxt_re_create_shadow_qp_ah
972 (struct bnxt_re_pd *pd,
973 struct bnxt_qplib_res *qp1_res,
974 struct bnxt_qplib_qp *qp1_qp)
975 {
976 struct bnxt_re_dev *rdev = pd->rdev;
977 struct bnxt_re_ah *ah;
978 union ib_gid sgid;
979 int rc;
980
981 ah = kzalloc(sizeof(*ah), GFP_KERNEL);
982 if (!ah)
983 return NULL;
984
985 ah->rdev = rdev;
986 ah->qplib_ah.pd = &pd->qplib_pd;
987
988 rc = bnxt_re_query_gid(&rdev->ibdev, 1, 0, &sgid);
989 if (rc)
990 goto fail;
991
992 /* supply the dgid data same as sgid */
993 memcpy(ah->qplib_ah.dgid.data, &sgid.raw,
994 sizeof(union ib_gid));
995 ah->qplib_ah.sgid_index = 0;
996
997 ah->qplib_ah.traffic_class = 0;
998 ah->qplib_ah.flow_label = 0;
999 ah->qplib_ah.hop_limit = 1;
1000 ah->qplib_ah.sl = 0;
1001 /* Have DMAC same as SMAC */
1002 ether_addr_copy(ah->qplib_ah.dmac, rdev->netdev->dev_addr);
1003
1004 rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah, false);
1005 if (rc) {
1006 ibdev_err(&rdev->ibdev,
1007 "Failed to allocate HW AH for Shadow QP");
1008 goto fail;
1009 }
1010
1011 return ah;
1012
1013 fail:
1014 kfree(ah);
1015 return NULL;
1016 }
1017
bnxt_re_create_shadow_qp(struct bnxt_re_pd * pd,struct bnxt_qplib_res * qp1_res,struct bnxt_qplib_qp * qp1_qp)1018 static struct bnxt_re_qp *bnxt_re_create_shadow_qp
1019 (struct bnxt_re_pd *pd,
1020 struct bnxt_qplib_res *qp1_res,
1021 struct bnxt_qplib_qp *qp1_qp)
1022 {
1023 struct bnxt_re_dev *rdev = pd->rdev;
1024 struct bnxt_re_qp *qp;
1025 int rc;
1026
1027 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
1028 if (!qp)
1029 return NULL;
1030
1031 qp->rdev = rdev;
1032
1033 /* Initialize the shadow QP structure from the QP1 values */
1034 ether_addr_copy(qp->qplib_qp.smac, rdev->netdev->dev_addr);
1035
1036 qp->qplib_qp.pd = &pd->qplib_pd;
1037 qp->qplib_qp.qp_handle = (u64)(unsigned long)(&qp->qplib_qp);
1038 qp->qplib_qp.type = IB_QPT_UD;
1039
1040 qp->qplib_qp.max_inline_data = 0;
1041 qp->qplib_qp.sig_type = true;
1042
1043 /* Shadow QP SQ depth should be same as QP1 RQ depth */
1044 qp->qplib_qp.sq.wqe_size = bnxt_re_get_wqe_size(0, 6);
1045 qp->qplib_qp.sq.max_wqe = qp1_qp->rq.max_wqe;
1046 qp->qplib_qp.sq.max_sge = 2;
1047 /* Q full delta can be 1 since it is internal QP */
1048 qp->qplib_qp.sq.q_full_delta = 1;
1049 qp->qplib_qp.sq.sg_info.pgsize = PAGE_SIZE;
1050 qp->qplib_qp.sq.sg_info.pgshft = PAGE_SHIFT;
1051
1052 qp->qplib_qp.scq = qp1_qp->scq;
1053 qp->qplib_qp.rcq = qp1_qp->rcq;
1054
1055 qp->qplib_qp.rq.wqe_size = bnxt_re_get_rwqe_size(6);
1056 qp->qplib_qp.rq.max_wqe = qp1_qp->rq.max_wqe;
1057 qp->qplib_qp.rq.max_sge = qp1_qp->rq.max_sge;
1058 /* Q full delta can be 1 since it is internal QP */
1059 qp->qplib_qp.rq.q_full_delta = 1;
1060 qp->qplib_qp.rq.sg_info.pgsize = PAGE_SIZE;
1061 qp->qplib_qp.rq.sg_info.pgshft = PAGE_SHIFT;
1062
1063 qp->qplib_qp.mtu = qp1_qp->mtu;
1064
1065 qp->qplib_qp.sq_hdr_buf_size = 0;
1066 qp->qplib_qp.rq_hdr_buf_size = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6;
1067 qp->qplib_qp.dpi = &rdev->dpi_privileged;
1068
1069 rc = bnxt_qplib_create_qp(qp1_res, &qp->qplib_qp);
1070 if (rc)
1071 goto fail;
1072
1073 spin_lock_init(&qp->sq_lock);
1074 INIT_LIST_HEAD(&qp->list);
1075 mutex_lock(&rdev->qp_lock);
1076 list_add_tail(&qp->list, &rdev->qp_list);
1077 atomic_inc(&rdev->qp_count);
1078 mutex_unlock(&rdev->qp_lock);
1079 return qp;
1080 fail:
1081 kfree(qp);
1082 return NULL;
1083 }
1084
bnxt_re_init_rq_attr(struct bnxt_re_qp * qp,struct ib_qp_init_attr * init_attr)1085 static int bnxt_re_init_rq_attr(struct bnxt_re_qp *qp,
1086 struct ib_qp_init_attr *init_attr)
1087 {
1088 struct bnxt_qplib_dev_attr *dev_attr;
1089 struct bnxt_qplib_qp *qplqp;
1090 struct bnxt_re_dev *rdev;
1091 struct bnxt_qplib_q *rq;
1092 int entries;
1093
1094 rdev = qp->rdev;
1095 qplqp = &qp->qplib_qp;
1096 rq = &qplqp->rq;
1097 dev_attr = &rdev->dev_attr;
1098
1099 if (init_attr->srq) {
1100 struct bnxt_re_srq *srq;
1101
1102 srq = container_of(init_attr->srq, struct bnxt_re_srq, ib_srq);
1103 if (!srq) {
1104 ibdev_err(&rdev->ibdev, "SRQ not found");
1105 return -EINVAL;
1106 }
1107 qplqp->srq = &srq->qplib_srq;
1108 rq->max_wqe = 0;
1109 } else {
1110 rq->max_sge = init_attr->cap.max_recv_sge;
1111 if (rq->max_sge > dev_attr->max_qp_sges)
1112 rq->max_sge = dev_attr->max_qp_sges;
1113 init_attr->cap.max_recv_sge = rq->max_sge;
1114 rq->wqe_size = bnxt_re_setup_rwqe_size(qplqp, rq->max_sge,
1115 dev_attr->max_qp_sges);
1116 /* Allocate 1 more than what's provided so posting max doesn't
1117 * mean empty.
1118 */
1119 entries = roundup_pow_of_two(init_attr->cap.max_recv_wr + 1);
1120 rq->max_wqe = min_t(u32, entries, dev_attr->max_qp_wqes + 1);
1121 rq->q_full_delta = 0;
1122 rq->sg_info.pgsize = PAGE_SIZE;
1123 rq->sg_info.pgshft = PAGE_SHIFT;
1124 }
1125
1126 return 0;
1127 }
1128
bnxt_re_adjust_gsi_rq_attr(struct bnxt_re_qp * qp)1129 static void bnxt_re_adjust_gsi_rq_attr(struct bnxt_re_qp *qp)
1130 {
1131 struct bnxt_qplib_dev_attr *dev_attr;
1132 struct bnxt_qplib_qp *qplqp;
1133 struct bnxt_re_dev *rdev;
1134
1135 rdev = qp->rdev;
1136 qplqp = &qp->qplib_qp;
1137 dev_attr = &rdev->dev_attr;
1138
1139 if (!bnxt_qplib_is_chip_gen_p5(rdev->chip_ctx)) {
1140 qplqp->rq.max_sge = dev_attr->max_qp_sges;
1141 if (qplqp->rq.max_sge > dev_attr->max_qp_sges)
1142 qplqp->rq.max_sge = dev_attr->max_qp_sges;
1143 qplqp->rq.max_sge = 6;
1144 }
1145 }
1146
bnxt_re_init_sq_attr(struct bnxt_re_qp * qp,struct ib_qp_init_attr * init_attr,struct ib_udata * udata)1147 static int bnxt_re_init_sq_attr(struct bnxt_re_qp *qp,
1148 struct ib_qp_init_attr *init_attr,
1149 struct ib_udata *udata)
1150 {
1151 struct bnxt_qplib_dev_attr *dev_attr;
1152 struct bnxt_qplib_qp *qplqp;
1153 struct bnxt_re_dev *rdev;
1154 struct bnxt_qplib_q *sq;
1155 int entries;
1156 int diff;
1157 int rc;
1158
1159 rdev = qp->rdev;
1160 qplqp = &qp->qplib_qp;
1161 sq = &qplqp->sq;
1162 dev_attr = &rdev->dev_attr;
1163
1164 sq->max_sge = init_attr->cap.max_send_sge;
1165 if (sq->max_sge > dev_attr->max_qp_sges) {
1166 sq->max_sge = dev_attr->max_qp_sges;
1167 init_attr->cap.max_send_sge = sq->max_sge;
1168 }
1169
1170 rc = bnxt_re_setup_swqe_size(qp, init_attr);
1171 if (rc)
1172 return rc;
1173
1174 entries = init_attr->cap.max_send_wr;
1175 /* Allocate 128 + 1 more than what's provided */
1176 diff = (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_VARIABLE) ?
1177 0 : BNXT_QPLIB_RESERVED_QP_WRS;
1178 entries = roundup_pow_of_two(entries + diff + 1);
1179 sq->max_wqe = min_t(u32, entries, dev_attr->max_qp_wqes + diff + 1);
1180 sq->q_full_delta = diff + 1;
1181 /*
1182 * Reserving one slot for Phantom WQE. Application can
1183 * post one extra entry in this case. But allowing this to avoid
1184 * unexpected Queue full condition
1185 */
1186 qplqp->sq.q_full_delta -= 1;
1187 qplqp->sq.sg_info.pgsize = PAGE_SIZE;
1188 qplqp->sq.sg_info.pgshft = PAGE_SHIFT;
1189
1190 return 0;
1191 }
1192
bnxt_re_adjust_gsi_sq_attr(struct bnxt_re_qp * qp,struct ib_qp_init_attr * init_attr)1193 static void bnxt_re_adjust_gsi_sq_attr(struct bnxt_re_qp *qp,
1194 struct ib_qp_init_attr *init_attr)
1195 {
1196 struct bnxt_qplib_dev_attr *dev_attr;
1197 struct bnxt_qplib_qp *qplqp;
1198 struct bnxt_re_dev *rdev;
1199 int entries;
1200
1201 rdev = qp->rdev;
1202 qplqp = &qp->qplib_qp;
1203 dev_attr = &rdev->dev_attr;
1204
1205 if (!bnxt_qplib_is_chip_gen_p5(rdev->chip_ctx)) {
1206 entries = roundup_pow_of_two(init_attr->cap.max_send_wr + 1);
1207 qplqp->sq.max_wqe = min_t(u32, entries,
1208 dev_attr->max_qp_wqes + 1);
1209 qplqp->sq.q_full_delta = qplqp->sq.max_wqe -
1210 init_attr->cap.max_send_wr;
1211 qplqp->sq.max_sge++; /* Need one extra sge to put UD header */
1212 if (qplqp->sq.max_sge > dev_attr->max_qp_sges)
1213 qplqp->sq.max_sge = dev_attr->max_qp_sges;
1214 }
1215 }
1216
bnxt_re_init_qp_type(struct bnxt_re_dev * rdev,struct ib_qp_init_attr * init_attr)1217 static int bnxt_re_init_qp_type(struct bnxt_re_dev *rdev,
1218 struct ib_qp_init_attr *init_attr)
1219 {
1220 struct bnxt_qplib_chip_ctx *chip_ctx;
1221 int qptype;
1222
1223 chip_ctx = rdev->chip_ctx;
1224
1225 qptype = __from_ib_qp_type(init_attr->qp_type);
1226 if (qptype == IB_QPT_MAX) {
1227 ibdev_err(&rdev->ibdev, "QP type 0x%x not supported", qptype);
1228 qptype = -EOPNOTSUPP;
1229 goto out;
1230 }
1231
1232 if (bnxt_qplib_is_chip_gen_p5(chip_ctx) &&
1233 init_attr->qp_type == IB_QPT_GSI)
1234 qptype = CMDQ_CREATE_QP_TYPE_GSI;
1235 out:
1236 return qptype;
1237 }
1238
bnxt_re_init_qp_attr(struct bnxt_re_qp * qp,struct bnxt_re_pd * pd,struct ib_qp_init_attr * init_attr,struct ib_udata * udata)1239 static int bnxt_re_init_qp_attr(struct bnxt_re_qp *qp, struct bnxt_re_pd *pd,
1240 struct ib_qp_init_attr *init_attr,
1241 struct ib_udata *udata)
1242 {
1243 struct bnxt_qplib_dev_attr *dev_attr;
1244 struct bnxt_qplib_qp *qplqp;
1245 struct bnxt_re_dev *rdev;
1246 struct bnxt_re_cq *cq;
1247 int rc = 0, qptype;
1248
1249 rdev = qp->rdev;
1250 qplqp = &qp->qplib_qp;
1251 dev_attr = &rdev->dev_attr;
1252
1253 /* Setup misc params */
1254 ether_addr_copy(qplqp->smac, rdev->netdev->dev_addr);
1255 qplqp->pd = &pd->qplib_pd;
1256 qplqp->qp_handle = (u64)qplqp;
1257 qplqp->max_inline_data = init_attr->cap.max_inline_data;
1258 qplqp->sig_type = ((init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) ?
1259 true : false);
1260 qptype = bnxt_re_init_qp_type(rdev, init_attr);
1261 if (qptype < 0) {
1262 rc = qptype;
1263 goto out;
1264 }
1265 qplqp->type = (u8)qptype;
1266 qplqp->wqe_mode = rdev->chip_ctx->modes.wqe_mode;
1267
1268 if (init_attr->qp_type == IB_QPT_RC) {
1269 qplqp->max_rd_atomic = dev_attr->max_qp_rd_atom;
1270 qplqp->max_dest_rd_atomic = dev_attr->max_qp_init_rd_atom;
1271 }
1272 qplqp->mtu = ib_mtu_enum_to_int(iboe_get_mtu(rdev->netdev->mtu));
1273 qplqp->dpi = &rdev->dpi_privileged; /* Doorbell page */
1274 if (init_attr->create_flags)
1275 ibdev_dbg(&rdev->ibdev,
1276 "QP create flags 0x%x not supported",
1277 init_attr->create_flags);
1278
1279 /* Setup CQs */
1280 if (init_attr->send_cq) {
1281 cq = container_of(init_attr->send_cq, struct bnxt_re_cq, ib_cq);
1282 if (!cq) {
1283 ibdev_err(&rdev->ibdev, "Send CQ not found");
1284 rc = -EINVAL;
1285 goto out;
1286 }
1287 qplqp->scq = &cq->qplib_cq;
1288 qp->scq = cq;
1289 }
1290
1291 if (init_attr->recv_cq) {
1292 cq = container_of(init_attr->recv_cq, struct bnxt_re_cq, ib_cq);
1293 if (!cq) {
1294 ibdev_err(&rdev->ibdev, "Receive CQ not found");
1295 rc = -EINVAL;
1296 goto out;
1297 }
1298 qplqp->rcq = &cq->qplib_cq;
1299 qp->rcq = cq;
1300 }
1301
1302 /* Setup RQ/SRQ */
1303 rc = bnxt_re_init_rq_attr(qp, init_attr);
1304 if (rc)
1305 goto out;
1306 if (init_attr->qp_type == IB_QPT_GSI)
1307 bnxt_re_adjust_gsi_rq_attr(qp);
1308
1309 /* Setup SQ */
1310 rc = bnxt_re_init_sq_attr(qp, init_attr, udata);
1311 if (rc)
1312 goto out;
1313 if (init_attr->qp_type == IB_QPT_GSI)
1314 bnxt_re_adjust_gsi_sq_attr(qp, init_attr);
1315
1316 if (udata) /* This will update DPI and qp_handle */
1317 rc = bnxt_re_init_user_qp(rdev, pd, qp, udata);
1318 out:
1319 return rc;
1320 }
1321
bnxt_re_create_shadow_gsi(struct bnxt_re_qp * qp,struct bnxt_re_pd * pd)1322 static int bnxt_re_create_shadow_gsi(struct bnxt_re_qp *qp,
1323 struct bnxt_re_pd *pd)
1324 {
1325 struct bnxt_re_sqp_entries *sqp_tbl = NULL;
1326 struct bnxt_re_dev *rdev;
1327 struct bnxt_re_qp *sqp;
1328 struct bnxt_re_ah *sah;
1329 int rc = 0;
1330
1331 rdev = qp->rdev;
1332 /* Create a shadow QP to handle the QP1 traffic */
1333 sqp_tbl = kzalloc(sizeof(*sqp_tbl) * BNXT_RE_MAX_GSI_SQP_ENTRIES,
1334 GFP_KERNEL);
1335 if (!sqp_tbl)
1336 return -ENOMEM;
1337 rdev->gsi_ctx.sqp_tbl = sqp_tbl;
1338
1339 sqp = bnxt_re_create_shadow_qp(pd, &rdev->qplib_res, &qp->qplib_qp);
1340 if (!sqp) {
1341 rc = -ENODEV;
1342 ibdev_err(&rdev->ibdev, "Failed to create Shadow QP for QP1");
1343 goto out;
1344 }
1345 rdev->gsi_ctx.gsi_sqp = sqp;
1346
1347 sqp->rcq = qp->rcq;
1348 sqp->scq = qp->scq;
1349 sah = bnxt_re_create_shadow_qp_ah(pd, &rdev->qplib_res,
1350 &qp->qplib_qp);
1351 if (!sah) {
1352 bnxt_qplib_destroy_qp(&rdev->qplib_res,
1353 &sqp->qplib_qp);
1354 rc = -ENODEV;
1355 ibdev_err(&rdev->ibdev,
1356 "Failed to create AH entry for ShadowQP");
1357 goto out;
1358 }
1359 rdev->gsi_ctx.gsi_sah = sah;
1360
1361 return 0;
1362 out:
1363 kfree(sqp_tbl);
1364 return rc;
1365 }
1366
bnxt_re_create_gsi_qp(struct bnxt_re_qp * qp,struct bnxt_re_pd * pd,struct ib_qp_init_attr * init_attr)1367 static int bnxt_re_create_gsi_qp(struct bnxt_re_qp *qp, struct bnxt_re_pd *pd,
1368 struct ib_qp_init_attr *init_attr)
1369 {
1370 struct bnxt_re_dev *rdev;
1371 struct bnxt_qplib_qp *qplqp;
1372 int rc = 0;
1373
1374 rdev = qp->rdev;
1375 qplqp = &qp->qplib_qp;
1376
1377 qplqp->rq_hdr_buf_size = BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2;
1378 qplqp->sq_hdr_buf_size = BNXT_QPLIB_MAX_QP1_SQ_HDR_SIZE_V2;
1379
1380 rc = bnxt_qplib_create_qp1(&rdev->qplib_res, qplqp);
1381 if (rc) {
1382 ibdev_err(&rdev->ibdev, "create HW QP1 failed!");
1383 goto out;
1384 }
1385
1386 rc = bnxt_re_create_shadow_gsi(qp, pd);
1387 out:
1388 return rc;
1389 }
1390
bnxt_re_test_qp_limits(struct bnxt_re_dev * rdev,struct ib_qp_init_attr * init_attr,struct bnxt_qplib_dev_attr * dev_attr)1391 static bool bnxt_re_test_qp_limits(struct bnxt_re_dev *rdev,
1392 struct ib_qp_init_attr *init_attr,
1393 struct bnxt_qplib_dev_attr *dev_attr)
1394 {
1395 bool rc = true;
1396
1397 if (init_attr->cap.max_send_wr > dev_attr->max_qp_wqes ||
1398 init_attr->cap.max_recv_wr > dev_attr->max_qp_wqes ||
1399 init_attr->cap.max_send_sge > dev_attr->max_qp_sges ||
1400 init_attr->cap.max_recv_sge > dev_attr->max_qp_sges ||
1401 init_attr->cap.max_inline_data > dev_attr->max_inline_data) {
1402 ibdev_err(&rdev->ibdev,
1403 "Create QP failed - max exceeded! 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x",
1404 init_attr->cap.max_send_wr, dev_attr->max_qp_wqes,
1405 init_attr->cap.max_recv_wr, dev_attr->max_qp_wqes,
1406 init_attr->cap.max_send_sge, dev_attr->max_qp_sges,
1407 init_attr->cap.max_recv_sge, dev_attr->max_qp_sges,
1408 init_attr->cap.max_inline_data,
1409 dev_attr->max_inline_data);
1410 rc = false;
1411 }
1412 return rc;
1413 }
1414
bnxt_re_create_qp(struct ib_pd * ib_pd,struct ib_qp_init_attr * qp_init_attr,struct ib_udata * udata)1415 struct ib_qp *bnxt_re_create_qp(struct ib_pd *ib_pd,
1416 struct ib_qp_init_attr *qp_init_attr,
1417 struct ib_udata *udata)
1418 {
1419 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
1420 struct bnxt_re_dev *rdev = pd->rdev;
1421 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
1422 struct bnxt_re_qp *qp;
1423 int rc;
1424
1425 rc = bnxt_re_test_qp_limits(rdev, qp_init_attr, dev_attr);
1426 if (!rc) {
1427 rc = -EINVAL;
1428 goto exit;
1429 }
1430
1431 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
1432 if (!qp) {
1433 rc = -ENOMEM;
1434 goto exit;
1435 }
1436 qp->rdev = rdev;
1437 rc = bnxt_re_init_qp_attr(qp, pd, qp_init_attr, udata);
1438 if (rc)
1439 goto fail;
1440
1441 if (qp_init_attr->qp_type == IB_QPT_GSI &&
1442 !(bnxt_qplib_is_chip_gen_p5(rdev->chip_ctx))) {
1443 rc = bnxt_re_create_gsi_qp(qp, pd, qp_init_attr);
1444 if (rc == -ENODEV)
1445 goto qp_destroy;
1446 if (rc)
1447 goto fail;
1448 } else {
1449 rc = bnxt_qplib_create_qp(&rdev->qplib_res, &qp->qplib_qp);
1450 if (rc) {
1451 ibdev_err(&rdev->ibdev, "Failed to create HW QP");
1452 goto free_umem;
1453 }
1454 if (udata) {
1455 struct bnxt_re_qp_resp resp;
1456
1457 resp.qpid = qp->qplib_qp.id;
1458 resp.rsvd = 0;
1459 rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
1460 if (rc) {
1461 ibdev_err(&rdev->ibdev, "Failed to copy QP udata");
1462 goto qp_destroy;
1463 }
1464 }
1465 }
1466
1467 qp->ib_qp.qp_num = qp->qplib_qp.id;
1468 if (qp_init_attr->qp_type == IB_QPT_GSI)
1469 rdev->gsi_ctx.gsi_qp = qp;
1470 spin_lock_init(&qp->sq_lock);
1471 spin_lock_init(&qp->rq_lock);
1472 INIT_LIST_HEAD(&qp->list);
1473 mutex_lock(&rdev->qp_lock);
1474 list_add_tail(&qp->list, &rdev->qp_list);
1475 mutex_unlock(&rdev->qp_lock);
1476 atomic_inc(&rdev->qp_count);
1477
1478 return &qp->ib_qp;
1479 qp_destroy:
1480 bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp);
1481 free_umem:
1482 ib_umem_release(qp->rumem);
1483 ib_umem_release(qp->sumem);
1484 fail:
1485 kfree(qp);
1486 exit:
1487 return ERR_PTR(rc);
1488 }
1489
__from_ib_qp_state(enum ib_qp_state state)1490 static u8 __from_ib_qp_state(enum ib_qp_state state)
1491 {
1492 switch (state) {
1493 case IB_QPS_RESET:
1494 return CMDQ_MODIFY_QP_NEW_STATE_RESET;
1495 case IB_QPS_INIT:
1496 return CMDQ_MODIFY_QP_NEW_STATE_INIT;
1497 case IB_QPS_RTR:
1498 return CMDQ_MODIFY_QP_NEW_STATE_RTR;
1499 case IB_QPS_RTS:
1500 return CMDQ_MODIFY_QP_NEW_STATE_RTS;
1501 case IB_QPS_SQD:
1502 return CMDQ_MODIFY_QP_NEW_STATE_SQD;
1503 case IB_QPS_SQE:
1504 return CMDQ_MODIFY_QP_NEW_STATE_SQE;
1505 case IB_QPS_ERR:
1506 default:
1507 return CMDQ_MODIFY_QP_NEW_STATE_ERR;
1508 }
1509 }
1510
__to_ib_qp_state(u8 state)1511 static enum ib_qp_state __to_ib_qp_state(u8 state)
1512 {
1513 switch (state) {
1514 case CMDQ_MODIFY_QP_NEW_STATE_RESET:
1515 return IB_QPS_RESET;
1516 case CMDQ_MODIFY_QP_NEW_STATE_INIT:
1517 return IB_QPS_INIT;
1518 case CMDQ_MODIFY_QP_NEW_STATE_RTR:
1519 return IB_QPS_RTR;
1520 case CMDQ_MODIFY_QP_NEW_STATE_RTS:
1521 return IB_QPS_RTS;
1522 case CMDQ_MODIFY_QP_NEW_STATE_SQD:
1523 return IB_QPS_SQD;
1524 case CMDQ_MODIFY_QP_NEW_STATE_SQE:
1525 return IB_QPS_SQE;
1526 case CMDQ_MODIFY_QP_NEW_STATE_ERR:
1527 default:
1528 return IB_QPS_ERR;
1529 }
1530 }
1531
__from_ib_mtu(enum ib_mtu mtu)1532 static u32 __from_ib_mtu(enum ib_mtu mtu)
1533 {
1534 switch (mtu) {
1535 case IB_MTU_256:
1536 return CMDQ_MODIFY_QP_PATH_MTU_MTU_256;
1537 case IB_MTU_512:
1538 return CMDQ_MODIFY_QP_PATH_MTU_MTU_512;
1539 case IB_MTU_1024:
1540 return CMDQ_MODIFY_QP_PATH_MTU_MTU_1024;
1541 case IB_MTU_2048:
1542 return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048;
1543 case IB_MTU_4096:
1544 return CMDQ_MODIFY_QP_PATH_MTU_MTU_4096;
1545 default:
1546 return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048;
1547 }
1548 }
1549
__to_ib_mtu(u32 mtu)1550 static enum ib_mtu __to_ib_mtu(u32 mtu)
1551 {
1552 switch (mtu & CREQ_QUERY_QP_RESP_SB_PATH_MTU_MASK) {
1553 case CMDQ_MODIFY_QP_PATH_MTU_MTU_256:
1554 return IB_MTU_256;
1555 case CMDQ_MODIFY_QP_PATH_MTU_MTU_512:
1556 return IB_MTU_512;
1557 case CMDQ_MODIFY_QP_PATH_MTU_MTU_1024:
1558 return IB_MTU_1024;
1559 case CMDQ_MODIFY_QP_PATH_MTU_MTU_2048:
1560 return IB_MTU_2048;
1561 case CMDQ_MODIFY_QP_PATH_MTU_MTU_4096:
1562 return IB_MTU_4096;
1563 default:
1564 return IB_MTU_2048;
1565 }
1566 }
1567
1568 /* Shared Receive Queues */
bnxt_re_destroy_srq(struct ib_srq * ib_srq,struct ib_udata * udata)1569 int bnxt_re_destroy_srq(struct ib_srq *ib_srq, struct ib_udata *udata)
1570 {
1571 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq,
1572 ib_srq);
1573 struct bnxt_re_dev *rdev = srq->rdev;
1574 struct bnxt_qplib_srq *qplib_srq = &srq->qplib_srq;
1575 struct bnxt_qplib_nq *nq = NULL;
1576
1577 if (qplib_srq->cq)
1578 nq = qplib_srq->cq->nq;
1579 bnxt_qplib_destroy_srq(&rdev->qplib_res, qplib_srq);
1580 ib_umem_release(srq->umem);
1581 atomic_dec(&rdev->srq_count);
1582 if (nq)
1583 nq->budget--;
1584 return 0;
1585 }
1586
bnxt_re_init_user_srq(struct bnxt_re_dev * rdev,struct bnxt_re_pd * pd,struct bnxt_re_srq * srq,struct ib_udata * udata)1587 static int bnxt_re_init_user_srq(struct bnxt_re_dev *rdev,
1588 struct bnxt_re_pd *pd,
1589 struct bnxt_re_srq *srq,
1590 struct ib_udata *udata)
1591 {
1592 struct bnxt_re_srq_req ureq;
1593 struct bnxt_qplib_srq *qplib_srq = &srq->qplib_srq;
1594 struct ib_umem *umem;
1595 int bytes = 0;
1596 struct bnxt_re_ucontext *cntx = rdma_udata_to_drv_context(
1597 udata, struct bnxt_re_ucontext, ib_uctx);
1598
1599 if (ib_copy_from_udata(&ureq, udata, sizeof(ureq)))
1600 return -EFAULT;
1601
1602 bytes = (qplib_srq->max_wqe * qplib_srq->wqe_size);
1603 bytes = PAGE_ALIGN(bytes);
1604 umem = ib_umem_get(&rdev->ibdev, ureq.srqva, bytes,
1605 IB_ACCESS_LOCAL_WRITE);
1606 if (IS_ERR(umem))
1607 return PTR_ERR(umem);
1608
1609 srq->umem = umem;
1610 qplib_srq->sg_info.umem = umem;
1611 qplib_srq->sg_info.pgsize = PAGE_SIZE;
1612 qplib_srq->sg_info.pgshft = PAGE_SHIFT;
1613 qplib_srq->srq_handle = ureq.srq_handle;
1614 qplib_srq->dpi = &cntx->dpi;
1615
1616 return 0;
1617 }
1618
bnxt_re_create_srq(struct ib_srq * ib_srq,struct ib_srq_init_attr * srq_init_attr,struct ib_udata * udata)1619 int bnxt_re_create_srq(struct ib_srq *ib_srq,
1620 struct ib_srq_init_attr *srq_init_attr,
1621 struct ib_udata *udata)
1622 {
1623 struct bnxt_qplib_dev_attr *dev_attr;
1624 struct bnxt_qplib_nq *nq = NULL;
1625 struct bnxt_re_dev *rdev;
1626 struct bnxt_re_srq *srq;
1627 struct bnxt_re_pd *pd;
1628 struct ib_pd *ib_pd;
1629 int rc, entries;
1630
1631 ib_pd = ib_srq->pd;
1632 pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
1633 rdev = pd->rdev;
1634 dev_attr = &rdev->dev_attr;
1635 srq = container_of(ib_srq, struct bnxt_re_srq, ib_srq);
1636
1637 if (srq_init_attr->attr.max_wr >= dev_attr->max_srq_wqes) {
1638 ibdev_err(&rdev->ibdev, "Create CQ failed - max exceeded");
1639 rc = -EINVAL;
1640 goto exit;
1641 }
1642
1643 if (srq_init_attr->srq_type != IB_SRQT_BASIC) {
1644 rc = -EOPNOTSUPP;
1645 goto exit;
1646 }
1647
1648 srq->rdev = rdev;
1649 srq->qplib_srq.pd = &pd->qplib_pd;
1650 srq->qplib_srq.dpi = &rdev->dpi_privileged;
1651 /* Allocate 1 more than what's provided so posting max doesn't
1652 * mean empty
1653 */
1654 entries = roundup_pow_of_two(srq_init_attr->attr.max_wr + 1);
1655 if (entries > dev_attr->max_srq_wqes + 1)
1656 entries = dev_attr->max_srq_wqes + 1;
1657 srq->qplib_srq.max_wqe = entries;
1658
1659 srq->qplib_srq.max_sge = srq_init_attr->attr.max_sge;
1660 /* 128 byte wqe size for SRQ . So use max sges */
1661 srq->qplib_srq.wqe_size = bnxt_re_get_rwqe_size(dev_attr->max_srq_sges);
1662 srq->qplib_srq.threshold = srq_init_attr->attr.srq_limit;
1663 srq->srq_limit = srq_init_attr->attr.srq_limit;
1664 srq->qplib_srq.eventq_hw_ring_id = rdev->nq[0].ring_id;
1665 nq = &rdev->nq[0];
1666
1667 if (udata) {
1668 rc = bnxt_re_init_user_srq(rdev, pd, srq, udata);
1669 if (rc)
1670 goto fail;
1671 }
1672
1673 rc = bnxt_qplib_create_srq(&rdev->qplib_res, &srq->qplib_srq);
1674 if (rc) {
1675 ibdev_err(&rdev->ibdev, "Create HW SRQ failed!");
1676 goto fail;
1677 }
1678
1679 if (udata) {
1680 struct bnxt_re_srq_resp resp;
1681
1682 resp.srqid = srq->qplib_srq.id;
1683 rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
1684 if (rc) {
1685 ibdev_err(&rdev->ibdev, "SRQ copy to udata failed!");
1686 bnxt_qplib_destroy_srq(&rdev->qplib_res,
1687 &srq->qplib_srq);
1688 goto fail;
1689 }
1690 }
1691 if (nq)
1692 nq->budget++;
1693 atomic_inc(&rdev->srq_count);
1694 spin_lock_init(&srq->lock);
1695
1696 return 0;
1697
1698 fail:
1699 ib_umem_release(srq->umem);
1700 exit:
1701 return rc;
1702 }
1703
bnxt_re_modify_srq(struct ib_srq * ib_srq,struct ib_srq_attr * srq_attr,enum ib_srq_attr_mask srq_attr_mask,struct ib_udata * udata)1704 int bnxt_re_modify_srq(struct ib_srq *ib_srq, struct ib_srq_attr *srq_attr,
1705 enum ib_srq_attr_mask srq_attr_mask,
1706 struct ib_udata *udata)
1707 {
1708 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq,
1709 ib_srq);
1710 struct bnxt_re_dev *rdev = srq->rdev;
1711 int rc;
1712
1713 switch (srq_attr_mask) {
1714 case IB_SRQ_MAX_WR:
1715 /* SRQ resize is not supported */
1716 break;
1717 case IB_SRQ_LIMIT:
1718 /* Change the SRQ threshold */
1719 if (srq_attr->srq_limit > srq->qplib_srq.max_wqe)
1720 return -EINVAL;
1721
1722 srq->qplib_srq.threshold = srq_attr->srq_limit;
1723 rc = bnxt_qplib_modify_srq(&rdev->qplib_res, &srq->qplib_srq);
1724 if (rc) {
1725 ibdev_err(&rdev->ibdev, "Modify HW SRQ failed!");
1726 return rc;
1727 }
1728 /* On success, update the shadow */
1729 srq->srq_limit = srq_attr->srq_limit;
1730 /* No need to Build and send response back to udata */
1731 break;
1732 default:
1733 ibdev_err(&rdev->ibdev,
1734 "Unsupported srq_attr_mask 0x%x", srq_attr_mask);
1735 return -EINVAL;
1736 }
1737 return 0;
1738 }
1739
bnxt_re_query_srq(struct ib_srq * ib_srq,struct ib_srq_attr * srq_attr)1740 int bnxt_re_query_srq(struct ib_srq *ib_srq, struct ib_srq_attr *srq_attr)
1741 {
1742 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq,
1743 ib_srq);
1744 struct bnxt_re_srq tsrq;
1745 struct bnxt_re_dev *rdev = srq->rdev;
1746 int rc;
1747
1748 /* Get live SRQ attr */
1749 tsrq.qplib_srq.id = srq->qplib_srq.id;
1750 rc = bnxt_qplib_query_srq(&rdev->qplib_res, &tsrq.qplib_srq);
1751 if (rc) {
1752 ibdev_err(&rdev->ibdev, "Query HW SRQ failed!");
1753 return rc;
1754 }
1755 srq_attr->max_wr = srq->qplib_srq.max_wqe;
1756 srq_attr->max_sge = srq->qplib_srq.max_sge;
1757 srq_attr->srq_limit = tsrq.qplib_srq.threshold;
1758
1759 return 0;
1760 }
1761
bnxt_re_post_srq_recv(struct ib_srq * ib_srq,const struct ib_recv_wr * wr,const struct ib_recv_wr ** bad_wr)1762 int bnxt_re_post_srq_recv(struct ib_srq *ib_srq, const struct ib_recv_wr *wr,
1763 const struct ib_recv_wr **bad_wr)
1764 {
1765 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq,
1766 ib_srq);
1767 struct bnxt_qplib_swqe wqe;
1768 unsigned long flags;
1769 int rc = 0;
1770
1771 spin_lock_irqsave(&srq->lock, flags);
1772 while (wr) {
1773 /* Transcribe each ib_recv_wr to qplib_swqe */
1774 wqe.num_sge = wr->num_sge;
1775 bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, wr->num_sge);
1776 wqe.wr_id = wr->wr_id;
1777 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV;
1778
1779 rc = bnxt_qplib_post_srq_recv(&srq->qplib_srq, &wqe);
1780 if (rc) {
1781 *bad_wr = wr;
1782 break;
1783 }
1784 wr = wr->next;
1785 }
1786 spin_unlock_irqrestore(&srq->lock, flags);
1787
1788 return rc;
1789 }
bnxt_re_modify_shadow_qp(struct bnxt_re_dev * rdev,struct bnxt_re_qp * qp1_qp,int qp_attr_mask)1790 static int bnxt_re_modify_shadow_qp(struct bnxt_re_dev *rdev,
1791 struct bnxt_re_qp *qp1_qp,
1792 int qp_attr_mask)
1793 {
1794 struct bnxt_re_qp *qp = rdev->gsi_ctx.gsi_sqp;
1795 int rc = 0;
1796
1797 if (qp_attr_mask & IB_QP_STATE) {
1798 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE;
1799 qp->qplib_qp.state = qp1_qp->qplib_qp.state;
1800 }
1801 if (qp_attr_mask & IB_QP_PKEY_INDEX) {
1802 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY;
1803 qp->qplib_qp.pkey_index = qp1_qp->qplib_qp.pkey_index;
1804 }
1805
1806 if (qp_attr_mask & IB_QP_QKEY) {
1807 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY;
1808 /* Using a Random QKEY */
1809 qp->qplib_qp.qkey = 0x81818181;
1810 }
1811 if (qp_attr_mask & IB_QP_SQ_PSN) {
1812 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN;
1813 qp->qplib_qp.sq.psn = qp1_qp->qplib_qp.sq.psn;
1814 }
1815
1816 rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp);
1817 if (rc)
1818 ibdev_err(&rdev->ibdev, "Failed to modify Shadow QP for QP1");
1819 return rc;
1820 }
1821
bnxt_re_modify_qp(struct ib_qp * ib_qp,struct ib_qp_attr * qp_attr,int qp_attr_mask,struct ib_udata * udata)1822 int bnxt_re_modify_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr,
1823 int qp_attr_mask, struct ib_udata *udata)
1824 {
1825 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
1826 struct bnxt_re_dev *rdev = qp->rdev;
1827 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
1828 enum ib_qp_state curr_qp_state, new_qp_state;
1829 int rc, entries;
1830 unsigned int flags;
1831 u8 nw_type;
1832
1833 qp->qplib_qp.modify_flags = 0;
1834 if (qp_attr_mask & IB_QP_STATE) {
1835 curr_qp_state = __to_ib_qp_state(qp->qplib_qp.cur_qp_state);
1836 new_qp_state = qp_attr->qp_state;
1837 if (!ib_modify_qp_is_ok(curr_qp_state, new_qp_state,
1838 ib_qp->qp_type, qp_attr_mask)) {
1839 ibdev_err(&rdev->ibdev,
1840 "Invalid attribute mask: %#x specified ",
1841 qp_attr_mask);
1842 ibdev_err(&rdev->ibdev,
1843 "for qpn: %#x type: %#x",
1844 ib_qp->qp_num, ib_qp->qp_type);
1845 ibdev_err(&rdev->ibdev,
1846 "curr_qp_state=0x%x, new_qp_state=0x%x\n",
1847 curr_qp_state, new_qp_state);
1848 return -EINVAL;
1849 }
1850 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE;
1851 qp->qplib_qp.state = __from_ib_qp_state(qp_attr->qp_state);
1852
1853 if (!qp->sumem &&
1854 qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_ERR) {
1855 ibdev_dbg(&rdev->ibdev,
1856 "Move QP = %p to flush list\n", qp);
1857 flags = bnxt_re_lock_cqs(qp);
1858 bnxt_qplib_add_flush_qp(&qp->qplib_qp);
1859 bnxt_re_unlock_cqs(qp, flags);
1860 }
1861 if (!qp->sumem &&
1862 qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_RESET) {
1863 ibdev_dbg(&rdev->ibdev,
1864 "Move QP = %p out of flush list\n", qp);
1865 flags = bnxt_re_lock_cqs(qp);
1866 bnxt_qplib_clean_qp(&qp->qplib_qp);
1867 bnxt_re_unlock_cqs(qp, flags);
1868 }
1869 }
1870 if (qp_attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) {
1871 qp->qplib_qp.modify_flags |=
1872 CMDQ_MODIFY_QP_MODIFY_MASK_EN_SQD_ASYNC_NOTIFY;
1873 qp->qplib_qp.en_sqd_async_notify = true;
1874 }
1875 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) {
1876 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_ACCESS;
1877 qp->qplib_qp.access =
1878 __from_ib_access_flags(qp_attr->qp_access_flags);
1879 /* LOCAL_WRITE access must be set to allow RC receive */
1880 qp->qplib_qp.access |= BNXT_QPLIB_ACCESS_LOCAL_WRITE;
1881 /* Temp: Set all params on QP as of now */
1882 qp->qplib_qp.access |= CMDQ_MODIFY_QP_ACCESS_REMOTE_WRITE;
1883 qp->qplib_qp.access |= CMDQ_MODIFY_QP_ACCESS_REMOTE_READ;
1884 }
1885 if (qp_attr_mask & IB_QP_PKEY_INDEX) {
1886 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY;
1887 qp->qplib_qp.pkey_index = qp_attr->pkey_index;
1888 }
1889 if (qp_attr_mask & IB_QP_QKEY) {
1890 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY;
1891 qp->qplib_qp.qkey = qp_attr->qkey;
1892 }
1893 if (qp_attr_mask & IB_QP_AV) {
1894 const struct ib_global_route *grh =
1895 rdma_ah_read_grh(&qp_attr->ah_attr);
1896 const struct ib_gid_attr *sgid_attr;
1897 struct bnxt_re_gid_ctx *ctx;
1898
1899 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_DGID |
1900 CMDQ_MODIFY_QP_MODIFY_MASK_FLOW_LABEL |
1901 CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX |
1902 CMDQ_MODIFY_QP_MODIFY_MASK_HOP_LIMIT |
1903 CMDQ_MODIFY_QP_MODIFY_MASK_TRAFFIC_CLASS |
1904 CMDQ_MODIFY_QP_MODIFY_MASK_DEST_MAC |
1905 CMDQ_MODIFY_QP_MODIFY_MASK_VLAN_ID;
1906 memcpy(qp->qplib_qp.ah.dgid.data, grh->dgid.raw,
1907 sizeof(qp->qplib_qp.ah.dgid.data));
1908 qp->qplib_qp.ah.flow_label = grh->flow_label;
1909 sgid_attr = grh->sgid_attr;
1910 /* Get the HW context of the GID. The reference
1911 * of GID table entry is already taken by the caller.
1912 */
1913 ctx = rdma_read_gid_hw_context(sgid_attr);
1914 qp->qplib_qp.ah.sgid_index = ctx->idx;
1915 qp->qplib_qp.ah.host_sgid_index = grh->sgid_index;
1916 qp->qplib_qp.ah.hop_limit = grh->hop_limit;
1917 qp->qplib_qp.ah.traffic_class = grh->traffic_class;
1918 qp->qplib_qp.ah.sl = rdma_ah_get_sl(&qp_attr->ah_attr);
1919 ether_addr_copy(qp->qplib_qp.ah.dmac,
1920 qp_attr->ah_attr.roce.dmac);
1921
1922 rc = rdma_read_gid_l2_fields(sgid_attr, NULL,
1923 &qp->qplib_qp.smac[0]);
1924 if (rc)
1925 return rc;
1926
1927 nw_type = rdma_gid_attr_network_type(sgid_attr);
1928 switch (nw_type) {
1929 case RDMA_NETWORK_IPV4:
1930 qp->qplib_qp.nw_type =
1931 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV4;
1932 break;
1933 case RDMA_NETWORK_IPV6:
1934 qp->qplib_qp.nw_type =
1935 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6;
1936 break;
1937 default:
1938 qp->qplib_qp.nw_type =
1939 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV1;
1940 break;
1941 }
1942 }
1943
1944 if (qp_attr_mask & IB_QP_PATH_MTU) {
1945 qp->qplib_qp.modify_flags |=
1946 CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU;
1947 qp->qplib_qp.path_mtu = __from_ib_mtu(qp_attr->path_mtu);
1948 qp->qplib_qp.mtu = ib_mtu_enum_to_int(qp_attr->path_mtu);
1949 } else if (qp_attr->qp_state == IB_QPS_RTR) {
1950 qp->qplib_qp.modify_flags |=
1951 CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU;
1952 qp->qplib_qp.path_mtu =
1953 __from_ib_mtu(iboe_get_mtu(rdev->netdev->mtu));
1954 qp->qplib_qp.mtu =
1955 ib_mtu_enum_to_int(iboe_get_mtu(rdev->netdev->mtu));
1956 }
1957
1958 if (qp_attr_mask & IB_QP_TIMEOUT) {
1959 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_TIMEOUT;
1960 qp->qplib_qp.timeout = qp_attr->timeout;
1961 }
1962 if (qp_attr_mask & IB_QP_RETRY_CNT) {
1963 qp->qplib_qp.modify_flags |=
1964 CMDQ_MODIFY_QP_MODIFY_MASK_RETRY_CNT;
1965 qp->qplib_qp.retry_cnt = qp_attr->retry_cnt;
1966 }
1967 if (qp_attr_mask & IB_QP_RNR_RETRY) {
1968 qp->qplib_qp.modify_flags |=
1969 CMDQ_MODIFY_QP_MODIFY_MASK_RNR_RETRY;
1970 qp->qplib_qp.rnr_retry = qp_attr->rnr_retry;
1971 }
1972 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) {
1973 qp->qplib_qp.modify_flags |=
1974 CMDQ_MODIFY_QP_MODIFY_MASK_MIN_RNR_TIMER;
1975 qp->qplib_qp.min_rnr_timer = qp_attr->min_rnr_timer;
1976 }
1977 if (qp_attr_mask & IB_QP_RQ_PSN) {
1978 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_RQ_PSN;
1979 qp->qplib_qp.rq.psn = qp_attr->rq_psn;
1980 }
1981 if (qp_attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1982 qp->qplib_qp.modify_flags |=
1983 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_RD_ATOMIC;
1984 /* Cap the max_rd_atomic to device max */
1985 qp->qplib_qp.max_rd_atomic = min_t(u32, qp_attr->max_rd_atomic,
1986 dev_attr->max_qp_rd_atom);
1987 }
1988 if (qp_attr_mask & IB_QP_SQ_PSN) {
1989 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN;
1990 qp->qplib_qp.sq.psn = qp_attr->sq_psn;
1991 }
1992 if (qp_attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1993 if (qp_attr->max_dest_rd_atomic >
1994 dev_attr->max_qp_init_rd_atom) {
1995 ibdev_err(&rdev->ibdev,
1996 "max_dest_rd_atomic requested%d is > dev_max%d",
1997 qp_attr->max_dest_rd_atomic,
1998 dev_attr->max_qp_init_rd_atom);
1999 return -EINVAL;
2000 }
2001
2002 qp->qplib_qp.modify_flags |=
2003 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_DEST_RD_ATOMIC;
2004 qp->qplib_qp.max_dest_rd_atomic = qp_attr->max_dest_rd_atomic;
2005 }
2006 if (qp_attr_mask & IB_QP_CAP) {
2007 qp->qplib_qp.modify_flags |=
2008 CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SIZE |
2009 CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SIZE |
2010 CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SGE |
2011 CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SGE |
2012 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_INLINE_DATA;
2013 if ((qp_attr->cap.max_send_wr >= dev_attr->max_qp_wqes) ||
2014 (qp_attr->cap.max_recv_wr >= dev_attr->max_qp_wqes) ||
2015 (qp_attr->cap.max_send_sge >= dev_attr->max_qp_sges) ||
2016 (qp_attr->cap.max_recv_sge >= dev_attr->max_qp_sges) ||
2017 (qp_attr->cap.max_inline_data >=
2018 dev_attr->max_inline_data)) {
2019 ibdev_err(&rdev->ibdev,
2020 "Create QP failed - max exceeded");
2021 return -EINVAL;
2022 }
2023 entries = roundup_pow_of_two(qp_attr->cap.max_send_wr);
2024 qp->qplib_qp.sq.max_wqe = min_t(u32, entries,
2025 dev_attr->max_qp_wqes + 1);
2026 qp->qplib_qp.sq.q_full_delta = qp->qplib_qp.sq.max_wqe -
2027 qp_attr->cap.max_send_wr;
2028 /*
2029 * Reserving one slot for Phantom WQE. Some application can
2030 * post one extra entry in this case. Allowing this to avoid
2031 * unexpected Queue full condition
2032 */
2033 qp->qplib_qp.sq.q_full_delta -= 1;
2034 qp->qplib_qp.sq.max_sge = qp_attr->cap.max_send_sge;
2035 if (qp->qplib_qp.rq.max_wqe) {
2036 entries = roundup_pow_of_two(qp_attr->cap.max_recv_wr);
2037 qp->qplib_qp.rq.max_wqe =
2038 min_t(u32, entries, dev_attr->max_qp_wqes + 1);
2039 qp->qplib_qp.rq.q_full_delta = qp->qplib_qp.rq.max_wqe -
2040 qp_attr->cap.max_recv_wr;
2041 qp->qplib_qp.rq.max_sge = qp_attr->cap.max_recv_sge;
2042 } else {
2043 /* SRQ was used prior, just ignore the RQ caps */
2044 }
2045 }
2046 if (qp_attr_mask & IB_QP_DEST_QPN) {
2047 qp->qplib_qp.modify_flags |=
2048 CMDQ_MODIFY_QP_MODIFY_MASK_DEST_QP_ID;
2049 qp->qplib_qp.dest_qpn = qp_attr->dest_qp_num;
2050 }
2051 rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp);
2052 if (rc) {
2053 ibdev_err(&rdev->ibdev, "Failed to modify HW QP");
2054 return rc;
2055 }
2056 if (ib_qp->qp_type == IB_QPT_GSI && rdev->gsi_ctx.gsi_sqp)
2057 rc = bnxt_re_modify_shadow_qp(rdev, qp, qp_attr_mask);
2058 return rc;
2059 }
2060
bnxt_re_query_qp(struct ib_qp * ib_qp,struct ib_qp_attr * qp_attr,int qp_attr_mask,struct ib_qp_init_attr * qp_init_attr)2061 int bnxt_re_query_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr,
2062 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
2063 {
2064 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
2065 struct bnxt_re_dev *rdev = qp->rdev;
2066 struct bnxt_qplib_qp *qplib_qp;
2067 int rc;
2068
2069 qplib_qp = kzalloc(sizeof(*qplib_qp), GFP_KERNEL);
2070 if (!qplib_qp)
2071 return -ENOMEM;
2072
2073 qplib_qp->id = qp->qplib_qp.id;
2074 qplib_qp->ah.host_sgid_index = qp->qplib_qp.ah.host_sgid_index;
2075
2076 rc = bnxt_qplib_query_qp(&rdev->qplib_res, qplib_qp);
2077 if (rc) {
2078 ibdev_err(&rdev->ibdev, "Failed to query HW QP");
2079 goto out;
2080 }
2081 qp_attr->qp_state = __to_ib_qp_state(qplib_qp->state);
2082 qp_attr->cur_qp_state = __to_ib_qp_state(qplib_qp->cur_qp_state);
2083 qp_attr->en_sqd_async_notify = qplib_qp->en_sqd_async_notify ? 1 : 0;
2084 qp_attr->qp_access_flags = __to_ib_access_flags(qplib_qp->access);
2085 qp_attr->pkey_index = qplib_qp->pkey_index;
2086 qp_attr->qkey = qplib_qp->qkey;
2087 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
2088 rdma_ah_set_grh(&qp_attr->ah_attr, NULL, qplib_qp->ah.flow_label,
2089 qplib_qp->ah.host_sgid_index,
2090 qplib_qp->ah.hop_limit,
2091 qplib_qp->ah.traffic_class);
2092 rdma_ah_set_dgid_raw(&qp_attr->ah_attr, qplib_qp->ah.dgid.data);
2093 rdma_ah_set_sl(&qp_attr->ah_attr, qplib_qp->ah.sl);
2094 ether_addr_copy(qp_attr->ah_attr.roce.dmac, qplib_qp->ah.dmac);
2095 qp_attr->path_mtu = __to_ib_mtu(qplib_qp->path_mtu);
2096 qp_attr->timeout = qplib_qp->timeout;
2097 qp_attr->retry_cnt = qplib_qp->retry_cnt;
2098 qp_attr->rnr_retry = qplib_qp->rnr_retry;
2099 qp_attr->min_rnr_timer = qplib_qp->min_rnr_timer;
2100 qp_attr->rq_psn = qplib_qp->rq.psn;
2101 qp_attr->max_rd_atomic = qplib_qp->max_rd_atomic;
2102 qp_attr->sq_psn = qplib_qp->sq.psn;
2103 qp_attr->max_dest_rd_atomic = qplib_qp->max_dest_rd_atomic;
2104 qp_init_attr->sq_sig_type = qplib_qp->sig_type ? IB_SIGNAL_ALL_WR :
2105 IB_SIGNAL_REQ_WR;
2106 qp_attr->dest_qp_num = qplib_qp->dest_qpn;
2107
2108 qp_attr->cap.max_send_wr = qp->qplib_qp.sq.max_wqe;
2109 qp_attr->cap.max_send_sge = qp->qplib_qp.sq.max_sge;
2110 qp_attr->cap.max_recv_wr = qp->qplib_qp.rq.max_wqe;
2111 qp_attr->cap.max_recv_sge = qp->qplib_qp.rq.max_sge;
2112 qp_attr->cap.max_inline_data = qp->qplib_qp.max_inline_data;
2113 qp_init_attr->cap = qp_attr->cap;
2114
2115 out:
2116 kfree(qplib_qp);
2117 return rc;
2118 }
2119
2120 /* Routine for sending QP1 packets for RoCE V1 an V2
2121 */
bnxt_re_build_qp1_send_v2(struct bnxt_re_qp * qp,const struct ib_send_wr * wr,struct bnxt_qplib_swqe * wqe,int payload_size)2122 static int bnxt_re_build_qp1_send_v2(struct bnxt_re_qp *qp,
2123 const struct ib_send_wr *wr,
2124 struct bnxt_qplib_swqe *wqe,
2125 int payload_size)
2126 {
2127 struct bnxt_re_ah *ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah,
2128 ib_ah);
2129 struct bnxt_qplib_ah *qplib_ah = &ah->qplib_ah;
2130 const struct ib_gid_attr *sgid_attr = ah->ib_ah.sgid_attr;
2131 struct bnxt_qplib_sge sge;
2132 u8 nw_type;
2133 u16 ether_type;
2134 union ib_gid dgid;
2135 bool is_eth = false;
2136 bool is_vlan = false;
2137 bool is_grh = false;
2138 bool is_udp = false;
2139 u8 ip_version = 0;
2140 u16 vlan_id = 0xFFFF;
2141 void *buf;
2142 int i, rc = 0;
2143
2144 memset(&qp->qp1_hdr, 0, sizeof(qp->qp1_hdr));
2145
2146 rc = rdma_read_gid_l2_fields(sgid_attr, &vlan_id, NULL);
2147 if (rc)
2148 return rc;
2149
2150 /* Get network header type for this GID */
2151 nw_type = rdma_gid_attr_network_type(sgid_attr);
2152 switch (nw_type) {
2153 case RDMA_NETWORK_IPV4:
2154 nw_type = BNXT_RE_ROCEV2_IPV4_PACKET;
2155 break;
2156 case RDMA_NETWORK_IPV6:
2157 nw_type = BNXT_RE_ROCEV2_IPV6_PACKET;
2158 break;
2159 default:
2160 nw_type = BNXT_RE_ROCE_V1_PACKET;
2161 break;
2162 }
2163 memcpy(&dgid.raw, &qplib_ah->dgid, 16);
2164 is_udp = sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP;
2165 if (is_udp) {
2166 if (ipv6_addr_v4mapped((struct in6_addr *)&sgid_attr->gid)) {
2167 ip_version = 4;
2168 ether_type = ETH_P_IP;
2169 } else {
2170 ip_version = 6;
2171 ether_type = ETH_P_IPV6;
2172 }
2173 is_grh = false;
2174 } else {
2175 ether_type = ETH_P_IBOE;
2176 is_grh = true;
2177 }
2178
2179 is_eth = true;
2180 is_vlan = (vlan_id && (vlan_id < 0x1000)) ? true : false;
2181
2182 ib_ud_header_init(payload_size, !is_eth, is_eth, is_vlan, is_grh,
2183 ip_version, is_udp, 0, &qp->qp1_hdr);
2184
2185 /* ETH */
2186 ether_addr_copy(qp->qp1_hdr.eth.dmac_h, ah->qplib_ah.dmac);
2187 ether_addr_copy(qp->qp1_hdr.eth.smac_h, qp->qplib_qp.smac);
2188
2189 /* For vlan, check the sgid for vlan existence */
2190
2191 if (!is_vlan) {
2192 qp->qp1_hdr.eth.type = cpu_to_be16(ether_type);
2193 } else {
2194 qp->qp1_hdr.vlan.type = cpu_to_be16(ether_type);
2195 qp->qp1_hdr.vlan.tag = cpu_to_be16(vlan_id);
2196 }
2197
2198 if (is_grh || (ip_version == 6)) {
2199 memcpy(qp->qp1_hdr.grh.source_gid.raw, sgid_attr->gid.raw,
2200 sizeof(sgid_attr->gid));
2201 memcpy(qp->qp1_hdr.grh.destination_gid.raw, qplib_ah->dgid.data,
2202 sizeof(sgid_attr->gid));
2203 qp->qp1_hdr.grh.hop_limit = qplib_ah->hop_limit;
2204 }
2205
2206 if (ip_version == 4) {
2207 qp->qp1_hdr.ip4.tos = 0;
2208 qp->qp1_hdr.ip4.id = 0;
2209 qp->qp1_hdr.ip4.frag_off = htons(IP_DF);
2210 qp->qp1_hdr.ip4.ttl = qplib_ah->hop_limit;
2211
2212 memcpy(&qp->qp1_hdr.ip4.saddr, sgid_attr->gid.raw + 12, 4);
2213 memcpy(&qp->qp1_hdr.ip4.daddr, qplib_ah->dgid.data + 12, 4);
2214 qp->qp1_hdr.ip4.check = ib_ud_ip4_csum(&qp->qp1_hdr);
2215 }
2216
2217 if (is_udp) {
2218 qp->qp1_hdr.udp.dport = htons(ROCE_V2_UDP_DPORT);
2219 qp->qp1_hdr.udp.sport = htons(0x8CD1);
2220 qp->qp1_hdr.udp.csum = 0;
2221 }
2222
2223 /* BTH */
2224 if (wr->opcode == IB_WR_SEND_WITH_IMM) {
2225 qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
2226 qp->qp1_hdr.immediate_present = 1;
2227 } else {
2228 qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
2229 }
2230 if (wr->send_flags & IB_SEND_SOLICITED)
2231 qp->qp1_hdr.bth.solicited_event = 1;
2232 /* pad_count */
2233 qp->qp1_hdr.bth.pad_count = (4 - payload_size) & 3;
2234
2235 /* P_key for QP1 is for all members */
2236 qp->qp1_hdr.bth.pkey = cpu_to_be16(0xFFFF);
2237 qp->qp1_hdr.bth.destination_qpn = IB_QP1;
2238 qp->qp1_hdr.bth.ack_req = 0;
2239 qp->send_psn++;
2240 qp->send_psn &= BTH_PSN_MASK;
2241 qp->qp1_hdr.bth.psn = cpu_to_be32(qp->send_psn);
2242 /* DETH */
2243 /* Use the priviledged Q_Key for QP1 */
2244 qp->qp1_hdr.deth.qkey = cpu_to_be32(IB_QP1_QKEY);
2245 qp->qp1_hdr.deth.source_qpn = IB_QP1;
2246
2247 /* Pack the QP1 to the transmit buffer */
2248 buf = bnxt_qplib_get_qp1_sq_buf(&qp->qplib_qp, &sge);
2249 if (buf) {
2250 ib_ud_header_pack(&qp->qp1_hdr, buf);
2251 for (i = wqe->num_sge; i; i--) {
2252 wqe->sg_list[i].addr = wqe->sg_list[i - 1].addr;
2253 wqe->sg_list[i].lkey = wqe->sg_list[i - 1].lkey;
2254 wqe->sg_list[i].size = wqe->sg_list[i - 1].size;
2255 }
2256
2257 /*
2258 * Max Header buf size for IPV6 RoCE V2 is 86,
2259 * which is same as the QP1 SQ header buffer.
2260 * Header buf size for IPV4 RoCE V2 can be 66.
2261 * ETH(14) + VLAN(4)+ IP(20) + UDP (8) + BTH(20).
2262 * Subtract 20 bytes from QP1 SQ header buf size
2263 */
2264 if (is_udp && ip_version == 4)
2265 sge.size -= 20;
2266 /*
2267 * Max Header buf size for RoCE V1 is 78.
2268 * ETH(14) + VLAN(4) + GRH(40) + BTH(20).
2269 * Subtract 8 bytes from QP1 SQ header buf size
2270 */
2271 if (!is_udp)
2272 sge.size -= 8;
2273
2274 /* Subtract 4 bytes for non vlan packets */
2275 if (!is_vlan)
2276 sge.size -= 4;
2277
2278 wqe->sg_list[0].addr = sge.addr;
2279 wqe->sg_list[0].lkey = sge.lkey;
2280 wqe->sg_list[0].size = sge.size;
2281 wqe->num_sge++;
2282
2283 } else {
2284 ibdev_err(&qp->rdev->ibdev, "QP1 buffer is empty!");
2285 rc = -ENOMEM;
2286 }
2287 return rc;
2288 }
2289
2290 /* For the MAD layer, it only provides the recv SGE the size of
2291 * ib_grh + MAD datagram. No Ethernet headers, Ethertype, BTH, DETH,
2292 * nor RoCE iCRC. The Cu+ solution must provide buffer for the entire
2293 * receive packet (334 bytes) with no VLAN and then copy the GRH
2294 * and the MAD datagram out to the provided SGE.
2295 */
bnxt_re_build_qp1_shadow_qp_recv(struct bnxt_re_qp * qp,const struct ib_recv_wr * wr,struct bnxt_qplib_swqe * wqe,int payload_size)2296 static int bnxt_re_build_qp1_shadow_qp_recv(struct bnxt_re_qp *qp,
2297 const struct ib_recv_wr *wr,
2298 struct bnxt_qplib_swqe *wqe,
2299 int payload_size)
2300 {
2301 struct bnxt_re_sqp_entries *sqp_entry;
2302 struct bnxt_qplib_sge ref, sge;
2303 struct bnxt_re_dev *rdev;
2304 u32 rq_prod_index;
2305
2306 rdev = qp->rdev;
2307
2308 rq_prod_index = bnxt_qplib_get_rq_prod_index(&qp->qplib_qp);
2309
2310 if (!bnxt_qplib_get_qp1_rq_buf(&qp->qplib_qp, &sge))
2311 return -ENOMEM;
2312
2313 /* Create 1 SGE to receive the entire
2314 * ethernet packet
2315 */
2316 /* Save the reference from ULP */
2317 ref.addr = wqe->sg_list[0].addr;
2318 ref.lkey = wqe->sg_list[0].lkey;
2319 ref.size = wqe->sg_list[0].size;
2320
2321 sqp_entry = &rdev->gsi_ctx.sqp_tbl[rq_prod_index];
2322
2323 /* SGE 1 */
2324 wqe->sg_list[0].addr = sge.addr;
2325 wqe->sg_list[0].lkey = sge.lkey;
2326 wqe->sg_list[0].size = BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2;
2327 sge.size -= wqe->sg_list[0].size;
2328
2329 sqp_entry->sge.addr = ref.addr;
2330 sqp_entry->sge.lkey = ref.lkey;
2331 sqp_entry->sge.size = ref.size;
2332 /* Store the wrid for reporting completion */
2333 sqp_entry->wrid = wqe->wr_id;
2334 /* change the wqe->wrid to table index */
2335 wqe->wr_id = rq_prod_index;
2336 return 0;
2337 }
2338
is_ud_qp(struct bnxt_re_qp * qp)2339 static int is_ud_qp(struct bnxt_re_qp *qp)
2340 {
2341 return (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_UD ||
2342 qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_GSI);
2343 }
2344
bnxt_re_build_send_wqe(struct bnxt_re_qp * qp,const struct ib_send_wr * wr,struct bnxt_qplib_swqe * wqe)2345 static int bnxt_re_build_send_wqe(struct bnxt_re_qp *qp,
2346 const struct ib_send_wr *wr,
2347 struct bnxt_qplib_swqe *wqe)
2348 {
2349 struct bnxt_re_ah *ah = NULL;
2350
2351 if (is_ud_qp(qp)) {
2352 ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah, ib_ah);
2353 wqe->send.q_key = ud_wr(wr)->remote_qkey;
2354 wqe->send.dst_qp = ud_wr(wr)->remote_qpn;
2355 wqe->send.avid = ah->qplib_ah.id;
2356 }
2357 switch (wr->opcode) {
2358 case IB_WR_SEND:
2359 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND;
2360 break;
2361 case IB_WR_SEND_WITH_IMM:
2362 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM;
2363 wqe->send.imm_data = wr->ex.imm_data;
2364 break;
2365 case IB_WR_SEND_WITH_INV:
2366 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV;
2367 wqe->send.inv_key = wr->ex.invalidate_rkey;
2368 break;
2369 default:
2370 return -EINVAL;
2371 }
2372 if (wr->send_flags & IB_SEND_SIGNALED)
2373 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2374 if (wr->send_flags & IB_SEND_FENCE)
2375 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2376 if (wr->send_flags & IB_SEND_SOLICITED)
2377 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
2378 if (wr->send_flags & IB_SEND_INLINE)
2379 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE;
2380
2381 return 0;
2382 }
2383
bnxt_re_build_rdma_wqe(const struct ib_send_wr * wr,struct bnxt_qplib_swqe * wqe)2384 static int bnxt_re_build_rdma_wqe(const struct ib_send_wr *wr,
2385 struct bnxt_qplib_swqe *wqe)
2386 {
2387 switch (wr->opcode) {
2388 case IB_WR_RDMA_WRITE:
2389 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE;
2390 break;
2391 case IB_WR_RDMA_WRITE_WITH_IMM:
2392 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM;
2393 wqe->rdma.imm_data = wr->ex.imm_data;
2394 break;
2395 case IB_WR_RDMA_READ:
2396 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_READ;
2397 wqe->rdma.inv_key = wr->ex.invalidate_rkey;
2398 break;
2399 default:
2400 return -EINVAL;
2401 }
2402 wqe->rdma.remote_va = rdma_wr(wr)->remote_addr;
2403 wqe->rdma.r_key = rdma_wr(wr)->rkey;
2404 if (wr->send_flags & IB_SEND_SIGNALED)
2405 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2406 if (wr->send_flags & IB_SEND_FENCE)
2407 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2408 if (wr->send_flags & IB_SEND_SOLICITED)
2409 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
2410 if (wr->send_flags & IB_SEND_INLINE)
2411 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE;
2412
2413 return 0;
2414 }
2415
bnxt_re_build_atomic_wqe(const struct ib_send_wr * wr,struct bnxt_qplib_swqe * wqe)2416 static int bnxt_re_build_atomic_wqe(const struct ib_send_wr *wr,
2417 struct bnxt_qplib_swqe *wqe)
2418 {
2419 switch (wr->opcode) {
2420 case IB_WR_ATOMIC_CMP_AND_SWP:
2421 wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP;
2422 wqe->atomic.cmp_data = atomic_wr(wr)->compare_add;
2423 wqe->atomic.swap_data = atomic_wr(wr)->swap;
2424 break;
2425 case IB_WR_ATOMIC_FETCH_AND_ADD:
2426 wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD;
2427 wqe->atomic.cmp_data = atomic_wr(wr)->compare_add;
2428 break;
2429 default:
2430 return -EINVAL;
2431 }
2432 wqe->atomic.remote_va = atomic_wr(wr)->remote_addr;
2433 wqe->atomic.r_key = atomic_wr(wr)->rkey;
2434 if (wr->send_flags & IB_SEND_SIGNALED)
2435 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2436 if (wr->send_flags & IB_SEND_FENCE)
2437 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2438 if (wr->send_flags & IB_SEND_SOLICITED)
2439 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
2440 return 0;
2441 }
2442
bnxt_re_build_inv_wqe(const struct ib_send_wr * wr,struct bnxt_qplib_swqe * wqe)2443 static int bnxt_re_build_inv_wqe(const struct ib_send_wr *wr,
2444 struct bnxt_qplib_swqe *wqe)
2445 {
2446 wqe->type = BNXT_QPLIB_SWQE_TYPE_LOCAL_INV;
2447 wqe->local_inv.inv_l_key = wr->ex.invalidate_rkey;
2448
2449 /* Need unconditional fence for local invalidate
2450 * opcode to work as expected.
2451 */
2452 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2453
2454 if (wr->send_flags & IB_SEND_SIGNALED)
2455 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2456 if (wr->send_flags & IB_SEND_SOLICITED)
2457 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
2458
2459 return 0;
2460 }
2461
bnxt_re_build_reg_wqe(const struct ib_reg_wr * wr,struct bnxt_qplib_swqe * wqe)2462 static int bnxt_re_build_reg_wqe(const struct ib_reg_wr *wr,
2463 struct bnxt_qplib_swqe *wqe)
2464 {
2465 struct bnxt_re_mr *mr = container_of(wr->mr, struct bnxt_re_mr, ib_mr);
2466 struct bnxt_qplib_frpl *qplib_frpl = &mr->qplib_frpl;
2467 int access = wr->access;
2468
2469 wqe->frmr.pbl_ptr = (__le64 *)qplib_frpl->hwq.pbl_ptr[0];
2470 wqe->frmr.pbl_dma_ptr = qplib_frpl->hwq.pbl_dma_ptr[0];
2471 wqe->frmr.page_list = mr->pages;
2472 wqe->frmr.page_list_len = mr->npages;
2473 wqe->frmr.levels = qplib_frpl->hwq.level;
2474 wqe->type = BNXT_QPLIB_SWQE_TYPE_REG_MR;
2475
2476 /* Need unconditional fence for reg_mr
2477 * opcode to function as expected.
2478 */
2479
2480 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2481
2482 if (wr->wr.send_flags & IB_SEND_SIGNALED)
2483 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2484
2485 if (access & IB_ACCESS_LOCAL_WRITE)
2486 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_LOCAL_WRITE;
2487 if (access & IB_ACCESS_REMOTE_READ)
2488 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_READ;
2489 if (access & IB_ACCESS_REMOTE_WRITE)
2490 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_WRITE;
2491 if (access & IB_ACCESS_REMOTE_ATOMIC)
2492 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_ATOMIC;
2493 if (access & IB_ACCESS_MW_BIND)
2494 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_WINDOW_BIND;
2495
2496 wqe->frmr.l_key = wr->key;
2497 wqe->frmr.length = wr->mr->length;
2498 wqe->frmr.pbl_pg_sz_log = (wr->mr->page_size >> PAGE_SHIFT_4K) - 1;
2499 wqe->frmr.va = wr->mr->iova;
2500 return 0;
2501 }
2502
bnxt_re_copy_inline_data(struct bnxt_re_dev * rdev,const struct ib_send_wr * wr,struct bnxt_qplib_swqe * wqe)2503 static int bnxt_re_copy_inline_data(struct bnxt_re_dev *rdev,
2504 const struct ib_send_wr *wr,
2505 struct bnxt_qplib_swqe *wqe)
2506 {
2507 /* Copy the inline data to the data field */
2508 u8 *in_data;
2509 u32 i, sge_len;
2510 void *sge_addr;
2511
2512 in_data = wqe->inline_data;
2513 for (i = 0; i < wr->num_sge; i++) {
2514 sge_addr = (void *)(unsigned long)
2515 wr->sg_list[i].addr;
2516 sge_len = wr->sg_list[i].length;
2517
2518 if ((sge_len + wqe->inline_len) >
2519 BNXT_QPLIB_SWQE_MAX_INLINE_LENGTH) {
2520 ibdev_err(&rdev->ibdev,
2521 "Inline data size requested > supported value");
2522 return -EINVAL;
2523 }
2524 sge_len = wr->sg_list[i].length;
2525
2526 memcpy(in_data, sge_addr, sge_len);
2527 in_data += wr->sg_list[i].length;
2528 wqe->inline_len += wr->sg_list[i].length;
2529 }
2530 return wqe->inline_len;
2531 }
2532
bnxt_re_copy_wr_payload(struct bnxt_re_dev * rdev,const struct ib_send_wr * wr,struct bnxt_qplib_swqe * wqe)2533 static int bnxt_re_copy_wr_payload(struct bnxt_re_dev *rdev,
2534 const struct ib_send_wr *wr,
2535 struct bnxt_qplib_swqe *wqe)
2536 {
2537 int payload_sz = 0;
2538
2539 if (wr->send_flags & IB_SEND_INLINE)
2540 payload_sz = bnxt_re_copy_inline_data(rdev, wr, wqe);
2541 else
2542 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe->sg_list,
2543 wqe->num_sge);
2544
2545 return payload_sz;
2546 }
2547
bnxt_ud_qp_hw_stall_workaround(struct bnxt_re_qp * qp)2548 static void bnxt_ud_qp_hw_stall_workaround(struct bnxt_re_qp *qp)
2549 {
2550 if ((qp->ib_qp.qp_type == IB_QPT_UD ||
2551 qp->ib_qp.qp_type == IB_QPT_GSI ||
2552 qp->ib_qp.qp_type == IB_QPT_RAW_ETHERTYPE) &&
2553 qp->qplib_qp.wqe_cnt == BNXT_RE_UD_QP_HW_STALL) {
2554 int qp_attr_mask;
2555 struct ib_qp_attr qp_attr;
2556
2557 qp_attr_mask = IB_QP_STATE;
2558 qp_attr.qp_state = IB_QPS_RTS;
2559 bnxt_re_modify_qp(&qp->ib_qp, &qp_attr, qp_attr_mask, NULL);
2560 qp->qplib_qp.wqe_cnt = 0;
2561 }
2562 }
2563
bnxt_re_post_send_shadow_qp(struct bnxt_re_dev * rdev,struct bnxt_re_qp * qp,const struct ib_send_wr * wr)2564 static int bnxt_re_post_send_shadow_qp(struct bnxt_re_dev *rdev,
2565 struct bnxt_re_qp *qp,
2566 const struct ib_send_wr *wr)
2567 {
2568 int rc = 0, payload_sz = 0;
2569 unsigned long flags;
2570
2571 spin_lock_irqsave(&qp->sq_lock, flags);
2572 while (wr) {
2573 struct bnxt_qplib_swqe wqe = {};
2574
2575 /* Common */
2576 wqe.num_sge = wr->num_sge;
2577 if (wr->num_sge > qp->qplib_qp.sq.max_sge) {
2578 ibdev_err(&rdev->ibdev,
2579 "Limit exceeded for Send SGEs");
2580 rc = -EINVAL;
2581 goto bad;
2582 }
2583
2584 payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe);
2585 if (payload_sz < 0) {
2586 rc = -EINVAL;
2587 goto bad;
2588 }
2589 wqe.wr_id = wr->wr_id;
2590
2591 wqe.type = BNXT_QPLIB_SWQE_TYPE_SEND;
2592
2593 rc = bnxt_re_build_send_wqe(qp, wr, &wqe);
2594 if (!rc)
2595 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe);
2596 bad:
2597 if (rc) {
2598 ibdev_err(&rdev->ibdev,
2599 "Post send failed opcode = %#x rc = %d",
2600 wr->opcode, rc);
2601 break;
2602 }
2603 wr = wr->next;
2604 }
2605 bnxt_qplib_post_send_db(&qp->qplib_qp);
2606 bnxt_ud_qp_hw_stall_workaround(qp);
2607 spin_unlock_irqrestore(&qp->sq_lock, flags);
2608 return rc;
2609 }
2610
bnxt_re_post_send(struct ib_qp * ib_qp,const struct ib_send_wr * wr,const struct ib_send_wr ** bad_wr)2611 int bnxt_re_post_send(struct ib_qp *ib_qp, const struct ib_send_wr *wr,
2612 const struct ib_send_wr **bad_wr)
2613 {
2614 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
2615 struct bnxt_qplib_swqe wqe;
2616 int rc = 0, payload_sz = 0;
2617 unsigned long flags;
2618
2619 spin_lock_irqsave(&qp->sq_lock, flags);
2620 while (wr) {
2621 /* House keeping */
2622 memset(&wqe, 0, sizeof(wqe));
2623
2624 /* Common */
2625 wqe.num_sge = wr->num_sge;
2626 if (wr->num_sge > qp->qplib_qp.sq.max_sge) {
2627 ibdev_err(&qp->rdev->ibdev,
2628 "Limit exceeded for Send SGEs");
2629 rc = -EINVAL;
2630 goto bad;
2631 }
2632
2633 payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe);
2634 if (payload_sz < 0) {
2635 rc = -EINVAL;
2636 goto bad;
2637 }
2638 wqe.wr_id = wr->wr_id;
2639
2640 switch (wr->opcode) {
2641 case IB_WR_SEND:
2642 case IB_WR_SEND_WITH_IMM:
2643 if (qp->qplib_qp.type == CMDQ_CREATE_QP1_TYPE_GSI) {
2644 rc = bnxt_re_build_qp1_send_v2(qp, wr, &wqe,
2645 payload_sz);
2646 if (rc)
2647 goto bad;
2648 wqe.rawqp1.lflags |=
2649 SQ_SEND_RAWETH_QP1_LFLAGS_ROCE_CRC;
2650 }
2651 switch (wr->send_flags) {
2652 case IB_SEND_IP_CSUM:
2653 wqe.rawqp1.lflags |=
2654 SQ_SEND_RAWETH_QP1_LFLAGS_IP_CHKSUM;
2655 break;
2656 default:
2657 break;
2658 }
2659 fallthrough;
2660 case IB_WR_SEND_WITH_INV:
2661 rc = bnxt_re_build_send_wqe(qp, wr, &wqe);
2662 break;
2663 case IB_WR_RDMA_WRITE:
2664 case IB_WR_RDMA_WRITE_WITH_IMM:
2665 case IB_WR_RDMA_READ:
2666 rc = bnxt_re_build_rdma_wqe(wr, &wqe);
2667 break;
2668 case IB_WR_ATOMIC_CMP_AND_SWP:
2669 case IB_WR_ATOMIC_FETCH_AND_ADD:
2670 rc = bnxt_re_build_atomic_wqe(wr, &wqe);
2671 break;
2672 case IB_WR_RDMA_READ_WITH_INV:
2673 ibdev_err(&qp->rdev->ibdev,
2674 "RDMA Read with Invalidate is not supported");
2675 rc = -EINVAL;
2676 goto bad;
2677 case IB_WR_LOCAL_INV:
2678 rc = bnxt_re_build_inv_wqe(wr, &wqe);
2679 break;
2680 case IB_WR_REG_MR:
2681 rc = bnxt_re_build_reg_wqe(reg_wr(wr), &wqe);
2682 break;
2683 default:
2684 /* Unsupported WRs */
2685 ibdev_err(&qp->rdev->ibdev,
2686 "WR (%#x) is not supported", wr->opcode);
2687 rc = -EINVAL;
2688 goto bad;
2689 }
2690 if (!rc)
2691 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe);
2692 bad:
2693 if (rc) {
2694 ibdev_err(&qp->rdev->ibdev,
2695 "post_send failed op:%#x qps = %#x rc = %d\n",
2696 wr->opcode, qp->qplib_qp.state, rc);
2697 *bad_wr = wr;
2698 break;
2699 }
2700 wr = wr->next;
2701 }
2702 bnxt_qplib_post_send_db(&qp->qplib_qp);
2703 bnxt_ud_qp_hw_stall_workaround(qp);
2704 spin_unlock_irqrestore(&qp->sq_lock, flags);
2705
2706 return rc;
2707 }
2708
bnxt_re_post_recv_shadow_qp(struct bnxt_re_dev * rdev,struct bnxt_re_qp * qp,const struct ib_recv_wr * wr)2709 static int bnxt_re_post_recv_shadow_qp(struct bnxt_re_dev *rdev,
2710 struct bnxt_re_qp *qp,
2711 const struct ib_recv_wr *wr)
2712 {
2713 struct bnxt_qplib_swqe wqe;
2714 int rc = 0;
2715
2716 memset(&wqe, 0, sizeof(wqe));
2717 while (wr) {
2718 /* House keeping */
2719 memset(&wqe, 0, sizeof(wqe));
2720
2721 /* Common */
2722 wqe.num_sge = wr->num_sge;
2723 if (wr->num_sge > qp->qplib_qp.rq.max_sge) {
2724 ibdev_err(&rdev->ibdev,
2725 "Limit exceeded for Receive SGEs");
2726 rc = -EINVAL;
2727 break;
2728 }
2729 bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, wr->num_sge);
2730 wqe.wr_id = wr->wr_id;
2731 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV;
2732
2733 rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe);
2734 if (rc)
2735 break;
2736
2737 wr = wr->next;
2738 }
2739 if (!rc)
2740 bnxt_qplib_post_recv_db(&qp->qplib_qp);
2741 return rc;
2742 }
2743
bnxt_re_post_recv(struct ib_qp * ib_qp,const struct ib_recv_wr * wr,const struct ib_recv_wr ** bad_wr)2744 int bnxt_re_post_recv(struct ib_qp *ib_qp, const struct ib_recv_wr *wr,
2745 const struct ib_recv_wr **bad_wr)
2746 {
2747 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
2748 struct bnxt_qplib_swqe wqe;
2749 int rc = 0, payload_sz = 0;
2750 unsigned long flags;
2751 u32 count = 0;
2752
2753 spin_lock_irqsave(&qp->rq_lock, flags);
2754 while (wr) {
2755 /* House keeping */
2756 memset(&wqe, 0, sizeof(wqe));
2757
2758 /* Common */
2759 wqe.num_sge = wr->num_sge;
2760 if (wr->num_sge > qp->qplib_qp.rq.max_sge) {
2761 ibdev_err(&qp->rdev->ibdev,
2762 "Limit exceeded for Receive SGEs");
2763 rc = -EINVAL;
2764 *bad_wr = wr;
2765 break;
2766 }
2767
2768 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe.sg_list,
2769 wr->num_sge);
2770 wqe.wr_id = wr->wr_id;
2771 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV;
2772
2773 if (ib_qp->qp_type == IB_QPT_GSI &&
2774 qp->qplib_qp.type != CMDQ_CREATE_QP_TYPE_GSI)
2775 rc = bnxt_re_build_qp1_shadow_qp_recv(qp, wr, &wqe,
2776 payload_sz);
2777 if (!rc)
2778 rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe);
2779 if (rc) {
2780 *bad_wr = wr;
2781 break;
2782 }
2783
2784 /* Ring DB if the RQEs posted reaches a threshold value */
2785 if (++count >= BNXT_RE_RQ_WQE_THRESHOLD) {
2786 bnxt_qplib_post_recv_db(&qp->qplib_qp);
2787 count = 0;
2788 }
2789
2790 wr = wr->next;
2791 }
2792
2793 if (count)
2794 bnxt_qplib_post_recv_db(&qp->qplib_qp);
2795
2796 spin_unlock_irqrestore(&qp->rq_lock, flags);
2797
2798 return rc;
2799 }
2800
2801 /* Completion Queues */
bnxt_re_destroy_cq(struct ib_cq * ib_cq,struct ib_udata * udata)2802 int bnxt_re_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata)
2803 {
2804 struct bnxt_re_cq *cq;
2805 struct bnxt_qplib_nq *nq;
2806 struct bnxt_re_dev *rdev;
2807
2808 cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
2809 rdev = cq->rdev;
2810 nq = cq->qplib_cq.nq;
2811
2812 bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq);
2813 ib_umem_release(cq->umem);
2814
2815 atomic_dec(&rdev->cq_count);
2816 nq->budget--;
2817 kfree(cq->cql);
2818 return 0;
2819 }
2820
bnxt_re_create_cq(struct ib_cq * ibcq,const struct ib_cq_init_attr * attr,struct ib_udata * udata)2821 int bnxt_re_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,
2822 struct ib_udata *udata)
2823 {
2824 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibcq->device, ibdev);
2825 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
2826 struct bnxt_re_cq *cq = container_of(ibcq, struct bnxt_re_cq, ib_cq);
2827 int rc, entries;
2828 int cqe = attr->cqe;
2829 struct bnxt_qplib_nq *nq = NULL;
2830 unsigned int nq_alloc_cnt;
2831
2832 /* Validate CQ fields */
2833 if (cqe < 1 || cqe > dev_attr->max_cq_wqes) {
2834 ibdev_err(&rdev->ibdev, "Failed to create CQ -max exceeded");
2835 return -EINVAL;
2836 }
2837
2838 cq->rdev = rdev;
2839 cq->qplib_cq.cq_handle = (u64)(unsigned long)(&cq->qplib_cq);
2840
2841 entries = roundup_pow_of_two(cqe + 1);
2842 if (entries > dev_attr->max_cq_wqes + 1)
2843 entries = dev_attr->max_cq_wqes + 1;
2844
2845 cq->qplib_cq.sg_info.pgsize = PAGE_SIZE;
2846 cq->qplib_cq.sg_info.pgshft = PAGE_SHIFT;
2847 if (udata) {
2848 struct bnxt_re_cq_req req;
2849 struct bnxt_re_ucontext *uctx = rdma_udata_to_drv_context(
2850 udata, struct bnxt_re_ucontext, ib_uctx);
2851 if (ib_copy_from_udata(&req, udata, sizeof(req))) {
2852 rc = -EFAULT;
2853 goto fail;
2854 }
2855
2856 cq->umem = ib_umem_get(&rdev->ibdev, req.cq_va,
2857 entries * sizeof(struct cq_base),
2858 IB_ACCESS_LOCAL_WRITE);
2859 if (IS_ERR(cq->umem)) {
2860 rc = PTR_ERR(cq->umem);
2861 goto fail;
2862 }
2863 cq->qplib_cq.sg_info.umem = cq->umem;
2864 cq->qplib_cq.dpi = &uctx->dpi;
2865 } else {
2866 cq->max_cql = min_t(u32, entries, MAX_CQL_PER_POLL);
2867 cq->cql = kcalloc(cq->max_cql, sizeof(struct bnxt_qplib_cqe),
2868 GFP_KERNEL);
2869 if (!cq->cql) {
2870 rc = -ENOMEM;
2871 goto fail;
2872 }
2873
2874 cq->qplib_cq.dpi = &rdev->dpi_privileged;
2875 }
2876 /*
2877 * Allocating the NQ in a round robin fashion. nq_alloc_cnt is a
2878 * used for getting the NQ index.
2879 */
2880 nq_alloc_cnt = atomic_inc_return(&rdev->nq_alloc_cnt);
2881 nq = &rdev->nq[nq_alloc_cnt % (rdev->num_msix - 1)];
2882 cq->qplib_cq.max_wqe = entries;
2883 cq->qplib_cq.cnq_hw_ring_id = nq->ring_id;
2884 cq->qplib_cq.nq = nq;
2885
2886 rc = bnxt_qplib_create_cq(&rdev->qplib_res, &cq->qplib_cq);
2887 if (rc) {
2888 ibdev_err(&rdev->ibdev, "Failed to create HW CQ");
2889 goto fail;
2890 }
2891
2892 cq->ib_cq.cqe = entries;
2893 cq->cq_period = cq->qplib_cq.period;
2894 nq->budget++;
2895
2896 atomic_inc(&rdev->cq_count);
2897 spin_lock_init(&cq->cq_lock);
2898
2899 if (udata) {
2900 struct bnxt_re_cq_resp resp;
2901
2902 resp.cqid = cq->qplib_cq.id;
2903 resp.tail = cq->qplib_cq.hwq.cons;
2904 resp.phase = cq->qplib_cq.period;
2905 resp.rsvd = 0;
2906 rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
2907 if (rc) {
2908 ibdev_err(&rdev->ibdev, "Failed to copy CQ udata");
2909 bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq);
2910 goto c2fail;
2911 }
2912 }
2913
2914 return 0;
2915
2916 c2fail:
2917 ib_umem_release(cq->umem);
2918 fail:
2919 kfree(cq->cql);
2920 return rc;
2921 }
2922
__req_to_ib_wc_status(u8 qstatus)2923 static u8 __req_to_ib_wc_status(u8 qstatus)
2924 {
2925 switch (qstatus) {
2926 case CQ_REQ_STATUS_OK:
2927 return IB_WC_SUCCESS;
2928 case CQ_REQ_STATUS_BAD_RESPONSE_ERR:
2929 return IB_WC_BAD_RESP_ERR;
2930 case CQ_REQ_STATUS_LOCAL_LENGTH_ERR:
2931 return IB_WC_LOC_LEN_ERR;
2932 case CQ_REQ_STATUS_LOCAL_QP_OPERATION_ERR:
2933 return IB_WC_LOC_QP_OP_ERR;
2934 case CQ_REQ_STATUS_LOCAL_PROTECTION_ERR:
2935 return IB_WC_LOC_PROT_ERR;
2936 case CQ_REQ_STATUS_MEMORY_MGT_OPERATION_ERR:
2937 return IB_WC_GENERAL_ERR;
2938 case CQ_REQ_STATUS_REMOTE_INVALID_REQUEST_ERR:
2939 return IB_WC_REM_INV_REQ_ERR;
2940 case CQ_REQ_STATUS_REMOTE_ACCESS_ERR:
2941 return IB_WC_REM_ACCESS_ERR;
2942 case CQ_REQ_STATUS_REMOTE_OPERATION_ERR:
2943 return IB_WC_REM_OP_ERR;
2944 case CQ_REQ_STATUS_RNR_NAK_RETRY_CNT_ERR:
2945 return IB_WC_RNR_RETRY_EXC_ERR;
2946 case CQ_REQ_STATUS_TRANSPORT_RETRY_CNT_ERR:
2947 return IB_WC_RETRY_EXC_ERR;
2948 case CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR:
2949 return IB_WC_WR_FLUSH_ERR;
2950 default:
2951 return IB_WC_GENERAL_ERR;
2952 }
2953 return 0;
2954 }
2955
__rawqp1_to_ib_wc_status(u8 qstatus)2956 static u8 __rawqp1_to_ib_wc_status(u8 qstatus)
2957 {
2958 switch (qstatus) {
2959 case CQ_RES_RAWETH_QP1_STATUS_OK:
2960 return IB_WC_SUCCESS;
2961 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_ACCESS_ERROR:
2962 return IB_WC_LOC_ACCESS_ERR;
2963 case CQ_RES_RAWETH_QP1_STATUS_HW_LOCAL_LENGTH_ERR:
2964 return IB_WC_LOC_LEN_ERR;
2965 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_PROTECTION_ERR:
2966 return IB_WC_LOC_PROT_ERR;
2967 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_QP_OPERATION_ERR:
2968 return IB_WC_LOC_QP_OP_ERR;
2969 case CQ_RES_RAWETH_QP1_STATUS_MEMORY_MGT_OPERATION_ERR:
2970 return IB_WC_GENERAL_ERR;
2971 case CQ_RES_RAWETH_QP1_STATUS_WORK_REQUEST_FLUSHED_ERR:
2972 return IB_WC_WR_FLUSH_ERR;
2973 case CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR:
2974 return IB_WC_WR_FLUSH_ERR;
2975 default:
2976 return IB_WC_GENERAL_ERR;
2977 }
2978 }
2979
__rc_to_ib_wc_status(u8 qstatus)2980 static u8 __rc_to_ib_wc_status(u8 qstatus)
2981 {
2982 switch (qstatus) {
2983 case CQ_RES_RC_STATUS_OK:
2984 return IB_WC_SUCCESS;
2985 case CQ_RES_RC_STATUS_LOCAL_ACCESS_ERROR:
2986 return IB_WC_LOC_ACCESS_ERR;
2987 case CQ_RES_RC_STATUS_LOCAL_LENGTH_ERR:
2988 return IB_WC_LOC_LEN_ERR;
2989 case CQ_RES_RC_STATUS_LOCAL_PROTECTION_ERR:
2990 return IB_WC_LOC_PROT_ERR;
2991 case CQ_RES_RC_STATUS_LOCAL_QP_OPERATION_ERR:
2992 return IB_WC_LOC_QP_OP_ERR;
2993 case CQ_RES_RC_STATUS_MEMORY_MGT_OPERATION_ERR:
2994 return IB_WC_GENERAL_ERR;
2995 case CQ_RES_RC_STATUS_REMOTE_INVALID_REQUEST_ERR:
2996 return IB_WC_REM_INV_REQ_ERR;
2997 case CQ_RES_RC_STATUS_WORK_REQUEST_FLUSHED_ERR:
2998 return IB_WC_WR_FLUSH_ERR;
2999 case CQ_RES_RC_STATUS_HW_FLUSH_ERR:
3000 return IB_WC_WR_FLUSH_ERR;
3001 default:
3002 return IB_WC_GENERAL_ERR;
3003 }
3004 }
3005
bnxt_re_process_req_wc(struct ib_wc * wc,struct bnxt_qplib_cqe * cqe)3006 static void bnxt_re_process_req_wc(struct ib_wc *wc, struct bnxt_qplib_cqe *cqe)
3007 {
3008 switch (cqe->type) {
3009 case BNXT_QPLIB_SWQE_TYPE_SEND:
3010 wc->opcode = IB_WC_SEND;
3011 break;
3012 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM:
3013 wc->opcode = IB_WC_SEND;
3014 wc->wc_flags |= IB_WC_WITH_IMM;
3015 break;
3016 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV:
3017 wc->opcode = IB_WC_SEND;
3018 wc->wc_flags |= IB_WC_WITH_INVALIDATE;
3019 break;
3020 case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE:
3021 wc->opcode = IB_WC_RDMA_WRITE;
3022 break;
3023 case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM:
3024 wc->opcode = IB_WC_RDMA_WRITE;
3025 wc->wc_flags |= IB_WC_WITH_IMM;
3026 break;
3027 case BNXT_QPLIB_SWQE_TYPE_RDMA_READ:
3028 wc->opcode = IB_WC_RDMA_READ;
3029 break;
3030 case BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP:
3031 wc->opcode = IB_WC_COMP_SWAP;
3032 break;
3033 case BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD:
3034 wc->opcode = IB_WC_FETCH_ADD;
3035 break;
3036 case BNXT_QPLIB_SWQE_TYPE_LOCAL_INV:
3037 wc->opcode = IB_WC_LOCAL_INV;
3038 break;
3039 case BNXT_QPLIB_SWQE_TYPE_REG_MR:
3040 wc->opcode = IB_WC_REG_MR;
3041 break;
3042 default:
3043 wc->opcode = IB_WC_SEND;
3044 break;
3045 }
3046
3047 wc->status = __req_to_ib_wc_status(cqe->status);
3048 }
3049
bnxt_re_check_packet_type(u16 raweth_qp1_flags,u16 raweth_qp1_flags2)3050 static int bnxt_re_check_packet_type(u16 raweth_qp1_flags,
3051 u16 raweth_qp1_flags2)
3052 {
3053 bool is_ipv6 = false, is_ipv4 = false;
3054
3055 /* raweth_qp1_flags Bit 9-6 indicates itype */
3056 if ((raweth_qp1_flags & CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE)
3057 != CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE)
3058 return -1;
3059
3060 if (raweth_qp1_flags2 &
3061 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_CS_CALC &&
3062 raweth_qp1_flags2 &
3063 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_L4_CS_CALC) {
3064 /* raweth_qp1_flags2 Bit 8 indicates ip_type. 0-v4 1 - v6 */
3065 (raweth_qp1_flags2 &
3066 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_TYPE) ?
3067 (is_ipv6 = true) : (is_ipv4 = true);
3068 return ((is_ipv6) ?
3069 BNXT_RE_ROCEV2_IPV6_PACKET :
3070 BNXT_RE_ROCEV2_IPV4_PACKET);
3071 } else {
3072 return BNXT_RE_ROCE_V1_PACKET;
3073 }
3074 }
3075
bnxt_re_to_ib_nw_type(int nw_type)3076 static int bnxt_re_to_ib_nw_type(int nw_type)
3077 {
3078 u8 nw_hdr_type = 0xFF;
3079
3080 switch (nw_type) {
3081 case BNXT_RE_ROCE_V1_PACKET:
3082 nw_hdr_type = RDMA_NETWORK_ROCE_V1;
3083 break;
3084 case BNXT_RE_ROCEV2_IPV4_PACKET:
3085 nw_hdr_type = RDMA_NETWORK_IPV4;
3086 break;
3087 case BNXT_RE_ROCEV2_IPV6_PACKET:
3088 nw_hdr_type = RDMA_NETWORK_IPV6;
3089 break;
3090 }
3091 return nw_hdr_type;
3092 }
3093
bnxt_re_is_loopback_packet(struct bnxt_re_dev * rdev,void * rq_hdr_buf)3094 static bool bnxt_re_is_loopback_packet(struct bnxt_re_dev *rdev,
3095 void *rq_hdr_buf)
3096 {
3097 u8 *tmp_buf = NULL;
3098 struct ethhdr *eth_hdr;
3099 u16 eth_type;
3100 bool rc = false;
3101
3102 tmp_buf = (u8 *)rq_hdr_buf;
3103 /*
3104 * If dest mac is not same as I/F mac, this could be a
3105 * loopback address or multicast address, check whether
3106 * it is a loopback packet
3107 */
3108 if (!ether_addr_equal(tmp_buf, rdev->netdev->dev_addr)) {
3109 tmp_buf += 4;
3110 /* Check the ether type */
3111 eth_hdr = (struct ethhdr *)tmp_buf;
3112 eth_type = ntohs(eth_hdr->h_proto);
3113 switch (eth_type) {
3114 case ETH_P_IBOE:
3115 rc = true;
3116 break;
3117 case ETH_P_IP:
3118 case ETH_P_IPV6: {
3119 u32 len;
3120 struct udphdr *udp_hdr;
3121
3122 len = (eth_type == ETH_P_IP ? sizeof(struct iphdr) :
3123 sizeof(struct ipv6hdr));
3124 tmp_buf += sizeof(struct ethhdr) + len;
3125 udp_hdr = (struct udphdr *)tmp_buf;
3126 if (ntohs(udp_hdr->dest) ==
3127 ROCE_V2_UDP_DPORT)
3128 rc = true;
3129 break;
3130 }
3131 default:
3132 break;
3133 }
3134 }
3135
3136 return rc;
3137 }
3138
bnxt_re_process_raw_qp_pkt_rx(struct bnxt_re_qp * gsi_qp,struct bnxt_qplib_cqe * cqe)3139 static int bnxt_re_process_raw_qp_pkt_rx(struct bnxt_re_qp *gsi_qp,
3140 struct bnxt_qplib_cqe *cqe)
3141 {
3142 struct bnxt_re_dev *rdev = gsi_qp->rdev;
3143 struct bnxt_re_sqp_entries *sqp_entry = NULL;
3144 struct bnxt_re_qp *gsi_sqp = rdev->gsi_ctx.gsi_sqp;
3145 struct bnxt_re_ah *gsi_sah;
3146 struct ib_send_wr *swr;
3147 struct ib_ud_wr udwr;
3148 struct ib_recv_wr rwr;
3149 int pkt_type = 0;
3150 u32 tbl_idx;
3151 void *rq_hdr_buf;
3152 dma_addr_t rq_hdr_buf_map;
3153 dma_addr_t shrq_hdr_buf_map;
3154 u32 offset = 0;
3155 u32 skip_bytes = 0;
3156 struct ib_sge s_sge[2];
3157 struct ib_sge r_sge[2];
3158 int rc;
3159
3160 memset(&udwr, 0, sizeof(udwr));
3161 memset(&rwr, 0, sizeof(rwr));
3162 memset(&s_sge, 0, sizeof(s_sge));
3163 memset(&r_sge, 0, sizeof(r_sge));
3164
3165 swr = &udwr.wr;
3166 tbl_idx = cqe->wr_id;
3167
3168 rq_hdr_buf = gsi_qp->qplib_qp.rq_hdr_buf +
3169 (tbl_idx * gsi_qp->qplib_qp.rq_hdr_buf_size);
3170 rq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&gsi_qp->qplib_qp,
3171 tbl_idx);
3172
3173 /* Shadow QP header buffer */
3174 shrq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&gsi_qp->qplib_qp,
3175 tbl_idx);
3176 sqp_entry = &rdev->gsi_ctx.sqp_tbl[tbl_idx];
3177
3178 /* Store this cqe */
3179 memcpy(&sqp_entry->cqe, cqe, sizeof(struct bnxt_qplib_cqe));
3180 sqp_entry->qp1_qp = gsi_qp;
3181
3182 /* Find packet type from the cqe */
3183
3184 pkt_type = bnxt_re_check_packet_type(cqe->raweth_qp1_flags,
3185 cqe->raweth_qp1_flags2);
3186 if (pkt_type < 0) {
3187 ibdev_err(&rdev->ibdev, "Invalid packet\n");
3188 return -EINVAL;
3189 }
3190
3191 /* Adjust the offset for the user buffer and post in the rq */
3192
3193 if (pkt_type == BNXT_RE_ROCEV2_IPV4_PACKET)
3194 offset = 20;
3195
3196 /*
3197 * QP1 loopback packet has 4 bytes of internal header before
3198 * ether header. Skip these four bytes.
3199 */
3200 if (bnxt_re_is_loopback_packet(rdev, rq_hdr_buf))
3201 skip_bytes = 4;
3202
3203 /* First send SGE . Skip the ether header*/
3204 s_sge[0].addr = rq_hdr_buf_map + BNXT_QPLIB_MAX_QP1_RQ_ETH_HDR_SIZE
3205 + skip_bytes;
3206 s_sge[0].lkey = 0xFFFFFFFF;
3207 s_sge[0].length = offset ? BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV4 :
3208 BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6;
3209
3210 /* Second Send SGE */
3211 s_sge[1].addr = s_sge[0].addr + s_sge[0].length +
3212 BNXT_QPLIB_MAX_QP1_RQ_BDETH_HDR_SIZE;
3213 if (pkt_type != BNXT_RE_ROCE_V1_PACKET)
3214 s_sge[1].addr += 8;
3215 s_sge[1].lkey = 0xFFFFFFFF;
3216 s_sge[1].length = 256;
3217
3218 /* First recv SGE */
3219
3220 r_sge[0].addr = shrq_hdr_buf_map;
3221 r_sge[0].lkey = 0xFFFFFFFF;
3222 r_sge[0].length = 40;
3223
3224 r_sge[1].addr = sqp_entry->sge.addr + offset;
3225 r_sge[1].lkey = sqp_entry->sge.lkey;
3226 r_sge[1].length = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6 + 256 - offset;
3227
3228 /* Create receive work request */
3229 rwr.num_sge = 2;
3230 rwr.sg_list = r_sge;
3231 rwr.wr_id = tbl_idx;
3232 rwr.next = NULL;
3233
3234 rc = bnxt_re_post_recv_shadow_qp(rdev, gsi_sqp, &rwr);
3235 if (rc) {
3236 ibdev_err(&rdev->ibdev,
3237 "Failed to post Rx buffers to shadow QP");
3238 return -ENOMEM;
3239 }
3240
3241 swr->num_sge = 2;
3242 swr->sg_list = s_sge;
3243 swr->wr_id = tbl_idx;
3244 swr->opcode = IB_WR_SEND;
3245 swr->next = NULL;
3246 gsi_sah = rdev->gsi_ctx.gsi_sah;
3247 udwr.ah = &gsi_sah->ib_ah;
3248 udwr.remote_qpn = gsi_sqp->qplib_qp.id;
3249 udwr.remote_qkey = gsi_sqp->qplib_qp.qkey;
3250
3251 /* post data received in the send queue */
3252 rc = bnxt_re_post_send_shadow_qp(rdev, gsi_sqp, swr);
3253
3254 return 0;
3255 }
3256
bnxt_re_process_res_rawqp1_wc(struct ib_wc * wc,struct bnxt_qplib_cqe * cqe)3257 static void bnxt_re_process_res_rawqp1_wc(struct ib_wc *wc,
3258 struct bnxt_qplib_cqe *cqe)
3259 {
3260 wc->opcode = IB_WC_RECV;
3261 wc->status = __rawqp1_to_ib_wc_status(cqe->status);
3262 wc->wc_flags |= IB_WC_GRH;
3263 }
3264
bnxt_re_check_if_vlan_valid(struct bnxt_re_dev * rdev,u16 vlan_id)3265 static bool bnxt_re_check_if_vlan_valid(struct bnxt_re_dev *rdev,
3266 u16 vlan_id)
3267 {
3268 /*
3269 * Check if the vlan is configured in the host. If not configured, it
3270 * can be a transparent VLAN. So dont report the vlan id.
3271 */
3272 if (!__vlan_find_dev_deep_rcu(rdev->netdev,
3273 htons(ETH_P_8021Q), vlan_id))
3274 return false;
3275 return true;
3276 }
3277
bnxt_re_is_vlan_pkt(struct bnxt_qplib_cqe * orig_cqe,u16 * vid,u8 * sl)3278 static bool bnxt_re_is_vlan_pkt(struct bnxt_qplib_cqe *orig_cqe,
3279 u16 *vid, u8 *sl)
3280 {
3281 bool ret = false;
3282 u32 metadata;
3283 u16 tpid;
3284
3285 metadata = orig_cqe->raweth_qp1_metadata;
3286 if (orig_cqe->raweth_qp1_flags2 &
3287 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_VLAN) {
3288 tpid = ((metadata &
3289 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_MASK) >>
3290 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_SFT);
3291 if (tpid == ETH_P_8021Q) {
3292 *vid = metadata &
3293 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_MASK;
3294 *sl = (metadata &
3295 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_MASK) >>
3296 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_SFT;
3297 ret = true;
3298 }
3299 }
3300
3301 return ret;
3302 }
3303
bnxt_re_process_res_rc_wc(struct ib_wc * wc,struct bnxt_qplib_cqe * cqe)3304 static void bnxt_re_process_res_rc_wc(struct ib_wc *wc,
3305 struct bnxt_qplib_cqe *cqe)
3306 {
3307 wc->opcode = IB_WC_RECV;
3308 wc->status = __rc_to_ib_wc_status(cqe->status);
3309
3310 if (cqe->flags & CQ_RES_RC_FLAGS_IMM)
3311 wc->wc_flags |= IB_WC_WITH_IMM;
3312 if (cqe->flags & CQ_RES_RC_FLAGS_INV)
3313 wc->wc_flags |= IB_WC_WITH_INVALIDATE;
3314 if ((cqe->flags & (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) ==
3315 (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM))
3316 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
3317 }
3318
bnxt_re_process_res_shadow_qp_wc(struct bnxt_re_qp * gsi_sqp,struct ib_wc * wc,struct bnxt_qplib_cqe * cqe)3319 static void bnxt_re_process_res_shadow_qp_wc(struct bnxt_re_qp *gsi_sqp,
3320 struct ib_wc *wc,
3321 struct bnxt_qplib_cqe *cqe)
3322 {
3323 struct bnxt_re_dev *rdev = gsi_sqp->rdev;
3324 struct bnxt_re_qp *gsi_qp = NULL;
3325 struct bnxt_qplib_cqe *orig_cqe = NULL;
3326 struct bnxt_re_sqp_entries *sqp_entry = NULL;
3327 int nw_type;
3328 u32 tbl_idx;
3329 u16 vlan_id;
3330 u8 sl;
3331
3332 tbl_idx = cqe->wr_id;
3333
3334 sqp_entry = &rdev->gsi_ctx.sqp_tbl[tbl_idx];
3335 gsi_qp = sqp_entry->qp1_qp;
3336 orig_cqe = &sqp_entry->cqe;
3337
3338 wc->wr_id = sqp_entry->wrid;
3339 wc->byte_len = orig_cqe->length;
3340 wc->qp = &gsi_qp->ib_qp;
3341
3342 wc->ex.imm_data = orig_cqe->immdata;
3343 wc->src_qp = orig_cqe->src_qp;
3344 memcpy(wc->smac, orig_cqe->smac, ETH_ALEN);
3345 if (bnxt_re_is_vlan_pkt(orig_cqe, &vlan_id, &sl)) {
3346 if (bnxt_re_check_if_vlan_valid(rdev, vlan_id)) {
3347 wc->vlan_id = vlan_id;
3348 wc->sl = sl;
3349 wc->wc_flags |= IB_WC_WITH_VLAN;
3350 }
3351 }
3352 wc->port_num = 1;
3353 wc->vendor_err = orig_cqe->status;
3354
3355 wc->opcode = IB_WC_RECV;
3356 wc->status = __rawqp1_to_ib_wc_status(orig_cqe->status);
3357 wc->wc_flags |= IB_WC_GRH;
3358
3359 nw_type = bnxt_re_check_packet_type(orig_cqe->raweth_qp1_flags,
3360 orig_cqe->raweth_qp1_flags2);
3361 if (nw_type >= 0) {
3362 wc->network_hdr_type = bnxt_re_to_ib_nw_type(nw_type);
3363 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE;
3364 }
3365 }
3366
bnxt_re_process_res_ud_wc(struct bnxt_re_qp * qp,struct ib_wc * wc,struct bnxt_qplib_cqe * cqe)3367 static void bnxt_re_process_res_ud_wc(struct bnxt_re_qp *qp,
3368 struct ib_wc *wc,
3369 struct bnxt_qplib_cqe *cqe)
3370 {
3371 struct bnxt_re_dev *rdev;
3372 u16 vlan_id = 0;
3373 u8 nw_type;
3374
3375 rdev = qp->rdev;
3376 wc->opcode = IB_WC_RECV;
3377 wc->status = __rc_to_ib_wc_status(cqe->status);
3378
3379 if (cqe->flags & CQ_RES_UD_FLAGS_IMM)
3380 wc->wc_flags |= IB_WC_WITH_IMM;
3381 /* report only on GSI QP for Thor */
3382 if (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_GSI) {
3383 wc->wc_flags |= IB_WC_GRH;
3384 memcpy(wc->smac, cqe->smac, ETH_ALEN);
3385 wc->wc_flags |= IB_WC_WITH_SMAC;
3386 if (cqe->flags & CQ_RES_UD_FLAGS_META_FORMAT_VLAN) {
3387 vlan_id = (cqe->cfa_meta & 0xFFF);
3388 }
3389 /* Mark only if vlan_id is non zero */
3390 if (vlan_id && bnxt_re_check_if_vlan_valid(rdev, vlan_id)) {
3391 wc->vlan_id = vlan_id;
3392 wc->wc_flags |= IB_WC_WITH_VLAN;
3393 }
3394 nw_type = (cqe->flags & CQ_RES_UD_FLAGS_ROCE_IP_VER_MASK) >>
3395 CQ_RES_UD_FLAGS_ROCE_IP_VER_SFT;
3396 wc->network_hdr_type = bnxt_re_to_ib_nw_type(nw_type);
3397 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE;
3398 }
3399
3400 }
3401
send_phantom_wqe(struct bnxt_re_qp * qp)3402 static int send_phantom_wqe(struct bnxt_re_qp *qp)
3403 {
3404 struct bnxt_qplib_qp *lib_qp = &qp->qplib_qp;
3405 unsigned long flags;
3406 int rc = 0;
3407
3408 spin_lock_irqsave(&qp->sq_lock, flags);
3409
3410 rc = bnxt_re_bind_fence_mw(lib_qp);
3411 if (!rc) {
3412 lib_qp->sq.phantom_wqe_cnt++;
3413 ibdev_dbg(&qp->rdev->ibdev,
3414 "qp %#x sq->prod %#x sw_prod %#x phantom_wqe_cnt %d\n",
3415 lib_qp->id, lib_qp->sq.hwq.prod,
3416 HWQ_CMP(lib_qp->sq.hwq.prod, &lib_qp->sq.hwq),
3417 lib_qp->sq.phantom_wqe_cnt);
3418 }
3419
3420 spin_unlock_irqrestore(&qp->sq_lock, flags);
3421 return rc;
3422 }
3423
bnxt_re_poll_cq(struct ib_cq * ib_cq,int num_entries,struct ib_wc * wc)3424 int bnxt_re_poll_cq(struct ib_cq *ib_cq, int num_entries, struct ib_wc *wc)
3425 {
3426 struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
3427 struct bnxt_re_qp *qp, *sh_qp;
3428 struct bnxt_qplib_cqe *cqe;
3429 int i, ncqe, budget;
3430 struct bnxt_qplib_q *sq;
3431 struct bnxt_qplib_qp *lib_qp;
3432 u32 tbl_idx;
3433 struct bnxt_re_sqp_entries *sqp_entry = NULL;
3434 unsigned long flags;
3435
3436 spin_lock_irqsave(&cq->cq_lock, flags);
3437 budget = min_t(u32, num_entries, cq->max_cql);
3438 num_entries = budget;
3439 if (!cq->cql) {
3440 ibdev_err(&cq->rdev->ibdev, "POLL CQ : no CQL to use");
3441 goto exit;
3442 }
3443 cqe = &cq->cql[0];
3444 while (budget) {
3445 lib_qp = NULL;
3446 ncqe = bnxt_qplib_poll_cq(&cq->qplib_cq, cqe, budget, &lib_qp);
3447 if (lib_qp) {
3448 sq = &lib_qp->sq;
3449 if (sq->send_phantom) {
3450 qp = container_of(lib_qp,
3451 struct bnxt_re_qp, qplib_qp);
3452 if (send_phantom_wqe(qp) == -ENOMEM)
3453 ibdev_err(&cq->rdev->ibdev,
3454 "Phantom failed! Scheduled to send again\n");
3455 else
3456 sq->send_phantom = false;
3457 }
3458 }
3459 if (ncqe < budget)
3460 ncqe += bnxt_qplib_process_flush_list(&cq->qplib_cq,
3461 cqe + ncqe,
3462 budget - ncqe);
3463
3464 if (!ncqe)
3465 break;
3466
3467 for (i = 0; i < ncqe; i++, cqe++) {
3468 /* Transcribe each qplib_wqe back to ib_wc */
3469 memset(wc, 0, sizeof(*wc));
3470
3471 wc->wr_id = cqe->wr_id;
3472 wc->byte_len = cqe->length;
3473 qp = container_of
3474 ((struct bnxt_qplib_qp *)
3475 (unsigned long)(cqe->qp_handle),
3476 struct bnxt_re_qp, qplib_qp);
3477 if (!qp) {
3478 ibdev_err(&cq->rdev->ibdev, "POLL CQ : bad QP handle");
3479 continue;
3480 }
3481 wc->qp = &qp->ib_qp;
3482 wc->ex.imm_data = cqe->immdata;
3483 wc->src_qp = cqe->src_qp;
3484 memcpy(wc->smac, cqe->smac, ETH_ALEN);
3485 wc->port_num = 1;
3486 wc->vendor_err = cqe->status;
3487
3488 switch (cqe->opcode) {
3489 case CQ_BASE_CQE_TYPE_REQ:
3490 sh_qp = qp->rdev->gsi_ctx.gsi_sqp;
3491 if (sh_qp &&
3492 qp->qplib_qp.id == sh_qp->qplib_qp.id) {
3493 /* Handle this completion with
3494 * the stored completion
3495 */
3496 memset(wc, 0, sizeof(*wc));
3497 continue;
3498 }
3499 bnxt_re_process_req_wc(wc, cqe);
3500 break;
3501 case CQ_BASE_CQE_TYPE_RES_RAWETH_QP1:
3502 if (!cqe->status) {
3503 int rc = 0;
3504
3505 rc = bnxt_re_process_raw_qp_pkt_rx
3506 (qp, cqe);
3507 if (!rc) {
3508 memset(wc, 0, sizeof(*wc));
3509 continue;
3510 }
3511 cqe->status = -1;
3512 }
3513 /* Errors need not be looped back.
3514 * But change the wr_id to the one
3515 * stored in the table
3516 */
3517 tbl_idx = cqe->wr_id;
3518 sqp_entry = &cq->rdev->gsi_ctx.sqp_tbl[tbl_idx];
3519 wc->wr_id = sqp_entry->wrid;
3520 bnxt_re_process_res_rawqp1_wc(wc, cqe);
3521 break;
3522 case CQ_BASE_CQE_TYPE_RES_RC:
3523 bnxt_re_process_res_rc_wc(wc, cqe);
3524 break;
3525 case CQ_BASE_CQE_TYPE_RES_UD:
3526 sh_qp = qp->rdev->gsi_ctx.gsi_sqp;
3527 if (sh_qp &&
3528 qp->qplib_qp.id == sh_qp->qplib_qp.id) {
3529 /* Handle this completion with
3530 * the stored completion
3531 */
3532 if (cqe->status) {
3533 continue;
3534 } else {
3535 bnxt_re_process_res_shadow_qp_wc
3536 (qp, wc, cqe);
3537 break;
3538 }
3539 }
3540 bnxt_re_process_res_ud_wc(qp, wc, cqe);
3541 break;
3542 default:
3543 ibdev_err(&cq->rdev->ibdev,
3544 "POLL CQ : type 0x%x not handled",
3545 cqe->opcode);
3546 continue;
3547 }
3548 wc++;
3549 budget--;
3550 }
3551 }
3552 exit:
3553 spin_unlock_irqrestore(&cq->cq_lock, flags);
3554 return num_entries - budget;
3555 }
3556
bnxt_re_req_notify_cq(struct ib_cq * ib_cq,enum ib_cq_notify_flags ib_cqn_flags)3557 int bnxt_re_req_notify_cq(struct ib_cq *ib_cq,
3558 enum ib_cq_notify_flags ib_cqn_flags)
3559 {
3560 struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
3561 int type = 0, rc = 0;
3562 unsigned long flags;
3563
3564 spin_lock_irqsave(&cq->cq_lock, flags);
3565 /* Trigger on the very next completion */
3566 if (ib_cqn_flags & IB_CQ_NEXT_COMP)
3567 type = DBC_DBC_TYPE_CQ_ARMALL;
3568 /* Trigger on the next solicited completion */
3569 else if (ib_cqn_flags & IB_CQ_SOLICITED)
3570 type = DBC_DBC_TYPE_CQ_ARMSE;
3571
3572 /* Poll to see if there are missed events */
3573 if ((ib_cqn_flags & IB_CQ_REPORT_MISSED_EVENTS) &&
3574 !(bnxt_qplib_is_cq_empty(&cq->qplib_cq))) {
3575 rc = 1;
3576 goto exit;
3577 }
3578 bnxt_qplib_req_notify_cq(&cq->qplib_cq, type);
3579
3580 exit:
3581 spin_unlock_irqrestore(&cq->cq_lock, flags);
3582 return rc;
3583 }
3584
3585 /* Memory Regions */
bnxt_re_get_dma_mr(struct ib_pd * ib_pd,int mr_access_flags)3586 struct ib_mr *bnxt_re_get_dma_mr(struct ib_pd *ib_pd, int mr_access_flags)
3587 {
3588 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
3589 struct bnxt_re_dev *rdev = pd->rdev;
3590 struct bnxt_re_mr *mr;
3591 u64 pbl = 0;
3592 int rc;
3593
3594 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
3595 if (!mr)
3596 return ERR_PTR(-ENOMEM);
3597
3598 mr->rdev = rdev;
3599 mr->qplib_mr.pd = &pd->qplib_pd;
3600 mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags);
3601 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR;
3602
3603 /* Allocate and register 0 as the address */
3604 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
3605 if (rc)
3606 goto fail;
3607
3608 mr->qplib_mr.hwq.level = PBL_LVL_MAX;
3609 mr->qplib_mr.total_size = -1; /* Infinte length */
3610 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, &pbl, 0, false,
3611 PAGE_SIZE);
3612 if (rc)
3613 goto fail_mr;
3614
3615 mr->ib_mr.lkey = mr->qplib_mr.lkey;
3616 if (mr_access_flags & (IB_ACCESS_REMOTE_WRITE | IB_ACCESS_REMOTE_READ |
3617 IB_ACCESS_REMOTE_ATOMIC))
3618 mr->ib_mr.rkey = mr->ib_mr.lkey;
3619 atomic_inc(&rdev->mr_count);
3620
3621 return &mr->ib_mr;
3622
3623 fail_mr:
3624 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
3625 fail:
3626 kfree(mr);
3627 return ERR_PTR(rc);
3628 }
3629
bnxt_re_dereg_mr(struct ib_mr * ib_mr,struct ib_udata * udata)3630 int bnxt_re_dereg_mr(struct ib_mr *ib_mr, struct ib_udata *udata)
3631 {
3632 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
3633 struct bnxt_re_dev *rdev = mr->rdev;
3634 int rc;
3635
3636 rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
3637 if (rc) {
3638 ibdev_err(&rdev->ibdev, "Dereg MR failed: %#x\n", rc);
3639 return rc;
3640 }
3641
3642 if (mr->pages) {
3643 rc = bnxt_qplib_free_fast_reg_page_list(&rdev->qplib_res,
3644 &mr->qplib_frpl);
3645 kfree(mr->pages);
3646 mr->npages = 0;
3647 mr->pages = NULL;
3648 }
3649 ib_umem_release(mr->ib_umem);
3650
3651 kfree(mr);
3652 atomic_dec(&rdev->mr_count);
3653 return rc;
3654 }
3655
bnxt_re_set_page(struct ib_mr * ib_mr,u64 addr)3656 static int bnxt_re_set_page(struct ib_mr *ib_mr, u64 addr)
3657 {
3658 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
3659
3660 if (unlikely(mr->npages == mr->qplib_frpl.max_pg_ptrs))
3661 return -ENOMEM;
3662
3663 mr->pages[mr->npages++] = addr;
3664 return 0;
3665 }
3666
bnxt_re_map_mr_sg(struct ib_mr * ib_mr,struct scatterlist * sg,int sg_nents,unsigned int * sg_offset)3667 int bnxt_re_map_mr_sg(struct ib_mr *ib_mr, struct scatterlist *sg, int sg_nents,
3668 unsigned int *sg_offset)
3669 {
3670 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
3671
3672 mr->npages = 0;
3673 return ib_sg_to_pages(ib_mr, sg, sg_nents, sg_offset, bnxt_re_set_page);
3674 }
3675
bnxt_re_alloc_mr(struct ib_pd * ib_pd,enum ib_mr_type type,u32 max_num_sg)3676 struct ib_mr *bnxt_re_alloc_mr(struct ib_pd *ib_pd, enum ib_mr_type type,
3677 u32 max_num_sg)
3678 {
3679 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
3680 struct bnxt_re_dev *rdev = pd->rdev;
3681 struct bnxt_re_mr *mr = NULL;
3682 int rc;
3683
3684 if (type != IB_MR_TYPE_MEM_REG) {
3685 ibdev_dbg(&rdev->ibdev, "MR type 0x%x not supported", type);
3686 return ERR_PTR(-EINVAL);
3687 }
3688 if (max_num_sg > MAX_PBL_LVL_1_PGS)
3689 return ERR_PTR(-EINVAL);
3690
3691 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
3692 if (!mr)
3693 return ERR_PTR(-ENOMEM);
3694
3695 mr->rdev = rdev;
3696 mr->qplib_mr.pd = &pd->qplib_pd;
3697 mr->qplib_mr.flags = BNXT_QPLIB_FR_PMR;
3698 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR;
3699
3700 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
3701 if (rc)
3702 goto bail;
3703
3704 mr->ib_mr.lkey = mr->qplib_mr.lkey;
3705 mr->ib_mr.rkey = mr->ib_mr.lkey;
3706
3707 mr->pages = kcalloc(max_num_sg, sizeof(u64), GFP_KERNEL);
3708 if (!mr->pages) {
3709 rc = -ENOMEM;
3710 goto fail;
3711 }
3712 rc = bnxt_qplib_alloc_fast_reg_page_list(&rdev->qplib_res,
3713 &mr->qplib_frpl, max_num_sg);
3714 if (rc) {
3715 ibdev_err(&rdev->ibdev,
3716 "Failed to allocate HW FR page list");
3717 goto fail_mr;
3718 }
3719
3720 atomic_inc(&rdev->mr_count);
3721 return &mr->ib_mr;
3722
3723 fail_mr:
3724 kfree(mr->pages);
3725 fail:
3726 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
3727 bail:
3728 kfree(mr);
3729 return ERR_PTR(rc);
3730 }
3731
bnxt_re_alloc_mw(struct ib_pd * ib_pd,enum ib_mw_type type,struct ib_udata * udata)3732 struct ib_mw *bnxt_re_alloc_mw(struct ib_pd *ib_pd, enum ib_mw_type type,
3733 struct ib_udata *udata)
3734 {
3735 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
3736 struct bnxt_re_dev *rdev = pd->rdev;
3737 struct bnxt_re_mw *mw;
3738 int rc;
3739
3740 mw = kzalloc(sizeof(*mw), GFP_KERNEL);
3741 if (!mw)
3742 return ERR_PTR(-ENOMEM);
3743 mw->rdev = rdev;
3744 mw->qplib_mw.pd = &pd->qplib_pd;
3745
3746 mw->qplib_mw.type = (type == IB_MW_TYPE_1 ?
3747 CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1 :
3748 CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B);
3749 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mw->qplib_mw);
3750 if (rc) {
3751 ibdev_err(&rdev->ibdev, "Allocate MW failed!");
3752 goto fail;
3753 }
3754 mw->ib_mw.rkey = mw->qplib_mw.rkey;
3755
3756 atomic_inc(&rdev->mw_count);
3757 return &mw->ib_mw;
3758
3759 fail:
3760 kfree(mw);
3761 return ERR_PTR(rc);
3762 }
3763
bnxt_re_dealloc_mw(struct ib_mw * ib_mw)3764 int bnxt_re_dealloc_mw(struct ib_mw *ib_mw)
3765 {
3766 struct bnxt_re_mw *mw = container_of(ib_mw, struct bnxt_re_mw, ib_mw);
3767 struct bnxt_re_dev *rdev = mw->rdev;
3768 int rc;
3769
3770 rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mw->qplib_mw);
3771 if (rc) {
3772 ibdev_err(&rdev->ibdev, "Free MW failed: %#x\n", rc);
3773 return rc;
3774 }
3775
3776 kfree(mw);
3777 atomic_dec(&rdev->mw_count);
3778 return rc;
3779 }
3780
fill_umem_pbl_tbl(struct ib_umem * umem,u64 * pbl_tbl_orig,int page_shift)3781 static int fill_umem_pbl_tbl(struct ib_umem *umem, u64 *pbl_tbl_orig,
3782 int page_shift)
3783 {
3784 u64 *pbl_tbl = pbl_tbl_orig;
3785 u64 page_size = BIT_ULL(page_shift);
3786 struct ib_block_iter biter;
3787
3788 rdma_umem_for_each_dma_block(umem, &biter, page_size)
3789 *pbl_tbl++ = rdma_block_iter_dma_address(&biter);
3790
3791 return pbl_tbl - pbl_tbl_orig;
3792 }
3793
3794 /* uverbs */
bnxt_re_reg_user_mr(struct ib_pd * ib_pd,u64 start,u64 length,u64 virt_addr,int mr_access_flags,struct ib_udata * udata)3795 struct ib_mr *bnxt_re_reg_user_mr(struct ib_pd *ib_pd, u64 start, u64 length,
3796 u64 virt_addr, int mr_access_flags,
3797 struct ib_udata *udata)
3798 {
3799 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
3800 struct bnxt_re_dev *rdev = pd->rdev;
3801 struct bnxt_re_mr *mr;
3802 struct ib_umem *umem;
3803 u64 *pbl_tbl = NULL;
3804 unsigned long page_size;
3805 int umem_pgs, rc;
3806
3807 if (length > BNXT_RE_MAX_MR_SIZE) {
3808 ibdev_err(&rdev->ibdev, "MR Size: %lld > Max supported:%lld\n",
3809 length, BNXT_RE_MAX_MR_SIZE);
3810 return ERR_PTR(-ENOMEM);
3811 }
3812
3813 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
3814 if (!mr)
3815 return ERR_PTR(-ENOMEM);
3816
3817 mr->rdev = rdev;
3818 mr->qplib_mr.pd = &pd->qplib_pd;
3819 mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags);
3820 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_MR;
3821
3822 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
3823 if (rc) {
3824 ibdev_err(&rdev->ibdev, "Failed to allocate MR");
3825 goto free_mr;
3826 }
3827 /* The fixed portion of the rkey is the same as the lkey */
3828 mr->ib_mr.rkey = mr->qplib_mr.rkey;
3829
3830 umem = ib_umem_get(&rdev->ibdev, start, length, mr_access_flags);
3831 if (IS_ERR(umem)) {
3832 ibdev_err(&rdev->ibdev, "Failed to get umem");
3833 rc = -EFAULT;
3834 goto free_mrw;
3835 }
3836 mr->ib_umem = umem;
3837
3838 mr->qplib_mr.va = virt_addr;
3839 page_size = ib_umem_find_best_pgsz(
3840 umem, BNXT_RE_PAGE_SIZE_4K | BNXT_RE_PAGE_SIZE_2M, virt_addr);
3841 if (!page_size) {
3842 ibdev_err(&rdev->ibdev, "umem page size unsupported!");
3843 rc = -EFAULT;
3844 goto free_umem;
3845 }
3846 mr->qplib_mr.total_size = length;
3847
3848 if (page_size == BNXT_RE_PAGE_SIZE_4K &&
3849 length > BNXT_RE_MAX_MR_SIZE_LOW) {
3850 ibdev_err(&rdev->ibdev, "Requested MR Sz:%llu Max sup:%llu",
3851 length, (u64)BNXT_RE_MAX_MR_SIZE_LOW);
3852 rc = -EINVAL;
3853 goto free_umem;
3854 }
3855
3856 umem_pgs = ib_umem_num_dma_blocks(umem, page_size);
3857 pbl_tbl = kcalloc(umem_pgs, sizeof(*pbl_tbl), GFP_KERNEL);
3858 if (!pbl_tbl) {
3859 rc = -ENOMEM;
3860 goto free_umem;
3861 }
3862
3863 /* Map umem buf ptrs to the PBL */
3864 umem_pgs = fill_umem_pbl_tbl(umem, pbl_tbl, order_base_2(page_size));
3865 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, pbl_tbl,
3866 umem_pgs, false, page_size);
3867 if (rc) {
3868 ibdev_err(&rdev->ibdev, "Failed to register user MR");
3869 goto fail;
3870 }
3871
3872 kfree(pbl_tbl);
3873
3874 mr->ib_mr.lkey = mr->qplib_mr.lkey;
3875 mr->ib_mr.rkey = mr->qplib_mr.lkey;
3876 atomic_inc(&rdev->mr_count);
3877
3878 return &mr->ib_mr;
3879 fail:
3880 kfree(pbl_tbl);
3881 free_umem:
3882 ib_umem_release(umem);
3883 free_mrw:
3884 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
3885 free_mr:
3886 kfree(mr);
3887 return ERR_PTR(rc);
3888 }
3889
bnxt_re_alloc_ucontext(struct ib_ucontext * ctx,struct ib_udata * udata)3890 int bnxt_re_alloc_ucontext(struct ib_ucontext *ctx, struct ib_udata *udata)
3891 {
3892 struct ib_device *ibdev = ctx->device;
3893 struct bnxt_re_ucontext *uctx =
3894 container_of(ctx, struct bnxt_re_ucontext, ib_uctx);
3895 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
3896 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
3897 struct bnxt_re_uctx_resp resp;
3898 u32 chip_met_rev_num = 0;
3899 int rc;
3900
3901 ibdev_dbg(ibdev, "ABI version requested %u", ibdev->ops.uverbs_abi_ver);
3902
3903 if (ibdev->ops.uverbs_abi_ver != BNXT_RE_ABI_VERSION) {
3904 ibdev_dbg(ibdev, " is different from the device %d ",
3905 BNXT_RE_ABI_VERSION);
3906 return -EPERM;
3907 }
3908
3909 uctx->rdev = rdev;
3910
3911 uctx->shpg = (void *)__get_free_page(GFP_KERNEL);
3912 if (!uctx->shpg) {
3913 rc = -ENOMEM;
3914 goto fail;
3915 }
3916 spin_lock_init(&uctx->sh_lock);
3917
3918 resp.comp_mask = BNXT_RE_UCNTX_CMASK_HAVE_CCTX;
3919 chip_met_rev_num = rdev->chip_ctx->chip_num;
3920 chip_met_rev_num |= ((u32)rdev->chip_ctx->chip_rev & 0xFF) <<
3921 BNXT_RE_CHIP_ID0_CHIP_REV_SFT;
3922 chip_met_rev_num |= ((u32)rdev->chip_ctx->chip_metal & 0xFF) <<
3923 BNXT_RE_CHIP_ID0_CHIP_MET_SFT;
3924 resp.chip_id0 = chip_met_rev_num;
3925 /* Future extension of chip info */
3926 resp.chip_id1 = 0;
3927 /*Temp, Use xa_alloc instead */
3928 resp.dev_id = rdev->en_dev->pdev->devfn;
3929 resp.max_qp = rdev->qplib_ctx.qpc_count;
3930 resp.pg_size = PAGE_SIZE;
3931 resp.cqe_sz = sizeof(struct cq_base);
3932 resp.max_cqd = dev_attr->max_cq_wqes;
3933 resp.rsvd = 0;
3934
3935 rc = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp)));
3936 if (rc) {
3937 ibdev_err(ibdev, "Failed to copy user context");
3938 rc = -EFAULT;
3939 goto cfail;
3940 }
3941
3942 return 0;
3943 cfail:
3944 free_page((unsigned long)uctx->shpg);
3945 uctx->shpg = NULL;
3946 fail:
3947 return rc;
3948 }
3949
bnxt_re_dealloc_ucontext(struct ib_ucontext * ib_uctx)3950 void bnxt_re_dealloc_ucontext(struct ib_ucontext *ib_uctx)
3951 {
3952 struct bnxt_re_ucontext *uctx = container_of(ib_uctx,
3953 struct bnxt_re_ucontext,
3954 ib_uctx);
3955
3956 struct bnxt_re_dev *rdev = uctx->rdev;
3957
3958 if (uctx->shpg)
3959 free_page((unsigned long)uctx->shpg);
3960
3961 if (uctx->dpi.dbr) {
3962 /* Free DPI only if this is the first PD allocated by the
3963 * application and mark the context dpi as NULL
3964 */
3965 bnxt_qplib_dealloc_dpi(&rdev->qplib_res,
3966 &rdev->qplib_res.dpi_tbl, &uctx->dpi);
3967 uctx->dpi.dbr = NULL;
3968 }
3969 }
3970
3971 /* Helper function to mmap the virtual memory from user app */
bnxt_re_mmap(struct ib_ucontext * ib_uctx,struct vm_area_struct * vma)3972 int bnxt_re_mmap(struct ib_ucontext *ib_uctx, struct vm_area_struct *vma)
3973 {
3974 struct bnxt_re_ucontext *uctx = container_of(ib_uctx,
3975 struct bnxt_re_ucontext,
3976 ib_uctx);
3977 struct bnxt_re_dev *rdev = uctx->rdev;
3978 u64 pfn;
3979
3980 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
3981 return -EINVAL;
3982
3983 if (vma->vm_pgoff) {
3984 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
3985 if (io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
3986 PAGE_SIZE, vma->vm_page_prot)) {
3987 ibdev_err(&rdev->ibdev, "Failed to map DPI");
3988 return -EAGAIN;
3989 }
3990 } else {
3991 pfn = virt_to_phys(uctx->shpg) >> PAGE_SHIFT;
3992 if (remap_pfn_range(vma, vma->vm_start,
3993 pfn, PAGE_SIZE, vma->vm_page_prot)) {
3994 ibdev_err(&rdev->ibdev, "Failed to map shared page");
3995 return -EAGAIN;
3996 }
3997 }
3998
3999 return 0;
4000 }
4001