1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Amlogic SD/eMMC driver for the GX/S905 family SoCs
4 *
5 * Copyright (c) 2016 BayLibre, SAS.
6 * Author: Kevin Hilman <khilman@baylibre.com>
7 */
8 #include <linux/kernel.h>
9 #include <linux/module.h>
10 #include <linux/init.h>
11 #include <linux/delay.h>
12 #include <linux/device.h>
13 #include <linux/iopoll.h>
14 #include <linux/of_device.h>
15 #include <linux/platform_device.h>
16 #include <linux/ioport.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/mmc/host.h>
19 #include <linux/mmc/mmc.h>
20 #include <linux/mmc/sdio.h>
21 #include <linux/mmc/slot-gpio.h>
22 #include <linux/io.h>
23 #include <linux/clk.h>
24 #include <linux/clk-provider.h>
25 #include <linux/regulator/consumer.h>
26 #include <linux/reset.h>
27 #include <linux/interrupt.h>
28 #include <linux/bitfield.h>
29 #include <linux/pinctrl/consumer.h>
30
31 #define DRIVER_NAME "meson-gx-mmc"
32
33 #define SD_EMMC_CLOCK 0x0
34 #define CLK_DIV_MASK GENMASK(5, 0)
35 #define CLK_SRC_MASK GENMASK(7, 6)
36 #define CLK_CORE_PHASE_MASK GENMASK(9, 8)
37 #define CLK_TX_PHASE_MASK GENMASK(11, 10)
38 #define CLK_RX_PHASE_MASK GENMASK(13, 12)
39 #define CLK_PHASE_0 0
40 #define CLK_PHASE_180 2
41 #define CLK_V2_TX_DELAY_MASK GENMASK(19, 16)
42 #define CLK_V2_RX_DELAY_MASK GENMASK(23, 20)
43 #define CLK_V2_ALWAYS_ON BIT(24)
44
45 #define CLK_V3_TX_DELAY_MASK GENMASK(21, 16)
46 #define CLK_V3_RX_DELAY_MASK GENMASK(27, 22)
47 #define CLK_V3_ALWAYS_ON BIT(28)
48
49 #define CLK_TX_DELAY_MASK(h) (h->data->tx_delay_mask)
50 #define CLK_RX_DELAY_MASK(h) (h->data->rx_delay_mask)
51 #define CLK_ALWAYS_ON(h) (h->data->always_on)
52
53 #define SD_EMMC_DELAY 0x4
54 #define SD_EMMC_ADJUST 0x8
55 #define ADJUST_ADJ_DELAY_MASK GENMASK(21, 16)
56 #define ADJUST_DS_EN BIT(15)
57 #define ADJUST_ADJ_EN BIT(13)
58
59 #define SD_EMMC_DELAY1 0x4
60 #define SD_EMMC_DELAY2 0x8
61 #define SD_EMMC_V3_ADJUST 0xc
62
63 #define SD_EMMC_CALOUT 0x10
64 #define SD_EMMC_START 0x40
65 #define START_DESC_INIT BIT(0)
66 #define START_DESC_BUSY BIT(1)
67 #define START_DESC_ADDR_MASK GENMASK(31, 2)
68
69 #define SD_EMMC_CFG 0x44
70 #define CFG_BUS_WIDTH_MASK GENMASK(1, 0)
71 #define CFG_BUS_WIDTH_1 0x0
72 #define CFG_BUS_WIDTH_4 0x1
73 #define CFG_BUS_WIDTH_8 0x2
74 #define CFG_DDR BIT(2)
75 #define CFG_BLK_LEN_MASK GENMASK(7, 4)
76 #define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8)
77 #define CFG_RC_CC_MASK GENMASK(15, 12)
78 #define CFG_STOP_CLOCK BIT(22)
79 #define CFG_CLK_ALWAYS_ON BIT(18)
80 #define CFG_CHK_DS BIT(20)
81 #define CFG_AUTO_CLK BIT(23)
82 #define CFG_ERR_ABORT BIT(27)
83
84 #define SD_EMMC_STATUS 0x48
85 #define STATUS_BUSY BIT(31)
86 #define STATUS_DESC_BUSY BIT(30)
87 #define STATUS_DATI GENMASK(23, 16)
88
89 #define SD_EMMC_IRQ_EN 0x4c
90 #define IRQ_RXD_ERR_MASK GENMASK(7, 0)
91 #define IRQ_TXD_ERR BIT(8)
92 #define IRQ_DESC_ERR BIT(9)
93 #define IRQ_RESP_ERR BIT(10)
94 #define IRQ_CRC_ERR \
95 (IRQ_RXD_ERR_MASK | IRQ_TXD_ERR | IRQ_DESC_ERR | IRQ_RESP_ERR)
96 #define IRQ_RESP_TIMEOUT BIT(11)
97 #define IRQ_DESC_TIMEOUT BIT(12)
98 #define IRQ_TIMEOUTS \
99 (IRQ_RESP_TIMEOUT | IRQ_DESC_TIMEOUT)
100 #define IRQ_END_OF_CHAIN BIT(13)
101 #define IRQ_RESP_STATUS BIT(14)
102 #define IRQ_SDIO BIT(15)
103 #define IRQ_EN_MASK \
104 (IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN | IRQ_RESP_STATUS |\
105 IRQ_SDIO)
106
107 #define SD_EMMC_CMD_CFG 0x50
108 #define SD_EMMC_CMD_ARG 0x54
109 #define SD_EMMC_CMD_DAT 0x58
110 #define SD_EMMC_CMD_RSP 0x5c
111 #define SD_EMMC_CMD_RSP1 0x60
112 #define SD_EMMC_CMD_RSP2 0x64
113 #define SD_EMMC_CMD_RSP3 0x68
114
115 #define SD_EMMC_RXD 0x94
116 #define SD_EMMC_TXD 0x94
117 #define SD_EMMC_LAST_REG SD_EMMC_TXD
118
119 #define SD_EMMC_SRAM_DATA_BUF_LEN 1536
120 #define SD_EMMC_SRAM_DATA_BUF_OFF 0x200
121
122 #define SD_EMMC_CFG_BLK_SIZE 512 /* internal buffer max: 512 bytes */
123 #define SD_EMMC_CFG_RESP_TIMEOUT 256 /* in clock cycles */
124 #define SD_EMMC_CMD_TIMEOUT 1024 /* in ms */
125 #define SD_EMMC_CMD_TIMEOUT_DATA 4096 /* in ms */
126 #define SD_EMMC_CFG_CMD_GAP 16 /* in clock cycles */
127 #define SD_EMMC_DESC_BUF_LEN PAGE_SIZE
128
129 #define SD_EMMC_PRE_REQ_DONE BIT(0)
130 #define SD_EMMC_DESC_CHAIN_MODE BIT(1)
131
132 #define MUX_CLK_NUM_PARENTS 2
133
134 struct meson_mmc_data {
135 unsigned int tx_delay_mask;
136 unsigned int rx_delay_mask;
137 unsigned int always_on;
138 unsigned int adjust;
139 };
140
141 struct sd_emmc_desc {
142 u32 cmd_cfg;
143 u32 cmd_arg;
144 u32 cmd_data;
145 u32 cmd_resp;
146 };
147
148 struct meson_host {
149 struct device *dev;
150 struct meson_mmc_data *data;
151 struct mmc_host *mmc;
152 struct mmc_command *cmd;
153
154 void __iomem *regs;
155 struct clk *core_clk;
156 struct clk *mux_clk;
157 struct clk *mmc_clk;
158 unsigned long req_rate;
159 bool ddr;
160
161 bool dram_access_quirk;
162
163 struct pinctrl *pinctrl;
164 struct pinctrl_state *pins_clk_gate;
165
166 unsigned int bounce_buf_size;
167 void *bounce_buf;
168 void __iomem *bounce_iomem_buf;
169 dma_addr_t bounce_dma_addr;
170 struct sd_emmc_desc *descs;
171 dma_addr_t descs_dma_addr;
172
173 int irq;
174
175 bool vqmmc_enabled;
176 };
177
178 #define CMD_CFG_LENGTH_MASK GENMASK(8, 0)
179 #define CMD_CFG_BLOCK_MODE BIT(9)
180 #define CMD_CFG_R1B BIT(10)
181 #define CMD_CFG_END_OF_CHAIN BIT(11)
182 #define CMD_CFG_TIMEOUT_MASK GENMASK(15, 12)
183 #define CMD_CFG_NO_RESP BIT(16)
184 #define CMD_CFG_NO_CMD BIT(17)
185 #define CMD_CFG_DATA_IO BIT(18)
186 #define CMD_CFG_DATA_WR BIT(19)
187 #define CMD_CFG_RESP_NOCRC BIT(20)
188 #define CMD_CFG_RESP_128 BIT(21)
189 #define CMD_CFG_RESP_NUM BIT(22)
190 #define CMD_CFG_DATA_NUM BIT(23)
191 #define CMD_CFG_CMD_INDEX_MASK GENMASK(29, 24)
192 #define CMD_CFG_ERROR BIT(30)
193 #define CMD_CFG_OWNER BIT(31)
194
195 #define CMD_DATA_MASK GENMASK(31, 2)
196 #define CMD_DATA_BIG_ENDIAN BIT(1)
197 #define CMD_DATA_SRAM BIT(0)
198 #define CMD_RESP_MASK GENMASK(31, 1)
199 #define CMD_RESP_SRAM BIT(0)
200
meson_mmc_get_timeout_msecs(struct mmc_data * data)201 static unsigned int meson_mmc_get_timeout_msecs(struct mmc_data *data)
202 {
203 unsigned int timeout = data->timeout_ns / NSEC_PER_MSEC;
204
205 if (!timeout)
206 return SD_EMMC_CMD_TIMEOUT_DATA;
207
208 timeout = roundup_pow_of_two(timeout);
209
210 return min(timeout, 32768U); /* max. 2^15 ms */
211 }
212
meson_mmc_get_next_command(struct mmc_command * cmd)213 static struct mmc_command *meson_mmc_get_next_command(struct mmc_command *cmd)
214 {
215 if (cmd->opcode == MMC_SET_BLOCK_COUNT && !cmd->error)
216 return cmd->mrq->cmd;
217 else if (mmc_op_multi(cmd->opcode) &&
218 (!cmd->mrq->sbc || cmd->error || cmd->data->error))
219 return cmd->mrq->stop;
220 else
221 return NULL;
222 }
223
meson_mmc_get_transfer_mode(struct mmc_host * mmc,struct mmc_request * mrq)224 static void meson_mmc_get_transfer_mode(struct mmc_host *mmc,
225 struct mmc_request *mrq)
226 {
227 struct meson_host *host = mmc_priv(mmc);
228 struct mmc_data *data = mrq->data;
229 struct scatterlist *sg;
230 int i;
231 bool use_desc_chain_mode = true;
232
233 /*
234 * When Controller DMA cannot directly access DDR memory, disable
235 * support for Chain Mode to directly use the internal SRAM using
236 * the bounce buffer mode.
237 */
238 if (host->dram_access_quirk)
239 return;
240
241 /*
242 * Broken SDIO with AP6255-based WiFi on Khadas VIM Pro has been
243 * reported. For some strange reason this occurs in descriptor
244 * chain mode only. So let's fall back to bounce buffer mode
245 * for command SD_IO_RW_EXTENDED.
246 */
247 if (mrq->cmd->opcode == SD_IO_RW_EXTENDED)
248 return;
249
250 for_each_sg(data->sg, sg, data->sg_len, i)
251 /* check for 8 byte alignment */
252 if (sg->offset & 7) {
253 WARN_ONCE(1, "unaligned scatterlist buffer\n");
254 use_desc_chain_mode = false;
255 break;
256 }
257
258 if (use_desc_chain_mode)
259 data->host_cookie |= SD_EMMC_DESC_CHAIN_MODE;
260 }
261
meson_mmc_desc_chain_mode(const struct mmc_data * data)262 static inline bool meson_mmc_desc_chain_mode(const struct mmc_data *data)
263 {
264 return data->host_cookie & SD_EMMC_DESC_CHAIN_MODE;
265 }
266
meson_mmc_bounce_buf_read(const struct mmc_data * data)267 static inline bool meson_mmc_bounce_buf_read(const struct mmc_data *data)
268 {
269 return data && data->flags & MMC_DATA_READ &&
270 !meson_mmc_desc_chain_mode(data);
271 }
272
meson_mmc_pre_req(struct mmc_host * mmc,struct mmc_request * mrq)273 static void meson_mmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
274 {
275 struct mmc_data *data = mrq->data;
276
277 if (!data)
278 return;
279
280 meson_mmc_get_transfer_mode(mmc, mrq);
281 data->host_cookie |= SD_EMMC_PRE_REQ_DONE;
282
283 if (!meson_mmc_desc_chain_mode(data))
284 return;
285
286 data->sg_count = dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len,
287 mmc_get_dma_dir(data));
288 if (!data->sg_count)
289 dev_err(mmc_dev(mmc), "dma_map_sg failed");
290 }
291
meson_mmc_post_req(struct mmc_host * mmc,struct mmc_request * mrq,int err)292 static void meson_mmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
293 int err)
294 {
295 struct mmc_data *data = mrq->data;
296
297 if (data && meson_mmc_desc_chain_mode(data) && data->sg_count)
298 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len,
299 mmc_get_dma_dir(data));
300 }
301
302 /*
303 * Gating the clock on this controller is tricky. It seems the mmc clock
304 * is also used by the controller. It may crash during some operation if the
305 * clock is stopped. The safest thing to do, whenever possible, is to keep
306 * clock running at stop it at the pad using the pinmux.
307 */
meson_mmc_clk_gate(struct meson_host * host)308 static void meson_mmc_clk_gate(struct meson_host *host)
309 {
310 u32 cfg;
311
312 if (host->pins_clk_gate) {
313 pinctrl_select_state(host->pinctrl, host->pins_clk_gate);
314 } else {
315 /*
316 * If the pinmux is not provided - default to the classic and
317 * unsafe method
318 */
319 cfg = readl(host->regs + SD_EMMC_CFG);
320 cfg |= CFG_STOP_CLOCK;
321 writel(cfg, host->regs + SD_EMMC_CFG);
322 }
323 }
324
meson_mmc_clk_ungate(struct meson_host * host)325 static void meson_mmc_clk_ungate(struct meson_host *host)
326 {
327 u32 cfg;
328
329 if (host->pins_clk_gate)
330 pinctrl_select_default_state(host->dev);
331
332 /* Make sure the clock is not stopped in the controller */
333 cfg = readl(host->regs + SD_EMMC_CFG);
334 cfg &= ~CFG_STOP_CLOCK;
335 writel(cfg, host->regs + SD_EMMC_CFG);
336 }
337
meson_mmc_clk_set(struct meson_host * host,unsigned long rate,bool ddr)338 static int meson_mmc_clk_set(struct meson_host *host, unsigned long rate,
339 bool ddr)
340 {
341 struct mmc_host *mmc = host->mmc;
342 int ret;
343 u32 cfg;
344
345 /* Same request - bail-out */
346 if (host->ddr == ddr && host->req_rate == rate)
347 return 0;
348
349 /* stop clock */
350 meson_mmc_clk_gate(host);
351 host->req_rate = 0;
352 mmc->actual_clock = 0;
353
354 /* return with clock being stopped */
355 if (!rate)
356 return 0;
357
358 /* Stop the clock during rate change to avoid glitches */
359 cfg = readl(host->regs + SD_EMMC_CFG);
360 cfg |= CFG_STOP_CLOCK;
361 writel(cfg, host->regs + SD_EMMC_CFG);
362
363 if (ddr) {
364 /* DDR modes require higher module clock */
365 rate <<= 1;
366 cfg |= CFG_DDR;
367 } else {
368 cfg &= ~CFG_DDR;
369 }
370 writel(cfg, host->regs + SD_EMMC_CFG);
371 host->ddr = ddr;
372
373 ret = clk_set_rate(host->mmc_clk, rate);
374 if (ret) {
375 dev_err(host->dev, "Unable to set cfg_div_clk to %lu. ret=%d\n",
376 rate, ret);
377 return ret;
378 }
379
380 host->req_rate = rate;
381 mmc->actual_clock = clk_get_rate(host->mmc_clk);
382
383 /* We should report the real output frequency of the controller */
384 if (ddr) {
385 host->req_rate >>= 1;
386 mmc->actual_clock >>= 1;
387 }
388
389 dev_dbg(host->dev, "clk rate: %u Hz\n", mmc->actual_clock);
390 if (rate != mmc->actual_clock)
391 dev_dbg(host->dev, "requested rate was %lu\n", rate);
392
393 /* (re)start clock */
394 meson_mmc_clk_ungate(host);
395
396 return 0;
397 }
398
399 /*
400 * The SD/eMMC IP block has an internal mux and divider used for
401 * generating the MMC clock. Use the clock framework to create and
402 * manage these clocks.
403 */
meson_mmc_clk_init(struct meson_host * host)404 static int meson_mmc_clk_init(struct meson_host *host)
405 {
406 struct clk_init_data init;
407 struct clk_mux *mux;
408 struct clk_divider *div;
409 char clk_name[32];
410 int i, ret = 0;
411 const char *mux_parent_names[MUX_CLK_NUM_PARENTS];
412 const char *clk_parent[1];
413 u32 clk_reg;
414
415 /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
416 clk_reg = CLK_ALWAYS_ON(host);
417 clk_reg |= CLK_DIV_MASK;
418 clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180);
419 clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0);
420 clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
421 writel(clk_reg, host->regs + SD_EMMC_CLOCK);
422
423 /* get the mux parents */
424 for (i = 0; i < MUX_CLK_NUM_PARENTS; i++) {
425 struct clk *clk;
426 char name[16];
427
428 snprintf(name, sizeof(name), "clkin%d", i);
429 clk = devm_clk_get(host->dev, name);
430 if (IS_ERR(clk))
431 return dev_err_probe(host->dev, PTR_ERR(clk),
432 "Missing clock %s\n", name);
433
434 mux_parent_names[i] = __clk_get_name(clk);
435 }
436
437 /* create the mux */
438 mux = devm_kzalloc(host->dev, sizeof(*mux), GFP_KERNEL);
439 if (!mux)
440 return -ENOMEM;
441
442 snprintf(clk_name, sizeof(clk_name), "%s#mux", dev_name(host->dev));
443 init.name = clk_name;
444 init.ops = &clk_mux_ops;
445 init.flags = 0;
446 init.parent_names = mux_parent_names;
447 init.num_parents = MUX_CLK_NUM_PARENTS;
448
449 mux->reg = host->regs + SD_EMMC_CLOCK;
450 mux->shift = __ffs(CLK_SRC_MASK);
451 mux->mask = CLK_SRC_MASK >> mux->shift;
452 mux->hw.init = &init;
453
454 host->mux_clk = devm_clk_register(host->dev, &mux->hw);
455 if (WARN_ON(IS_ERR(host->mux_clk)))
456 return PTR_ERR(host->mux_clk);
457
458 /* create the divider */
459 div = devm_kzalloc(host->dev, sizeof(*div), GFP_KERNEL);
460 if (!div)
461 return -ENOMEM;
462
463 snprintf(clk_name, sizeof(clk_name), "%s#div", dev_name(host->dev));
464 init.name = clk_name;
465 init.ops = &clk_divider_ops;
466 init.flags = CLK_SET_RATE_PARENT;
467 clk_parent[0] = __clk_get_name(host->mux_clk);
468 init.parent_names = clk_parent;
469 init.num_parents = 1;
470
471 div->reg = host->regs + SD_EMMC_CLOCK;
472 div->shift = __ffs(CLK_DIV_MASK);
473 div->width = __builtin_popcountl(CLK_DIV_MASK);
474 div->hw.init = &init;
475 div->flags = CLK_DIVIDER_ONE_BASED;
476
477 host->mmc_clk = devm_clk_register(host->dev, &div->hw);
478 if (WARN_ON(IS_ERR(host->mmc_clk)))
479 return PTR_ERR(host->mmc_clk);
480
481 /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
482 host->mmc->f_min = clk_round_rate(host->mmc_clk, 400000);
483 ret = clk_set_rate(host->mmc_clk, host->mmc->f_min);
484 if (ret)
485 return ret;
486
487 return clk_prepare_enable(host->mmc_clk);
488 }
489
meson_mmc_disable_resampling(struct meson_host * host)490 static void meson_mmc_disable_resampling(struct meson_host *host)
491 {
492 unsigned int val = readl(host->regs + host->data->adjust);
493
494 val &= ~ADJUST_ADJ_EN;
495 writel(val, host->regs + host->data->adjust);
496 }
497
meson_mmc_reset_resampling(struct meson_host * host)498 static void meson_mmc_reset_resampling(struct meson_host *host)
499 {
500 unsigned int val;
501
502 meson_mmc_disable_resampling(host);
503
504 val = readl(host->regs + host->data->adjust);
505 val &= ~ADJUST_ADJ_DELAY_MASK;
506 writel(val, host->regs + host->data->adjust);
507 }
508
meson_mmc_resampling_tuning(struct mmc_host * mmc,u32 opcode)509 static int meson_mmc_resampling_tuning(struct mmc_host *mmc, u32 opcode)
510 {
511 struct meson_host *host = mmc_priv(mmc);
512 unsigned int val, dly, max_dly, i;
513 int ret;
514
515 /* Resampling is done using the source clock */
516 max_dly = DIV_ROUND_UP(clk_get_rate(host->mux_clk),
517 clk_get_rate(host->mmc_clk));
518
519 val = readl(host->regs + host->data->adjust);
520 val |= ADJUST_ADJ_EN;
521 writel(val, host->regs + host->data->adjust);
522
523 if (mmc_doing_retune(mmc))
524 dly = FIELD_GET(ADJUST_ADJ_DELAY_MASK, val) + 1;
525 else
526 dly = 0;
527
528 for (i = 0; i < max_dly; i++) {
529 val &= ~ADJUST_ADJ_DELAY_MASK;
530 val |= FIELD_PREP(ADJUST_ADJ_DELAY_MASK, (dly + i) % max_dly);
531 writel(val, host->regs + host->data->adjust);
532
533 ret = mmc_send_tuning(mmc, opcode, NULL);
534 if (!ret) {
535 dev_dbg(mmc_dev(mmc), "resampling delay: %u\n",
536 (dly + i) % max_dly);
537 return 0;
538 }
539 }
540
541 meson_mmc_reset_resampling(host);
542 return -EIO;
543 }
544
meson_mmc_prepare_ios_clock(struct meson_host * host,struct mmc_ios * ios)545 static int meson_mmc_prepare_ios_clock(struct meson_host *host,
546 struct mmc_ios *ios)
547 {
548 bool ddr;
549
550 switch (ios->timing) {
551 case MMC_TIMING_MMC_DDR52:
552 case MMC_TIMING_UHS_DDR50:
553 ddr = true;
554 break;
555
556 default:
557 ddr = false;
558 break;
559 }
560
561 return meson_mmc_clk_set(host, ios->clock, ddr);
562 }
563
meson_mmc_check_resampling(struct meson_host * host,struct mmc_ios * ios)564 static void meson_mmc_check_resampling(struct meson_host *host,
565 struct mmc_ios *ios)
566 {
567 switch (ios->timing) {
568 case MMC_TIMING_LEGACY:
569 case MMC_TIMING_MMC_HS:
570 case MMC_TIMING_SD_HS:
571 case MMC_TIMING_MMC_DDR52:
572 meson_mmc_disable_resampling(host);
573 break;
574 }
575 }
576
meson_mmc_set_ios(struct mmc_host * mmc,struct mmc_ios * ios)577 static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
578 {
579 struct meson_host *host = mmc_priv(mmc);
580 u32 bus_width, val;
581 int err;
582
583 /*
584 * GPIO regulator, only controls switching between 1v8 and
585 * 3v3, doesn't support MMC_POWER_OFF, MMC_POWER_ON.
586 */
587 switch (ios->power_mode) {
588 case MMC_POWER_OFF:
589 if (!IS_ERR(mmc->supply.vmmc))
590 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
591
592 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
593 regulator_disable(mmc->supply.vqmmc);
594 host->vqmmc_enabled = false;
595 }
596
597 break;
598
599 case MMC_POWER_UP:
600 if (!IS_ERR(mmc->supply.vmmc))
601 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
602
603 break;
604
605 case MMC_POWER_ON:
606 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
607 int ret = regulator_enable(mmc->supply.vqmmc);
608
609 if (ret < 0)
610 dev_err(host->dev,
611 "failed to enable vqmmc regulator\n");
612 else
613 host->vqmmc_enabled = true;
614 }
615
616 break;
617 }
618
619 /* Bus width */
620 switch (ios->bus_width) {
621 case MMC_BUS_WIDTH_1:
622 bus_width = CFG_BUS_WIDTH_1;
623 break;
624 case MMC_BUS_WIDTH_4:
625 bus_width = CFG_BUS_WIDTH_4;
626 break;
627 case MMC_BUS_WIDTH_8:
628 bus_width = CFG_BUS_WIDTH_8;
629 break;
630 default:
631 dev_err(host->dev, "Invalid ios->bus_width: %u. Setting to 4.\n",
632 ios->bus_width);
633 bus_width = CFG_BUS_WIDTH_4;
634 }
635
636 val = readl(host->regs + SD_EMMC_CFG);
637 val &= ~CFG_BUS_WIDTH_MASK;
638 val |= FIELD_PREP(CFG_BUS_WIDTH_MASK, bus_width);
639 writel(val, host->regs + SD_EMMC_CFG);
640
641 meson_mmc_check_resampling(host, ios);
642 err = meson_mmc_prepare_ios_clock(host, ios);
643 if (err)
644 dev_err(host->dev, "Failed to set clock: %d\n,", err);
645
646 dev_dbg(host->dev, "SD_EMMC_CFG: 0x%08x\n", val);
647 }
648
meson_mmc_request_done(struct mmc_host * mmc,struct mmc_request * mrq)649 static void meson_mmc_request_done(struct mmc_host *mmc,
650 struct mmc_request *mrq)
651 {
652 struct meson_host *host = mmc_priv(mmc);
653
654 host->cmd = NULL;
655 mmc_request_done(host->mmc, mrq);
656 }
657
meson_mmc_set_blksz(struct mmc_host * mmc,unsigned int blksz)658 static void meson_mmc_set_blksz(struct mmc_host *mmc, unsigned int blksz)
659 {
660 struct meson_host *host = mmc_priv(mmc);
661 u32 cfg, blksz_old;
662
663 cfg = readl(host->regs + SD_EMMC_CFG);
664 blksz_old = FIELD_GET(CFG_BLK_LEN_MASK, cfg);
665
666 if (!is_power_of_2(blksz))
667 dev_err(host->dev, "blksz %u is not a power of 2\n", blksz);
668
669 blksz = ilog2(blksz);
670
671 /* check if block-size matches, if not update */
672 if (blksz == blksz_old)
673 return;
674
675 dev_dbg(host->dev, "%s: update blk_len %d -> %d\n", __func__,
676 blksz_old, blksz);
677
678 cfg &= ~CFG_BLK_LEN_MASK;
679 cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, blksz);
680 writel(cfg, host->regs + SD_EMMC_CFG);
681 }
682
meson_mmc_set_response_bits(struct mmc_command * cmd,u32 * cmd_cfg)683 static void meson_mmc_set_response_bits(struct mmc_command *cmd, u32 *cmd_cfg)
684 {
685 if (cmd->flags & MMC_RSP_PRESENT) {
686 if (cmd->flags & MMC_RSP_136)
687 *cmd_cfg |= CMD_CFG_RESP_128;
688 *cmd_cfg |= CMD_CFG_RESP_NUM;
689
690 if (!(cmd->flags & MMC_RSP_CRC))
691 *cmd_cfg |= CMD_CFG_RESP_NOCRC;
692
693 if (cmd->flags & MMC_RSP_BUSY)
694 *cmd_cfg |= CMD_CFG_R1B;
695 } else {
696 *cmd_cfg |= CMD_CFG_NO_RESP;
697 }
698 }
699
meson_mmc_desc_chain_transfer(struct mmc_host * mmc,u32 cmd_cfg)700 static void meson_mmc_desc_chain_transfer(struct mmc_host *mmc, u32 cmd_cfg)
701 {
702 struct meson_host *host = mmc_priv(mmc);
703 struct sd_emmc_desc *desc = host->descs;
704 struct mmc_data *data = host->cmd->data;
705 struct scatterlist *sg;
706 u32 start;
707 int i;
708
709 if (data->flags & MMC_DATA_WRITE)
710 cmd_cfg |= CMD_CFG_DATA_WR;
711
712 if (data->blocks > 1) {
713 cmd_cfg |= CMD_CFG_BLOCK_MODE;
714 meson_mmc_set_blksz(mmc, data->blksz);
715 }
716
717 for_each_sg(data->sg, sg, data->sg_count, i) {
718 unsigned int len = sg_dma_len(sg);
719
720 if (data->blocks > 1)
721 len /= data->blksz;
722
723 desc[i].cmd_cfg = cmd_cfg;
724 desc[i].cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, len);
725 if (i > 0)
726 desc[i].cmd_cfg |= CMD_CFG_NO_CMD;
727 desc[i].cmd_arg = host->cmd->arg;
728 desc[i].cmd_resp = 0;
729 desc[i].cmd_data = sg_dma_address(sg);
730 }
731 desc[data->sg_count - 1].cmd_cfg |= CMD_CFG_END_OF_CHAIN;
732
733 dma_wmb(); /* ensure descriptor is written before kicked */
734 start = host->descs_dma_addr | START_DESC_BUSY;
735 writel(start, host->regs + SD_EMMC_START);
736 }
737
738 /* local sg copy for dram_access_quirk */
meson_mmc_copy_buffer(struct meson_host * host,struct mmc_data * data,size_t buflen,bool to_buffer)739 static void meson_mmc_copy_buffer(struct meson_host *host, struct mmc_data *data,
740 size_t buflen, bool to_buffer)
741 {
742 unsigned int sg_flags = SG_MITER_ATOMIC;
743 struct scatterlist *sgl = data->sg;
744 unsigned int nents = data->sg_len;
745 struct sg_mapping_iter miter;
746 unsigned int offset = 0;
747
748 if (to_buffer)
749 sg_flags |= SG_MITER_FROM_SG;
750 else
751 sg_flags |= SG_MITER_TO_SG;
752
753 sg_miter_start(&miter, sgl, nents, sg_flags);
754
755 while ((offset < buflen) && sg_miter_next(&miter)) {
756 unsigned int buf_offset = 0;
757 unsigned int len, left;
758 u32 *buf = miter.addr;
759
760 len = min(miter.length, buflen - offset);
761 left = len;
762
763 if (to_buffer) {
764 do {
765 writel(*buf++, host->bounce_iomem_buf + offset + buf_offset);
766
767 buf_offset += 4;
768 left -= 4;
769 } while (left);
770 } else {
771 do {
772 *buf++ = readl(host->bounce_iomem_buf + offset + buf_offset);
773
774 buf_offset += 4;
775 left -= 4;
776 } while (left);
777 }
778
779 offset += len;
780 }
781
782 sg_miter_stop(&miter);
783 }
784
meson_mmc_start_cmd(struct mmc_host * mmc,struct mmc_command * cmd)785 static void meson_mmc_start_cmd(struct mmc_host *mmc, struct mmc_command *cmd)
786 {
787 struct meson_host *host = mmc_priv(mmc);
788 struct mmc_data *data = cmd->data;
789 u32 cmd_cfg = 0, cmd_data = 0;
790 unsigned int xfer_bytes = 0;
791
792 /* Setup descriptors */
793 dma_rmb();
794
795 host->cmd = cmd;
796
797 cmd_cfg |= FIELD_PREP(CMD_CFG_CMD_INDEX_MASK, cmd->opcode);
798 cmd_cfg |= CMD_CFG_OWNER; /* owned by CPU */
799 cmd_cfg |= CMD_CFG_ERROR; /* stop in case of error */
800
801 meson_mmc_set_response_bits(cmd, &cmd_cfg);
802
803 /* data? */
804 if (data) {
805 data->bytes_xfered = 0;
806 cmd_cfg |= CMD_CFG_DATA_IO;
807 cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK,
808 ilog2(meson_mmc_get_timeout_msecs(data)));
809
810 if (meson_mmc_desc_chain_mode(data)) {
811 meson_mmc_desc_chain_transfer(mmc, cmd_cfg);
812 return;
813 }
814
815 if (data->blocks > 1) {
816 cmd_cfg |= CMD_CFG_BLOCK_MODE;
817 cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK,
818 data->blocks);
819 meson_mmc_set_blksz(mmc, data->blksz);
820 } else {
821 cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, data->blksz);
822 }
823
824 xfer_bytes = data->blksz * data->blocks;
825 if (data->flags & MMC_DATA_WRITE) {
826 cmd_cfg |= CMD_CFG_DATA_WR;
827 WARN_ON(xfer_bytes > host->bounce_buf_size);
828 if (host->dram_access_quirk)
829 meson_mmc_copy_buffer(host, data, xfer_bytes, true);
830 else
831 sg_copy_to_buffer(data->sg, data->sg_len,
832 host->bounce_buf, xfer_bytes);
833 dma_wmb();
834 }
835
836 cmd_data = host->bounce_dma_addr & CMD_DATA_MASK;
837 } else {
838 cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK,
839 ilog2(SD_EMMC_CMD_TIMEOUT));
840 }
841
842 /* Last descriptor */
843 cmd_cfg |= CMD_CFG_END_OF_CHAIN;
844 writel(cmd_cfg, host->regs + SD_EMMC_CMD_CFG);
845 writel(cmd_data, host->regs + SD_EMMC_CMD_DAT);
846 writel(0, host->regs + SD_EMMC_CMD_RSP);
847 wmb(); /* ensure descriptor is written before kicked */
848 writel(cmd->arg, host->regs + SD_EMMC_CMD_ARG);
849 }
850
meson_mmc_validate_dram_access(struct mmc_host * mmc,struct mmc_data * data)851 static int meson_mmc_validate_dram_access(struct mmc_host *mmc, struct mmc_data *data)
852 {
853 struct scatterlist *sg;
854 int i;
855
856 /* Reject request if any element offset or size is not 32bit aligned */
857 for_each_sg(data->sg, sg, data->sg_len, i) {
858 if (!IS_ALIGNED(sg->offset, sizeof(u32)) ||
859 !IS_ALIGNED(sg->length, sizeof(u32))) {
860 dev_err(mmc_dev(mmc), "unaligned sg offset %u len %u\n",
861 data->sg->offset, data->sg->length);
862 return -EINVAL;
863 }
864 }
865
866 return 0;
867 }
868
meson_mmc_request(struct mmc_host * mmc,struct mmc_request * mrq)869 static void meson_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
870 {
871 struct meson_host *host = mmc_priv(mmc);
872 bool needs_pre_post_req = mrq->data &&
873 !(mrq->data->host_cookie & SD_EMMC_PRE_REQ_DONE);
874
875 /*
876 * The memory at the end of the controller used as bounce buffer for
877 * the dram_access_quirk only accepts 32bit read/write access,
878 * check the aligment and length of the data before starting the request.
879 */
880 if (host->dram_access_quirk && mrq->data) {
881 mrq->cmd->error = meson_mmc_validate_dram_access(mmc, mrq->data);
882 if (mrq->cmd->error) {
883 mmc_request_done(mmc, mrq);
884 return;
885 }
886 }
887
888 if (needs_pre_post_req) {
889 meson_mmc_get_transfer_mode(mmc, mrq);
890 if (!meson_mmc_desc_chain_mode(mrq->data))
891 needs_pre_post_req = false;
892 }
893
894 if (needs_pre_post_req)
895 meson_mmc_pre_req(mmc, mrq);
896
897 /* Stop execution */
898 writel(0, host->regs + SD_EMMC_START);
899
900 meson_mmc_start_cmd(mmc, mrq->sbc ?: mrq->cmd);
901
902 if (needs_pre_post_req)
903 meson_mmc_post_req(mmc, mrq, 0);
904 }
905
meson_mmc_read_resp(struct mmc_host * mmc,struct mmc_command * cmd)906 static void meson_mmc_read_resp(struct mmc_host *mmc, struct mmc_command *cmd)
907 {
908 struct meson_host *host = mmc_priv(mmc);
909
910 if (cmd->flags & MMC_RSP_136) {
911 cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP3);
912 cmd->resp[1] = readl(host->regs + SD_EMMC_CMD_RSP2);
913 cmd->resp[2] = readl(host->regs + SD_EMMC_CMD_RSP1);
914 cmd->resp[3] = readl(host->regs + SD_EMMC_CMD_RSP);
915 } else if (cmd->flags & MMC_RSP_PRESENT) {
916 cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP);
917 }
918 }
919
meson_mmc_irq(int irq,void * dev_id)920 static irqreturn_t meson_mmc_irq(int irq, void *dev_id)
921 {
922 struct meson_host *host = dev_id;
923 struct mmc_command *cmd;
924 struct mmc_data *data;
925 u32 irq_en, status, raw_status;
926 irqreturn_t ret = IRQ_NONE;
927
928 irq_en = readl(host->regs + SD_EMMC_IRQ_EN);
929 raw_status = readl(host->regs + SD_EMMC_STATUS);
930 status = raw_status & irq_en;
931
932 if (!status) {
933 dev_dbg(host->dev,
934 "Unexpected IRQ! irq_en 0x%08x - status 0x%08x\n",
935 irq_en, raw_status);
936 return IRQ_NONE;
937 }
938
939 if (WARN_ON(!host) || WARN_ON(!host->cmd))
940 return IRQ_NONE;
941
942 /* ack all raised interrupts */
943 writel(status, host->regs + SD_EMMC_STATUS);
944
945 cmd = host->cmd;
946 data = cmd->data;
947 cmd->error = 0;
948 if (status & IRQ_CRC_ERR) {
949 dev_dbg(host->dev, "CRC Error - status 0x%08x\n", status);
950 cmd->error = -EILSEQ;
951 ret = IRQ_WAKE_THREAD;
952 goto out;
953 }
954
955 if (status & IRQ_TIMEOUTS) {
956 dev_dbg(host->dev, "Timeout - status 0x%08x\n", status);
957 cmd->error = -ETIMEDOUT;
958 ret = IRQ_WAKE_THREAD;
959 goto out;
960 }
961
962 meson_mmc_read_resp(host->mmc, cmd);
963
964 if (status & IRQ_SDIO) {
965 dev_dbg(host->dev, "IRQ: SDIO TODO.\n");
966 ret = IRQ_HANDLED;
967 }
968
969 if (status & (IRQ_END_OF_CHAIN | IRQ_RESP_STATUS)) {
970 if (data && !cmd->error)
971 data->bytes_xfered = data->blksz * data->blocks;
972 if (meson_mmc_bounce_buf_read(data) ||
973 meson_mmc_get_next_command(cmd))
974 ret = IRQ_WAKE_THREAD;
975 else
976 ret = IRQ_HANDLED;
977 }
978
979 out:
980 if (cmd->error) {
981 /* Stop desc in case of errors */
982 u32 start = readl(host->regs + SD_EMMC_START);
983
984 start &= ~START_DESC_BUSY;
985 writel(start, host->regs + SD_EMMC_START);
986 }
987
988 if (ret == IRQ_HANDLED)
989 meson_mmc_request_done(host->mmc, cmd->mrq);
990
991 return ret;
992 }
993
meson_mmc_wait_desc_stop(struct meson_host * host)994 static int meson_mmc_wait_desc_stop(struct meson_host *host)
995 {
996 u32 status;
997
998 /*
999 * It may sometimes take a while for it to actually halt. Here, we
1000 * are giving it 5ms to comply
1001 *
1002 * If we don't confirm the descriptor is stopped, it might raise new
1003 * IRQs after we have called mmc_request_done() which is bad.
1004 */
1005
1006 return readl_poll_timeout(host->regs + SD_EMMC_STATUS, status,
1007 !(status & (STATUS_BUSY | STATUS_DESC_BUSY)),
1008 100, 5000);
1009 }
1010
meson_mmc_irq_thread(int irq,void * dev_id)1011 static irqreturn_t meson_mmc_irq_thread(int irq, void *dev_id)
1012 {
1013 struct meson_host *host = dev_id;
1014 struct mmc_command *next_cmd, *cmd = host->cmd;
1015 struct mmc_data *data;
1016 unsigned int xfer_bytes;
1017
1018 if (WARN_ON(!cmd))
1019 return IRQ_NONE;
1020
1021 if (cmd->error) {
1022 meson_mmc_wait_desc_stop(host);
1023 meson_mmc_request_done(host->mmc, cmd->mrq);
1024
1025 return IRQ_HANDLED;
1026 }
1027
1028 data = cmd->data;
1029 if (meson_mmc_bounce_buf_read(data)) {
1030 xfer_bytes = data->blksz * data->blocks;
1031 WARN_ON(xfer_bytes > host->bounce_buf_size);
1032 if (host->dram_access_quirk)
1033 meson_mmc_copy_buffer(host, data, xfer_bytes, false);
1034 else
1035 sg_copy_from_buffer(data->sg, data->sg_len,
1036 host->bounce_buf, xfer_bytes);
1037 }
1038
1039 next_cmd = meson_mmc_get_next_command(cmd);
1040 if (next_cmd)
1041 meson_mmc_start_cmd(host->mmc, next_cmd);
1042 else
1043 meson_mmc_request_done(host->mmc, cmd->mrq);
1044
1045 return IRQ_HANDLED;
1046 }
1047
1048 /*
1049 * NOTE: we only need this until the GPIO/pinctrl driver can handle
1050 * interrupts. For now, the MMC core will use this for polling.
1051 */
meson_mmc_get_cd(struct mmc_host * mmc)1052 static int meson_mmc_get_cd(struct mmc_host *mmc)
1053 {
1054 int status = mmc_gpio_get_cd(mmc);
1055
1056 if (status == -ENOSYS)
1057 return 1; /* assume present */
1058
1059 return status;
1060 }
1061
meson_mmc_cfg_init(struct meson_host * host)1062 static void meson_mmc_cfg_init(struct meson_host *host)
1063 {
1064 u32 cfg = 0;
1065
1066 cfg |= FIELD_PREP(CFG_RESP_TIMEOUT_MASK,
1067 ilog2(SD_EMMC_CFG_RESP_TIMEOUT));
1068 cfg |= FIELD_PREP(CFG_RC_CC_MASK, ilog2(SD_EMMC_CFG_CMD_GAP));
1069 cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, ilog2(SD_EMMC_CFG_BLK_SIZE));
1070
1071 /* abort chain on R/W errors */
1072 cfg |= CFG_ERR_ABORT;
1073
1074 writel(cfg, host->regs + SD_EMMC_CFG);
1075 }
1076
meson_mmc_card_busy(struct mmc_host * mmc)1077 static int meson_mmc_card_busy(struct mmc_host *mmc)
1078 {
1079 struct meson_host *host = mmc_priv(mmc);
1080 u32 regval;
1081
1082 regval = readl(host->regs + SD_EMMC_STATUS);
1083
1084 /* We are only interrested in lines 0 to 3, so mask the other ones */
1085 return !(FIELD_GET(STATUS_DATI, regval) & 0xf);
1086 }
1087
meson_mmc_voltage_switch(struct mmc_host * mmc,struct mmc_ios * ios)1088 static int meson_mmc_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios)
1089 {
1090 int ret;
1091
1092 /* vqmmc regulator is available */
1093 if (!IS_ERR(mmc->supply.vqmmc)) {
1094 /*
1095 * The usual amlogic setup uses a GPIO to switch from one
1096 * regulator to the other. While the voltage ramp up is
1097 * pretty fast, care must be taken when switching from 3.3v
1098 * to 1.8v. Please make sure the regulator framework is aware
1099 * of your own regulator constraints
1100 */
1101 ret = mmc_regulator_set_vqmmc(mmc, ios);
1102 return ret < 0 ? ret : 0;
1103 }
1104
1105 /* no vqmmc regulator, assume fixed regulator at 3/3.3V */
1106 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1107 return 0;
1108
1109 return -EINVAL;
1110 }
1111
1112 static const struct mmc_host_ops meson_mmc_ops = {
1113 .request = meson_mmc_request,
1114 .set_ios = meson_mmc_set_ios,
1115 .get_cd = meson_mmc_get_cd,
1116 .pre_req = meson_mmc_pre_req,
1117 .post_req = meson_mmc_post_req,
1118 .execute_tuning = meson_mmc_resampling_tuning,
1119 .card_busy = meson_mmc_card_busy,
1120 .start_signal_voltage_switch = meson_mmc_voltage_switch,
1121 };
1122
meson_mmc_probe(struct platform_device * pdev)1123 static int meson_mmc_probe(struct platform_device *pdev)
1124 {
1125 struct resource *res;
1126 struct meson_host *host;
1127 struct mmc_host *mmc;
1128 int ret;
1129
1130 mmc = mmc_alloc_host(sizeof(struct meson_host), &pdev->dev);
1131 if (!mmc)
1132 return -ENOMEM;
1133 host = mmc_priv(mmc);
1134 host->mmc = mmc;
1135 host->dev = &pdev->dev;
1136 dev_set_drvdata(&pdev->dev, host);
1137
1138 /* The G12A SDIO Controller needs an SRAM bounce buffer */
1139 host->dram_access_quirk = device_property_read_bool(&pdev->dev,
1140 "amlogic,dram-access-quirk");
1141
1142 /* Get regulators and the supported OCR mask */
1143 host->vqmmc_enabled = false;
1144 ret = mmc_regulator_get_supply(mmc);
1145 if (ret)
1146 goto free_host;
1147
1148 ret = mmc_of_parse(mmc);
1149 if (ret) {
1150 if (ret != -EPROBE_DEFER)
1151 dev_warn(&pdev->dev, "error parsing DT: %d\n", ret);
1152 goto free_host;
1153 }
1154
1155 host->data = (struct meson_mmc_data *)
1156 of_device_get_match_data(&pdev->dev);
1157 if (!host->data) {
1158 ret = -EINVAL;
1159 goto free_host;
1160 }
1161
1162 ret = device_reset_optional(&pdev->dev);
1163 if (ret)
1164 return dev_err_probe(&pdev->dev, ret, "device reset failed\n");
1165
1166 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1167 host->regs = devm_ioremap_resource(&pdev->dev, res);
1168 if (IS_ERR(host->regs)) {
1169 ret = PTR_ERR(host->regs);
1170 goto free_host;
1171 }
1172
1173 host->irq = platform_get_irq(pdev, 0);
1174 if (host->irq <= 0) {
1175 ret = -EINVAL;
1176 goto free_host;
1177 }
1178
1179 host->pinctrl = devm_pinctrl_get(&pdev->dev);
1180 if (IS_ERR(host->pinctrl)) {
1181 ret = PTR_ERR(host->pinctrl);
1182 goto free_host;
1183 }
1184
1185 host->pins_clk_gate = pinctrl_lookup_state(host->pinctrl,
1186 "clk-gate");
1187 if (IS_ERR(host->pins_clk_gate)) {
1188 dev_warn(&pdev->dev,
1189 "can't get clk-gate pinctrl, using clk_stop bit\n");
1190 host->pins_clk_gate = NULL;
1191 }
1192
1193 host->core_clk = devm_clk_get(&pdev->dev, "core");
1194 if (IS_ERR(host->core_clk)) {
1195 ret = PTR_ERR(host->core_clk);
1196 goto free_host;
1197 }
1198
1199 ret = clk_prepare_enable(host->core_clk);
1200 if (ret)
1201 goto free_host;
1202
1203 ret = meson_mmc_clk_init(host);
1204 if (ret)
1205 goto err_core_clk;
1206
1207 /* set config to sane default */
1208 meson_mmc_cfg_init(host);
1209
1210 /* Stop execution */
1211 writel(0, host->regs + SD_EMMC_START);
1212
1213 /* clear, ack and enable interrupts */
1214 writel(0, host->regs + SD_EMMC_IRQ_EN);
1215 writel(IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN,
1216 host->regs + SD_EMMC_STATUS);
1217 writel(IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN,
1218 host->regs + SD_EMMC_IRQ_EN);
1219
1220 ret = request_threaded_irq(host->irq, meson_mmc_irq,
1221 meson_mmc_irq_thread, IRQF_ONESHOT,
1222 dev_name(&pdev->dev), host);
1223 if (ret)
1224 goto err_init_clk;
1225
1226 mmc->caps |= MMC_CAP_CMD23;
1227 if (host->dram_access_quirk) {
1228 /* Limit segments to 1 due to low available sram memory */
1229 mmc->max_segs = 1;
1230 /* Limit to the available sram memory */
1231 mmc->max_blk_count = SD_EMMC_SRAM_DATA_BUF_LEN /
1232 mmc->max_blk_size;
1233 } else {
1234 mmc->max_blk_count = CMD_CFG_LENGTH_MASK;
1235 mmc->max_segs = SD_EMMC_DESC_BUF_LEN /
1236 sizeof(struct sd_emmc_desc);
1237 }
1238 mmc->max_req_size = mmc->max_blk_count * mmc->max_blk_size;
1239 mmc->max_seg_size = mmc->max_req_size;
1240
1241 /*
1242 * At the moment, we don't know how to reliably enable HS400.
1243 * From the different datasheets, it is not even clear if this mode
1244 * is officially supported by any of the SoCs
1245 */
1246 mmc->caps2 &= ~MMC_CAP2_HS400;
1247
1248 if (host->dram_access_quirk) {
1249 /*
1250 * The MMC Controller embeds 1,5KiB of internal SRAM
1251 * that can be used to be used as bounce buffer.
1252 * In the case of the G12A SDIO controller, use these
1253 * instead of the DDR memory
1254 */
1255 host->bounce_buf_size = SD_EMMC_SRAM_DATA_BUF_LEN;
1256 host->bounce_iomem_buf = host->regs + SD_EMMC_SRAM_DATA_BUF_OFF;
1257 host->bounce_dma_addr = res->start + SD_EMMC_SRAM_DATA_BUF_OFF;
1258 } else {
1259 /* data bounce buffer */
1260 host->bounce_buf_size = mmc->max_req_size;
1261 host->bounce_buf =
1262 dma_alloc_coherent(host->dev, host->bounce_buf_size,
1263 &host->bounce_dma_addr, GFP_KERNEL);
1264 if (host->bounce_buf == NULL) {
1265 dev_err(host->dev, "Unable to map allocate DMA bounce buffer.\n");
1266 ret = -ENOMEM;
1267 goto err_free_irq;
1268 }
1269 }
1270
1271 host->descs = dma_alloc_coherent(host->dev, SD_EMMC_DESC_BUF_LEN,
1272 &host->descs_dma_addr, GFP_KERNEL);
1273 if (!host->descs) {
1274 dev_err(host->dev, "Allocating descriptor DMA buffer failed\n");
1275 ret = -ENOMEM;
1276 goto err_bounce_buf;
1277 }
1278
1279 mmc->ops = &meson_mmc_ops;
1280 mmc_add_host(mmc);
1281
1282 return 0;
1283
1284 err_bounce_buf:
1285 if (!host->dram_access_quirk)
1286 dma_free_coherent(host->dev, host->bounce_buf_size,
1287 host->bounce_buf, host->bounce_dma_addr);
1288 err_free_irq:
1289 free_irq(host->irq, host);
1290 err_init_clk:
1291 clk_disable_unprepare(host->mmc_clk);
1292 err_core_clk:
1293 clk_disable_unprepare(host->core_clk);
1294 free_host:
1295 mmc_free_host(mmc);
1296 return ret;
1297 }
1298
meson_mmc_remove(struct platform_device * pdev)1299 static int meson_mmc_remove(struct platform_device *pdev)
1300 {
1301 struct meson_host *host = dev_get_drvdata(&pdev->dev);
1302
1303 mmc_remove_host(host->mmc);
1304
1305 /* disable interrupts */
1306 writel(0, host->regs + SD_EMMC_IRQ_EN);
1307 free_irq(host->irq, host);
1308
1309 dma_free_coherent(host->dev, SD_EMMC_DESC_BUF_LEN,
1310 host->descs, host->descs_dma_addr);
1311
1312 if (!host->dram_access_quirk)
1313 dma_free_coherent(host->dev, host->bounce_buf_size,
1314 host->bounce_buf, host->bounce_dma_addr);
1315
1316 clk_disable_unprepare(host->mmc_clk);
1317 clk_disable_unprepare(host->core_clk);
1318
1319 mmc_free_host(host->mmc);
1320 return 0;
1321 }
1322
1323 static const struct meson_mmc_data meson_gx_data = {
1324 .tx_delay_mask = CLK_V2_TX_DELAY_MASK,
1325 .rx_delay_mask = CLK_V2_RX_DELAY_MASK,
1326 .always_on = CLK_V2_ALWAYS_ON,
1327 .adjust = SD_EMMC_ADJUST,
1328 };
1329
1330 static const struct meson_mmc_data meson_axg_data = {
1331 .tx_delay_mask = CLK_V3_TX_DELAY_MASK,
1332 .rx_delay_mask = CLK_V3_RX_DELAY_MASK,
1333 .always_on = CLK_V3_ALWAYS_ON,
1334 .adjust = SD_EMMC_V3_ADJUST,
1335 };
1336
1337 static const struct of_device_id meson_mmc_of_match[] = {
1338 { .compatible = "amlogic,meson-gx-mmc", .data = &meson_gx_data },
1339 { .compatible = "amlogic,meson-gxbb-mmc", .data = &meson_gx_data },
1340 { .compatible = "amlogic,meson-gxl-mmc", .data = &meson_gx_data },
1341 { .compatible = "amlogic,meson-gxm-mmc", .data = &meson_gx_data },
1342 { .compatible = "amlogic,meson-axg-mmc", .data = &meson_axg_data },
1343 {}
1344 };
1345 MODULE_DEVICE_TABLE(of, meson_mmc_of_match);
1346
1347 static struct platform_driver meson_mmc_driver = {
1348 .probe = meson_mmc_probe,
1349 .remove = meson_mmc_remove,
1350 .driver = {
1351 .name = DRIVER_NAME,
1352 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1353 .of_match_table = of_match_ptr(meson_mmc_of_match),
1354 },
1355 };
1356
1357 module_platform_driver(meson_mmc_driver);
1358
1359 MODULE_DESCRIPTION("Amlogic S905*/GX*/AXG SD/eMMC driver");
1360 MODULE_AUTHOR("Kevin Hilman <khilman@baylibre.com>");
1361 MODULE_LICENSE("GPL v2");
1362