1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Marvell 88e6xxx Ethernet switch single-chip support
4 *
5 * Copyright (c) 2008 Marvell Semiconductor
6 *
7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
8 *
9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
11 */
12
13 #include <linux/bitfield.h>
14 #include <linux/delay.h>
15 #include <linux/etherdevice.h>
16 #include <linux/ethtool.h>
17 #include <linux/if_bridge.h>
18 #include <linux/interrupt.h>
19 #include <linux/irq.h>
20 #include <linux/irqdomain.h>
21 #include <linux/jiffies.h>
22 #include <linux/list.h>
23 #include <linux/mdio.h>
24 #include <linux/module.h>
25 #include <linux/of_device.h>
26 #include <linux/of_irq.h>
27 #include <linux/of_mdio.h>
28 #include <linux/platform_data/mv88e6xxx.h>
29 #include <linux/netdevice.h>
30 #include <linux/gpio/consumer.h>
31 #include <linux/phylink.h>
32 #include <net/dsa.h>
33
34 #include "chip.h"
35 #include "devlink.h"
36 #include "global1.h"
37 #include "global2.h"
38 #include "hwtstamp.h"
39 #include "phy.h"
40 #include "port.h"
41 #include "ptp.h"
42 #include "serdes.h"
43 #include "smi.h"
44
assert_reg_lock(struct mv88e6xxx_chip * chip)45 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
46 {
47 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
48 dev_err(chip->dev, "Switch registers lock not held!\n");
49 dump_stack();
50 }
51 }
52
mv88e6xxx_read(struct mv88e6xxx_chip * chip,int addr,int reg,u16 * val)53 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
54 {
55 int err;
56
57 assert_reg_lock(chip);
58
59 err = mv88e6xxx_smi_read(chip, addr, reg, val);
60 if (err)
61 return err;
62
63 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
64 addr, reg, *val);
65
66 return 0;
67 }
68
mv88e6xxx_write(struct mv88e6xxx_chip * chip,int addr,int reg,u16 val)69 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
70 {
71 int err;
72
73 assert_reg_lock(chip);
74
75 err = mv88e6xxx_smi_write(chip, addr, reg, val);
76 if (err)
77 return err;
78
79 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
80 addr, reg, val);
81
82 return 0;
83 }
84
mv88e6xxx_wait_mask(struct mv88e6xxx_chip * chip,int addr,int reg,u16 mask,u16 val)85 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
86 u16 mask, u16 val)
87 {
88 u16 data;
89 int err;
90 int i;
91
92 /* There's no bus specific operation to wait for a mask */
93 for (i = 0; i < 16; i++) {
94 err = mv88e6xxx_read(chip, addr, reg, &data);
95 if (err)
96 return err;
97
98 if ((data & mask) == val)
99 return 0;
100
101 usleep_range(1000, 2000);
102 }
103
104 dev_err(chip->dev, "Timeout while waiting for switch\n");
105 return -ETIMEDOUT;
106 }
107
mv88e6xxx_wait_bit(struct mv88e6xxx_chip * chip,int addr,int reg,int bit,int val)108 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
109 int bit, int val)
110 {
111 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit),
112 val ? BIT(bit) : 0x0000);
113 }
114
mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip * chip)115 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
116 {
117 struct mv88e6xxx_mdio_bus *mdio_bus;
118
119 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
120 list);
121 if (!mdio_bus)
122 return NULL;
123
124 return mdio_bus->bus;
125 }
126
mv88e6xxx_g1_irq_mask(struct irq_data * d)127 static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
128 {
129 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
130 unsigned int n = d->hwirq;
131
132 chip->g1_irq.masked |= (1 << n);
133 }
134
mv88e6xxx_g1_irq_unmask(struct irq_data * d)135 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
136 {
137 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
138 unsigned int n = d->hwirq;
139
140 chip->g1_irq.masked &= ~(1 << n);
141 }
142
mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip * chip)143 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip)
144 {
145 unsigned int nhandled = 0;
146 unsigned int sub_irq;
147 unsigned int n;
148 u16 reg;
149 u16 ctl1;
150 int err;
151
152 mv88e6xxx_reg_lock(chip);
153 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
154 mv88e6xxx_reg_unlock(chip);
155
156 if (err)
157 goto out;
158
159 do {
160 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
161 if (reg & (1 << n)) {
162 sub_irq = irq_find_mapping(chip->g1_irq.domain,
163 n);
164 handle_nested_irq(sub_irq);
165 ++nhandled;
166 }
167 }
168
169 mv88e6xxx_reg_lock(chip);
170 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1);
171 if (err)
172 goto unlock;
173 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
174 unlock:
175 mv88e6xxx_reg_unlock(chip);
176 if (err)
177 goto out;
178 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0);
179 } while (reg & ctl1);
180
181 out:
182 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
183 }
184
mv88e6xxx_g1_irq_thread_fn(int irq,void * dev_id)185 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
186 {
187 struct mv88e6xxx_chip *chip = dev_id;
188
189 return mv88e6xxx_g1_irq_thread_work(chip);
190 }
191
mv88e6xxx_g1_irq_bus_lock(struct irq_data * d)192 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
193 {
194 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
195
196 mv88e6xxx_reg_lock(chip);
197 }
198
mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data * d)199 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
200 {
201 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
202 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
203 u16 reg;
204 int err;
205
206 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®);
207 if (err)
208 goto out;
209
210 reg &= ~mask;
211 reg |= (~chip->g1_irq.masked & mask);
212
213 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
214 if (err)
215 goto out;
216
217 out:
218 mv88e6xxx_reg_unlock(chip);
219 }
220
221 static const struct irq_chip mv88e6xxx_g1_irq_chip = {
222 .name = "mv88e6xxx-g1",
223 .irq_mask = mv88e6xxx_g1_irq_mask,
224 .irq_unmask = mv88e6xxx_g1_irq_unmask,
225 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
226 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
227 };
228
mv88e6xxx_g1_irq_domain_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hwirq)229 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
230 unsigned int irq,
231 irq_hw_number_t hwirq)
232 {
233 struct mv88e6xxx_chip *chip = d->host_data;
234
235 irq_set_chip_data(irq, d->host_data);
236 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
237 irq_set_noprobe(irq);
238
239 return 0;
240 }
241
242 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
243 .map = mv88e6xxx_g1_irq_domain_map,
244 .xlate = irq_domain_xlate_twocell,
245 };
246
247 /* To be called with reg_lock held */
mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip * chip)248 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip)
249 {
250 int irq, virq;
251 u16 mask;
252
253 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
254 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
255 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
256
257 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
258 virq = irq_find_mapping(chip->g1_irq.domain, irq);
259 irq_dispose_mapping(virq);
260 }
261
262 irq_domain_remove(chip->g1_irq.domain);
263 }
264
mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip * chip)265 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
266 {
267 /*
268 * free_irq must be called without reg_lock taken because the irq
269 * handler takes this lock, too.
270 */
271 free_irq(chip->irq, chip);
272
273 mv88e6xxx_reg_lock(chip);
274 mv88e6xxx_g1_irq_free_common(chip);
275 mv88e6xxx_reg_unlock(chip);
276 }
277
mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip * chip)278 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip)
279 {
280 int err, irq, virq;
281 u16 reg, mask;
282
283 chip->g1_irq.nirqs = chip->info->g1_irqs;
284 chip->g1_irq.domain = irq_domain_add_simple(
285 NULL, chip->g1_irq.nirqs, 0,
286 &mv88e6xxx_g1_irq_domain_ops, chip);
287 if (!chip->g1_irq.domain)
288 return -ENOMEM;
289
290 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
291 irq_create_mapping(chip->g1_irq.domain, irq);
292
293 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
294 chip->g1_irq.masked = ~0;
295
296 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
297 if (err)
298 goto out_mapping;
299
300 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
301
302 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
303 if (err)
304 goto out_disable;
305
306 /* Reading the interrupt status clears (most of) them */
307 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
308 if (err)
309 goto out_disable;
310
311 return 0;
312
313 out_disable:
314 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
315 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
316
317 out_mapping:
318 for (irq = 0; irq < 16; irq++) {
319 virq = irq_find_mapping(chip->g1_irq.domain, irq);
320 irq_dispose_mapping(virq);
321 }
322
323 irq_domain_remove(chip->g1_irq.domain);
324
325 return err;
326 }
327
mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip * chip)328 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
329 {
330 static struct lock_class_key lock_key;
331 static struct lock_class_key request_key;
332 int err;
333
334 err = mv88e6xxx_g1_irq_setup_common(chip);
335 if (err)
336 return err;
337
338 /* These lock classes tells lockdep that global 1 irqs are in
339 * a different category than their parent GPIO, so it won't
340 * report false recursion.
341 */
342 irq_set_lockdep_class(chip->irq, &lock_key, &request_key);
343
344 snprintf(chip->irq_name, sizeof(chip->irq_name),
345 "mv88e6xxx-%s", dev_name(chip->dev));
346
347 mv88e6xxx_reg_unlock(chip);
348 err = request_threaded_irq(chip->irq, NULL,
349 mv88e6xxx_g1_irq_thread_fn,
350 IRQF_ONESHOT | IRQF_SHARED,
351 chip->irq_name, chip);
352 mv88e6xxx_reg_lock(chip);
353 if (err)
354 mv88e6xxx_g1_irq_free_common(chip);
355
356 return err;
357 }
358
mv88e6xxx_irq_poll(struct kthread_work * work)359 static void mv88e6xxx_irq_poll(struct kthread_work *work)
360 {
361 struct mv88e6xxx_chip *chip = container_of(work,
362 struct mv88e6xxx_chip,
363 irq_poll_work.work);
364 mv88e6xxx_g1_irq_thread_work(chip);
365
366 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
367 msecs_to_jiffies(100));
368 }
369
mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip * chip)370 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip)
371 {
372 int err;
373
374 err = mv88e6xxx_g1_irq_setup_common(chip);
375 if (err)
376 return err;
377
378 kthread_init_delayed_work(&chip->irq_poll_work,
379 mv88e6xxx_irq_poll);
380
381 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev));
382 if (IS_ERR(chip->kworker))
383 return PTR_ERR(chip->kworker);
384
385 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
386 msecs_to_jiffies(100));
387
388 return 0;
389 }
390
mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip * chip)391 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip)
392 {
393 kthread_cancel_delayed_work_sync(&chip->irq_poll_work);
394 kthread_destroy_worker(chip->kworker);
395
396 mv88e6xxx_reg_lock(chip);
397 mv88e6xxx_g1_irq_free_common(chip);
398 mv88e6xxx_reg_unlock(chip);
399 }
400
mv88e6xxx_port_config_interface(struct mv88e6xxx_chip * chip,int port,phy_interface_t interface)401 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip,
402 int port, phy_interface_t interface)
403 {
404 int err;
405
406 if (chip->info->ops->port_set_rgmii_delay) {
407 err = chip->info->ops->port_set_rgmii_delay(chip, port,
408 interface);
409 if (err && err != -EOPNOTSUPP)
410 return err;
411 }
412
413 if (chip->info->ops->port_set_cmode) {
414 err = chip->info->ops->port_set_cmode(chip, port,
415 interface);
416 if (err && err != -EOPNOTSUPP)
417 return err;
418 }
419
420 return 0;
421 }
422
mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip * chip,int port,int link,int speed,int duplex,int pause,phy_interface_t mode)423 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
424 int link, int speed, int duplex, int pause,
425 phy_interface_t mode)
426 {
427 int err;
428
429 if (!chip->info->ops->port_set_link)
430 return 0;
431
432 /* Port's MAC control must not be changed unless the link is down */
433 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN);
434 if (err)
435 return err;
436
437 if (chip->info->ops->port_set_speed_duplex) {
438 err = chip->info->ops->port_set_speed_duplex(chip, port,
439 speed, duplex);
440 if (err && err != -EOPNOTSUPP)
441 goto restore_link;
442 }
443
444 if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode)
445 mode = chip->info->ops->port_max_speed_mode(port);
446
447 if (chip->info->ops->port_set_pause) {
448 err = chip->info->ops->port_set_pause(chip, port, pause);
449 if (err)
450 goto restore_link;
451 }
452
453 err = mv88e6xxx_port_config_interface(chip, port, mode);
454 restore_link:
455 if (chip->info->ops->port_set_link(chip, port, link))
456 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
457
458 return err;
459 }
460
mv88e6xxx_phy_is_internal(struct dsa_switch * ds,int port)461 static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port)
462 {
463 struct mv88e6xxx_chip *chip = ds->priv;
464
465 return port < chip->info->num_internal_phys;
466 }
467
mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip * chip,int port)468 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port)
469 {
470 u16 reg;
471 int err;
472
473 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
474 if (err) {
475 dev_err(chip->dev,
476 "p%d: %s: failed to read port status\n",
477 port, __func__);
478 return err;
479 }
480
481 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT);
482 }
483
mv88e6xxx_serdes_pcs_get_state(struct dsa_switch * ds,int port,struct phylink_link_state * state)484 static int mv88e6xxx_serdes_pcs_get_state(struct dsa_switch *ds, int port,
485 struct phylink_link_state *state)
486 {
487 struct mv88e6xxx_chip *chip = ds->priv;
488 u8 lane;
489 int err;
490
491 mv88e6xxx_reg_lock(chip);
492 lane = mv88e6xxx_serdes_get_lane(chip, port);
493 if (lane && chip->info->ops->serdes_pcs_get_state)
494 err = chip->info->ops->serdes_pcs_get_state(chip, port, lane,
495 state);
496 else
497 err = -EOPNOTSUPP;
498 mv88e6xxx_reg_unlock(chip);
499
500 return err;
501 }
502
mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip * chip,int port,unsigned int mode,phy_interface_t interface,const unsigned long * advertise)503 static int mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port,
504 unsigned int mode,
505 phy_interface_t interface,
506 const unsigned long *advertise)
507 {
508 const struct mv88e6xxx_ops *ops = chip->info->ops;
509 u8 lane;
510
511 if (ops->serdes_pcs_config) {
512 lane = mv88e6xxx_serdes_get_lane(chip, port);
513 if (lane)
514 return ops->serdes_pcs_config(chip, port, lane, mode,
515 interface, advertise);
516 }
517
518 return 0;
519 }
520
mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch * ds,int port)521 static void mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch *ds, int port)
522 {
523 struct mv88e6xxx_chip *chip = ds->priv;
524 const struct mv88e6xxx_ops *ops;
525 int err = 0;
526 u8 lane;
527
528 ops = chip->info->ops;
529
530 if (ops->serdes_pcs_an_restart) {
531 mv88e6xxx_reg_lock(chip);
532 lane = mv88e6xxx_serdes_get_lane(chip, port);
533 if (lane)
534 err = ops->serdes_pcs_an_restart(chip, port, lane);
535 mv88e6xxx_reg_unlock(chip);
536
537 if (err)
538 dev_err(ds->dev, "p%d: failed to restart AN\n", port);
539 }
540 }
541
mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip * chip,int port,unsigned int mode,int speed,int duplex)542 static int mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port,
543 unsigned int mode,
544 int speed, int duplex)
545 {
546 const struct mv88e6xxx_ops *ops = chip->info->ops;
547 u8 lane;
548
549 if (!phylink_autoneg_inband(mode) && ops->serdes_pcs_link_up) {
550 lane = mv88e6xxx_serdes_get_lane(chip, port);
551 if (lane)
552 return ops->serdes_pcs_link_up(chip, port, lane,
553 speed, duplex);
554 }
555
556 return 0;
557 }
558
mv88e6065_phylink_validate(struct mv88e6xxx_chip * chip,int port,unsigned long * mask,struct phylink_link_state * state)559 static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port,
560 unsigned long *mask,
561 struct phylink_link_state *state)
562 {
563 if (!phy_interface_mode_is_8023z(state->interface)) {
564 /* 10M and 100M are only supported in non-802.3z mode */
565 phylink_set(mask, 10baseT_Half);
566 phylink_set(mask, 10baseT_Full);
567 phylink_set(mask, 100baseT_Half);
568 phylink_set(mask, 100baseT_Full);
569 }
570 }
571
mv88e6185_phylink_validate(struct mv88e6xxx_chip * chip,int port,unsigned long * mask,struct phylink_link_state * state)572 static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port,
573 unsigned long *mask,
574 struct phylink_link_state *state)
575 {
576 /* FIXME: if the port is in 1000Base-X mode, then it only supports
577 * 1000M FD speeds. In this case, CMODE will indicate 5.
578 */
579 phylink_set(mask, 1000baseT_Full);
580 phylink_set(mask, 1000baseX_Full);
581
582 mv88e6065_phylink_validate(chip, port, mask, state);
583 }
584
mv88e6341_phylink_validate(struct mv88e6xxx_chip * chip,int port,unsigned long * mask,struct phylink_link_state * state)585 static void mv88e6341_phylink_validate(struct mv88e6xxx_chip *chip, int port,
586 unsigned long *mask,
587 struct phylink_link_state *state)
588 {
589 if (port >= 5)
590 phylink_set(mask, 2500baseX_Full);
591
592 /* No ethtool bits for 200Mbps */
593 phylink_set(mask, 1000baseT_Full);
594 phylink_set(mask, 1000baseX_Full);
595
596 mv88e6065_phylink_validate(chip, port, mask, state);
597 }
598
mv88e6352_phylink_validate(struct mv88e6xxx_chip * chip,int port,unsigned long * mask,struct phylink_link_state * state)599 static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port,
600 unsigned long *mask,
601 struct phylink_link_state *state)
602 {
603 /* No ethtool bits for 200Mbps */
604 phylink_set(mask, 1000baseT_Full);
605 phylink_set(mask, 1000baseX_Full);
606
607 mv88e6065_phylink_validate(chip, port, mask, state);
608 }
609
mv88e6390_phylink_validate(struct mv88e6xxx_chip * chip,int port,unsigned long * mask,struct phylink_link_state * state)610 static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port,
611 unsigned long *mask,
612 struct phylink_link_state *state)
613 {
614 if (port >= 9) {
615 phylink_set(mask, 2500baseX_Full);
616 phylink_set(mask, 2500baseT_Full);
617 }
618
619 /* No ethtool bits for 200Mbps */
620 phylink_set(mask, 1000baseT_Full);
621 phylink_set(mask, 1000baseX_Full);
622
623 mv88e6065_phylink_validate(chip, port, mask, state);
624 }
625
mv88e6390x_phylink_validate(struct mv88e6xxx_chip * chip,int port,unsigned long * mask,struct phylink_link_state * state)626 static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port,
627 unsigned long *mask,
628 struct phylink_link_state *state)
629 {
630 if (port >= 9) {
631 phylink_set(mask, 10000baseT_Full);
632 phylink_set(mask, 10000baseKR_Full);
633 }
634
635 mv88e6390_phylink_validate(chip, port, mask, state);
636 }
637
mv88e6xxx_validate(struct dsa_switch * ds,int port,unsigned long * supported,struct phylink_link_state * state)638 static void mv88e6xxx_validate(struct dsa_switch *ds, int port,
639 unsigned long *supported,
640 struct phylink_link_state *state)
641 {
642 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
643 struct mv88e6xxx_chip *chip = ds->priv;
644
645 /* Allow all the expected bits */
646 phylink_set(mask, Autoneg);
647 phylink_set(mask, Pause);
648 phylink_set_port_modes(mask);
649
650 if (chip->info->ops->phylink_validate)
651 chip->info->ops->phylink_validate(chip, port, mask, state);
652
653 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
654 bitmap_and(state->advertising, state->advertising, mask,
655 __ETHTOOL_LINK_MODE_MASK_NBITS);
656
657 /* We can only operate at 2500BaseX or 1000BaseX. If requested
658 * to advertise both, only report advertising at 2500BaseX.
659 */
660 phylink_helper_basex_speed(state);
661 }
662
mv88e6xxx_mac_config(struct dsa_switch * ds,int port,unsigned int mode,const struct phylink_link_state * state)663 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port,
664 unsigned int mode,
665 const struct phylink_link_state *state)
666 {
667 struct mv88e6xxx_chip *chip = ds->priv;
668 struct mv88e6xxx_port *p;
669 int err;
670
671 p = &chip->ports[port];
672
673 /* FIXME: is this the correct test? If we're in fixed mode on an
674 * internal port, why should we process this any different from
675 * PHY mode? On the other hand, the port may be automedia between
676 * an internal PHY and the serdes...
677 */
678 if ((mode == MLO_AN_PHY) && mv88e6xxx_phy_is_internal(ds, port))
679 return;
680
681 mv88e6xxx_reg_lock(chip);
682 /* In inband mode, the link may come up at any time while the link
683 * is not forced down. Force the link down while we reconfigure the
684 * interface mode.
685 */
686 if (mode == MLO_AN_INBAND && p->interface != state->interface &&
687 chip->info->ops->port_set_link)
688 chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN);
689
690 err = mv88e6xxx_port_config_interface(chip, port, state->interface);
691 if (err && err != -EOPNOTSUPP)
692 goto err_unlock;
693
694 err = mv88e6xxx_serdes_pcs_config(chip, port, mode, state->interface,
695 state->advertising);
696 /* FIXME: we should restart negotiation if something changed - which
697 * is something we get if we convert to using phylinks PCS operations.
698 */
699 if (err > 0)
700 err = 0;
701
702 /* Undo the forced down state above after completing configuration
703 * irrespective of its state on entry, which allows the link to come up.
704 */
705 if (mode == MLO_AN_INBAND && p->interface != state->interface &&
706 chip->info->ops->port_set_link)
707 chip->info->ops->port_set_link(chip, port, LINK_UNFORCED);
708
709 p->interface = state->interface;
710
711 err_unlock:
712 mv88e6xxx_reg_unlock(chip);
713
714 if (err && err != -EOPNOTSUPP)
715 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port);
716 }
717
mv88e6xxx_mac_link_down(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface)718 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port,
719 unsigned int mode,
720 phy_interface_t interface)
721 {
722 struct mv88e6xxx_chip *chip = ds->priv;
723 const struct mv88e6xxx_ops *ops;
724 int err = 0;
725
726 ops = chip->info->ops;
727
728 mv88e6xxx_reg_lock(chip);
729 /* Internal PHYs propagate their configuration directly to the MAC.
730 * External PHYs depend on whether the PPU is enabled for this port.
731 */
732 if (((!mv88e6xxx_phy_is_internal(ds, port) &&
733 !mv88e6xxx_port_ppu_updates(chip, port)) ||
734 mode == MLO_AN_FIXED) && ops->port_set_link)
735 err = ops->port_set_link(chip, port, LINK_FORCED_DOWN);
736 mv88e6xxx_reg_unlock(chip);
737
738 if (err)
739 dev_err(chip->dev,
740 "p%d: failed to force MAC link down\n", port);
741 }
742
mv88e6xxx_mac_link_up(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface,struct phy_device * phydev,int speed,int duplex,bool tx_pause,bool rx_pause)743 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port,
744 unsigned int mode, phy_interface_t interface,
745 struct phy_device *phydev,
746 int speed, int duplex,
747 bool tx_pause, bool rx_pause)
748 {
749 struct mv88e6xxx_chip *chip = ds->priv;
750 const struct mv88e6xxx_ops *ops;
751 int err = 0;
752
753 ops = chip->info->ops;
754
755 mv88e6xxx_reg_lock(chip);
756 /* Internal PHYs propagate their configuration directly to the MAC.
757 * External PHYs depend on whether the PPU is enabled for this port.
758 */
759 if ((!mv88e6xxx_phy_is_internal(ds, port) &&
760 !mv88e6xxx_port_ppu_updates(chip, port)) ||
761 mode == MLO_AN_FIXED) {
762 /* FIXME: for an automedia port, should we force the link
763 * down here - what if the link comes up due to "other" media
764 * while we're bringing the port up, how is the exclusivity
765 * handled in the Marvell hardware? E.g. port 2 on 88E6390
766 * shared between internal PHY and Serdes.
767 */
768 err = mv88e6xxx_serdes_pcs_link_up(chip, port, mode, speed,
769 duplex);
770 if (err)
771 goto error;
772
773 if (ops->port_set_speed_duplex) {
774 err = ops->port_set_speed_duplex(chip, port,
775 speed, duplex);
776 if (err && err != -EOPNOTSUPP)
777 goto error;
778 }
779
780 if (ops->port_set_link)
781 err = ops->port_set_link(chip, port, LINK_FORCED_UP);
782 }
783 error:
784 mv88e6xxx_reg_unlock(chip);
785
786 if (err && err != -EOPNOTSUPP)
787 dev_err(ds->dev,
788 "p%d: failed to configure MAC link up\n", port);
789 }
790
mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip * chip,int port)791 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
792 {
793 if (!chip->info->ops->stats_snapshot)
794 return -EOPNOTSUPP;
795
796 return chip->info->ops->stats_snapshot(chip, port);
797 }
798
799 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
800 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, },
801 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, },
802 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, },
803 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, },
804 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, },
805 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, },
806 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, },
807 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, },
808 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, },
809 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, },
810 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, },
811 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, },
812 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, },
813 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, },
814 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, },
815 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, },
816 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, },
817 { "excessive", 4, 0x11, STATS_TYPE_BANK0, },
818 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, },
819 { "deferred", 4, 0x05, STATS_TYPE_BANK0, },
820 { "single", 4, 0x14, STATS_TYPE_BANK0, },
821 { "multiple", 4, 0x17, STATS_TYPE_BANK0, },
822 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, },
823 { "late", 4, 0x1f, STATS_TYPE_BANK0, },
824 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, },
825 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, },
826 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, },
827 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, },
828 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, },
829 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, },
830 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, },
831 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, },
832 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, },
833 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, },
834 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, },
835 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, },
836 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, },
837 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, },
838 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, },
839 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, },
840 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, },
841 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, },
842 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, },
843 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, },
844 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, },
845 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, },
846 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, },
847 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, },
848 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, },
849 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, },
850 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, },
851 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, },
852 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, },
853 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, },
854 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, },
855 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, },
856 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, },
857 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, },
858 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, },
859 };
860
_mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip * chip,struct mv88e6xxx_hw_stat * s,int port,u16 bank1_select,u16 histogram)861 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
862 struct mv88e6xxx_hw_stat *s,
863 int port, u16 bank1_select,
864 u16 histogram)
865 {
866 u32 low;
867 u32 high = 0;
868 u16 reg = 0;
869 int err;
870 u64 value;
871
872 switch (s->type) {
873 case STATS_TYPE_PORT:
874 err = mv88e6xxx_port_read(chip, port, s->reg, ®);
875 if (err)
876 return U64_MAX;
877
878 low = reg;
879 if (s->size == 4) {
880 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®);
881 if (err)
882 return U64_MAX;
883 low |= ((u32)reg) << 16;
884 }
885 break;
886 case STATS_TYPE_BANK1:
887 reg = bank1_select;
888 fallthrough;
889 case STATS_TYPE_BANK0:
890 reg |= s->reg | histogram;
891 mv88e6xxx_g1_stats_read(chip, reg, &low);
892 if (s->size == 8)
893 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
894 break;
895 default:
896 return U64_MAX;
897 }
898 value = (((u64)high) << 32) | low;
899 return value;
900 }
901
mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip * chip,uint8_t * data,int types)902 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
903 uint8_t *data, int types)
904 {
905 struct mv88e6xxx_hw_stat *stat;
906 int i, j;
907
908 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
909 stat = &mv88e6xxx_hw_stats[i];
910 if (stat->type & types) {
911 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
912 ETH_GSTRING_LEN);
913 j++;
914 }
915 }
916
917 return j;
918 }
919
mv88e6095_stats_get_strings(struct mv88e6xxx_chip * chip,uint8_t * data)920 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
921 uint8_t *data)
922 {
923 return mv88e6xxx_stats_get_strings(chip, data,
924 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
925 }
926
mv88e6250_stats_get_strings(struct mv88e6xxx_chip * chip,uint8_t * data)927 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip,
928 uint8_t *data)
929 {
930 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0);
931 }
932
mv88e6320_stats_get_strings(struct mv88e6xxx_chip * chip,uint8_t * data)933 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
934 uint8_t *data)
935 {
936 return mv88e6xxx_stats_get_strings(chip, data,
937 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
938 }
939
940 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = {
941 "atu_member_violation",
942 "atu_miss_violation",
943 "atu_full_violation",
944 "vtu_member_violation",
945 "vtu_miss_violation",
946 };
947
mv88e6xxx_atu_vtu_get_strings(uint8_t * data)948 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data)
949 {
950 unsigned int i;
951
952 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++)
953 strlcpy(data + i * ETH_GSTRING_LEN,
954 mv88e6xxx_atu_vtu_stats_strings[i],
955 ETH_GSTRING_LEN);
956 }
957
mv88e6xxx_get_strings(struct dsa_switch * ds,int port,u32 stringset,uint8_t * data)958 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
959 u32 stringset, uint8_t *data)
960 {
961 struct mv88e6xxx_chip *chip = ds->priv;
962 int count = 0;
963
964 if (stringset != ETH_SS_STATS)
965 return;
966
967 mv88e6xxx_reg_lock(chip);
968
969 if (chip->info->ops->stats_get_strings)
970 count = chip->info->ops->stats_get_strings(chip, data);
971
972 if (chip->info->ops->serdes_get_strings) {
973 data += count * ETH_GSTRING_LEN;
974 count = chip->info->ops->serdes_get_strings(chip, port, data);
975 }
976
977 data += count * ETH_GSTRING_LEN;
978 mv88e6xxx_atu_vtu_get_strings(data);
979
980 mv88e6xxx_reg_unlock(chip);
981 }
982
mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip * chip,int types)983 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
984 int types)
985 {
986 struct mv88e6xxx_hw_stat *stat;
987 int i, j;
988
989 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
990 stat = &mv88e6xxx_hw_stats[i];
991 if (stat->type & types)
992 j++;
993 }
994 return j;
995 }
996
mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip * chip)997 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
998 {
999 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1000 STATS_TYPE_PORT);
1001 }
1002
mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip * chip)1003 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1004 {
1005 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0);
1006 }
1007
mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip * chip)1008 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1009 {
1010 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1011 STATS_TYPE_BANK1);
1012 }
1013
mv88e6xxx_get_sset_count(struct dsa_switch * ds,int port,int sset)1014 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset)
1015 {
1016 struct mv88e6xxx_chip *chip = ds->priv;
1017 int serdes_count = 0;
1018 int count = 0;
1019
1020 if (sset != ETH_SS_STATS)
1021 return 0;
1022
1023 mv88e6xxx_reg_lock(chip);
1024 if (chip->info->ops->stats_get_sset_count)
1025 count = chip->info->ops->stats_get_sset_count(chip);
1026 if (count < 0)
1027 goto out;
1028
1029 if (chip->info->ops->serdes_get_sset_count)
1030 serdes_count = chip->info->ops->serdes_get_sset_count(chip,
1031 port);
1032 if (serdes_count < 0) {
1033 count = serdes_count;
1034 goto out;
1035 }
1036 count += serdes_count;
1037 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings);
1038
1039 out:
1040 mv88e6xxx_reg_unlock(chip);
1041
1042 return count;
1043 }
1044
mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data,int types,u16 bank1_select,u16 histogram)1045 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1046 uint64_t *data, int types,
1047 u16 bank1_select, u16 histogram)
1048 {
1049 struct mv88e6xxx_hw_stat *stat;
1050 int i, j;
1051
1052 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1053 stat = &mv88e6xxx_hw_stats[i];
1054 if (stat->type & types) {
1055 mv88e6xxx_reg_lock(chip);
1056 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
1057 bank1_select,
1058 histogram);
1059 mv88e6xxx_reg_unlock(chip);
1060
1061 j++;
1062 }
1063 }
1064 return j;
1065 }
1066
mv88e6095_stats_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data)1067 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1068 uint64_t *data)
1069 {
1070 return mv88e6xxx_stats_get_stats(chip, port, data,
1071 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
1072 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1073 }
1074
mv88e6250_stats_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data)1075 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1076 uint64_t *data)
1077 {
1078 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0,
1079 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1080 }
1081
mv88e6320_stats_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data)1082 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1083 uint64_t *data)
1084 {
1085 return mv88e6xxx_stats_get_stats(chip, port, data,
1086 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
1087 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
1088 MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1089 }
1090
mv88e6390_stats_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data)1091 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1092 uint64_t *data)
1093 {
1094 return mv88e6xxx_stats_get_stats(chip, port, data,
1095 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
1096 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
1097 0);
1098 }
1099
mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data)1100 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port,
1101 uint64_t *data)
1102 {
1103 *data++ = chip->ports[port].atu_member_violation;
1104 *data++ = chip->ports[port].atu_miss_violation;
1105 *data++ = chip->ports[port].atu_full_violation;
1106 *data++ = chip->ports[port].vtu_member_violation;
1107 *data++ = chip->ports[port].vtu_miss_violation;
1108 }
1109
mv88e6xxx_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data)1110 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
1111 uint64_t *data)
1112 {
1113 int count = 0;
1114
1115 if (chip->info->ops->stats_get_stats)
1116 count = chip->info->ops->stats_get_stats(chip, port, data);
1117
1118 mv88e6xxx_reg_lock(chip);
1119 if (chip->info->ops->serdes_get_stats) {
1120 data += count;
1121 count = chip->info->ops->serdes_get_stats(chip, port, data);
1122 }
1123 data += count;
1124 mv88e6xxx_atu_vtu_get_stats(chip, port, data);
1125 mv88e6xxx_reg_unlock(chip);
1126 }
1127
mv88e6xxx_get_ethtool_stats(struct dsa_switch * ds,int port,uint64_t * data)1128 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
1129 uint64_t *data)
1130 {
1131 struct mv88e6xxx_chip *chip = ds->priv;
1132 int ret;
1133
1134 mv88e6xxx_reg_lock(chip);
1135
1136 ret = mv88e6xxx_stats_snapshot(chip, port);
1137 mv88e6xxx_reg_unlock(chip);
1138
1139 if (ret < 0)
1140 return;
1141
1142 mv88e6xxx_get_stats(chip, port, data);
1143
1144 }
1145
mv88e6xxx_get_regs_len(struct dsa_switch * ds,int port)1146 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
1147 {
1148 struct mv88e6xxx_chip *chip = ds->priv;
1149 int len;
1150
1151 len = 32 * sizeof(u16);
1152 if (chip->info->ops->serdes_get_regs_len)
1153 len += chip->info->ops->serdes_get_regs_len(chip, port);
1154
1155 return len;
1156 }
1157
mv88e6xxx_get_regs(struct dsa_switch * ds,int port,struct ethtool_regs * regs,void * _p)1158 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1159 struct ethtool_regs *regs, void *_p)
1160 {
1161 struct mv88e6xxx_chip *chip = ds->priv;
1162 int err;
1163 u16 reg;
1164 u16 *p = _p;
1165 int i;
1166
1167 regs->version = chip->info->prod_num;
1168
1169 memset(p, 0xff, 32 * sizeof(u16));
1170
1171 mv88e6xxx_reg_lock(chip);
1172
1173 for (i = 0; i < 32; i++) {
1174
1175 err = mv88e6xxx_port_read(chip, port, i, ®);
1176 if (!err)
1177 p[i] = reg;
1178 }
1179
1180 if (chip->info->ops->serdes_get_regs)
1181 chip->info->ops->serdes_get_regs(chip, port, &p[i]);
1182
1183 mv88e6xxx_reg_unlock(chip);
1184 }
1185
mv88e6xxx_get_mac_eee(struct dsa_switch * ds,int port,struct ethtool_eee * e)1186 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
1187 struct ethtool_eee *e)
1188 {
1189 /* Nothing to do on the port's MAC */
1190 return 0;
1191 }
1192
mv88e6xxx_set_mac_eee(struct dsa_switch * ds,int port,struct ethtool_eee * e)1193 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
1194 struct ethtool_eee *e)
1195 {
1196 /* Nothing to do on the port's MAC */
1197 return 0;
1198 }
1199
1200 /* Mask of the local ports allowed to receive frames from a given fabric port */
mv88e6xxx_port_vlan(struct mv88e6xxx_chip * chip,int dev,int port)1201 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
1202 {
1203 struct dsa_switch *ds = chip->ds;
1204 struct dsa_switch_tree *dst = ds->dst;
1205 struct net_device *br;
1206 struct dsa_port *dp;
1207 bool found = false;
1208 u16 pvlan;
1209
1210 list_for_each_entry(dp, &dst->ports, list) {
1211 if (dp->ds->index == dev && dp->index == port) {
1212 found = true;
1213 break;
1214 }
1215 }
1216
1217 /* Prevent frames from unknown switch or port */
1218 if (!found)
1219 return 0;
1220
1221 /* Frames from DSA links and CPU ports can egress any local port */
1222 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA)
1223 return mv88e6xxx_port_mask(chip);
1224
1225 br = dp->bridge_dev;
1226 pvlan = 0;
1227
1228 /* Frames from user ports can egress any local DSA links and CPU ports,
1229 * as well as any local member of their bridge group.
1230 */
1231 list_for_each_entry(dp, &dst->ports, list)
1232 if (dp->ds == ds &&
1233 (dp->type == DSA_PORT_TYPE_CPU ||
1234 dp->type == DSA_PORT_TYPE_DSA ||
1235 (br && dp->bridge_dev == br)))
1236 pvlan |= BIT(dp->index);
1237
1238 return pvlan;
1239 }
1240
mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip * chip,int port)1241 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
1242 {
1243 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
1244
1245 /* prevent frames from going back out of the port they came in on */
1246 output_ports &= ~BIT(port);
1247
1248 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
1249 }
1250
mv88e6xxx_port_stp_state_set(struct dsa_switch * ds,int port,u8 state)1251 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1252 u8 state)
1253 {
1254 struct mv88e6xxx_chip *chip = ds->priv;
1255 int err;
1256
1257 mv88e6xxx_reg_lock(chip);
1258 err = mv88e6xxx_port_set_state(chip, port, state);
1259 mv88e6xxx_reg_unlock(chip);
1260
1261 if (err)
1262 dev_err(ds->dev, "p%d: failed to update state\n", port);
1263 }
1264
mv88e6xxx_pri_setup(struct mv88e6xxx_chip * chip)1265 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip)
1266 {
1267 int err;
1268
1269 if (chip->info->ops->ieee_pri_map) {
1270 err = chip->info->ops->ieee_pri_map(chip);
1271 if (err)
1272 return err;
1273 }
1274
1275 if (chip->info->ops->ip_pri_map) {
1276 err = chip->info->ops->ip_pri_map(chip);
1277 if (err)
1278 return err;
1279 }
1280
1281 return 0;
1282 }
1283
mv88e6xxx_devmap_setup(struct mv88e6xxx_chip * chip)1284 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip)
1285 {
1286 struct dsa_switch *ds = chip->ds;
1287 int target, port;
1288 int err;
1289
1290 if (!chip->info->global2_addr)
1291 return 0;
1292
1293 /* Initialize the routing port to the 32 possible target devices */
1294 for (target = 0; target < 32; target++) {
1295 port = dsa_routing_port(ds, target);
1296 if (port == ds->num_ports)
1297 port = 0x1f;
1298
1299 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
1300 if (err)
1301 return err;
1302 }
1303
1304 if (chip->info->ops->set_cascade_port) {
1305 port = MV88E6XXX_CASCADE_PORT_MULTIPLE;
1306 err = chip->info->ops->set_cascade_port(chip, port);
1307 if (err)
1308 return err;
1309 }
1310
1311 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index);
1312 if (err)
1313 return err;
1314
1315 return 0;
1316 }
1317
mv88e6xxx_trunk_setup(struct mv88e6xxx_chip * chip)1318 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip)
1319 {
1320 /* Clear all trunk masks and mapping */
1321 if (chip->info->global2_addr)
1322 return mv88e6xxx_g2_trunk_clear(chip);
1323
1324 return 0;
1325 }
1326
mv88e6xxx_rmu_setup(struct mv88e6xxx_chip * chip)1327 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip)
1328 {
1329 if (chip->info->ops->rmu_disable)
1330 return chip->info->ops->rmu_disable(chip);
1331
1332 return 0;
1333 }
1334
mv88e6xxx_pot_setup(struct mv88e6xxx_chip * chip)1335 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
1336 {
1337 if (chip->info->ops->pot_clear)
1338 return chip->info->ops->pot_clear(chip);
1339
1340 return 0;
1341 }
1342
mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip * chip)1343 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
1344 {
1345 if (chip->info->ops->mgmt_rsvd2cpu)
1346 return chip->info->ops->mgmt_rsvd2cpu(chip);
1347
1348 return 0;
1349 }
1350
mv88e6xxx_atu_setup(struct mv88e6xxx_chip * chip)1351 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
1352 {
1353 int err;
1354
1355 err = mv88e6xxx_g1_atu_flush(chip, 0, true);
1356 if (err)
1357 return err;
1358
1359 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
1360 if (err)
1361 return err;
1362
1363 return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
1364 }
1365
mv88e6xxx_irl_setup(struct mv88e6xxx_chip * chip)1366 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
1367 {
1368 int port;
1369 int err;
1370
1371 if (!chip->info->ops->irl_init_all)
1372 return 0;
1373
1374 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1375 /* Disable ingress rate limiting by resetting all per port
1376 * ingress rate limit resources to their initial state.
1377 */
1378 err = chip->info->ops->irl_init_all(chip, port);
1379 if (err)
1380 return err;
1381 }
1382
1383 return 0;
1384 }
1385
mv88e6xxx_mac_setup(struct mv88e6xxx_chip * chip)1386 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
1387 {
1388 if (chip->info->ops->set_switch_mac) {
1389 u8 addr[ETH_ALEN];
1390
1391 eth_random_addr(addr);
1392
1393 return chip->info->ops->set_switch_mac(chip, addr);
1394 }
1395
1396 return 0;
1397 }
1398
mv88e6xxx_pvt_map(struct mv88e6xxx_chip * chip,int dev,int port)1399 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
1400 {
1401 u16 pvlan = 0;
1402
1403 if (!mv88e6xxx_has_pvt(chip))
1404 return 0;
1405
1406 /* Skip the local source device, which uses in-chip port VLAN */
1407 if (dev != chip->ds->index)
1408 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
1409
1410 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
1411 }
1412
mv88e6xxx_pvt_setup(struct mv88e6xxx_chip * chip)1413 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
1414 {
1415 int dev, port;
1416 int err;
1417
1418 if (!mv88e6xxx_has_pvt(chip))
1419 return 0;
1420
1421 /* Clear 5 Bit Port for usage with Marvell Link Street devices:
1422 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
1423 */
1424 err = mv88e6xxx_g2_misc_4_bit_port(chip);
1425 if (err)
1426 return err;
1427
1428 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
1429 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
1430 err = mv88e6xxx_pvt_map(chip, dev, port);
1431 if (err)
1432 return err;
1433 }
1434 }
1435
1436 return 0;
1437 }
1438
mv88e6xxx_port_fast_age(struct dsa_switch * ds,int port)1439 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1440 {
1441 struct mv88e6xxx_chip *chip = ds->priv;
1442 int err;
1443
1444 mv88e6xxx_reg_lock(chip);
1445 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
1446 mv88e6xxx_reg_unlock(chip);
1447
1448 if (err)
1449 dev_err(ds->dev, "p%d: failed to flush ATU\n", port);
1450 }
1451
mv88e6xxx_vtu_setup(struct mv88e6xxx_chip * chip)1452 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1453 {
1454 if (!chip->info->max_vid)
1455 return 0;
1456
1457 return mv88e6xxx_g1_vtu_flush(chip);
1458 }
1459
mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip * chip,struct mv88e6xxx_vtu_entry * entry)1460 static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
1461 struct mv88e6xxx_vtu_entry *entry)
1462 {
1463 if (!chip->info->ops->vtu_getnext)
1464 return -EOPNOTSUPP;
1465
1466 return chip->info->ops->vtu_getnext(chip, entry);
1467 }
1468
mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip * chip,struct mv88e6xxx_vtu_entry * entry)1469 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1470 struct mv88e6xxx_vtu_entry *entry)
1471 {
1472 if (!chip->info->ops->vtu_loadpurge)
1473 return -EOPNOTSUPP;
1474
1475 return chip->info->ops->vtu_loadpurge(chip, entry);
1476 }
1477
mv88e6xxx_fid_map(struct mv88e6xxx_chip * chip,unsigned long * fid_bitmap)1478 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap)
1479 {
1480 struct mv88e6xxx_vtu_entry vlan;
1481 int i, err;
1482 u16 fid;
1483
1484 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1485
1486 /* Set every FID bit used by the (un)bridged ports */
1487 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1488 err = mv88e6xxx_port_get_fid(chip, i, &fid);
1489 if (err)
1490 return err;
1491
1492 set_bit(fid, fid_bitmap);
1493 }
1494
1495 /* Set every FID bit used by the VLAN entries */
1496 vlan.vid = chip->info->max_vid;
1497 vlan.valid = false;
1498
1499 do {
1500 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1501 if (err)
1502 return err;
1503
1504 if (!vlan.valid)
1505 break;
1506
1507 set_bit(vlan.fid, fid_bitmap);
1508 } while (vlan.vid < chip->info->max_vid);
1509
1510 return 0;
1511 }
1512
mv88e6xxx_atu_new(struct mv88e6xxx_chip * chip,u16 * fid)1513 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1514 {
1515 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1516 int err;
1517
1518 err = mv88e6xxx_fid_map(chip, fid_bitmap);
1519 if (err)
1520 return err;
1521
1522 /* The reset value 0x000 is used to indicate that multiple address
1523 * databases are not needed. Return the next positive available.
1524 */
1525 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1526 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1527 return -ENOSPC;
1528
1529 /* Clear the database */
1530 return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1531 }
1532
mv88e6xxx_port_check_hw_vlan(struct dsa_switch * ds,int port,u16 vid_begin,u16 vid_end)1533 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1534 u16 vid_begin, u16 vid_end)
1535 {
1536 struct mv88e6xxx_chip *chip = ds->priv;
1537 struct mv88e6xxx_vtu_entry vlan;
1538 int i, err;
1539
1540 /* DSA and CPU ports have to be members of multiple vlans */
1541 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1542 return 0;
1543
1544 if (!vid_begin)
1545 return -EOPNOTSUPP;
1546
1547 vlan.vid = vid_begin - 1;
1548 vlan.valid = false;
1549
1550 do {
1551 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1552 if (err)
1553 return err;
1554
1555 if (!vlan.valid)
1556 break;
1557
1558 if (vlan.vid > vid_end)
1559 break;
1560
1561 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1562 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1563 continue;
1564
1565 if (!dsa_to_port(ds, i)->slave)
1566 continue;
1567
1568 if (vlan.member[i] ==
1569 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1570 continue;
1571
1572 if (dsa_to_port(ds, i)->bridge_dev ==
1573 dsa_to_port(ds, port)->bridge_dev)
1574 break; /* same bridge, check next VLAN */
1575
1576 if (!dsa_to_port(ds, i)->bridge_dev)
1577 continue;
1578
1579 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
1580 port, vlan.vid, i,
1581 netdev_name(dsa_to_port(ds, i)->bridge_dev));
1582 return -EOPNOTSUPP;
1583 }
1584 } while (vlan.vid < vid_end);
1585
1586 return 0;
1587 }
1588
mv88e6xxx_port_vlan_filtering(struct dsa_switch * ds,int port,bool vlan_filtering,struct switchdev_trans * trans)1589 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1590 bool vlan_filtering,
1591 struct switchdev_trans *trans)
1592 {
1593 struct mv88e6xxx_chip *chip = ds->priv;
1594 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
1595 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
1596 int err;
1597
1598 if (switchdev_trans_ph_prepare(trans))
1599 return chip->info->max_vid ? 0 : -EOPNOTSUPP;
1600
1601 mv88e6xxx_reg_lock(chip);
1602 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
1603 mv88e6xxx_reg_unlock(chip);
1604
1605 return err;
1606 }
1607
1608 static int
mv88e6xxx_port_vlan_prepare(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan)1609 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1610 const struct switchdev_obj_port_vlan *vlan)
1611 {
1612 struct mv88e6xxx_chip *chip = ds->priv;
1613 int err;
1614
1615 if (!chip->info->max_vid)
1616 return -EOPNOTSUPP;
1617
1618 /* If the requested port doesn't belong to the same bridge as the VLAN
1619 * members, do not support it (yet) and fallback to software VLAN.
1620 */
1621 mv88e6xxx_reg_lock(chip);
1622 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1623 vlan->vid_end);
1624 mv88e6xxx_reg_unlock(chip);
1625
1626 /* We don't need any dynamic resource from the kernel (yet),
1627 * so skip the prepare phase.
1628 */
1629 return err;
1630 }
1631
mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip * chip,int port,const unsigned char * addr,u16 vid,u8 state)1632 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
1633 const unsigned char *addr, u16 vid,
1634 u8 state)
1635 {
1636 struct mv88e6xxx_atu_entry entry;
1637 struct mv88e6xxx_vtu_entry vlan;
1638 u16 fid;
1639 int err;
1640
1641 /* Null VLAN ID corresponds to the port private database */
1642 if (vid == 0) {
1643 err = mv88e6xxx_port_get_fid(chip, port, &fid);
1644 if (err)
1645 return err;
1646 } else {
1647 vlan.vid = vid - 1;
1648 vlan.valid = false;
1649
1650 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1651 if (err)
1652 return err;
1653
1654 /* switchdev expects -EOPNOTSUPP to honor software VLANs */
1655 if (vlan.vid != vid || !vlan.valid)
1656 return -EOPNOTSUPP;
1657
1658 fid = vlan.fid;
1659 }
1660
1661 entry.state = 0;
1662 ether_addr_copy(entry.mac, addr);
1663 eth_addr_dec(entry.mac);
1664
1665 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry);
1666 if (err)
1667 return err;
1668
1669 /* Initialize a fresh ATU entry if it isn't found */
1670 if (!entry.state || !ether_addr_equal(entry.mac, addr)) {
1671 memset(&entry, 0, sizeof(entry));
1672 ether_addr_copy(entry.mac, addr);
1673 }
1674
1675 /* Purge the ATU entry only if no port is using it anymore */
1676 if (!state) {
1677 entry.portvec &= ~BIT(port);
1678 if (!entry.portvec)
1679 entry.state = 0;
1680 } else {
1681 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC)
1682 entry.portvec = BIT(port);
1683 else
1684 entry.portvec |= BIT(port);
1685
1686 entry.state = state;
1687 }
1688
1689 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry);
1690 }
1691
mv88e6xxx_policy_apply(struct mv88e6xxx_chip * chip,int port,const struct mv88e6xxx_policy * policy)1692 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port,
1693 const struct mv88e6xxx_policy *policy)
1694 {
1695 enum mv88e6xxx_policy_mapping mapping = policy->mapping;
1696 enum mv88e6xxx_policy_action action = policy->action;
1697 const u8 *addr = policy->addr;
1698 u16 vid = policy->vid;
1699 u8 state;
1700 int err;
1701 int id;
1702
1703 if (!chip->info->ops->port_set_policy)
1704 return -EOPNOTSUPP;
1705
1706 switch (mapping) {
1707 case MV88E6XXX_POLICY_MAPPING_DA:
1708 case MV88E6XXX_POLICY_MAPPING_SA:
1709 if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
1710 state = 0; /* Dissociate the port and address */
1711 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
1712 is_multicast_ether_addr(addr))
1713 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY;
1714 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
1715 is_unicast_ether_addr(addr))
1716 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY;
1717 else
1718 return -EOPNOTSUPP;
1719
1720 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1721 state);
1722 if (err)
1723 return err;
1724 break;
1725 default:
1726 return -EOPNOTSUPP;
1727 }
1728
1729 /* Skip the port's policy clearing if the mapping is still in use */
1730 if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
1731 idr_for_each_entry(&chip->policies, policy, id)
1732 if (policy->port == port &&
1733 policy->mapping == mapping &&
1734 policy->action != action)
1735 return 0;
1736
1737 return chip->info->ops->port_set_policy(chip, port, mapping, action);
1738 }
1739
mv88e6xxx_policy_insert(struct mv88e6xxx_chip * chip,int port,struct ethtool_rx_flow_spec * fs)1740 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port,
1741 struct ethtool_rx_flow_spec *fs)
1742 {
1743 struct ethhdr *mac_entry = &fs->h_u.ether_spec;
1744 struct ethhdr *mac_mask = &fs->m_u.ether_spec;
1745 enum mv88e6xxx_policy_mapping mapping;
1746 enum mv88e6xxx_policy_action action;
1747 struct mv88e6xxx_policy *policy;
1748 u16 vid = 0;
1749 u8 *addr;
1750 int err;
1751 int id;
1752
1753 if (fs->location != RX_CLS_LOC_ANY)
1754 return -EINVAL;
1755
1756 if (fs->ring_cookie == RX_CLS_FLOW_DISC)
1757 action = MV88E6XXX_POLICY_ACTION_DISCARD;
1758 else
1759 return -EOPNOTSUPP;
1760
1761 switch (fs->flow_type & ~FLOW_EXT) {
1762 case ETHER_FLOW:
1763 if (!is_zero_ether_addr(mac_mask->h_dest) &&
1764 is_zero_ether_addr(mac_mask->h_source)) {
1765 mapping = MV88E6XXX_POLICY_MAPPING_DA;
1766 addr = mac_entry->h_dest;
1767 } else if (is_zero_ether_addr(mac_mask->h_dest) &&
1768 !is_zero_ether_addr(mac_mask->h_source)) {
1769 mapping = MV88E6XXX_POLICY_MAPPING_SA;
1770 addr = mac_entry->h_source;
1771 } else {
1772 /* Cannot support DA and SA mapping in the same rule */
1773 return -EOPNOTSUPP;
1774 }
1775 break;
1776 default:
1777 return -EOPNOTSUPP;
1778 }
1779
1780 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) {
1781 if (fs->m_ext.vlan_tci != htons(0xffff))
1782 return -EOPNOTSUPP;
1783 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK;
1784 }
1785
1786 idr_for_each_entry(&chip->policies, policy, id) {
1787 if (policy->port == port && policy->mapping == mapping &&
1788 policy->action == action && policy->vid == vid &&
1789 ether_addr_equal(policy->addr, addr))
1790 return -EEXIST;
1791 }
1792
1793 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL);
1794 if (!policy)
1795 return -ENOMEM;
1796
1797 fs->location = 0;
1798 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff,
1799 GFP_KERNEL);
1800 if (err) {
1801 devm_kfree(chip->dev, policy);
1802 return err;
1803 }
1804
1805 memcpy(&policy->fs, fs, sizeof(*fs));
1806 ether_addr_copy(policy->addr, addr);
1807 policy->mapping = mapping;
1808 policy->action = action;
1809 policy->port = port;
1810 policy->vid = vid;
1811
1812 err = mv88e6xxx_policy_apply(chip, port, policy);
1813 if (err) {
1814 idr_remove(&chip->policies, fs->location);
1815 devm_kfree(chip->dev, policy);
1816 return err;
1817 }
1818
1819 return 0;
1820 }
1821
mv88e6xxx_get_rxnfc(struct dsa_switch * ds,int port,struct ethtool_rxnfc * rxnfc,u32 * rule_locs)1822 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port,
1823 struct ethtool_rxnfc *rxnfc, u32 *rule_locs)
1824 {
1825 struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
1826 struct mv88e6xxx_chip *chip = ds->priv;
1827 struct mv88e6xxx_policy *policy;
1828 int err;
1829 int id;
1830
1831 mv88e6xxx_reg_lock(chip);
1832
1833 switch (rxnfc->cmd) {
1834 case ETHTOOL_GRXCLSRLCNT:
1835 rxnfc->data = 0;
1836 rxnfc->data |= RX_CLS_LOC_SPECIAL;
1837 rxnfc->rule_cnt = 0;
1838 idr_for_each_entry(&chip->policies, policy, id)
1839 if (policy->port == port)
1840 rxnfc->rule_cnt++;
1841 err = 0;
1842 break;
1843 case ETHTOOL_GRXCLSRULE:
1844 err = -ENOENT;
1845 policy = idr_find(&chip->policies, fs->location);
1846 if (policy) {
1847 memcpy(fs, &policy->fs, sizeof(*fs));
1848 err = 0;
1849 }
1850 break;
1851 case ETHTOOL_GRXCLSRLALL:
1852 rxnfc->data = 0;
1853 rxnfc->rule_cnt = 0;
1854 idr_for_each_entry(&chip->policies, policy, id)
1855 if (policy->port == port)
1856 rule_locs[rxnfc->rule_cnt++] = id;
1857 err = 0;
1858 break;
1859 default:
1860 err = -EOPNOTSUPP;
1861 break;
1862 }
1863
1864 mv88e6xxx_reg_unlock(chip);
1865
1866 return err;
1867 }
1868
mv88e6xxx_set_rxnfc(struct dsa_switch * ds,int port,struct ethtool_rxnfc * rxnfc)1869 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port,
1870 struct ethtool_rxnfc *rxnfc)
1871 {
1872 struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
1873 struct mv88e6xxx_chip *chip = ds->priv;
1874 struct mv88e6xxx_policy *policy;
1875 int err;
1876
1877 mv88e6xxx_reg_lock(chip);
1878
1879 switch (rxnfc->cmd) {
1880 case ETHTOOL_SRXCLSRLINS:
1881 err = mv88e6xxx_policy_insert(chip, port, fs);
1882 break;
1883 case ETHTOOL_SRXCLSRLDEL:
1884 err = -ENOENT;
1885 policy = idr_remove(&chip->policies, fs->location);
1886 if (policy) {
1887 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL;
1888 err = mv88e6xxx_policy_apply(chip, port, policy);
1889 devm_kfree(chip->dev, policy);
1890 }
1891 break;
1892 default:
1893 err = -EOPNOTSUPP;
1894 break;
1895 }
1896
1897 mv88e6xxx_reg_unlock(chip);
1898
1899 return err;
1900 }
1901
mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip * chip,int port,u16 vid)1902 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
1903 u16 vid)
1904 {
1905 const char broadcast[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1906 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
1907
1908 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
1909 }
1910
mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip * chip,u16 vid)1911 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
1912 {
1913 int port;
1914 int err;
1915
1916 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1917 err = mv88e6xxx_port_add_broadcast(chip, port, vid);
1918 if (err)
1919 return err;
1920 }
1921
1922 return 0;
1923 }
1924
mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip * chip,int port,u16 vid,u8 member,bool warn)1925 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port,
1926 u16 vid, u8 member, bool warn)
1927 {
1928 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1929 struct mv88e6xxx_vtu_entry vlan;
1930 int i, err;
1931
1932 if (!vid)
1933 return -EOPNOTSUPP;
1934
1935 vlan.vid = vid - 1;
1936 vlan.valid = false;
1937
1938 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1939 if (err)
1940 return err;
1941
1942 if (vlan.vid != vid || !vlan.valid) {
1943 memset(&vlan, 0, sizeof(vlan));
1944
1945 err = mv88e6xxx_atu_new(chip, &vlan.fid);
1946 if (err)
1947 return err;
1948
1949 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
1950 if (i == port)
1951 vlan.member[i] = member;
1952 else
1953 vlan.member[i] = non_member;
1954
1955 vlan.vid = vid;
1956 vlan.valid = true;
1957
1958 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1959 if (err)
1960 return err;
1961
1962 err = mv88e6xxx_broadcast_setup(chip, vlan.vid);
1963 if (err)
1964 return err;
1965 } else if (vlan.member[port] != member) {
1966 vlan.member[port] = member;
1967
1968 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1969 if (err)
1970 return err;
1971 } else if (warn) {
1972 dev_info(chip->dev, "p%d: already a member of VLAN %d\n",
1973 port, vid);
1974 }
1975
1976 return 0;
1977 }
1978
mv88e6xxx_port_vlan_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan)1979 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1980 const struct switchdev_obj_port_vlan *vlan)
1981 {
1982 struct mv88e6xxx_chip *chip = ds->priv;
1983 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1984 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1985 bool warn;
1986 u8 member;
1987 u16 vid;
1988
1989 if (!chip->info->max_vid)
1990 return;
1991
1992 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1993 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
1994 else if (untagged)
1995 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
1996 else
1997 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
1998
1999 /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port
2000 * and then the CPU port. Do not warn for duplicates for the CPU port.
2001 */
2002 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port);
2003
2004 mv88e6xxx_reg_lock(chip);
2005
2006 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
2007 if (mv88e6xxx_port_vlan_join(chip, port, vid, member, warn))
2008 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
2009 vid, untagged ? 'u' : 't');
2010
2011 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
2012 dev_err(ds->dev, "p%d: failed to set PVID %d\n", port,
2013 vlan->vid_end);
2014
2015 mv88e6xxx_reg_unlock(chip);
2016 }
2017
mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip * chip,int port,u16 vid)2018 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip,
2019 int port, u16 vid)
2020 {
2021 struct mv88e6xxx_vtu_entry vlan;
2022 int i, err;
2023
2024 if (!vid)
2025 return -EOPNOTSUPP;
2026
2027 vlan.vid = vid - 1;
2028 vlan.valid = false;
2029
2030 err = mv88e6xxx_vtu_getnext(chip, &vlan);
2031 if (err)
2032 return err;
2033
2034 /* If the VLAN doesn't exist in hardware or the port isn't a member,
2035 * tell switchdev that this VLAN is likely handled in software.
2036 */
2037 if (vlan.vid != vid || !vlan.valid ||
2038 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2039 return -EOPNOTSUPP;
2040
2041 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2042
2043 /* keep the VLAN unless all ports are excluded */
2044 vlan.valid = false;
2045 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
2046 if (vlan.member[i] !=
2047 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
2048 vlan.valid = true;
2049 break;
2050 }
2051 }
2052
2053 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2054 if (err)
2055 return err;
2056
2057 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
2058 }
2059
mv88e6xxx_port_vlan_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan)2060 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
2061 const struct switchdev_obj_port_vlan *vlan)
2062 {
2063 struct mv88e6xxx_chip *chip = ds->priv;
2064 u16 pvid, vid;
2065 int err = 0;
2066
2067 if (!chip->info->max_vid)
2068 return -EOPNOTSUPP;
2069
2070 mv88e6xxx_reg_lock(chip);
2071
2072 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
2073 if (err)
2074 goto unlock;
2075
2076 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
2077 err = mv88e6xxx_port_vlan_leave(chip, port, vid);
2078 if (err)
2079 goto unlock;
2080
2081 if (vid == pvid) {
2082 err = mv88e6xxx_port_set_pvid(chip, port, 0);
2083 if (err)
2084 goto unlock;
2085 }
2086 }
2087
2088 unlock:
2089 mv88e6xxx_reg_unlock(chip);
2090
2091 return err;
2092 }
2093
mv88e6xxx_port_fdb_add(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid)2094 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2095 const unsigned char *addr, u16 vid)
2096 {
2097 struct mv88e6xxx_chip *chip = ds->priv;
2098 int err;
2099
2100 mv88e6xxx_reg_lock(chip);
2101 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
2102 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2103 mv88e6xxx_reg_unlock(chip);
2104
2105 return err;
2106 }
2107
mv88e6xxx_port_fdb_del(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid)2108 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2109 const unsigned char *addr, u16 vid)
2110 {
2111 struct mv88e6xxx_chip *chip = ds->priv;
2112 int err;
2113
2114 mv88e6xxx_reg_lock(chip);
2115 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0);
2116 mv88e6xxx_reg_unlock(chip);
2117
2118 return err;
2119 }
2120
mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip * chip,u16 fid,u16 vid,int port,dsa_fdb_dump_cb_t * cb,void * data)2121 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2122 u16 fid, u16 vid, int port,
2123 dsa_fdb_dump_cb_t *cb, void *data)
2124 {
2125 struct mv88e6xxx_atu_entry addr;
2126 bool is_static;
2127 int err;
2128
2129 addr.state = 0;
2130 eth_broadcast_addr(addr.mac);
2131
2132 do {
2133 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
2134 if (err)
2135 return err;
2136
2137 if (!addr.state)
2138 break;
2139
2140 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
2141 continue;
2142
2143 if (!is_unicast_ether_addr(addr.mac))
2144 continue;
2145
2146 is_static = (addr.state ==
2147 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2148 err = cb(addr.mac, vid, is_static, data);
2149 if (err)
2150 return err;
2151 } while (!is_broadcast_ether_addr(addr.mac));
2152
2153 return err;
2154 }
2155
mv88e6xxx_port_db_dump(struct mv88e6xxx_chip * chip,int port,dsa_fdb_dump_cb_t * cb,void * data)2156 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2157 dsa_fdb_dump_cb_t *cb, void *data)
2158 {
2159 struct mv88e6xxx_vtu_entry vlan;
2160 u16 fid;
2161 int err;
2162
2163 /* Dump port's default Filtering Information Database (VLAN ID 0) */
2164 err = mv88e6xxx_port_get_fid(chip, port, &fid);
2165 if (err)
2166 return err;
2167
2168 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
2169 if (err)
2170 return err;
2171
2172 /* Dump VLANs' Filtering Information Databases */
2173 vlan.vid = chip->info->max_vid;
2174 vlan.valid = false;
2175
2176 do {
2177 err = mv88e6xxx_vtu_getnext(chip, &vlan);
2178 if (err)
2179 return err;
2180
2181 if (!vlan.valid)
2182 break;
2183
2184 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
2185 cb, data);
2186 if (err)
2187 return err;
2188 } while (vlan.vid < chip->info->max_vid);
2189
2190 return err;
2191 }
2192
mv88e6xxx_port_fdb_dump(struct dsa_switch * ds,int port,dsa_fdb_dump_cb_t * cb,void * data)2193 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2194 dsa_fdb_dump_cb_t *cb, void *data)
2195 {
2196 struct mv88e6xxx_chip *chip = ds->priv;
2197 int err;
2198
2199 mv88e6xxx_reg_lock(chip);
2200 err = mv88e6xxx_port_db_dump(chip, port, cb, data);
2201 mv88e6xxx_reg_unlock(chip);
2202
2203 return err;
2204 }
2205
mv88e6xxx_bridge_map(struct mv88e6xxx_chip * chip,struct net_device * br)2206 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
2207 struct net_device *br)
2208 {
2209 struct dsa_switch *ds = chip->ds;
2210 struct dsa_switch_tree *dst = ds->dst;
2211 struct dsa_port *dp;
2212 int err;
2213
2214 list_for_each_entry(dp, &dst->ports, list) {
2215 if (dp->bridge_dev == br) {
2216 if (dp->ds == ds) {
2217 /* This is a local bridge group member,
2218 * remap its Port VLAN Map.
2219 */
2220 err = mv88e6xxx_port_vlan_map(chip, dp->index);
2221 if (err)
2222 return err;
2223 } else {
2224 /* This is an external bridge group member,
2225 * remap its cross-chip Port VLAN Table entry.
2226 */
2227 err = mv88e6xxx_pvt_map(chip, dp->ds->index,
2228 dp->index);
2229 if (err)
2230 return err;
2231 }
2232 }
2233 }
2234
2235 return 0;
2236 }
2237
mv88e6xxx_port_bridge_join(struct dsa_switch * ds,int port,struct net_device * br)2238 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2239 struct net_device *br)
2240 {
2241 struct mv88e6xxx_chip *chip = ds->priv;
2242 int err;
2243
2244 mv88e6xxx_reg_lock(chip);
2245 err = mv88e6xxx_bridge_map(chip, br);
2246 mv88e6xxx_reg_unlock(chip);
2247
2248 return err;
2249 }
2250
mv88e6xxx_port_bridge_leave(struct dsa_switch * ds,int port,struct net_device * br)2251 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
2252 struct net_device *br)
2253 {
2254 struct mv88e6xxx_chip *chip = ds->priv;
2255
2256 mv88e6xxx_reg_lock(chip);
2257 if (mv88e6xxx_bridge_map(chip, br) ||
2258 mv88e6xxx_port_vlan_map(chip, port))
2259 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
2260 mv88e6xxx_reg_unlock(chip);
2261 }
2262
mv88e6xxx_crosschip_bridge_join(struct dsa_switch * ds,int tree_index,int sw_index,int port,struct net_device * br)2263 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds,
2264 int tree_index, int sw_index,
2265 int port, struct net_device *br)
2266 {
2267 struct mv88e6xxx_chip *chip = ds->priv;
2268 int err;
2269
2270 if (tree_index != ds->dst->index)
2271 return 0;
2272
2273 mv88e6xxx_reg_lock(chip);
2274 err = mv88e6xxx_pvt_map(chip, sw_index, port);
2275 mv88e6xxx_reg_unlock(chip);
2276
2277 return err;
2278 }
2279
mv88e6xxx_crosschip_bridge_leave(struct dsa_switch * ds,int tree_index,int sw_index,int port,struct net_device * br)2280 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds,
2281 int tree_index, int sw_index,
2282 int port, struct net_device *br)
2283 {
2284 struct mv88e6xxx_chip *chip = ds->priv;
2285
2286 if (tree_index != ds->dst->index)
2287 return;
2288
2289 mv88e6xxx_reg_lock(chip);
2290 if (mv88e6xxx_pvt_map(chip, sw_index, port))
2291 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
2292 mv88e6xxx_reg_unlock(chip);
2293 }
2294
mv88e6xxx_software_reset(struct mv88e6xxx_chip * chip)2295 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
2296 {
2297 if (chip->info->ops->reset)
2298 return chip->info->ops->reset(chip);
2299
2300 return 0;
2301 }
2302
mv88e6xxx_hardware_reset(struct mv88e6xxx_chip * chip)2303 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
2304 {
2305 struct gpio_desc *gpiod = chip->reset;
2306
2307 /* If there is a GPIO connected to the reset pin, toggle it */
2308 if (gpiod) {
2309 gpiod_set_value_cansleep(gpiod, 1);
2310 usleep_range(10000, 20000);
2311 gpiod_set_value_cansleep(gpiod, 0);
2312 usleep_range(10000, 20000);
2313
2314 mv88e6xxx_g1_wait_eeprom_done(chip);
2315 }
2316 }
2317
mv88e6xxx_disable_ports(struct mv88e6xxx_chip * chip)2318 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
2319 {
2320 int i, err;
2321
2322 /* Set all ports to the Disabled state */
2323 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2324 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
2325 if (err)
2326 return err;
2327 }
2328
2329 /* Wait for transmit queues to drain,
2330 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
2331 */
2332 usleep_range(2000, 4000);
2333
2334 return 0;
2335 }
2336
mv88e6xxx_switch_reset(struct mv88e6xxx_chip * chip)2337 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
2338 {
2339 int err;
2340
2341 err = mv88e6xxx_disable_ports(chip);
2342 if (err)
2343 return err;
2344
2345 mv88e6xxx_hardware_reset(chip);
2346
2347 return mv88e6xxx_software_reset(chip);
2348 }
2349
mv88e6xxx_set_port_mode(struct mv88e6xxx_chip * chip,int port,enum mv88e6xxx_frame_mode frame,enum mv88e6xxx_egress_mode egress,u16 etype)2350 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
2351 enum mv88e6xxx_frame_mode frame,
2352 enum mv88e6xxx_egress_mode egress, u16 etype)
2353 {
2354 int err;
2355
2356 if (!chip->info->ops->port_set_frame_mode)
2357 return -EOPNOTSUPP;
2358
2359 err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
2360 if (err)
2361 return err;
2362
2363 err = chip->info->ops->port_set_frame_mode(chip, port, frame);
2364 if (err)
2365 return err;
2366
2367 if (chip->info->ops->port_set_ether_type)
2368 return chip->info->ops->port_set_ether_type(chip, port, etype);
2369
2370 return 0;
2371 }
2372
mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip * chip,int port)2373 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
2374 {
2375 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
2376 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
2377 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
2378 }
2379
mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip * chip,int port)2380 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
2381 {
2382 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
2383 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
2384 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
2385 }
2386
mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip * chip,int port)2387 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
2388 {
2389 return mv88e6xxx_set_port_mode(chip, port,
2390 MV88E6XXX_FRAME_MODE_ETHERTYPE,
2391 MV88E6XXX_EGRESS_MODE_ETHERTYPE,
2392 ETH_P_EDSA);
2393 }
2394
mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip * chip,int port)2395 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
2396 {
2397 if (dsa_is_dsa_port(chip->ds, port))
2398 return mv88e6xxx_set_port_mode_dsa(chip, port);
2399
2400 if (dsa_is_user_port(chip->ds, port))
2401 return mv88e6xxx_set_port_mode_normal(chip, port);
2402
2403 /* Setup CPU port mode depending on its supported tag format */
2404 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA)
2405 return mv88e6xxx_set_port_mode_dsa(chip, port);
2406
2407 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA)
2408 return mv88e6xxx_set_port_mode_edsa(chip, port);
2409
2410 return -EINVAL;
2411 }
2412
mv88e6xxx_setup_message_port(struct mv88e6xxx_chip * chip,int port)2413 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
2414 {
2415 bool message = dsa_is_dsa_port(chip->ds, port);
2416
2417 return mv88e6xxx_port_set_message_port(chip, port, message);
2418 }
2419
mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip * chip,int port)2420 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
2421 {
2422 struct dsa_switch *ds = chip->ds;
2423 bool flood;
2424
2425 /* Upstream ports flood frames with unknown unicast or multicast DA */
2426 flood = dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port);
2427 if (chip->info->ops->port_set_egress_floods)
2428 return chip->info->ops->port_set_egress_floods(chip, port,
2429 flood, flood);
2430
2431 return 0;
2432 }
2433
mv88e6xxx_serdes_irq_thread_fn(int irq,void * dev_id)2434 static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id)
2435 {
2436 struct mv88e6xxx_port *mvp = dev_id;
2437 struct mv88e6xxx_chip *chip = mvp->chip;
2438 irqreturn_t ret = IRQ_NONE;
2439 int port = mvp->port;
2440 u8 lane;
2441
2442 mv88e6xxx_reg_lock(chip);
2443 lane = mv88e6xxx_serdes_get_lane(chip, port);
2444 if (lane)
2445 ret = mv88e6xxx_serdes_irq_status(chip, port, lane);
2446 mv88e6xxx_reg_unlock(chip);
2447
2448 return ret;
2449 }
2450
mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip * chip,int port,u8 lane)2451 static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port,
2452 u8 lane)
2453 {
2454 struct mv88e6xxx_port *dev_id = &chip->ports[port];
2455 unsigned int irq;
2456 int err;
2457
2458 /* Nothing to request if this SERDES port has no IRQ */
2459 irq = mv88e6xxx_serdes_irq_mapping(chip, port);
2460 if (!irq)
2461 return 0;
2462
2463 snprintf(dev_id->serdes_irq_name, sizeof(dev_id->serdes_irq_name),
2464 "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port);
2465
2466 /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */
2467 mv88e6xxx_reg_unlock(chip);
2468 err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn,
2469 IRQF_ONESHOT, dev_id->serdes_irq_name,
2470 dev_id);
2471 mv88e6xxx_reg_lock(chip);
2472 if (err)
2473 return err;
2474
2475 dev_id->serdes_irq = irq;
2476
2477 return mv88e6xxx_serdes_irq_enable(chip, port, lane);
2478 }
2479
mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip * chip,int port,u8 lane)2480 static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port,
2481 u8 lane)
2482 {
2483 struct mv88e6xxx_port *dev_id = &chip->ports[port];
2484 unsigned int irq = dev_id->serdes_irq;
2485 int err;
2486
2487 /* Nothing to free if no IRQ has been requested */
2488 if (!irq)
2489 return 0;
2490
2491 err = mv88e6xxx_serdes_irq_disable(chip, port, lane);
2492
2493 /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */
2494 mv88e6xxx_reg_unlock(chip);
2495 free_irq(irq, dev_id);
2496 mv88e6xxx_reg_lock(chip);
2497
2498 dev_id->serdes_irq = 0;
2499
2500 return err;
2501 }
2502
mv88e6xxx_serdes_power(struct mv88e6xxx_chip * chip,int port,bool on)2503 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port,
2504 bool on)
2505 {
2506 u8 lane;
2507 int err;
2508
2509 lane = mv88e6xxx_serdes_get_lane(chip, port);
2510 if (!lane)
2511 return 0;
2512
2513 if (on) {
2514 err = mv88e6xxx_serdes_power_up(chip, port, lane);
2515 if (err)
2516 return err;
2517
2518 err = mv88e6xxx_serdes_irq_request(chip, port, lane);
2519 } else {
2520 err = mv88e6xxx_serdes_irq_free(chip, port, lane);
2521 if (err)
2522 return err;
2523
2524 err = mv88e6xxx_serdes_power_down(chip, port, lane);
2525 }
2526
2527 return err;
2528 }
2529
mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip * chip,int port)2530 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
2531 {
2532 struct dsa_switch *ds = chip->ds;
2533 int upstream_port;
2534 int err;
2535
2536 upstream_port = dsa_upstream_port(ds, port);
2537 if (chip->info->ops->port_set_upstream_port) {
2538 err = chip->info->ops->port_set_upstream_port(chip, port,
2539 upstream_port);
2540 if (err)
2541 return err;
2542 }
2543
2544 if (port == upstream_port) {
2545 if (chip->info->ops->set_cpu_port) {
2546 err = chip->info->ops->set_cpu_port(chip,
2547 upstream_port);
2548 if (err)
2549 return err;
2550 }
2551
2552 if (chip->info->ops->set_egress_port) {
2553 err = chip->info->ops->set_egress_port(chip,
2554 MV88E6XXX_EGRESS_DIR_INGRESS,
2555 upstream_port);
2556 if (err)
2557 return err;
2558
2559 err = chip->info->ops->set_egress_port(chip,
2560 MV88E6XXX_EGRESS_DIR_EGRESS,
2561 upstream_port);
2562 if (err)
2563 return err;
2564 }
2565 }
2566
2567 return 0;
2568 }
2569
mv88e6xxx_setup_port(struct mv88e6xxx_chip * chip,int port)2570 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
2571 {
2572 struct dsa_switch *ds = chip->ds;
2573 int err;
2574 u16 reg;
2575
2576 chip->ports[port].chip = chip;
2577 chip->ports[port].port = port;
2578
2579 /* MAC Forcing register: don't force link, speed, duplex or flow control
2580 * state to any particular values on physical ports, but force the CPU
2581 * port and all DSA ports to their maximum bandwidth and full duplex.
2582 */
2583 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2584 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
2585 SPEED_MAX, DUPLEX_FULL,
2586 PAUSE_OFF,
2587 PHY_INTERFACE_MODE_NA);
2588 else
2589 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
2590 SPEED_UNFORCED, DUPLEX_UNFORCED,
2591 PAUSE_ON,
2592 PHY_INTERFACE_MODE_NA);
2593 if (err)
2594 return err;
2595
2596 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2597 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2598 * tunneling, determine priority by looking at 802.1p and IP
2599 * priority fields (IP prio has precedence), and set STP state
2600 * to Forwarding.
2601 *
2602 * If this is the CPU link, use DSA or EDSA tagging depending
2603 * on which tagging mode was configured.
2604 *
2605 * If this is a link to another switch, use DSA tagging mode.
2606 *
2607 * If this is the upstream port for this switch, enable
2608 * forwarding of unknown unicasts and multicasts.
2609 */
2610 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP |
2611 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
2612 MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
2613 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
2614 if (err)
2615 return err;
2616
2617 err = mv88e6xxx_setup_port_mode(chip, port);
2618 if (err)
2619 return err;
2620
2621 err = mv88e6xxx_setup_egress_floods(chip, port);
2622 if (err)
2623 return err;
2624
2625 /* Port Control 2: don't force a good FCS, set the MTU size to
2626 * 10222 bytes, disable 802.1q tags checking, don't discard tagged or
2627 * untagged frames on this port, do a destination address lookup on all
2628 * received packets as usual, disable ARP mirroring and don't send a
2629 * copy of all transmitted/received frames on this port to the CPU.
2630 */
2631 err = mv88e6xxx_port_set_map_da(chip, port);
2632 if (err)
2633 return err;
2634
2635 err = mv88e6xxx_setup_upstream_port(chip, port);
2636 if (err)
2637 return err;
2638
2639 err = mv88e6xxx_port_set_8021q_mode(chip, port,
2640 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED);
2641 if (err)
2642 return err;
2643
2644 if (chip->info->ops->port_set_jumbo_size) {
2645 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218);
2646 if (err)
2647 return err;
2648 }
2649
2650 /* Port Association Vector: when learning source addresses
2651 * of packets, add the address to the address database using
2652 * a port bitmap that has only the bit for this port set and
2653 * the other bits clear.
2654 */
2655 reg = 1 << port;
2656 /* Disable learning for CPU port */
2657 if (dsa_is_cpu_port(ds, port))
2658 reg = 0;
2659
2660 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
2661 reg);
2662 if (err)
2663 return err;
2664
2665 /* Egress rate control 2: disable egress rate control. */
2666 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
2667 0x0000);
2668 if (err)
2669 return err;
2670
2671 if (chip->info->ops->port_pause_limit) {
2672 err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
2673 if (err)
2674 return err;
2675 }
2676
2677 if (chip->info->ops->port_disable_learn_limit) {
2678 err = chip->info->ops->port_disable_learn_limit(chip, port);
2679 if (err)
2680 return err;
2681 }
2682
2683 if (chip->info->ops->port_disable_pri_override) {
2684 err = chip->info->ops->port_disable_pri_override(chip, port);
2685 if (err)
2686 return err;
2687 }
2688
2689 if (chip->info->ops->port_tag_remap) {
2690 err = chip->info->ops->port_tag_remap(chip, port);
2691 if (err)
2692 return err;
2693 }
2694
2695 if (chip->info->ops->port_egress_rate_limiting) {
2696 err = chip->info->ops->port_egress_rate_limiting(chip, port);
2697 if (err)
2698 return err;
2699 }
2700
2701 if (chip->info->ops->port_setup_message_port) {
2702 err = chip->info->ops->port_setup_message_port(chip, port);
2703 if (err)
2704 return err;
2705 }
2706
2707 /* Port based VLAN map: give each port the same default address
2708 * database, and allow bidirectional communication between the
2709 * CPU and DSA port(s), and the other ports.
2710 */
2711 err = mv88e6xxx_port_set_fid(chip, port, 0);
2712 if (err)
2713 return err;
2714
2715 err = mv88e6xxx_port_vlan_map(chip, port);
2716 if (err)
2717 return err;
2718
2719 /* Default VLAN ID and priority: don't set a default VLAN
2720 * ID, and set the default packet priority to zero.
2721 */
2722 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
2723 }
2724
mv88e6xxx_get_max_mtu(struct dsa_switch * ds,int port)2725 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port)
2726 {
2727 struct mv88e6xxx_chip *chip = ds->priv;
2728
2729 if (chip->info->ops->port_set_jumbo_size)
2730 return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
2731 else if (chip->info->ops->set_max_frame_size)
2732 return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
2733 return 1522 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
2734 }
2735
mv88e6xxx_change_mtu(struct dsa_switch * ds,int port,int new_mtu)2736 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
2737 {
2738 struct mv88e6xxx_chip *chip = ds->priv;
2739 int ret = 0;
2740
2741 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
2742 new_mtu += EDSA_HLEN;
2743
2744 mv88e6xxx_reg_lock(chip);
2745 if (chip->info->ops->port_set_jumbo_size)
2746 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu);
2747 else if (chip->info->ops->set_max_frame_size)
2748 ret = chip->info->ops->set_max_frame_size(chip, new_mtu);
2749 else
2750 if (new_mtu > 1522)
2751 ret = -EINVAL;
2752 mv88e6xxx_reg_unlock(chip);
2753
2754 return ret;
2755 }
2756
mv88e6xxx_port_enable(struct dsa_switch * ds,int port,struct phy_device * phydev)2757 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
2758 struct phy_device *phydev)
2759 {
2760 struct mv88e6xxx_chip *chip = ds->priv;
2761 int err;
2762
2763 mv88e6xxx_reg_lock(chip);
2764 err = mv88e6xxx_serdes_power(chip, port, true);
2765 mv88e6xxx_reg_unlock(chip);
2766
2767 return err;
2768 }
2769
mv88e6xxx_port_disable(struct dsa_switch * ds,int port)2770 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port)
2771 {
2772 struct mv88e6xxx_chip *chip = ds->priv;
2773
2774 mv88e6xxx_reg_lock(chip);
2775 if (mv88e6xxx_serdes_power(chip, port, false))
2776 dev_err(chip->dev, "failed to power off SERDES\n");
2777 mv88e6xxx_reg_unlock(chip);
2778 }
2779
mv88e6xxx_set_ageing_time(struct dsa_switch * ds,unsigned int ageing_time)2780 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2781 unsigned int ageing_time)
2782 {
2783 struct mv88e6xxx_chip *chip = ds->priv;
2784 int err;
2785
2786 mv88e6xxx_reg_lock(chip);
2787 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
2788 mv88e6xxx_reg_unlock(chip);
2789
2790 return err;
2791 }
2792
mv88e6xxx_stats_setup(struct mv88e6xxx_chip * chip)2793 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip)
2794 {
2795 int err;
2796
2797 /* Initialize the statistics unit */
2798 if (chip->info->ops->stats_set_histogram) {
2799 err = chip->info->ops->stats_set_histogram(chip);
2800 if (err)
2801 return err;
2802 }
2803
2804 return mv88e6xxx_g1_stats_clear(chip);
2805 }
2806
2807 /* Check if the errata has already been applied. */
mv88e6390_setup_errata_applied(struct mv88e6xxx_chip * chip)2808 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip)
2809 {
2810 int port;
2811 int err;
2812 u16 val;
2813
2814 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2815 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val);
2816 if (err) {
2817 dev_err(chip->dev,
2818 "Error reading hidden register: %d\n", err);
2819 return false;
2820 }
2821 if (val != 0x01c0)
2822 return false;
2823 }
2824
2825 return true;
2826 }
2827
2828 /* The 6390 copper ports have an errata which require poking magic
2829 * values into undocumented hidden registers and then performing a
2830 * software reset.
2831 */
mv88e6390_setup_errata(struct mv88e6xxx_chip * chip)2832 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip)
2833 {
2834 int port;
2835 int err;
2836
2837 if (mv88e6390_setup_errata_applied(chip))
2838 return 0;
2839
2840 /* Set the ports into blocking mode */
2841 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2842 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED);
2843 if (err)
2844 return err;
2845 }
2846
2847 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2848 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0);
2849 if (err)
2850 return err;
2851 }
2852
2853 return mv88e6xxx_software_reset(chip);
2854 }
2855
mv88e6xxx_teardown(struct dsa_switch * ds)2856 static void mv88e6xxx_teardown(struct dsa_switch *ds)
2857 {
2858 mv88e6xxx_teardown_devlink_params(ds);
2859 dsa_devlink_resources_unregister(ds);
2860 mv88e6xxx_teardown_devlink_regions(ds);
2861 }
2862
mv88e6xxx_setup(struct dsa_switch * ds)2863 static int mv88e6xxx_setup(struct dsa_switch *ds)
2864 {
2865 struct mv88e6xxx_chip *chip = ds->priv;
2866 u8 cmode;
2867 int err;
2868 int i;
2869
2870 chip->ds = ds;
2871 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
2872
2873 mv88e6xxx_reg_lock(chip);
2874
2875 if (chip->info->ops->setup_errata) {
2876 err = chip->info->ops->setup_errata(chip);
2877 if (err)
2878 goto unlock;
2879 }
2880
2881 /* Cache the cmode of each port. */
2882 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2883 if (chip->info->ops->port_get_cmode) {
2884 err = chip->info->ops->port_get_cmode(chip, i, &cmode);
2885 if (err)
2886 goto unlock;
2887
2888 chip->ports[i].cmode = cmode;
2889 }
2890 }
2891
2892 /* Setup Switch Port Registers */
2893 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2894 if (dsa_is_unused_port(ds, i))
2895 continue;
2896
2897 /* Prevent the use of an invalid port. */
2898 if (mv88e6xxx_is_invalid_port(chip, i)) {
2899 dev_err(chip->dev, "port %d is invalid\n", i);
2900 err = -EINVAL;
2901 goto unlock;
2902 }
2903
2904 err = mv88e6xxx_setup_port(chip, i);
2905 if (err)
2906 goto unlock;
2907 }
2908
2909 err = mv88e6xxx_irl_setup(chip);
2910 if (err)
2911 goto unlock;
2912
2913 err = mv88e6xxx_mac_setup(chip);
2914 if (err)
2915 goto unlock;
2916
2917 err = mv88e6xxx_phy_setup(chip);
2918 if (err)
2919 goto unlock;
2920
2921 err = mv88e6xxx_vtu_setup(chip);
2922 if (err)
2923 goto unlock;
2924
2925 err = mv88e6xxx_pvt_setup(chip);
2926 if (err)
2927 goto unlock;
2928
2929 err = mv88e6xxx_atu_setup(chip);
2930 if (err)
2931 goto unlock;
2932
2933 err = mv88e6xxx_broadcast_setup(chip, 0);
2934 if (err)
2935 goto unlock;
2936
2937 err = mv88e6xxx_pot_setup(chip);
2938 if (err)
2939 goto unlock;
2940
2941 err = mv88e6xxx_rmu_setup(chip);
2942 if (err)
2943 goto unlock;
2944
2945 err = mv88e6xxx_rsvd2cpu_setup(chip);
2946 if (err)
2947 goto unlock;
2948
2949 err = mv88e6xxx_trunk_setup(chip);
2950 if (err)
2951 goto unlock;
2952
2953 err = mv88e6xxx_devmap_setup(chip);
2954 if (err)
2955 goto unlock;
2956
2957 err = mv88e6xxx_pri_setup(chip);
2958 if (err)
2959 goto unlock;
2960
2961 /* Setup PTP Hardware Clock and timestamping */
2962 if (chip->info->ptp_support) {
2963 err = mv88e6xxx_ptp_setup(chip);
2964 if (err)
2965 goto unlock;
2966
2967 err = mv88e6xxx_hwtstamp_setup(chip);
2968 if (err)
2969 goto unlock;
2970 }
2971
2972 err = mv88e6xxx_stats_setup(chip);
2973 if (err)
2974 goto unlock;
2975
2976 unlock:
2977 mv88e6xxx_reg_unlock(chip);
2978
2979 if (err)
2980 return err;
2981
2982 /* Have to be called without holding the register lock, since
2983 * they take the devlink lock, and we later take the locks in
2984 * the reverse order when getting/setting parameters or
2985 * resource occupancy.
2986 */
2987 err = mv88e6xxx_setup_devlink_resources(ds);
2988 if (err)
2989 return err;
2990
2991 err = mv88e6xxx_setup_devlink_params(ds);
2992 if (err)
2993 goto out_resources;
2994
2995 err = mv88e6xxx_setup_devlink_regions(ds);
2996 if (err)
2997 goto out_params;
2998
2999 return 0;
3000
3001 out_params:
3002 mv88e6xxx_teardown_devlink_params(ds);
3003 out_resources:
3004 dsa_devlink_resources_unregister(ds);
3005
3006 return err;
3007 }
3008
3009 /* prod_id for switch families which do not have a PHY model number */
3010 static const u16 family_prod_id_table[] = {
3011 [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
3012 [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
3013 };
3014
mv88e6xxx_mdio_read(struct mii_bus * bus,int phy,int reg)3015 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
3016 {
3017 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3018 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3019 u16 prod_id;
3020 u16 val;
3021 int err;
3022
3023 if (!chip->info->ops->phy_read)
3024 return -EOPNOTSUPP;
3025
3026 mv88e6xxx_reg_lock(chip);
3027 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
3028 mv88e6xxx_reg_unlock(chip);
3029
3030 /* Some internal PHYs don't have a model number. */
3031 if (reg == MII_PHYSID2 && !(val & 0x3f0) &&
3032 chip->info->family < ARRAY_SIZE(family_prod_id_table)) {
3033 prod_id = family_prod_id_table[chip->info->family];
3034 if (prod_id)
3035 val |= prod_id >> 4;
3036 }
3037
3038 return err ? err : val;
3039 }
3040
mv88e6xxx_mdio_write(struct mii_bus * bus,int phy,int reg,u16 val)3041 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
3042 {
3043 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3044 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3045 int err;
3046
3047 if (!chip->info->ops->phy_write)
3048 return -EOPNOTSUPP;
3049
3050 mv88e6xxx_reg_lock(chip);
3051 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
3052 mv88e6xxx_reg_unlock(chip);
3053
3054 return err;
3055 }
3056
mv88e6xxx_mdio_register(struct mv88e6xxx_chip * chip,struct device_node * np,bool external)3057 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
3058 struct device_node *np,
3059 bool external)
3060 {
3061 static int index;
3062 struct mv88e6xxx_mdio_bus *mdio_bus;
3063 struct mii_bus *bus;
3064 int err;
3065
3066 if (external) {
3067 mv88e6xxx_reg_lock(chip);
3068 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true);
3069 mv88e6xxx_reg_unlock(chip);
3070
3071 if (err)
3072 return err;
3073 }
3074
3075 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
3076 if (!bus)
3077 return -ENOMEM;
3078
3079 mdio_bus = bus->priv;
3080 mdio_bus->bus = bus;
3081 mdio_bus->chip = chip;
3082 INIT_LIST_HEAD(&mdio_bus->list);
3083 mdio_bus->external = external;
3084
3085 if (np) {
3086 bus->name = np->full_name;
3087 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
3088 } else {
3089 bus->name = "mv88e6xxx SMI";
3090 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
3091 }
3092
3093 bus->read = mv88e6xxx_mdio_read;
3094 bus->write = mv88e6xxx_mdio_write;
3095 bus->parent = chip->dev;
3096
3097 if (!external) {
3098 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus);
3099 if (err)
3100 return err;
3101 }
3102
3103 err = of_mdiobus_register(bus, np);
3104 if (err) {
3105 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
3106 mv88e6xxx_g2_irq_mdio_free(chip, bus);
3107 return err;
3108 }
3109
3110 if (external)
3111 list_add_tail(&mdio_bus->list, &chip->mdios);
3112 else
3113 list_add(&mdio_bus->list, &chip->mdios);
3114
3115 return 0;
3116 }
3117
mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip * chip)3118 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
3119
3120 {
3121 struct mv88e6xxx_mdio_bus *mdio_bus;
3122 struct mii_bus *bus;
3123
3124 list_for_each_entry(mdio_bus, &chip->mdios, list) {
3125 bus = mdio_bus->bus;
3126
3127 if (!mdio_bus->external)
3128 mv88e6xxx_g2_irq_mdio_free(chip, bus);
3129
3130 mdiobus_unregister(bus);
3131 }
3132 }
3133
mv88e6xxx_mdios_register(struct mv88e6xxx_chip * chip,struct device_node * np)3134 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
3135 struct device_node *np)
3136 {
3137 struct device_node *child;
3138 int err;
3139
3140 /* Always register one mdio bus for the internal/default mdio
3141 * bus. This maybe represented in the device tree, but is
3142 * optional.
3143 */
3144 child = of_get_child_by_name(np, "mdio");
3145 err = mv88e6xxx_mdio_register(chip, child, false);
3146 if (err)
3147 return err;
3148
3149 /* Walk the device tree, and see if there are any other nodes
3150 * which say they are compatible with the external mdio
3151 * bus.
3152 */
3153 for_each_available_child_of_node(np, child) {
3154 if (of_device_is_compatible(
3155 child, "marvell,mv88e6xxx-mdio-external")) {
3156 err = mv88e6xxx_mdio_register(chip, child, true);
3157 if (err) {
3158 mv88e6xxx_mdios_unregister(chip);
3159 of_node_put(child);
3160 return err;
3161 }
3162 }
3163 }
3164
3165 return 0;
3166 }
3167
mv88e6xxx_get_eeprom_len(struct dsa_switch * ds)3168 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3169 {
3170 struct mv88e6xxx_chip *chip = ds->priv;
3171
3172 return chip->eeprom_len;
3173 }
3174
mv88e6xxx_get_eeprom(struct dsa_switch * ds,struct ethtool_eeprom * eeprom,u8 * data)3175 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3176 struct ethtool_eeprom *eeprom, u8 *data)
3177 {
3178 struct mv88e6xxx_chip *chip = ds->priv;
3179 int err;
3180
3181 if (!chip->info->ops->get_eeprom)
3182 return -EOPNOTSUPP;
3183
3184 mv88e6xxx_reg_lock(chip);
3185 err = chip->info->ops->get_eeprom(chip, eeprom, data);
3186 mv88e6xxx_reg_unlock(chip);
3187
3188 if (err)
3189 return err;
3190
3191 eeprom->magic = 0xc3ec4951;
3192
3193 return 0;
3194 }
3195
mv88e6xxx_set_eeprom(struct dsa_switch * ds,struct ethtool_eeprom * eeprom,u8 * data)3196 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
3197 struct ethtool_eeprom *eeprom, u8 *data)
3198 {
3199 struct mv88e6xxx_chip *chip = ds->priv;
3200 int err;
3201
3202 if (!chip->info->ops->set_eeprom)
3203 return -EOPNOTSUPP;
3204
3205 if (eeprom->magic != 0xc3ec4951)
3206 return -EINVAL;
3207
3208 mv88e6xxx_reg_lock(chip);
3209 err = chip->info->ops->set_eeprom(chip, eeprom, data);
3210 mv88e6xxx_reg_unlock(chip);
3211
3212 return err;
3213 }
3214
3215 static const struct mv88e6xxx_ops mv88e6085_ops = {
3216 /* MV88E6XXX_FAMILY_6097 */
3217 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3218 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3219 .irl_init_all = mv88e6352_g2_irl_init_all,
3220 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3221 .phy_read = mv88e6185_phy_ppu_read,
3222 .phy_write = mv88e6185_phy_ppu_write,
3223 .port_set_link = mv88e6xxx_port_set_link,
3224 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3225 .port_tag_remap = mv88e6095_port_tag_remap,
3226 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3227 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3228 .port_set_ether_type = mv88e6351_port_set_ether_type,
3229 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3230 .port_pause_limit = mv88e6097_port_pause_limit,
3231 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3232 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3233 .port_get_cmode = mv88e6185_port_get_cmode,
3234 .port_setup_message_port = mv88e6xxx_setup_message_port,
3235 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3236 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3237 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3238 .stats_get_strings = mv88e6095_stats_get_strings,
3239 .stats_get_stats = mv88e6095_stats_get_stats,
3240 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3241 .set_egress_port = mv88e6095_g1_set_egress_port,
3242 .watchdog_ops = &mv88e6097_watchdog_ops,
3243 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3244 .pot_clear = mv88e6xxx_g2_pot_clear,
3245 .ppu_enable = mv88e6185_g1_ppu_enable,
3246 .ppu_disable = mv88e6185_g1_ppu_disable,
3247 .reset = mv88e6185_g1_reset,
3248 .rmu_disable = mv88e6085_g1_rmu_disable,
3249 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3250 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3251 .phylink_validate = mv88e6185_phylink_validate,
3252 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
3253 };
3254
3255 static const struct mv88e6xxx_ops mv88e6095_ops = {
3256 /* MV88E6XXX_FAMILY_6095 */
3257 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3258 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3259 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3260 .phy_read = mv88e6185_phy_ppu_read,
3261 .phy_write = mv88e6185_phy_ppu_write,
3262 .port_set_link = mv88e6xxx_port_set_link,
3263 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3264 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3265 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
3266 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
3267 .port_get_cmode = mv88e6185_port_get_cmode,
3268 .port_setup_message_port = mv88e6xxx_setup_message_port,
3269 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3270 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3271 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3272 .stats_get_strings = mv88e6095_stats_get_strings,
3273 .stats_get_stats = mv88e6095_stats_get_stats,
3274 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
3275 .ppu_enable = mv88e6185_g1_ppu_enable,
3276 .ppu_disable = mv88e6185_g1_ppu_disable,
3277 .reset = mv88e6185_g1_reset,
3278 .vtu_getnext = mv88e6185_g1_vtu_getnext,
3279 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3280 .phylink_validate = mv88e6185_phylink_validate,
3281 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
3282 };
3283
3284 static const struct mv88e6xxx_ops mv88e6097_ops = {
3285 /* MV88E6XXX_FAMILY_6097 */
3286 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3287 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3288 .irl_init_all = mv88e6352_g2_irl_init_all,
3289 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3290 .phy_read = mv88e6xxx_g2_smi_phy_read,
3291 .phy_write = mv88e6xxx_g2_smi_phy_write,
3292 .port_set_link = mv88e6xxx_port_set_link,
3293 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3294 .port_tag_remap = mv88e6095_port_tag_remap,
3295 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3296 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3297 .port_set_ether_type = mv88e6351_port_set_ether_type,
3298 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
3299 .port_pause_limit = mv88e6097_port_pause_limit,
3300 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3301 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3302 .port_get_cmode = mv88e6185_port_get_cmode,
3303 .port_setup_message_port = mv88e6xxx_setup_message_port,
3304 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3305 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3306 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3307 .stats_get_strings = mv88e6095_stats_get_strings,
3308 .stats_get_stats = mv88e6095_stats_get_stats,
3309 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3310 .set_egress_port = mv88e6095_g1_set_egress_port,
3311 .watchdog_ops = &mv88e6097_watchdog_ops,
3312 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3313 .pot_clear = mv88e6xxx_g2_pot_clear,
3314 .reset = mv88e6352_g1_reset,
3315 .rmu_disable = mv88e6085_g1_rmu_disable,
3316 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3317 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3318 .phylink_validate = mv88e6185_phylink_validate,
3319 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
3320 };
3321
3322 static const struct mv88e6xxx_ops mv88e6123_ops = {
3323 /* MV88E6XXX_FAMILY_6165 */
3324 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3325 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3326 .irl_init_all = mv88e6352_g2_irl_init_all,
3327 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3328 .phy_read = mv88e6xxx_g2_smi_phy_read,
3329 .phy_write = mv88e6xxx_g2_smi_phy_write,
3330 .port_set_link = mv88e6xxx_port_set_link,
3331 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3332 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3333 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3334 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3335 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3336 .port_get_cmode = mv88e6185_port_get_cmode,
3337 .port_setup_message_port = mv88e6xxx_setup_message_port,
3338 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3339 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3340 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3341 .stats_get_strings = mv88e6095_stats_get_strings,
3342 .stats_get_stats = mv88e6095_stats_get_stats,
3343 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3344 .set_egress_port = mv88e6095_g1_set_egress_port,
3345 .watchdog_ops = &mv88e6097_watchdog_ops,
3346 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3347 .pot_clear = mv88e6xxx_g2_pot_clear,
3348 .reset = mv88e6352_g1_reset,
3349 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3350 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3351 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3352 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3353 .phylink_validate = mv88e6185_phylink_validate,
3354 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
3355 };
3356
3357 static const struct mv88e6xxx_ops mv88e6131_ops = {
3358 /* MV88E6XXX_FAMILY_6185 */
3359 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3360 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3361 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3362 .phy_read = mv88e6185_phy_ppu_read,
3363 .phy_write = mv88e6185_phy_ppu_write,
3364 .port_set_link = mv88e6xxx_port_set_link,
3365 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3366 .port_tag_remap = mv88e6095_port_tag_remap,
3367 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3368 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
3369 .port_set_ether_type = mv88e6351_port_set_ether_type,
3370 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
3371 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3372 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3373 .port_pause_limit = mv88e6097_port_pause_limit,
3374 .port_set_pause = mv88e6185_port_set_pause,
3375 .port_get_cmode = mv88e6185_port_get_cmode,
3376 .port_setup_message_port = mv88e6xxx_setup_message_port,
3377 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3378 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3379 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3380 .stats_get_strings = mv88e6095_stats_get_strings,
3381 .stats_get_stats = mv88e6095_stats_get_stats,
3382 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3383 .set_egress_port = mv88e6095_g1_set_egress_port,
3384 .watchdog_ops = &mv88e6097_watchdog_ops,
3385 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
3386 .ppu_enable = mv88e6185_g1_ppu_enable,
3387 .set_cascade_port = mv88e6185_g1_set_cascade_port,
3388 .ppu_disable = mv88e6185_g1_ppu_disable,
3389 .reset = mv88e6185_g1_reset,
3390 .vtu_getnext = mv88e6185_g1_vtu_getnext,
3391 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3392 .phylink_validate = mv88e6185_phylink_validate,
3393 };
3394
3395 static const struct mv88e6xxx_ops mv88e6141_ops = {
3396 /* MV88E6XXX_FAMILY_6341 */
3397 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3398 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3399 .irl_init_all = mv88e6352_g2_irl_init_all,
3400 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3401 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3402 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3403 .phy_read = mv88e6xxx_g2_smi_phy_read,
3404 .phy_write = mv88e6xxx_g2_smi_phy_write,
3405 .port_set_link = mv88e6xxx_port_set_link,
3406 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3407 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
3408 .port_max_speed_mode = mv88e6341_port_max_speed_mode,
3409 .port_tag_remap = mv88e6095_port_tag_remap,
3410 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3411 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3412 .port_set_ether_type = mv88e6351_port_set_ether_type,
3413 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3414 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3415 .port_pause_limit = mv88e6097_port_pause_limit,
3416 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3417 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3418 .port_get_cmode = mv88e6352_port_get_cmode,
3419 .port_set_cmode = mv88e6341_port_set_cmode,
3420 .port_setup_message_port = mv88e6xxx_setup_message_port,
3421 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3422 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3423 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3424 .stats_get_strings = mv88e6320_stats_get_strings,
3425 .stats_get_stats = mv88e6390_stats_get_stats,
3426 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3427 .set_egress_port = mv88e6390_g1_set_egress_port,
3428 .watchdog_ops = &mv88e6390_watchdog_ops,
3429 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3430 .pot_clear = mv88e6xxx_g2_pot_clear,
3431 .reset = mv88e6352_g1_reset,
3432 .rmu_disable = mv88e6390_g1_rmu_disable,
3433 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3434 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3435 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3436 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3437 .serdes_power = mv88e6390_serdes_power,
3438 .serdes_get_lane = mv88e6341_serdes_get_lane,
3439 /* Check status register pause & lpa register */
3440 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
3441 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
3442 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
3443 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
3444 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
3445 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
3446 .serdes_irq_status = mv88e6390_serdes_irq_status,
3447 .gpio_ops = &mv88e6352_gpio_ops,
3448 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
3449 .serdes_get_strings = mv88e6390_serdes_get_strings,
3450 .serdes_get_stats = mv88e6390_serdes_get_stats,
3451 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
3452 .serdes_get_regs = mv88e6390_serdes_get_regs,
3453 .phylink_validate = mv88e6341_phylink_validate,
3454 };
3455
3456 static const struct mv88e6xxx_ops mv88e6161_ops = {
3457 /* MV88E6XXX_FAMILY_6165 */
3458 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3459 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3460 .irl_init_all = mv88e6352_g2_irl_init_all,
3461 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3462 .phy_read = mv88e6xxx_g2_smi_phy_read,
3463 .phy_write = mv88e6xxx_g2_smi_phy_write,
3464 .port_set_link = mv88e6xxx_port_set_link,
3465 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3466 .port_tag_remap = mv88e6095_port_tag_remap,
3467 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3468 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3469 .port_set_ether_type = mv88e6351_port_set_ether_type,
3470 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3471 .port_pause_limit = mv88e6097_port_pause_limit,
3472 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3473 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3474 .port_get_cmode = mv88e6185_port_get_cmode,
3475 .port_setup_message_port = mv88e6xxx_setup_message_port,
3476 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3477 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3478 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3479 .stats_get_strings = mv88e6095_stats_get_strings,
3480 .stats_get_stats = mv88e6095_stats_get_stats,
3481 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3482 .set_egress_port = mv88e6095_g1_set_egress_port,
3483 .watchdog_ops = &mv88e6097_watchdog_ops,
3484 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3485 .pot_clear = mv88e6xxx_g2_pot_clear,
3486 .reset = mv88e6352_g1_reset,
3487 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3488 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3489 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3490 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3491 .avb_ops = &mv88e6165_avb_ops,
3492 .ptp_ops = &mv88e6165_ptp_ops,
3493 .phylink_validate = mv88e6185_phylink_validate,
3494 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
3495 };
3496
3497 static const struct mv88e6xxx_ops mv88e6165_ops = {
3498 /* MV88E6XXX_FAMILY_6165 */
3499 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3500 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3501 .irl_init_all = mv88e6352_g2_irl_init_all,
3502 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3503 .phy_read = mv88e6165_phy_read,
3504 .phy_write = mv88e6165_phy_write,
3505 .port_set_link = mv88e6xxx_port_set_link,
3506 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3507 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3508 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3509 .port_get_cmode = mv88e6185_port_get_cmode,
3510 .port_setup_message_port = mv88e6xxx_setup_message_port,
3511 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3512 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3513 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3514 .stats_get_strings = mv88e6095_stats_get_strings,
3515 .stats_get_stats = mv88e6095_stats_get_stats,
3516 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3517 .set_egress_port = mv88e6095_g1_set_egress_port,
3518 .watchdog_ops = &mv88e6097_watchdog_ops,
3519 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3520 .pot_clear = mv88e6xxx_g2_pot_clear,
3521 .reset = mv88e6352_g1_reset,
3522 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3523 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3524 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3525 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3526 .avb_ops = &mv88e6165_avb_ops,
3527 .ptp_ops = &mv88e6165_ptp_ops,
3528 .phylink_validate = mv88e6185_phylink_validate,
3529 };
3530
3531 static const struct mv88e6xxx_ops mv88e6171_ops = {
3532 /* MV88E6XXX_FAMILY_6351 */
3533 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3534 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3535 .irl_init_all = mv88e6352_g2_irl_init_all,
3536 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3537 .phy_read = mv88e6xxx_g2_smi_phy_read,
3538 .phy_write = mv88e6xxx_g2_smi_phy_write,
3539 .port_set_link = mv88e6xxx_port_set_link,
3540 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3541 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3542 .port_tag_remap = mv88e6095_port_tag_remap,
3543 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3544 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3545 .port_set_ether_type = mv88e6351_port_set_ether_type,
3546 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3547 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3548 .port_pause_limit = mv88e6097_port_pause_limit,
3549 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3550 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3551 .port_get_cmode = mv88e6352_port_get_cmode,
3552 .port_setup_message_port = mv88e6xxx_setup_message_port,
3553 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3554 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3555 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3556 .stats_get_strings = mv88e6095_stats_get_strings,
3557 .stats_get_stats = mv88e6095_stats_get_stats,
3558 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3559 .set_egress_port = mv88e6095_g1_set_egress_port,
3560 .watchdog_ops = &mv88e6097_watchdog_ops,
3561 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3562 .pot_clear = mv88e6xxx_g2_pot_clear,
3563 .reset = mv88e6352_g1_reset,
3564 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3565 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3566 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3567 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3568 .phylink_validate = mv88e6185_phylink_validate,
3569 };
3570
3571 static const struct mv88e6xxx_ops mv88e6172_ops = {
3572 /* MV88E6XXX_FAMILY_6352 */
3573 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3574 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3575 .irl_init_all = mv88e6352_g2_irl_init_all,
3576 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3577 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3578 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3579 .phy_read = mv88e6xxx_g2_smi_phy_read,
3580 .phy_write = mv88e6xxx_g2_smi_phy_write,
3581 .port_set_link = mv88e6xxx_port_set_link,
3582 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3583 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
3584 .port_tag_remap = mv88e6095_port_tag_remap,
3585 .port_set_policy = mv88e6352_port_set_policy,
3586 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3587 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3588 .port_set_ether_type = mv88e6351_port_set_ether_type,
3589 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3590 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3591 .port_pause_limit = mv88e6097_port_pause_limit,
3592 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3593 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3594 .port_get_cmode = mv88e6352_port_get_cmode,
3595 .port_setup_message_port = mv88e6xxx_setup_message_port,
3596 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3597 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3598 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3599 .stats_get_strings = mv88e6095_stats_get_strings,
3600 .stats_get_stats = mv88e6095_stats_get_stats,
3601 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3602 .set_egress_port = mv88e6095_g1_set_egress_port,
3603 .watchdog_ops = &mv88e6097_watchdog_ops,
3604 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3605 .pot_clear = mv88e6xxx_g2_pot_clear,
3606 .reset = mv88e6352_g1_reset,
3607 .rmu_disable = mv88e6352_g1_rmu_disable,
3608 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3609 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3610 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3611 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3612 .serdes_get_lane = mv88e6352_serdes_get_lane,
3613 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
3614 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
3615 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
3616 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
3617 .serdes_power = mv88e6352_serdes_power,
3618 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
3619 .serdes_get_regs = mv88e6352_serdes_get_regs,
3620 .gpio_ops = &mv88e6352_gpio_ops,
3621 .phylink_validate = mv88e6352_phylink_validate,
3622 };
3623
3624 static const struct mv88e6xxx_ops mv88e6175_ops = {
3625 /* MV88E6XXX_FAMILY_6351 */
3626 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3627 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3628 .irl_init_all = mv88e6352_g2_irl_init_all,
3629 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3630 .phy_read = mv88e6xxx_g2_smi_phy_read,
3631 .phy_write = mv88e6xxx_g2_smi_phy_write,
3632 .port_set_link = mv88e6xxx_port_set_link,
3633 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3634 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3635 .port_tag_remap = mv88e6095_port_tag_remap,
3636 .port_set_policy = mv88e6352_port_set_policy,
3637 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3638 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3639 .port_set_ether_type = mv88e6351_port_set_ether_type,
3640 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3641 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3642 .port_pause_limit = mv88e6097_port_pause_limit,
3643 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3644 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3645 .port_get_cmode = mv88e6352_port_get_cmode,
3646 .port_setup_message_port = mv88e6xxx_setup_message_port,
3647 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3648 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3649 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3650 .stats_get_strings = mv88e6095_stats_get_strings,
3651 .stats_get_stats = mv88e6095_stats_get_stats,
3652 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3653 .set_egress_port = mv88e6095_g1_set_egress_port,
3654 .watchdog_ops = &mv88e6097_watchdog_ops,
3655 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3656 .pot_clear = mv88e6xxx_g2_pot_clear,
3657 .reset = mv88e6352_g1_reset,
3658 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3659 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3660 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3661 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3662 .phylink_validate = mv88e6185_phylink_validate,
3663 };
3664
3665 static const struct mv88e6xxx_ops mv88e6176_ops = {
3666 /* MV88E6XXX_FAMILY_6352 */
3667 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3668 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3669 .irl_init_all = mv88e6352_g2_irl_init_all,
3670 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3671 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3672 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3673 .phy_read = mv88e6xxx_g2_smi_phy_read,
3674 .phy_write = mv88e6xxx_g2_smi_phy_write,
3675 .port_set_link = mv88e6xxx_port_set_link,
3676 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3677 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
3678 .port_tag_remap = mv88e6095_port_tag_remap,
3679 .port_set_policy = mv88e6352_port_set_policy,
3680 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3681 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3682 .port_set_ether_type = mv88e6351_port_set_ether_type,
3683 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3684 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3685 .port_pause_limit = mv88e6097_port_pause_limit,
3686 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3687 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3688 .port_get_cmode = mv88e6352_port_get_cmode,
3689 .port_setup_message_port = mv88e6xxx_setup_message_port,
3690 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3691 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3692 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3693 .stats_get_strings = mv88e6095_stats_get_strings,
3694 .stats_get_stats = mv88e6095_stats_get_stats,
3695 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3696 .set_egress_port = mv88e6095_g1_set_egress_port,
3697 .watchdog_ops = &mv88e6097_watchdog_ops,
3698 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3699 .pot_clear = mv88e6xxx_g2_pot_clear,
3700 .reset = mv88e6352_g1_reset,
3701 .rmu_disable = mv88e6352_g1_rmu_disable,
3702 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3703 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3704 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3705 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3706 .serdes_get_lane = mv88e6352_serdes_get_lane,
3707 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
3708 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
3709 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
3710 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
3711 .serdes_power = mv88e6352_serdes_power,
3712 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
3713 .serdes_irq_enable = mv88e6352_serdes_irq_enable,
3714 .serdes_irq_status = mv88e6352_serdes_irq_status,
3715 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
3716 .serdes_get_regs = mv88e6352_serdes_get_regs,
3717 .gpio_ops = &mv88e6352_gpio_ops,
3718 .phylink_validate = mv88e6352_phylink_validate,
3719 };
3720
3721 static const struct mv88e6xxx_ops mv88e6185_ops = {
3722 /* MV88E6XXX_FAMILY_6185 */
3723 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3724 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3725 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3726 .phy_read = mv88e6185_phy_ppu_read,
3727 .phy_write = mv88e6185_phy_ppu_write,
3728 .port_set_link = mv88e6xxx_port_set_link,
3729 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3730 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3731 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
3732 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
3733 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
3734 .port_set_pause = mv88e6185_port_set_pause,
3735 .port_get_cmode = mv88e6185_port_get_cmode,
3736 .port_setup_message_port = mv88e6xxx_setup_message_port,
3737 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3738 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3739 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3740 .stats_get_strings = mv88e6095_stats_get_strings,
3741 .stats_get_stats = mv88e6095_stats_get_stats,
3742 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3743 .set_egress_port = mv88e6095_g1_set_egress_port,
3744 .watchdog_ops = &mv88e6097_watchdog_ops,
3745 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
3746 .set_cascade_port = mv88e6185_g1_set_cascade_port,
3747 .ppu_enable = mv88e6185_g1_ppu_enable,
3748 .ppu_disable = mv88e6185_g1_ppu_disable,
3749 .reset = mv88e6185_g1_reset,
3750 .vtu_getnext = mv88e6185_g1_vtu_getnext,
3751 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3752 .phylink_validate = mv88e6185_phylink_validate,
3753 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
3754 };
3755
3756 static const struct mv88e6xxx_ops mv88e6190_ops = {
3757 /* MV88E6XXX_FAMILY_6390 */
3758 .setup_errata = mv88e6390_setup_errata,
3759 .irl_init_all = mv88e6390_g2_irl_init_all,
3760 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3761 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3762 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3763 .phy_read = mv88e6xxx_g2_smi_phy_read,
3764 .phy_write = mv88e6xxx_g2_smi_phy_write,
3765 .port_set_link = mv88e6xxx_port_set_link,
3766 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3767 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
3768 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
3769 .port_tag_remap = mv88e6390_port_tag_remap,
3770 .port_set_policy = mv88e6352_port_set_policy,
3771 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3772 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3773 .port_set_ether_type = mv88e6351_port_set_ether_type,
3774 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3775 .port_pause_limit = mv88e6390_port_pause_limit,
3776 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3777 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3778 .port_get_cmode = mv88e6352_port_get_cmode,
3779 .port_set_cmode = mv88e6390_port_set_cmode,
3780 .port_setup_message_port = mv88e6xxx_setup_message_port,
3781 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3782 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3783 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3784 .stats_get_strings = mv88e6320_stats_get_strings,
3785 .stats_get_stats = mv88e6390_stats_get_stats,
3786 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3787 .set_egress_port = mv88e6390_g1_set_egress_port,
3788 .watchdog_ops = &mv88e6390_watchdog_ops,
3789 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3790 .pot_clear = mv88e6xxx_g2_pot_clear,
3791 .reset = mv88e6352_g1_reset,
3792 .rmu_disable = mv88e6390_g1_rmu_disable,
3793 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3794 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3795 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3796 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3797 .serdes_power = mv88e6390_serdes_power,
3798 .serdes_get_lane = mv88e6390_serdes_get_lane,
3799 /* Check status register pause & lpa register */
3800 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
3801 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
3802 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
3803 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
3804 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
3805 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
3806 .serdes_irq_status = mv88e6390_serdes_irq_status,
3807 .serdes_get_strings = mv88e6390_serdes_get_strings,
3808 .serdes_get_stats = mv88e6390_serdes_get_stats,
3809 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
3810 .serdes_get_regs = mv88e6390_serdes_get_regs,
3811 .gpio_ops = &mv88e6352_gpio_ops,
3812 .phylink_validate = mv88e6390_phylink_validate,
3813 };
3814
3815 static const struct mv88e6xxx_ops mv88e6190x_ops = {
3816 /* MV88E6XXX_FAMILY_6390 */
3817 .setup_errata = mv88e6390_setup_errata,
3818 .irl_init_all = mv88e6390_g2_irl_init_all,
3819 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3820 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3821 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3822 .phy_read = mv88e6xxx_g2_smi_phy_read,
3823 .phy_write = mv88e6xxx_g2_smi_phy_write,
3824 .port_set_link = mv88e6xxx_port_set_link,
3825 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3826 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
3827 .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
3828 .port_tag_remap = mv88e6390_port_tag_remap,
3829 .port_set_policy = mv88e6352_port_set_policy,
3830 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3831 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3832 .port_set_ether_type = mv88e6351_port_set_ether_type,
3833 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3834 .port_pause_limit = mv88e6390_port_pause_limit,
3835 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3836 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3837 .port_get_cmode = mv88e6352_port_get_cmode,
3838 .port_set_cmode = mv88e6390x_port_set_cmode,
3839 .port_setup_message_port = mv88e6xxx_setup_message_port,
3840 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3841 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3842 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3843 .stats_get_strings = mv88e6320_stats_get_strings,
3844 .stats_get_stats = mv88e6390_stats_get_stats,
3845 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3846 .set_egress_port = mv88e6390_g1_set_egress_port,
3847 .watchdog_ops = &mv88e6390_watchdog_ops,
3848 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3849 .pot_clear = mv88e6xxx_g2_pot_clear,
3850 .reset = mv88e6352_g1_reset,
3851 .rmu_disable = mv88e6390_g1_rmu_disable,
3852 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3853 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3854 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3855 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3856 .serdes_power = mv88e6390_serdes_power,
3857 .serdes_get_lane = mv88e6390x_serdes_get_lane,
3858 /* Check status register pause & lpa register */
3859 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
3860 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
3861 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
3862 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
3863 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
3864 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
3865 .serdes_irq_status = mv88e6390_serdes_irq_status,
3866 .serdes_get_strings = mv88e6390_serdes_get_strings,
3867 .serdes_get_stats = mv88e6390_serdes_get_stats,
3868 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
3869 .serdes_get_regs = mv88e6390_serdes_get_regs,
3870 .gpio_ops = &mv88e6352_gpio_ops,
3871 .phylink_validate = mv88e6390x_phylink_validate,
3872 };
3873
3874 static const struct mv88e6xxx_ops mv88e6191_ops = {
3875 /* MV88E6XXX_FAMILY_6390 */
3876 .setup_errata = mv88e6390_setup_errata,
3877 .irl_init_all = mv88e6390_g2_irl_init_all,
3878 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3879 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3880 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3881 .phy_read = mv88e6xxx_g2_smi_phy_read,
3882 .phy_write = mv88e6xxx_g2_smi_phy_write,
3883 .port_set_link = mv88e6xxx_port_set_link,
3884 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3885 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
3886 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
3887 .port_tag_remap = mv88e6390_port_tag_remap,
3888 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3889 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3890 .port_set_ether_type = mv88e6351_port_set_ether_type,
3891 .port_pause_limit = mv88e6390_port_pause_limit,
3892 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3893 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3894 .port_get_cmode = mv88e6352_port_get_cmode,
3895 .port_set_cmode = mv88e6390_port_set_cmode,
3896 .port_setup_message_port = mv88e6xxx_setup_message_port,
3897 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3898 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3899 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3900 .stats_get_strings = mv88e6320_stats_get_strings,
3901 .stats_get_stats = mv88e6390_stats_get_stats,
3902 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3903 .set_egress_port = mv88e6390_g1_set_egress_port,
3904 .watchdog_ops = &mv88e6390_watchdog_ops,
3905 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3906 .pot_clear = mv88e6xxx_g2_pot_clear,
3907 .reset = mv88e6352_g1_reset,
3908 .rmu_disable = mv88e6390_g1_rmu_disable,
3909 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3910 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3911 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3912 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3913 .serdes_power = mv88e6390_serdes_power,
3914 .serdes_get_lane = mv88e6390_serdes_get_lane,
3915 /* Check status register pause & lpa register */
3916 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
3917 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
3918 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
3919 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
3920 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
3921 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
3922 .serdes_irq_status = mv88e6390_serdes_irq_status,
3923 .serdes_get_strings = mv88e6390_serdes_get_strings,
3924 .serdes_get_stats = mv88e6390_serdes_get_stats,
3925 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
3926 .serdes_get_regs = mv88e6390_serdes_get_regs,
3927 .avb_ops = &mv88e6390_avb_ops,
3928 .ptp_ops = &mv88e6352_ptp_ops,
3929 .phylink_validate = mv88e6390_phylink_validate,
3930 };
3931
3932 static const struct mv88e6xxx_ops mv88e6240_ops = {
3933 /* MV88E6XXX_FAMILY_6352 */
3934 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3935 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3936 .irl_init_all = mv88e6352_g2_irl_init_all,
3937 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3938 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3939 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3940 .phy_read = mv88e6xxx_g2_smi_phy_read,
3941 .phy_write = mv88e6xxx_g2_smi_phy_write,
3942 .port_set_link = mv88e6xxx_port_set_link,
3943 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3944 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
3945 .port_tag_remap = mv88e6095_port_tag_remap,
3946 .port_set_policy = mv88e6352_port_set_policy,
3947 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3948 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3949 .port_set_ether_type = mv88e6351_port_set_ether_type,
3950 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3951 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3952 .port_pause_limit = mv88e6097_port_pause_limit,
3953 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3954 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3955 .port_get_cmode = mv88e6352_port_get_cmode,
3956 .port_setup_message_port = mv88e6xxx_setup_message_port,
3957 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3958 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3959 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3960 .stats_get_strings = mv88e6095_stats_get_strings,
3961 .stats_get_stats = mv88e6095_stats_get_stats,
3962 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3963 .set_egress_port = mv88e6095_g1_set_egress_port,
3964 .watchdog_ops = &mv88e6097_watchdog_ops,
3965 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3966 .pot_clear = mv88e6xxx_g2_pot_clear,
3967 .reset = mv88e6352_g1_reset,
3968 .rmu_disable = mv88e6352_g1_rmu_disable,
3969 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3970 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3971 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3972 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3973 .serdes_get_lane = mv88e6352_serdes_get_lane,
3974 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
3975 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
3976 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
3977 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
3978 .serdes_power = mv88e6352_serdes_power,
3979 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
3980 .serdes_irq_enable = mv88e6352_serdes_irq_enable,
3981 .serdes_irq_status = mv88e6352_serdes_irq_status,
3982 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
3983 .serdes_get_regs = mv88e6352_serdes_get_regs,
3984 .gpio_ops = &mv88e6352_gpio_ops,
3985 .avb_ops = &mv88e6352_avb_ops,
3986 .ptp_ops = &mv88e6352_ptp_ops,
3987 .phylink_validate = mv88e6352_phylink_validate,
3988 };
3989
3990 static const struct mv88e6xxx_ops mv88e6250_ops = {
3991 /* MV88E6XXX_FAMILY_6250 */
3992 .ieee_pri_map = mv88e6250_g1_ieee_pri_map,
3993 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3994 .irl_init_all = mv88e6352_g2_irl_init_all,
3995 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3996 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3997 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3998 .phy_read = mv88e6xxx_g2_smi_phy_read,
3999 .phy_write = mv88e6xxx_g2_smi_phy_write,
4000 .port_set_link = mv88e6xxx_port_set_link,
4001 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4002 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex,
4003 .port_tag_remap = mv88e6095_port_tag_remap,
4004 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4005 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4006 .port_set_ether_type = mv88e6351_port_set_ether_type,
4007 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4008 .port_pause_limit = mv88e6097_port_pause_limit,
4009 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4010 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4011 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4012 .stats_get_sset_count = mv88e6250_stats_get_sset_count,
4013 .stats_get_strings = mv88e6250_stats_get_strings,
4014 .stats_get_stats = mv88e6250_stats_get_stats,
4015 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4016 .set_egress_port = mv88e6095_g1_set_egress_port,
4017 .watchdog_ops = &mv88e6250_watchdog_ops,
4018 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4019 .pot_clear = mv88e6xxx_g2_pot_clear,
4020 .reset = mv88e6250_g1_reset,
4021 .vtu_getnext = mv88e6250_g1_vtu_getnext,
4022 .vtu_loadpurge = mv88e6250_g1_vtu_loadpurge,
4023 .avb_ops = &mv88e6352_avb_ops,
4024 .ptp_ops = &mv88e6250_ptp_ops,
4025 .phylink_validate = mv88e6065_phylink_validate,
4026 };
4027
4028 static const struct mv88e6xxx_ops mv88e6290_ops = {
4029 /* MV88E6XXX_FAMILY_6390 */
4030 .setup_errata = mv88e6390_setup_errata,
4031 .irl_init_all = mv88e6390_g2_irl_init_all,
4032 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4033 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4034 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4035 .phy_read = mv88e6xxx_g2_smi_phy_read,
4036 .phy_write = mv88e6xxx_g2_smi_phy_write,
4037 .port_set_link = mv88e6xxx_port_set_link,
4038 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4039 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4040 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4041 .port_tag_remap = mv88e6390_port_tag_remap,
4042 .port_set_policy = mv88e6352_port_set_policy,
4043 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4044 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4045 .port_set_ether_type = mv88e6351_port_set_ether_type,
4046 .port_pause_limit = mv88e6390_port_pause_limit,
4047 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4048 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4049 .port_get_cmode = mv88e6352_port_get_cmode,
4050 .port_set_cmode = mv88e6390_port_set_cmode,
4051 .port_setup_message_port = mv88e6xxx_setup_message_port,
4052 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4053 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4054 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4055 .stats_get_strings = mv88e6320_stats_get_strings,
4056 .stats_get_stats = mv88e6390_stats_get_stats,
4057 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4058 .set_egress_port = mv88e6390_g1_set_egress_port,
4059 .watchdog_ops = &mv88e6390_watchdog_ops,
4060 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4061 .pot_clear = mv88e6xxx_g2_pot_clear,
4062 .reset = mv88e6352_g1_reset,
4063 .rmu_disable = mv88e6390_g1_rmu_disable,
4064 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4065 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4066 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4067 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4068 .serdes_power = mv88e6390_serdes_power,
4069 .serdes_get_lane = mv88e6390_serdes_get_lane,
4070 /* Check status register pause & lpa register */
4071 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4072 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4073 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4074 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4075 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4076 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4077 .serdes_irq_status = mv88e6390_serdes_irq_status,
4078 .serdes_get_strings = mv88e6390_serdes_get_strings,
4079 .serdes_get_stats = mv88e6390_serdes_get_stats,
4080 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4081 .serdes_get_regs = mv88e6390_serdes_get_regs,
4082 .gpio_ops = &mv88e6352_gpio_ops,
4083 .avb_ops = &mv88e6390_avb_ops,
4084 .ptp_ops = &mv88e6352_ptp_ops,
4085 .phylink_validate = mv88e6390_phylink_validate,
4086 };
4087
4088 static const struct mv88e6xxx_ops mv88e6320_ops = {
4089 /* MV88E6XXX_FAMILY_6320 */
4090 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4091 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4092 .irl_init_all = mv88e6352_g2_irl_init_all,
4093 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4094 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4095 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4096 .phy_read = mv88e6xxx_g2_smi_phy_read,
4097 .phy_write = mv88e6xxx_g2_smi_phy_write,
4098 .port_set_link = mv88e6xxx_port_set_link,
4099 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4100 .port_tag_remap = mv88e6095_port_tag_remap,
4101 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4102 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4103 .port_set_ether_type = mv88e6351_port_set_ether_type,
4104 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4105 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4106 .port_pause_limit = mv88e6097_port_pause_limit,
4107 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4108 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4109 .port_get_cmode = mv88e6352_port_get_cmode,
4110 .port_setup_message_port = mv88e6xxx_setup_message_port,
4111 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4112 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4113 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4114 .stats_get_strings = mv88e6320_stats_get_strings,
4115 .stats_get_stats = mv88e6320_stats_get_stats,
4116 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4117 .set_egress_port = mv88e6095_g1_set_egress_port,
4118 .watchdog_ops = &mv88e6390_watchdog_ops,
4119 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4120 .pot_clear = mv88e6xxx_g2_pot_clear,
4121 .reset = mv88e6352_g1_reset,
4122 .vtu_getnext = mv88e6185_g1_vtu_getnext,
4123 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4124 .gpio_ops = &mv88e6352_gpio_ops,
4125 .avb_ops = &mv88e6352_avb_ops,
4126 .ptp_ops = &mv88e6352_ptp_ops,
4127 .phylink_validate = mv88e6185_phylink_validate,
4128 };
4129
4130 static const struct mv88e6xxx_ops mv88e6321_ops = {
4131 /* MV88E6XXX_FAMILY_6320 */
4132 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4133 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4134 .irl_init_all = mv88e6352_g2_irl_init_all,
4135 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4136 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4137 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4138 .phy_read = mv88e6xxx_g2_smi_phy_read,
4139 .phy_write = mv88e6xxx_g2_smi_phy_write,
4140 .port_set_link = mv88e6xxx_port_set_link,
4141 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4142 .port_tag_remap = mv88e6095_port_tag_remap,
4143 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4144 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4145 .port_set_ether_type = mv88e6351_port_set_ether_type,
4146 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4147 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4148 .port_pause_limit = mv88e6097_port_pause_limit,
4149 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4150 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4151 .port_get_cmode = mv88e6352_port_get_cmode,
4152 .port_setup_message_port = mv88e6xxx_setup_message_port,
4153 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4154 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4155 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4156 .stats_get_strings = mv88e6320_stats_get_strings,
4157 .stats_get_stats = mv88e6320_stats_get_stats,
4158 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4159 .set_egress_port = mv88e6095_g1_set_egress_port,
4160 .watchdog_ops = &mv88e6390_watchdog_ops,
4161 .reset = mv88e6352_g1_reset,
4162 .vtu_getnext = mv88e6185_g1_vtu_getnext,
4163 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4164 .gpio_ops = &mv88e6352_gpio_ops,
4165 .avb_ops = &mv88e6352_avb_ops,
4166 .ptp_ops = &mv88e6352_ptp_ops,
4167 .phylink_validate = mv88e6185_phylink_validate,
4168 };
4169
4170 static const struct mv88e6xxx_ops mv88e6341_ops = {
4171 /* MV88E6XXX_FAMILY_6341 */
4172 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4173 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4174 .irl_init_all = mv88e6352_g2_irl_init_all,
4175 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4176 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4177 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4178 .phy_read = mv88e6xxx_g2_smi_phy_read,
4179 .phy_write = mv88e6xxx_g2_smi_phy_write,
4180 .port_set_link = mv88e6xxx_port_set_link,
4181 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4182 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
4183 .port_max_speed_mode = mv88e6341_port_max_speed_mode,
4184 .port_tag_remap = mv88e6095_port_tag_remap,
4185 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4186 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4187 .port_set_ether_type = mv88e6351_port_set_ether_type,
4188 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4189 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4190 .port_pause_limit = mv88e6097_port_pause_limit,
4191 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4192 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4193 .port_get_cmode = mv88e6352_port_get_cmode,
4194 .port_set_cmode = mv88e6341_port_set_cmode,
4195 .port_setup_message_port = mv88e6xxx_setup_message_port,
4196 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4197 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4198 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4199 .stats_get_strings = mv88e6320_stats_get_strings,
4200 .stats_get_stats = mv88e6390_stats_get_stats,
4201 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4202 .set_egress_port = mv88e6390_g1_set_egress_port,
4203 .watchdog_ops = &mv88e6390_watchdog_ops,
4204 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4205 .pot_clear = mv88e6xxx_g2_pot_clear,
4206 .reset = mv88e6352_g1_reset,
4207 .rmu_disable = mv88e6390_g1_rmu_disable,
4208 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4209 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4210 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4211 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4212 .serdes_power = mv88e6390_serdes_power,
4213 .serdes_get_lane = mv88e6341_serdes_get_lane,
4214 /* Check status register pause & lpa register */
4215 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4216 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4217 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4218 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4219 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4220 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4221 .serdes_irq_status = mv88e6390_serdes_irq_status,
4222 .gpio_ops = &mv88e6352_gpio_ops,
4223 .avb_ops = &mv88e6390_avb_ops,
4224 .ptp_ops = &mv88e6352_ptp_ops,
4225 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4226 .serdes_get_strings = mv88e6390_serdes_get_strings,
4227 .serdes_get_stats = mv88e6390_serdes_get_stats,
4228 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4229 .serdes_get_regs = mv88e6390_serdes_get_regs,
4230 .phylink_validate = mv88e6341_phylink_validate,
4231 };
4232
4233 static const struct mv88e6xxx_ops mv88e6350_ops = {
4234 /* MV88E6XXX_FAMILY_6351 */
4235 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4236 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4237 .irl_init_all = mv88e6352_g2_irl_init_all,
4238 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4239 .phy_read = mv88e6xxx_g2_smi_phy_read,
4240 .phy_write = mv88e6xxx_g2_smi_phy_write,
4241 .port_set_link = mv88e6xxx_port_set_link,
4242 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4243 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4244 .port_tag_remap = mv88e6095_port_tag_remap,
4245 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4246 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4247 .port_set_ether_type = mv88e6351_port_set_ether_type,
4248 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4249 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4250 .port_pause_limit = mv88e6097_port_pause_limit,
4251 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4252 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4253 .port_get_cmode = mv88e6352_port_get_cmode,
4254 .port_setup_message_port = mv88e6xxx_setup_message_port,
4255 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4256 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4257 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4258 .stats_get_strings = mv88e6095_stats_get_strings,
4259 .stats_get_stats = mv88e6095_stats_get_stats,
4260 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4261 .set_egress_port = mv88e6095_g1_set_egress_port,
4262 .watchdog_ops = &mv88e6097_watchdog_ops,
4263 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4264 .pot_clear = mv88e6xxx_g2_pot_clear,
4265 .reset = mv88e6352_g1_reset,
4266 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4267 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4268 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4269 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4270 .phylink_validate = mv88e6185_phylink_validate,
4271 };
4272
4273 static const struct mv88e6xxx_ops mv88e6351_ops = {
4274 /* MV88E6XXX_FAMILY_6351 */
4275 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4276 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4277 .irl_init_all = mv88e6352_g2_irl_init_all,
4278 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4279 .phy_read = mv88e6xxx_g2_smi_phy_read,
4280 .phy_write = mv88e6xxx_g2_smi_phy_write,
4281 .port_set_link = mv88e6xxx_port_set_link,
4282 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4283 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4284 .port_tag_remap = mv88e6095_port_tag_remap,
4285 .port_set_policy = mv88e6352_port_set_policy,
4286 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4287 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4288 .port_set_ether_type = mv88e6351_port_set_ether_type,
4289 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4290 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4291 .port_pause_limit = mv88e6097_port_pause_limit,
4292 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4293 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4294 .port_get_cmode = mv88e6352_port_get_cmode,
4295 .port_setup_message_port = mv88e6xxx_setup_message_port,
4296 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4297 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4298 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4299 .stats_get_strings = mv88e6095_stats_get_strings,
4300 .stats_get_stats = mv88e6095_stats_get_stats,
4301 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4302 .set_egress_port = mv88e6095_g1_set_egress_port,
4303 .watchdog_ops = &mv88e6097_watchdog_ops,
4304 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4305 .pot_clear = mv88e6xxx_g2_pot_clear,
4306 .reset = mv88e6352_g1_reset,
4307 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4308 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4309 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4310 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4311 .avb_ops = &mv88e6352_avb_ops,
4312 .ptp_ops = &mv88e6352_ptp_ops,
4313 .phylink_validate = mv88e6185_phylink_validate,
4314 };
4315
4316 static const struct mv88e6xxx_ops mv88e6352_ops = {
4317 /* MV88E6XXX_FAMILY_6352 */
4318 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4319 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4320 .irl_init_all = mv88e6352_g2_irl_init_all,
4321 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4322 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4323 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4324 .phy_read = mv88e6xxx_g2_smi_phy_read,
4325 .phy_write = mv88e6xxx_g2_smi_phy_write,
4326 .port_set_link = mv88e6xxx_port_set_link,
4327 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4328 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4329 .port_tag_remap = mv88e6095_port_tag_remap,
4330 .port_set_policy = mv88e6352_port_set_policy,
4331 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4332 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4333 .port_set_ether_type = mv88e6351_port_set_ether_type,
4334 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4335 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4336 .port_pause_limit = mv88e6097_port_pause_limit,
4337 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4338 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4339 .port_get_cmode = mv88e6352_port_get_cmode,
4340 .port_setup_message_port = mv88e6xxx_setup_message_port,
4341 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4342 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4343 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4344 .stats_get_strings = mv88e6095_stats_get_strings,
4345 .stats_get_stats = mv88e6095_stats_get_stats,
4346 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4347 .set_egress_port = mv88e6095_g1_set_egress_port,
4348 .watchdog_ops = &mv88e6097_watchdog_ops,
4349 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4350 .pot_clear = mv88e6xxx_g2_pot_clear,
4351 .reset = mv88e6352_g1_reset,
4352 .rmu_disable = mv88e6352_g1_rmu_disable,
4353 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4354 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4355 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4356 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4357 .serdes_get_lane = mv88e6352_serdes_get_lane,
4358 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
4359 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
4360 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
4361 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
4362 .serdes_power = mv88e6352_serdes_power,
4363 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
4364 .serdes_irq_enable = mv88e6352_serdes_irq_enable,
4365 .serdes_irq_status = mv88e6352_serdes_irq_status,
4366 .gpio_ops = &mv88e6352_gpio_ops,
4367 .avb_ops = &mv88e6352_avb_ops,
4368 .ptp_ops = &mv88e6352_ptp_ops,
4369 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count,
4370 .serdes_get_strings = mv88e6352_serdes_get_strings,
4371 .serdes_get_stats = mv88e6352_serdes_get_stats,
4372 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4373 .serdes_get_regs = mv88e6352_serdes_get_regs,
4374 .phylink_validate = mv88e6352_phylink_validate,
4375 };
4376
4377 static const struct mv88e6xxx_ops mv88e6390_ops = {
4378 /* MV88E6XXX_FAMILY_6390 */
4379 .setup_errata = mv88e6390_setup_errata,
4380 .irl_init_all = mv88e6390_g2_irl_init_all,
4381 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4382 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4383 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4384 .phy_read = mv88e6xxx_g2_smi_phy_read,
4385 .phy_write = mv88e6xxx_g2_smi_phy_write,
4386 .port_set_link = mv88e6xxx_port_set_link,
4387 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4388 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4389 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4390 .port_tag_remap = mv88e6390_port_tag_remap,
4391 .port_set_policy = mv88e6352_port_set_policy,
4392 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4393 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4394 .port_set_ether_type = mv88e6351_port_set_ether_type,
4395 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4396 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4397 .port_pause_limit = mv88e6390_port_pause_limit,
4398 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4399 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4400 .port_get_cmode = mv88e6352_port_get_cmode,
4401 .port_set_cmode = mv88e6390_port_set_cmode,
4402 .port_setup_message_port = mv88e6xxx_setup_message_port,
4403 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4404 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4405 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4406 .stats_get_strings = mv88e6320_stats_get_strings,
4407 .stats_get_stats = mv88e6390_stats_get_stats,
4408 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4409 .set_egress_port = mv88e6390_g1_set_egress_port,
4410 .watchdog_ops = &mv88e6390_watchdog_ops,
4411 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4412 .pot_clear = mv88e6xxx_g2_pot_clear,
4413 .reset = mv88e6352_g1_reset,
4414 .rmu_disable = mv88e6390_g1_rmu_disable,
4415 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4416 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4417 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4418 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4419 .serdes_power = mv88e6390_serdes_power,
4420 .serdes_get_lane = mv88e6390_serdes_get_lane,
4421 /* Check status register pause & lpa register */
4422 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4423 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4424 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4425 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4426 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4427 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4428 .serdes_irq_status = mv88e6390_serdes_irq_status,
4429 .gpio_ops = &mv88e6352_gpio_ops,
4430 .avb_ops = &mv88e6390_avb_ops,
4431 .ptp_ops = &mv88e6352_ptp_ops,
4432 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4433 .serdes_get_strings = mv88e6390_serdes_get_strings,
4434 .serdes_get_stats = mv88e6390_serdes_get_stats,
4435 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4436 .serdes_get_regs = mv88e6390_serdes_get_regs,
4437 .phylink_validate = mv88e6390_phylink_validate,
4438 };
4439
4440 static const struct mv88e6xxx_ops mv88e6390x_ops = {
4441 /* MV88E6XXX_FAMILY_6390 */
4442 .setup_errata = mv88e6390_setup_errata,
4443 .irl_init_all = mv88e6390_g2_irl_init_all,
4444 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4445 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4446 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4447 .phy_read = mv88e6xxx_g2_smi_phy_read,
4448 .phy_write = mv88e6xxx_g2_smi_phy_write,
4449 .port_set_link = mv88e6xxx_port_set_link,
4450 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4451 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
4452 .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
4453 .port_tag_remap = mv88e6390_port_tag_remap,
4454 .port_set_policy = mv88e6352_port_set_policy,
4455 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4456 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4457 .port_set_ether_type = mv88e6351_port_set_ether_type,
4458 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4459 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4460 .port_pause_limit = mv88e6390_port_pause_limit,
4461 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4462 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4463 .port_get_cmode = mv88e6352_port_get_cmode,
4464 .port_set_cmode = mv88e6390x_port_set_cmode,
4465 .port_setup_message_port = mv88e6xxx_setup_message_port,
4466 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4467 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4468 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4469 .stats_get_strings = mv88e6320_stats_get_strings,
4470 .stats_get_stats = mv88e6390_stats_get_stats,
4471 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4472 .set_egress_port = mv88e6390_g1_set_egress_port,
4473 .watchdog_ops = &mv88e6390_watchdog_ops,
4474 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4475 .pot_clear = mv88e6xxx_g2_pot_clear,
4476 .reset = mv88e6352_g1_reset,
4477 .rmu_disable = mv88e6390_g1_rmu_disable,
4478 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4479 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4480 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4481 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4482 .serdes_power = mv88e6390_serdes_power,
4483 .serdes_get_lane = mv88e6390x_serdes_get_lane,
4484 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4485 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4486 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4487 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4488 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4489 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4490 .serdes_irq_status = mv88e6390_serdes_irq_status,
4491 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4492 .serdes_get_strings = mv88e6390_serdes_get_strings,
4493 .serdes_get_stats = mv88e6390_serdes_get_stats,
4494 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4495 .serdes_get_regs = mv88e6390_serdes_get_regs,
4496 .gpio_ops = &mv88e6352_gpio_ops,
4497 .avb_ops = &mv88e6390_avb_ops,
4498 .ptp_ops = &mv88e6352_ptp_ops,
4499 .phylink_validate = mv88e6390x_phylink_validate,
4500 };
4501
4502 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
4503 [MV88E6085] = {
4504 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
4505 .family = MV88E6XXX_FAMILY_6097,
4506 .name = "Marvell 88E6085",
4507 .num_databases = 4096,
4508 .num_macs = 8192,
4509 .num_ports = 10,
4510 .num_internal_phys = 5,
4511 .max_vid = 4095,
4512 .port_base_addr = 0x10,
4513 .phy_base_addr = 0x0,
4514 .global1_addr = 0x1b,
4515 .global2_addr = 0x1c,
4516 .age_time_coeff = 15000,
4517 .g1_irqs = 8,
4518 .g2_irqs = 10,
4519 .atu_move_port_mask = 0xf,
4520 .pvt = true,
4521 .multi_chip = true,
4522 .tag_protocol = DSA_TAG_PROTO_DSA,
4523 .ops = &mv88e6085_ops,
4524 },
4525
4526 [MV88E6095] = {
4527 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
4528 .family = MV88E6XXX_FAMILY_6095,
4529 .name = "Marvell 88E6095/88E6095F",
4530 .num_databases = 256,
4531 .num_macs = 8192,
4532 .num_ports = 11,
4533 .num_internal_phys = 0,
4534 .max_vid = 4095,
4535 .port_base_addr = 0x10,
4536 .phy_base_addr = 0x0,
4537 .global1_addr = 0x1b,
4538 .global2_addr = 0x1c,
4539 .age_time_coeff = 15000,
4540 .g1_irqs = 8,
4541 .atu_move_port_mask = 0xf,
4542 .multi_chip = true,
4543 .tag_protocol = DSA_TAG_PROTO_DSA,
4544 .ops = &mv88e6095_ops,
4545 },
4546
4547 [MV88E6097] = {
4548 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
4549 .family = MV88E6XXX_FAMILY_6097,
4550 .name = "Marvell 88E6097/88E6097F",
4551 .num_databases = 4096,
4552 .num_macs = 8192,
4553 .num_ports = 11,
4554 .num_internal_phys = 8,
4555 .max_vid = 4095,
4556 .port_base_addr = 0x10,
4557 .phy_base_addr = 0x0,
4558 .global1_addr = 0x1b,
4559 .global2_addr = 0x1c,
4560 .age_time_coeff = 15000,
4561 .g1_irqs = 8,
4562 .g2_irqs = 10,
4563 .atu_move_port_mask = 0xf,
4564 .pvt = true,
4565 .multi_chip = true,
4566 .tag_protocol = DSA_TAG_PROTO_EDSA,
4567 .ops = &mv88e6097_ops,
4568 },
4569
4570 [MV88E6123] = {
4571 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
4572 .family = MV88E6XXX_FAMILY_6165,
4573 .name = "Marvell 88E6123",
4574 .num_databases = 4096,
4575 .num_macs = 1024,
4576 .num_ports = 3,
4577 .num_internal_phys = 5,
4578 .max_vid = 4095,
4579 .port_base_addr = 0x10,
4580 .phy_base_addr = 0x0,
4581 .global1_addr = 0x1b,
4582 .global2_addr = 0x1c,
4583 .age_time_coeff = 15000,
4584 .g1_irqs = 9,
4585 .g2_irqs = 10,
4586 .atu_move_port_mask = 0xf,
4587 .pvt = true,
4588 .multi_chip = true,
4589 .tag_protocol = DSA_TAG_PROTO_EDSA,
4590 .ops = &mv88e6123_ops,
4591 },
4592
4593 [MV88E6131] = {
4594 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
4595 .family = MV88E6XXX_FAMILY_6185,
4596 .name = "Marvell 88E6131",
4597 .num_databases = 256,
4598 .num_macs = 8192,
4599 .num_ports = 8,
4600 .num_internal_phys = 0,
4601 .max_vid = 4095,
4602 .port_base_addr = 0x10,
4603 .phy_base_addr = 0x0,
4604 .global1_addr = 0x1b,
4605 .global2_addr = 0x1c,
4606 .age_time_coeff = 15000,
4607 .g1_irqs = 9,
4608 .atu_move_port_mask = 0xf,
4609 .multi_chip = true,
4610 .tag_protocol = DSA_TAG_PROTO_DSA,
4611 .ops = &mv88e6131_ops,
4612 },
4613
4614 [MV88E6141] = {
4615 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
4616 .family = MV88E6XXX_FAMILY_6341,
4617 .name = "Marvell 88E6141",
4618 .num_databases = 4096,
4619 .num_macs = 2048,
4620 .num_ports = 6,
4621 .num_internal_phys = 5,
4622 .num_gpio = 11,
4623 .max_vid = 4095,
4624 .port_base_addr = 0x10,
4625 .phy_base_addr = 0x10,
4626 .global1_addr = 0x1b,
4627 .global2_addr = 0x1c,
4628 .age_time_coeff = 3750,
4629 .atu_move_port_mask = 0x1f,
4630 .g1_irqs = 9,
4631 .g2_irqs = 10,
4632 .pvt = true,
4633 .multi_chip = true,
4634 .tag_protocol = DSA_TAG_PROTO_EDSA,
4635 .ops = &mv88e6141_ops,
4636 },
4637
4638 [MV88E6161] = {
4639 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
4640 .family = MV88E6XXX_FAMILY_6165,
4641 .name = "Marvell 88E6161",
4642 .num_databases = 4096,
4643 .num_macs = 1024,
4644 .num_ports = 6,
4645 .num_internal_phys = 5,
4646 .max_vid = 4095,
4647 .port_base_addr = 0x10,
4648 .phy_base_addr = 0x0,
4649 .global1_addr = 0x1b,
4650 .global2_addr = 0x1c,
4651 .age_time_coeff = 15000,
4652 .g1_irqs = 9,
4653 .g2_irqs = 10,
4654 .atu_move_port_mask = 0xf,
4655 .pvt = true,
4656 .multi_chip = true,
4657 .tag_protocol = DSA_TAG_PROTO_EDSA,
4658 .ptp_support = true,
4659 .ops = &mv88e6161_ops,
4660 },
4661
4662 [MV88E6165] = {
4663 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
4664 .family = MV88E6XXX_FAMILY_6165,
4665 .name = "Marvell 88E6165",
4666 .num_databases = 4096,
4667 .num_macs = 8192,
4668 .num_ports = 6,
4669 .num_internal_phys = 0,
4670 .max_vid = 4095,
4671 .port_base_addr = 0x10,
4672 .phy_base_addr = 0x0,
4673 .global1_addr = 0x1b,
4674 .global2_addr = 0x1c,
4675 .age_time_coeff = 15000,
4676 .g1_irqs = 9,
4677 .g2_irqs = 10,
4678 .atu_move_port_mask = 0xf,
4679 .pvt = true,
4680 .multi_chip = true,
4681 .tag_protocol = DSA_TAG_PROTO_DSA,
4682 .ptp_support = true,
4683 .ops = &mv88e6165_ops,
4684 },
4685
4686 [MV88E6171] = {
4687 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
4688 .family = MV88E6XXX_FAMILY_6351,
4689 .name = "Marvell 88E6171",
4690 .num_databases = 4096,
4691 .num_macs = 8192,
4692 .num_ports = 7,
4693 .num_internal_phys = 5,
4694 .max_vid = 4095,
4695 .port_base_addr = 0x10,
4696 .phy_base_addr = 0x0,
4697 .global1_addr = 0x1b,
4698 .global2_addr = 0x1c,
4699 .age_time_coeff = 15000,
4700 .g1_irqs = 9,
4701 .g2_irqs = 10,
4702 .atu_move_port_mask = 0xf,
4703 .pvt = true,
4704 .multi_chip = true,
4705 .tag_protocol = DSA_TAG_PROTO_EDSA,
4706 .ops = &mv88e6171_ops,
4707 },
4708
4709 [MV88E6172] = {
4710 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
4711 .family = MV88E6XXX_FAMILY_6352,
4712 .name = "Marvell 88E6172",
4713 .num_databases = 4096,
4714 .num_macs = 8192,
4715 .num_ports = 7,
4716 .num_internal_phys = 5,
4717 .num_gpio = 15,
4718 .max_vid = 4095,
4719 .port_base_addr = 0x10,
4720 .phy_base_addr = 0x0,
4721 .global1_addr = 0x1b,
4722 .global2_addr = 0x1c,
4723 .age_time_coeff = 15000,
4724 .g1_irqs = 9,
4725 .g2_irqs = 10,
4726 .atu_move_port_mask = 0xf,
4727 .pvt = true,
4728 .multi_chip = true,
4729 .tag_protocol = DSA_TAG_PROTO_EDSA,
4730 .ops = &mv88e6172_ops,
4731 },
4732
4733 [MV88E6175] = {
4734 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
4735 .family = MV88E6XXX_FAMILY_6351,
4736 .name = "Marvell 88E6175",
4737 .num_databases = 4096,
4738 .num_macs = 8192,
4739 .num_ports = 7,
4740 .num_internal_phys = 5,
4741 .max_vid = 4095,
4742 .port_base_addr = 0x10,
4743 .phy_base_addr = 0x0,
4744 .global1_addr = 0x1b,
4745 .global2_addr = 0x1c,
4746 .age_time_coeff = 15000,
4747 .g1_irqs = 9,
4748 .g2_irqs = 10,
4749 .atu_move_port_mask = 0xf,
4750 .pvt = true,
4751 .multi_chip = true,
4752 .tag_protocol = DSA_TAG_PROTO_EDSA,
4753 .ops = &mv88e6175_ops,
4754 },
4755
4756 [MV88E6176] = {
4757 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
4758 .family = MV88E6XXX_FAMILY_6352,
4759 .name = "Marvell 88E6176",
4760 .num_databases = 4096,
4761 .num_macs = 8192,
4762 .num_ports = 7,
4763 .num_internal_phys = 5,
4764 .num_gpio = 15,
4765 .max_vid = 4095,
4766 .port_base_addr = 0x10,
4767 .phy_base_addr = 0x0,
4768 .global1_addr = 0x1b,
4769 .global2_addr = 0x1c,
4770 .age_time_coeff = 15000,
4771 .g1_irqs = 9,
4772 .g2_irqs = 10,
4773 .atu_move_port_mask = 0xf,
4774 .pvt = true,
4775 .multi_chip = true,
4776 .tag_protocol = DSA_TAG_PROTO_EDSA,
4777 .ops = &mv88e6176_ops,
4778 },
4779
4780 [MV88E6185] = {
4781 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
4782 .family = MV88E6XXX_FAMILY_6185,
4783 .name = "Marvell 88E6185",
4784 .num_databases = 256,
4785 .num_macs = 8192,
4786 .num_ports = 10,
4787 .num_internal_phys = 0,
4788 .max_vid = 4095,
4789 .port_base_addr = 0x10,
4790 .phy_base_addr = 0x0,
4791 .global1_addr = 0x1b,
4792 .global2_addr = 0x1c,
4793 .age_time_coeff = 15000,
4794 .g1_irqs = 8,
4795 .atu_move_port_mask = 0xf,
4796 .multi_chip = true,
4797 .tag_protocol = DSA_TAG_PROTO_EDSA,
4798 .ops = &mv88e6185_ops,
4799 },
4800
4801 [MV88E6190] = {
4802 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
4803 .family = MV88E6XXX_FAMILY_6390,
4804 .name = "Marvell 88E6190",
4805 .num_databases = 4096,
4806 .num_macs = 16384,
4807 .num_ports = 11, /* 10 + Z80 */
4808 .num_internal_phys = 9,
4809 .num_gpio = 16,
4810 .max_vid = 8191,
4811 .port_base_addr = 0x0,
4812 .phy_base_addr = 0x0,
4813 .global1_addr = 0x1b,
4814 .global2_addr = 0x1c,
4815 .tag_protocol = DSA_TAG_PROTO_DSA,
4816 .age_time_coeff = 3750,
4817 .g1_irqs = 9,
4818 .g2_irqs = 14,
4819 .pvt = true,
4820 .multi_chip = true,
4821 .atu_move_port_mask = 0x1f,
4822 .ops = &mv88e6190_ops,
4823 },
4824
4825 [MV88E6190X] = {
4826 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
4827 .family = MV88E6XXX_FAMILY_6390,
4828 .name = "Marvell 88E6190X",
4829 .num_databases = 4096,
4830 .num_macs = 16384,
4831 .num_ports = 11, /* 10 + Z80 */
4832 .num_internal_phys = 9,
4833 .num_gpio = 16,
4834 .max_vid = 8191,
4835 .port_base_addr = 0x0,
4836 .phy_base_addr = 0x0,
4837 .global1_addr = 0x1b,
4838 .global2_addr = 0x1c,
4839 .age_time_coeff = 3750,
4840 .g1_irqs = 9,
4841 .g2_irqs = 14,
4842 .atu_move_port_mask = 0x1f,
4843 .pvt = true,
4844 .multi_chip = true,
4845 .tag_protocol = DSA_TAG_PROTO_DSA,
4846 .ops = &mv88e6190x_ops,
4847 },
4848
4849 [MV88E6191] = {
4850 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
4851 .family = MV88E6XXX_FAMILY_6390,
4852 .name = "Marvell 88E6191",
4853 .num_databases = 4096,
4854 .num_macs = 16384,
4855 .num_ports = 11, /* 10 + Z80 */
4856 .num_internal_phys = 9,
4857 .max_vid = 8191,
4858 .port_base_addr = 0x0,
4859 .phy_base_addr = 0x0,
4860 .global1_addr = 0x1b,
4861 .global2_addr = 0x1c,
4862 .age_time_coeff = 3750,
4863 .g1_irqs = 9,
4864 .g2_irqs = 14,
4865 .atu_move_port_mask = 0x1f,
4866 .pvt = true,
4867 .multi_chip = true,
4868 .tag_protocol = DSA_TAG_PROTO_DSA,
4869 .ptp_support = true,
4870 .ops = &mv88e6191_ops,
4871 },
4872
4873 [MV88E6220] = {
4874 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220,
4875 .family = MV88E6XXX_FAMILY_6250,
4876 .name = "Marvell 88E6220",
4877 .num_databases = 64,
4878
4879 /* Ports 2-4 are not routed to pins
4880 * => usable ports 0, 1, 5, 6
4881 */
4882 .num_ports = 7,
4883 .num_internal_phys = 2,
4884 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4),
4885 .max_vid = 4095,
4886 .port_base_addr = 0x08,
4887 .phy_base_addr = 0x00,
4888 .global1_addr = 0x0f,
4889 .global2_addr = 0x07,
4890 .age_time_coeff = 15000,
4891 .g1_irqs = 9,
4892 .g2_irqs = 10,
4893 .atu_move_port_mask = 0xf,
4894 .dual_chip = true,
4895 .tag_protocol = DSA_TAG_PROTO_DSA,
4896 .ptp_support = true,
4897 .ops = &mv88e6250_ops,
4898 },
4899
4900 [MV88E6240] = {
4901 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
4902 .family = MV88E6XXX_FAMILY_6352,
4903 .name = "Marvell 88E6240",
4904 .num_databases = 4096,
4905 .num_macs = 8192,
4906 .num_ports = 7,
4907 .num_internal_phys = 5,
4908 .num_gpio = 15,
4909 .max_vid = 4095,
4910 .port_base_addr = 0x10,
4911 .phy_base_addr = 0x0,
4912 .global1_addr = 0x1b,
4913 .global2_addr = 0x1c,
4914 .age_time_coeff = 15000,
4915 .g1_irqs = 9,
4916 .g2_irqs = 10,
4917 .atu_move_port_mask = 0xf,
4918 .pvt = true,
4919 .multi_chip = true,
4920 .tag_protocol = DSA_TAG_PROTO_EDSA,
4921 .ptp_support = true,
4922 .ops = &mv88e6240_ops,
4923 },
4924
4925 [MV88E6250] = {
4926 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250,
4927 .family = MV88E6XXX_FAMILY_6250,
4928 .name = "Marvell 88E6250",
4929 .num_databases = 64,
4930 .num_ports = 7,
4931 .num_internal_phys = 5,
4932 .max_vid = 4095,
4933 .port_base_addr = 0x08,
4934 .phy_base_addr = 0x00,
4935 .global1_addr = 0x0f,
4936 .global2_addr = 0x07,
4937 .age_time_coeff = 15000,
4938 .g1_irqs = 9,
4939 .g2_irqs = 10,
4940 .atu_move_port_mask = 0xf,
4941 .dual_chip = true,
4942 .tag_protocol = DSA_TAG_PROTO_DSA,
4943 .ptp_support = true,
4944 .ops = &mv88e6250_ops,
4945 },
4946
4947 [MV88E6290] = {
4948 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
4949 .family = MV88E6XXX_FAMILY_6390,
4950 .name = "Marvell 88E6290",
4951 .num_databases = 4096,
4952 .num_ports = 11, /* 10 + Z80 */
4953 .num_internal_phys = 9,
4954 .num_gpio = 16,
4955 .max_vid = 8191,
4956 .port_base_addr = 0x0,
4957 .phy_base_addr = 0x0,
4958 .global1_addr = 0x1b,
4959 .global2_addr = 0x1c,
4960 .age_time_coeff = 3750,
4961 .g1_irqs = 9,
4962 .g2_irqs = 14,
4963 .atu_move_port_mask = 0x1f,
4964 .pvt = true,
4965 .multi_chip = true,
4966 .tag_protocol = DSA_TAG_PROTO_DSA,
4967 .ptp_support = true,
4968 .ops = &mv88e6290_ops,
4969 },
4970
4971 [MV88E6320] = {
4972 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
4973 .family = MV88E6XXX_FAMILY_6320,
4974 .name = "Marvell 88E6320",
4975 .num_databases = 4096,
4976 .num_macs = 8192,
4977 .num_ports = 7,
4978 .num_internal_phys = 5,
4979 .num_gpio = 15,
4980 .max_vid = 4095,
4981 .port_base_addr = 0x10,
4982 .phy_base_addr = 0x0,
4983 .global1_addr = 0x1b,
4984 .global2_addr = 0x1c,
4985 .age_time_coeff = 15000,
4986 .g1_irqs = 8,
4987 .g2_irqs = 10,
4988 .atu_move_port_mask = 0xf,
4989 .pvt = true,
4990 .multi_chip = true,
4991 .tag_protocol = DSA_TAG_PROTO_EDSA,
4992 .ptp_support = true,
4993 .ops = &mv88e6320_ops,
4994 },
4995
4996 [MV88E6321] = {
4997 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
4998 .family = MV88E6XXX_FAMILY_6320,
4999 .name = "Marvell 88E6321",
5000 .num_databases = 4096,
5001 .num_macs = 8192,
5002 .num_ports = 7,
5003 .num_internal_phys = 5,
5004 .num_gpio = 15,
5005 .max_vid = 4095,
5006 .port_base_addr = 0x10,
5007 .phy_base_addr = 0x0,
5008 .global1_addr = 0x1b,
5009 .global2_addr = 0x1c,
5010 .age_time_coeff = 15000,
5011 .g1_irqs = 8,
5012 .g2_irqs = 10,
5013 .atu_move_port_mask = 0xf,
5014 .multi_chip = true,
5015 .tag_protocol = DSA_TAG_PROTO_EDSA,
5016 .ptp_support = true,
5017 .ops = &mv88e6321_ops,
5018 },
5019
5020 [MV88E6341] = {
5021 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
5022 .family = MV88E6XXX_FAMILY_6341,
5023 .name = "Marvell 88E6341",
5024 .num_databases = 4096,
5025 .num_macs = 2048,
5026 .num_internal_phys = 5,
5027 .num_ports = 6,
5028 .num_gpio = 11,
5029 .max_vid = 4095,
5030 .port_base_addr = 0x10,
5031 .phy_base_addr = 0x10,
5032 .global1_addr = 0x1b,
5033 .global2_addr = 0x1c,
5034 .age_time_coeff = 3750,
5035 .atu_move_port_mask = 0x1f,
5036 .g1_irqs = 9,
5037 .g2_irqs = 10,
5038 .pvt = true,
5039 .multi_chip = true,
5040 .tag_protocol = DSA_TAG_PROTO_EDSA,
5041 .ptp_support = true,
5042 .ops = &mv88e6341_ops,
5043 },
5044
5045 [MV88E6350] = {
5046 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
5047 .family = MV88E6XXX_FAMILY_6351,
5048 .name = "Marvell 88E6350",
5049 .num_databases = 4096,
5050 .num_macs = 8192,
5051 .num_ports = 7,
5052 .num_internal_phys = 5,
5053 .max_vid = 4095,
5054 .port_base_addr = 0x10,
5055 .phy_base_addr = 0x0,
5056 .global1_addr = 0x1b,
5057 .global2_addr = 0x1c,
5058 .age_time_coeff = 15000,
5059 .g1_irqs = 9,
5060 .g2_irqs = 10,
5061 .atu_move_port_mask = 0xf,
5062 .pvt = true,
5063 .multi_chip = true,
5064 .tag_protocol = DSA_TAG_PROTO_EDSA,
5065 .ops = &mv88e6350_ops,
5066 },
5067
5068 [MV88E6351] = {
5069 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
5070 .family = MV88E6XXX_FAMILY_6351,
5071 .name = "Marvell 88E6351",
5072 .num_databases = 4096,
5073 .num_macs = 8192,
5074 .num_ports = 7,
5075 .num_internal_phys = 5,
5076 .max_vid = 4095,
5077 .port_base_addr = 0x10,
5078 .phy_base_addr = 0x0,
5079 .global1_addr = 0x1b,
5080 .global2_addr = 0x1c,
5081 .age_time_coeff = 15000,
5082 .g1_irqs = 9,
5083 .g2_irqs = 10,
5084 .atu_move_port_mask = 0xf,
5085 .pvt = true,
5086 .multi_chip = true,
5087 .tag_protocol = DSA_TAG_PROTO_EDSA,
5088 .ops = &mv88e6351_ops,
5089 },
5090
5091 [MV88E6352] = {
5092 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
5093 .family = MV88E6XXX_FAMILY_6352,
5094 .name = "Marvell 88E6352",
5095 .num_databases = 4096,
5096 .num_macs = 8192,
5097 .num_ports = 7,
5098 .num_internal_phys = 5,
5099 .num_gpio = 15,
5100 .max_vid = 4095,
5101 .port_base_addr = 0x10,
5102 .phy_base_addr = 0x0,
5103 .global1_addr = 0x1b,
5104 .global2_addr = 0x1c,
5105 .age_time_coeff = 15000,
5106 .g1_irqs = 9,
5107 .g2_irqs = 10,
5108 .atu_move_port_mask = 0xf,
5109 .pvt = true,
5110 .multi_chip = true,
5111 .tag_protocol = DSA_TAG_PROTO_EDSA,
5112 .ptp_support = true,
5113 .ops = &mv88e6352_ops,
5114 },
5115 [MV88E6390] = {
5116 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
5117 .family = MV88E6XXX_FAMILY_6390,
5118 .name = "Marvell 88E6390",
5119 .num_databases = 4096,
5120 .num_macs = 16384,
5121 .num_ports = 11, /* 10 + Z80 */
5122 .num_internal_phys = 9,
5123 .num_gpio = 16,
5124 .max_vid = 8191,
5125 .port_base_addr = 0x0,
5126 .phy_base_addr = 0x0,
5127 .global1_addr = 0x1b,
5128 .global2_addr = 0x1c,
5129 .age_time_coeff = 3750,
5130 .g1_irqs = 9,
5131 .g2_irqs = 14,
5132 .atu_move_port_mask = 0x1f,
5133 .pvt = true,
5134 .multi_chip = true,
5135 .tag_protocol = DSA_TAG_PROTO_DSA,
5136 .ptp_support = true,
5137 .ops = &mv88e6390_ops,
5138 },
5139 [MV88E6390X] = {
5140 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
5141 .family = MV88E6XXX_FAMILY_6390,
5142 .name = "Marvell 88E6390X",
5143 .num_databases = 4096,
5144 .num_macs = 16384,
5145 .num_ports = 11, /* 10 + Z80 */
5146 .num_internal_phys = 9,
5147 .num_gpio = 16,
5148 .max_vid = 8191,
5149 .port_base_addr = 0x0,
5150 .phy_base_addr = 0x0,
5151 .global1_addr = 0x1b,
5152 .global2_addr = 0x1c,
5153 .age_time_coeff = 3750,
5154 .g1_irqs = 9,
5155 .g2_irqs = 14,
5156 .atu_move_port_mask = 0x1f,
5157 .pvt = true,
5158 .multi_chip = true,
5159 .tag_protocol = DSA_TAG_PROTO_DSA,
5160 .ptp_support = true,
5161 .ops = &mv88e6390x_ops,
5162 },
5163 };
5164
mv88e6xxx_lookup_info(unsigned int prod_num)5165 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
5166 {
5167 int i;
5168
5169 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
5170 if (mv88e6xxx_table[i].prod_num == prod_num)
5171 return &mv88e6xxx_table[i];
5172
5173 return NULL;
5174 }
5175
mv88e6xxx_detect(struct mv88e6xxx_chip * chip)5176 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
5177 {
5178 const struct mv88e6xxx_info *info;
5179 unsigned int prod_num, rev;
5180 u16 id;
5181 int err;
5182
5183 mv88e6xxx_reg_lock(chip);
5184 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
5185 mv88e6xxx_reg_unlock(chip);
5186 if (err)
5187 return err;
5188
5189 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
5190 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
5191
5192 info = mv88e6xxx_lookup_info(prod_num);
5193 if (!info)
5194 return -ENODEV;
5195
5196 /* Update the compatible info with the probed one */
5197 chip->info = info;
5198
5199 err = mv88e6xxx_g2_require(chip);
5200 if (err)
5201 return err;
5202
5203 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
5204 chip->info->prod_num, chip->info->name, rev);
5205
5206 return 0;
5207 }
5208
mv88e6xxx_alloc_chip(struct device * dev)5209 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
5210 {
5211 struct mv88e6xxx_chip *chip;
5212
5213 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
5214 if (!chip)
5215 return NULL;
5216
5217 chip->dev = dev;
5218
5219 mutex_init(&chip->reg_lock);
5220 INIT_LIST_HEAD(&chip->mdios);
5221 idr_init(&chip->policies);
5222
5223 return chip;
5224 }
5225
mv88e6xxx_get_tag_protocol(struct dsa_switch * ds,int port,enum dsa_tag_protocol m)5226 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
5227 int port,
5228 enum dsa_tag_protocol m)
5229 {
5230 struct mv88e6xxx_chip *chip = ds->priv;
5231
5232 return chip->info->tag_protocol;
5233 }
5234
mv88e6xxx_port_mdb_prepare(struct dsa_switch * ds,int port,const struct switchdev_obj_port_mdb * mdb)5235 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
5236 const struct switchdev_obj_port_mdb *mdb)
5237 {
5238 /* We don't need any dynamic resource from the kernel (yet),
5239 * so skip the prepare phase.
5240 */
5241
5242 return 0;
5243 }
5244
mv88e6xxx_port_mdb_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_mdb * mdb)5245 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
5246 const struct switchdev_obj_port_mdb *mdb)
5247 {
5248 struct mv88e6xxx_chip *chip = ds->priv;
5249
5250 mv88e6xxx_reg_lock(chip);
5251 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
5252 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC))
5253 dev_err(ds->dev, "p%d: failed to load multicast MAC address\n",
5254 port);
5255 mv88e6xxx_reg_unlock(chip);
5256 }
5257
mv88e6xxx_port_mdb_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_mdb * mdb)5258 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
5259 const struct switchdev_obj_port_mdb *mdb)
5260 {
5261 struct mv88e6xxx_chip *chip = ds->priv;
5262 int err;
5263
5264 mv88e6xxx_reg_lock(chip);
5265 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0);
5266 mv88e6xxx_reg_unlock(chip);
5267
5268 return err;
5269 }
5270
mv88e6xxx_port_mirror_add(struct dsa_switch * ds,int port,struct dsa_mall_mirror_tc_entry * mirror,bool ingress)5271 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port,
5272 struct dsa_mall_mirror_tc_entry *mirror,
5273 bool ingress)
5274 {
5275 enum mv88e6xxx_egress_direction direction = ingress ?
5276 MV88E6XXX_EGRESS_DIR_INGRESS :
5277 MV88E6XXX_EGRESS_DIR_EGRESS;
5278 struct mv88e6xxx_chip *chip = ds->priv;
5279 bool other_mirrors = false;
5280 int i;
5281 int err;
5282
5283 if (!chip->info->ops->set_egress_port)
5284 return -EOPNOTSUPP;
5285
5286 mutex_lock(&chip->reg_lock);
5287 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) !=
5288 mirror->to_local_port) {
5289 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
5290 other_mirrors |= ingress ?
5291 chip->ports[i].mirror_ingress :
5292 chip->ports[i].mirror_egress;
5293
5294 /* Can't change egress port when other mirror is active */
5295 if (other_mirrors) {
5296 err = -EBUSY;
5297 goto out;
5298 }
5299
5300 err = chip->info->ops->set_egress_port(chip,
5301 direction,
5302 mirror->to_local_port);
5303 if (err)
5304 goto out;
5305 }
5306
5307 err = mv88e6xxx_port_set_mirror(chip, port, direction, true);
5308 out:
5309 mutex_unlock(&chip->reg_lock);
5310
5311 return err;
5312 }
5313
mv88e6xxx_port_mirror_del(struct dsa_switch * ds,int port,struct dsa_mall_mirror_tc_entry * mirror)5314 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port,
5315 struct dsa_mall_mirror_tc_entry *mirror)
5316 {
5317 enum mv88e6xxx_egress_direction direction = mirror->ingress ?
5318 MV88E6XXX_EGRESS_DIR_INGRESS :
5319 MV88E6XXX_EGRESS_DIR_EGRESS;
5320 struct mv88e6xxx_chip *chip = ds->priv;
5321 bool other_mirrors = false;
5322 int i;
5323
5324 mutex_lock(&chip->reg_lock);
5325 if (mv88e6xxx_port_set_mirror(chip, port, direction, false))
5326 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port);
5327
5328 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
5329 other_mirrors |= mirror->ingress ?
5330 chip->ports[i].mirror_ingress :
5331 chip->ports[i].mirror_egress;
5332
5333 /* Reset egress port when no other mirror is active */
5334 if (!other_mirrors) {
5335 if (chip->info->ops->set_egress_port(chip,
5336 direction,
5337 dsa_upstream_port(ds,
5338 port)))
5339 dev_err(ds->dev, "failed to set egress port\n");
5340 }
5341
5342 mutex_unlock(&chip->reg_lock);
5343 }
5344
mv88e6xxx_port_egress_floods(struct dsa_switch * ds,int port,bool unicast,bool multicast)5345 static int mv88e6xxx_port_egress_floods(struct dsa_switch *ds, int port,
5346 bool unicast, bool multicast)
5347 {
5348 struct mv88e6xxx_chip *chip = ds->priv;
5349 int err = -EOPNOTSUPP;
5350
5351 mv88e6xxx_reg_lock(chip);
5352 if (chip->info->ops->port_set_egress_floods)
5353 err = chip->info->ops->port_set_egress_floods(chip, port,
5354 unicast,
5355 multicast);
5356 mv88e6xxx_reg_unlock(chip);
5357
5358 return err;
5359 }
5360
5361 static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
5362 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
5363 .setup = mv88e6xxx_setup,
5364 .teardown = mv88e6xxx_teardown,
5365 .phylink_validate = mv88e6xxx_validate,
5366 .phylink_mac_link_state = mv88e6xxx_serdes_pcs_get_state,
5367 .phylink_mac_config = mv88e6xxx_mac_config,
5368 .phylink_mac_an_restart = mv88e6xxx_serdes_pcs_an_restart,
5369 .phylink_mac_link_down = mv88e6xxx_mac_link_down,
5370 .phylink_mac_link_up = mv88e6xxx_mac_link_up,
5371 .get_strings = mv88e6xxx_get_strings,
5372 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
5373 .get_sset_count = mv88e6xxx_get_sset_count,
5374 .port_enable = mv88e6xxx_port_enable,
5375 .port_disable = mv88e6xxx_port_disable,
5376 .port_max_mtu = mv88e6xxx_get_max_mtu,
5377 .port_change_mtu = mv88e6xxx_change_mtu,
5378 .get_mac_eee = mv88e6xxx_get_mac_eee,
5379 .set_mac_eee = mv88e6xxx_set_mac_eee,
5380 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
5381 .get_eeprom = mv88e6xxx_get_eeprom,
5382 .set_eeprom = mv88e6xxx_set_eeprom,
5383 .get_regs_len = mv88e6xxx_get_regs_len,
5384 .get_regs = mv88e6xxx_get_regs,
5385 .get_rxnfc = mv88e6xxx_get_rxnfc,
5386 .set_rxnfc = mv88e6xxx_set_rxnfc,
5387 .set_ageing_time = mv88e6xxx_set_ageing_time,
5388 .port_bridge_join = mv88e6xxx_port_bridge_join,
5389 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
5390 .port_egress_floods = mv88e6xxx_port_egress_floods,
5391 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
5392 .port_fast_age = mv88e6xxx_port_fast_age,
5393 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
5394 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
5395 .port_vlan_add = mv88e6xxx_port_vlan_add,
5396 .port_vlan_del = mv88e6xxx_port_vlan_del,
5397 .port_fdb_add = mv88e6xxx_port_fdb_add,
5398 .port_fdb_del = mv88e6xxx_port_fdb_del,
5399 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
5400 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare,
5401 .port_mdb_add = mv88e6xxx_port_mdb_add,
5402 .port_mdb_del = mv88e6xxx_port_mdb_del,
5403 .port_mirror_add = mv88e6xxx_port_mirror_add,
5404 .port_mirror_del = mv88e6xxx_port_mirror_del,
5405 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join,
5406 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
5407 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set,
5408 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get,
5409 .port_txtstamp = mv88e6xxx_port_txtstamp,
5410 .port_rxtstamp = mv88e6xxx_port_rxtstamp,
5411 .get_ts_info = mv88e6xxx_get_ts_info,
5412 .devlink_param_get = mv88e6xxx_devlink_param_get,
5413 .devlink_param_set = mv88e6xxx_devlink_param_set,
5414 .devlink_info_get = mv88e6xxx_devlink_info_get,
5415 };
5416
mv88e6xxx_register_switch(struct mv88e6xxx_chip * chip)5417 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
5418 {
5419 struct device *dev = chip->dev;
5420 struct dsa_switch *ds;
5421
5422 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
5423 if (!ds)
5424 return -ENOMEM;
5425
5426 ds->dev = dev;
5427 ds->num_ports = mv88e6xxx_num_ports(chip);
5428 ds->priv = chip;
5429 ds->dev = dev;
5430 ds->ops = &mv88e6xxx_switch_ops;
5431 ds->ageing_time_min = chip->info->age_time_coeff;
5432 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
5433
5434 dev_set_drvdata(dev, ds);
5435
5436 return dsa_register_switch(ds);
5437 }
5438
mv88e6xxx_unregister_switch(struct mv88e6xxx_chip * chip)5439 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
5440 {
5441 dsa_unregister_switch(chip->ds);
5442 }
5443
pdata_device_get_match_data(struct device * dev)5444 static const void *pdata_device_get_match_data(struct device *dev)
5445 {
5446 const struct of_device_id *matches = dev->driver->of_match_table;
5447 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data;
5448
5449 for (; matches->name[0] || matches->type[0] || matches->compatible[0];
5450 matches++) {
5451 if (!strcmp(pdata->compatible, matches->compatible))
5452 return matches->data;
5453 }
5454 return NULL;
5455 }
5456
5457 /* There is no suspend to RAM support at DSA level yet, the switch configuration
5458 * would be lost after a power cycle so prevent it to be suspended.
5459 */
mv88e6xxx_suspend(struct device * dev)5460 static int __maybe_unused mv88e6xxx_suspend(struct device *dev)
5461 {
5462 return -EOPNOTSUPP;
5463 }
5464
mv88e6xxx_resume(struct device * dev)5465 static int __maybe_unused mv88e6xxx_resume(struct device *dev)
5466 {
5467 return 0;
5468 }
5469
5470 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume);
5471
mv88e6xxx_probe(struct mdio_device * mdiodev)5472 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
5473 {
5474 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data;
5475 const struct mv88e6xxx_info *compat_info = NULL;
5476 struct device *dev = &mdiodev->dev;
5477 struct device_node *np = dev->of_node;
5478 struct mv88e6xxx_chip *chip;
5479 int port;
5480 int err;
5481
5482 if (!np && !pdata)
5483 return -EINVAL;
5484
5485 if (np)
5486 compat_info = of_device_get_match_data(dev);
5487
5488 if (pdata) {
5489 compat_info = pdata_device_get_match_data(dev);
5490
5491 if (!pdata->netdev)
5492 return -EINVAL;
5493
5494 for (port = 0; port < DSA_MAX_PORTS; port++) {
5495 if (!(pdata->enabled_ports & (1 << port)))
5496 continue;
5497 if (strcmp(pdata->cd.port_names[port], "cpu"))
5498 continue;
5499 pdata->cd.netdev[port] = &pdata->netdev->dev;
5500 break;
5501 }
5502 }
5503
5504 if (!compat_info)
5505 return -EINVAL;
5506
5507 chip = mv88e6xxx_alloc_chip(dev);
5508 if (!chip) {
5509 err = -ENOMEM;
5510 goto out;
5511 }
5512
5513 chip->info = compat_info;
5514
5515 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
5516 if (err)
5517 goto out;
5518
5519 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
5520 if (IS_ERR(chip->reset)) {
5521 err = PTR_ERR(chip->reset);
5522 goto out;
5523 }
5524 if (chip->reset)
5525 usleep_range(1000, 2000);
5526
5527 err = mv88e6xxx_detect(chip);
5528 if (err)
5529 goto out;
5530
5531 mv88e6xxx_phy_init(chip);
5532
5533 if (chip->info->ops->get_eeprom) {
5534 if (np)
5535 of_property_read_u32(np, "eeprom-length",
5536 &chip->eeprom_len);
5537 else
5538 chip->eeprom_len = pdata->eeprom_len;
5539 }
5540
5541 mv88e6xxx_reg_lock(chip);
5542 err = mv88e6xxx_switch_reset(chip);
5543 mv88e6xxx_reg_unlock(chip);
5544 if (err)
5545 goto out;
5546
5547 if (np) {
5548 chip->irq = of_irq_get(np, 0);
5549 if (chip->irq == -EPROBE_DEFER) {
5550 err = chip->irq;
5551 goto out;
5552 }
5553 }
5554
5555 if (pdata)
5556 chip->irq = pdata->irq;
5557
5558 /* Has to be performed before the MDIO bus is created, because
5559 * the PHYs will link their interrupts to these interrupt
5560 * controllers
5561 */
5562 mv88e6xxx_reg_lock(chip);
5563 if (chip->irq > 0)
5564 err = mv88e6xxx_g1_irq_setup(chip);
5565 else
5566 err = mv88e6xxx_irq_poll_setup(chip);
5567 mv88e6xxx_reg_unlock(chip);
5568
5569 if (err)
5570 goto out;
5571
5572 if (chip->info->g2_irqs > 0) {
5573 err = mv88e6xxx_g2_irq_setup(chip);
5574 if (err)
5575 goto out_g1_irq;
5576 }
5577
5578 err = mv88e6xxx_g1_atu_prob_irq_setup(chip);
5579 if (err)
5580 goto out_g2_irq;
5581
5582 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip);
5583 if (err)
5584 goto out_g1_atu_prob_irq;
5585
5586 err = mv88e6xxx_mdios_register(chip, np);
5587 if (err)
5588 goto out_g1_vtu_prob_irq;
5589
5590 err = mv88e6xxx_register_switch(chip);
5591 if (err)
5592 goto out_mdio;
5593
5594 return 0;
5595
5596 out_mdio:
5597 mv88e6xxx_mdios_unregister(chip);
5598 out_g1_vtu_prob_irq:
5599 mv88e6xxx_g1_vtu_prob_irq_free(chip);
5600 out_g1_atu_prob_irq:
5601 mv88e6xxx_g1_atu_prob_irq_free(chip);
5602 out_g2_irq:
5603 if (chip->info->g2_irqs > 0)
5604 mv88e6xxx_g2_irq_free(chip);
5605 out_g1_irq:
5606 if (chip->irq > 0)
5607 mv88e6xxx_g1_irq_free(chip);
5608 else
5609 mv88e6xxx_irq_poll_free(chip);
5610 out:
5611 if (pdata)
5612 dev_put(pdata->netdev);
5613
5614 return err;
5615 }
5616
mv88e6xxx_remove(struct mdio_device * mdiodev)5617 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
5618 {
5619 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
5620 struct mv88e6xxx_chip *chip = ds->priv;
5621
5622 if (chip->info->ptp_support) {
5623 mv88e6xxx_hwtstamp_free(chip);
5624 mv88e6xxx_ptp_free(chip);
5625 }
5626
5627 mv88e6xxx_phy_destroy(chip);
5628 mv88e6xxx_unregister_switch(chip);
5629 mv88e6xxx_mdios_unregister(chip);
5630
5631 mv88e6xxx_g1_vtu_prob_irq_free(chip);
5632 mv88e6xxx_g1_atu_prob_irq_free(chip);
5633
5634 if (chip->info->g2_irqs > 0)
5635 mv88e6xxx_g2_irq_free(chip);
5636
5637 if (chip->irq > 0)
5638 mv88e6xxx_g1_irq_free(chip);
5639 else
5640 mv88e6xxx_irq_poll_free(chip);
5641 }
5642
5643 static const struct of_device_id mv88e6xxx_of_match[] = {
5644 {
5645 .compatible = "marvell,mv88e6085",
5646 .data = &mv88e6xxx_table[MV88E6085],
5647 },
5648 {
5649 .compatible = "marvell,mv88e6190",
5650 .data = &mv88e6xxx_table[MV88E6190],
5651 },
5652 {
5653 .compatible = "marvell,mv88e6250",
5654 .data = &mv88e6xxx_table[MV88E6250],
5655 },
5656 { /* sentinel */ },
5657 };
5658
5659 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
5660
5661 static struct mdio_driver mv88e6xxx_driver = {
5662 .probe = mv88e6xxx_probe,
5663 .remove = mv88e6xxx_remove,
5664 .mdiodrv.driver = {
5665 .name = "mv88e6085",
5666 .of_match_table = mv88e6xxx_of_match,
5667 .pm = &mv88e6xxx_pm_ops,
5668 },
5669 };
5670
5671 mdio_module_driver(mv88e6xxx_driver);
5672
5673 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
5674 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
5675 MODULE_LICENSE("GPL");
5676