1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 1999 - 2010 Intel Corporation.
4 * Copyright (C) 2010 - 2012 LAPIS SEMICONDUCTOR CO., LTD.
5 *
6 * This code was derived from the Intel e1000e Linux driver.
7 */
8
9 #include "pch_gbe.h"
10 #include "pch_gbe_phy.h"
11 #include <linux/module.h>
12 #include <linux/net_tstamp.h>
13 #include <linux/ptp_classify.h>
14 #include <linux/gpio.h>
15
16 #define DRV_VERSION "1.01"
17 const char pch_driver_version[] = DRV_VERSION;
18
19 #define PCH_GBE_MAR_ENTRIES 16
20 #define PCH_GBE_SHORT_PKT 64
21 #define DSC_INIT16 0xC000
22 #define PCH_GBE_DMA_ALIGN 0
23 #define PCH_GBE_DMA_PADDING 2
24 #define PCH_GBE_WATCHDOG_PERIOD (5 * HZ) /* watchdog time */
25 #define PCH_GBE_PCI_BAR 1
26 #define PCH_GBE_RESERVE_MEMORY 0x200000 /* 2MB */
27
28 #define PCI_DEVICE_ID_INTEL_IOH1_GBE 0x8802
29
30 #define PCI_DEVICE_ID_ROHM_ML7223_GBE 0x8013
31 #define PCI_DEVICE_ID_ROHM_ML7831_GBE 0x8802
32
33 #define PCH_GBE_TX_WEIGHT 64
34 #define PCH_GBE_RX_WEIGHT 64
35 #define PCH_GBE_RX_BUFFER_WRITE 16
36
37 /* Initialize the wake-on-LAN settings */
38 #define PCH_GBE_WL_INIT_SETTING (PCH_GBE_WLC_MP)
39
40 #define PCH_GBE_MAC_RGMII_CTRL_SETTING ( \
41 PCH_GBE_CHIP_TYPE_INTERNAL | \
42 PCH_GBE_RGMII_MODE_RGMII \
43 )
44
45 /* Ethertype field values */
46 #define PCH_GBE_MAX_RX_BUFFER_SIZE 0x2880
47 #define PCH_GBE_MAX_JUMBO_FRAME_SIZE 10318
48 #define PCH_GBE_FRAME_SIZE_2048 2048
49 #define PCH_GBE_FRAME_SIZE_4096 4096
50 #define PCH_GBE_FRAME_SIZE_8192 8192
51
52 #define PCH_GBE_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i]))
53 #define PCH_GBE_RX_DESC(R, i) PCH_GBE_GET_DESC(R, i, pch_gbe_rx_desc)
54 #define PCH_GBE_TX_DESC(R, i) PCH_GBE_GET_DESC(R, i, pch_gbe_tx_desc)
55 #define PCH_GBE_DESC_UNUSED(R) \
56 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
57 (R)->next_to_clean - (R)->next_to_use - 1)
58
59 /* Pause packet value */
60 #define PCH_GBE_PAUSE_PKT1_VALUE 0x00C28001
61 #define PCH_GBE_PAUSE_PKT2_VALUE 0x00000100
62 #define PCH_GBE_PAUSE_PKT4_VALUE 0x01000888
63 #define PCH_GBE_PAUSE_PKT5_VALUE 0x0000FFFF
64
65
66 /* This defines the bits that are set in the Interrupt Mask
67 * Set/Read Register. Each bit is documented below:
68 * o RXT0 = Receiver Timer Interrupt (ring 0)
69 * o TXDW = Transmit Descriptor Written Back
70 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
71 * o RXSEQ = Receive Sequence Error
72 * o LSC = Link Status Change
73 */
74 #define PCH_GBE_INT_ENABLE_MASK ( \
75 PCH_GBE_INT_RX_DMA_CMPLT | \
76 PCH_GBE_INT_RX_DSC_EMP | \
77 PCH_GBE_INT_RX_FIFO_ERR | \
78 PCH_GBE_INT_WOL_DET | \
79 PCH_GBE_INT_TX_CMPLT \
80 )
81
82 #define PCH_GBE_INT_DISABLE_ALL 0
83
84 /* Macros for ieee1588 */
85 /* 0x40 Time Synchronization Channel Control Register Bits */
86 #define MASTER_MODE (1<<0)
87 #define SLAVE_MODE (0)
88 #define V2_MODE (1<<31)
89 #define CAP_MODE0 (0)
90 #define CAP_MODE2 (1<<17)
91
92 /* 0x44 Time Synchronization Channel Event Register Bits */
93 #define TX_SNAPSHOT_LOCKED (1<<0)
94 #define RX_SNAPSHOT_LOCKED (1<<1)
95
96 #define PTP_L4_MULTICAST_SA "01:00:5e:00:01:81"
97 #define PTP_L2_MULTICAST_SA "01:1b:19:00:00:00"
98
99 #define MINNOW_PHY_RESET_GPIO 13
100
101 static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg);
102 static void pch_gbe_mdio_write(struct net_device *netdev, int addr, int reg,
103 int data);
104 static void pch_gbe_set_multi(struct net_device *netdev);
105
pch_ptp_match(struct sk_buff * skb,u16 uid_hi,u32 uid_lo,u16 seqid)106 static int pch_ptp_match(struct sk_buff *skb, u16 uid_hi, u32 uid_lo, u16 seqid)
107 {
108 u8 *data = skb->data;
109 unsigned int offset;
110 u16 hi, id;
111 u32 lo;
112
113 if (ptp_classify_raw(skb) == PTP_CLASS_NONE)
114 return 0;
115
116 offset = ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN;
117
118 if (skb->len < offset + OFF_PTP_SEQUENCE_ID + sizeof(seqid))
119 return 0;
120
121 hi = get_unaligned_be16(data + offset + OFF_PTP_SOURCE_UUID + 0);
122 lo = get_unaligned_be32(data + offset + OFF_PTP_SOURCE_UUID + 2);
123 id = get_unaligned_be16(data + offset + OFF_PTP_SEQUENCE_ID);
124
125 return (uid_hi == hi && uid_lo == lo && seqid == id);
126 }
127
128 static void
pch_rx_timestamp(struct pch_gbe_adapter * adapter,struct sk_buff * skb)129 pch_rx_timestamp(struct pch_gbe_adapter *adapter, struct sk_buff *skb)
130 {
131 struct skb_shared_hwtstamps *shhwtstamps;
132 struct pci_dev *pdev;
133 u64 ns;
134 u32 hi, lo, val;
135
136 if (!adapter->hwts_rx_en)
137 return;
138
139 /* Get ieee1588's dev information */
140 pdev = adapter->ptp_pdev;
141
142 val = pch_ch_event_read(pdev);
143
144 if (!(val & RX_SNAPSHOT_LOCKED))
145 return;
146
147 lo = pch_src_uuid_lo_read(pdev);
148 hi = pch_src_uuid_hi_read(pdev);
149
150 if (!pch_ptp_match(skb, hi, lo, hi >> 16))
151 goto out;
152
153 ns = pch_rx_snap_read(pdev);
154
155 shhwtstamps = skb_hwtstamps(skb);
156 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
157 shhwtstamps->hwtstamp = ns_to_ktime(ns);
158 out:
159 pch_ch_event_write(pdev, RX_SNAPSHOT_LOCKED);
160 }
161
162 static void
pch_tx_timestamp(struct pch_gbe_adapter * adapter,struct sk_buff * skb)163 pch_tx_timestamp(struct pch_gbe_adapter *adapter, struct sk_buff *skb)
164 {
165 struct skb_shared_hwtstamps shhwtstamps;
166 struct pci_dev *pdev;
167 struct skb_shared_info *shtx;
168 u64 ns;
169 u32 cnt, val;
170
171 shtx = skb_shinfo(skb);
172 if (likely(!(shtx->tx_flags & SKBTX_HW_TSTAMP && adapter->hwts_tx_en)))
173 return;
174
175 shtx->tx_flags |= SKBTX_IN_PROGRESS;
176
177 /* Get ieee1588's dev information */
178 pdev = adapter->ptp_pdev;
179
180 /*
181 * This really stinks, but we have to poll for the Tx time stamp.
182 */
183 for (cnt = 0; cnt < 100; cnt++) {
184 val = pch_ch_event_read(pdev);
185 if (val & TX_SNAPSHOT_LOCKED)
186 break;
187 udelay(1);
188 }
189 if (!(val & TX_SNAPSHOT_LOCKED)) {
190 shtx->tx_flags &= ~SKBTX_IN_PROGRESS;
191 return;
192 }
193
194 ns = pch_tx_snap_read(pdev);
195
196 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
197 shhwtstamps.hwtstamp = ns_to_ktime(ns);
198 skb_tstamp_tx(skb, &shhwtstamps);
199
200 pch_ch_event_write(pdev, TX_SNAPSHOT_LOCKED);
201 }
202
hwtstamp_ioctl(struct net_device * netdev,struct ifreq * ifr,int cmd)203 static int hwtstamp_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
204 {
205 struct hwtstamp_config cfg;
206 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
207 struct pci_dev *pdev;
208 u8 station[20];
209
210 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
211 return -EFAULT;
212
213 if (cfg.flags) /* reserved for future extensions */
214 return -EINVAL;
215
216 /* Get ieee1588's dev information */
217 pdev = adapter->ptp_pdev;
218
219 if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
220 return -ERANGE;
221
222 switch (cfg.rx_filter) {
223 case HWTSTAMP_FILTER_NONE:
224 adapter->hwts_rx_en = 0;
225 break;
226 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
227 adapter->hwts_rx_en = 0;
228 pch_ch_control_write(pdev, SLAVE_MODE | CAP_MODE0);
229 break;
230 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
231 adapter->hwts_rx_en = 1;
232 pch_ch_control_write(pdev, MASTER_MODE | CAP_MODE0);
233 break;
234 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
235 adapter->hwts_rx_en = 1;
236 pch_ch_control_write(pdev, V2_MODE | CAP_MODE2);
237 strcpy(station, PTP_L4_MULTICAST_SA);
238 pch_set_station_address(station, pdev);
239 break;
240 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
241 adapter->hwts_rx_en = 1;
242 pch_ch_control_write(pdev, V2_MODE | CAP_MODE2);
243 strcpy(station, PTP_L2_MULTICAST_SA);
244 pch_set_station_address(station, pdev);
245 break;
246 default:
247 return -ERANGE;
248 }
249
250 adapter->hwts_tx_en = cfg.tx_type == HWTSTAMP_TX_ON;
251
252 /* Clear out any old time stamps. */
253 pch_ch_event_write(pdev, TX_SNAPSHOT_LOCKED | RX_SNAPSHOT_LOCKED);
254
255 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
256 }
257
pch_gbe_mac_load_mac_addr(struct pch_gbe_hw * hw)258 static inline void pch_gbe_mac_load_mac_addr(struct pch_gbe_hw *hw)
259 {
260 iowrite32(0x01, &hw->reg->MAC_ADDR_LOAD);
261 }
262
263 /**
264 * pch_gbe_mac_read_mac_addr - Read MAC address
265 * @hw: Pointer to the HW structure
266 * Returns:
267 * 0: Successful.
268 */
pch_gbe_mac_read_mac_addr(struct pch_gbe_hw * hw)269 static s32 pch_gbe_mac_read_mac_addr(struct pch_gbe_hw *hw)
270 {
271 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
272 u32 adr1a, adr1b;
273
274 adr1a = ioread32(&hw->reg->mac_adr[0].high);
275 adr1b = ioread32(&hw->reg->mac_adr[0].low);
276
277 hw->mac.addr[0] = (u8)(adr1a & 0xFF);
278 hw->mac.addr[1] = (u8)((adr1a >> 8) & 0xFF);
279 hw->mac.addr[2] = (u8)((adr1a >> 16) & 0xFF);
280 hw->mac.addr[3] = (u8)((adr1a >> 24) & 0xFF);
281 hw->mac.addr[4] = (u8)(adr1b & 0xFF);
282 hw->mac.addr[5] = (u8)((adr1b >> 8) & 0xFF);
283
284 netdev_dbg(adapter->netdev, "hw->mac.addr : %pM\n", hw->mac.addr);
285 return 0;
286 }
287
288 /**
289 * pch_gbe_wait_clr_bit - Wait to clear a bit
290 * @reg: Pointer of register
291 * @bit: Busy bit
292 */
pch_gbe_wait_clr_bit(void * reg,u32 bit)293 static void pch_gbe_wait_clr_bit(void *reg, u32 bit)
294 {
295 u32 tmp;
296
297 /* wait busy */
298 tmp = 1000;
299 while ((ioread32(reg) & bit) && --tmp)
300 cpu_relax();
301 if (!tmp)
302 pr_err("Error: busy bit is not cleared\n");
303 }
304
305 /**
306 * pch_gbe_mac_mar_set - Set MAC address register
307 * @hw: Pointer to the HW structure
308 * @addr: Pointer to the MAC address
309 * @index: MAC address array register
310 */
pch_gbe_mac_mar_set(struct pch_gbe_hw * hw,u8 * addr,u32 index)311 static void pch_gbe_mac_mar_set(struct pch_gbe_hw *hw, u8 * addr, u32 index)
312 {
313 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
314 u32 mar_low, mar_high, adrmask;
315
316 netdev_dbg(adapter->netdev, "index : 0x%x\n", index);
317
318 /*
319 * HW expects these in little endian so we reverse the byte order
320 * from network order (big endian) to little endian
321 */
322 mar_high = ((u32) addr[0] | ((u32) addr[1] << 8) |
323 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
324 mar_low = ((u32) addr[4] | ((u32) addr[5] << 8));
325 /* Stop the MAC Address of index. */
326 adrmask = ioread32(&hw->reg->ADDR_MASK);
327 iowrite32((adrmask | (0x0001 << index)), &hw->reg->ADDR_MASK);
328 /* wait busy */
329 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
330 /* Set the MAC address to the MAC address 1A/1B register */
331 iowrite32(mar_high, &hw->reg->mac_adr[index].high);
332 iowrite32(mar_low, &hw->reg->mac_adr[index].low);
333 /* Start the MAC address of index */
334 iowrite32((adrmask & ~(0x0001 << index)), &hw->reg->ADDR_MASK);
335 /* wait busy */
336 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
337 }
338
339 /**
340 * pch_gbe_mac_reset_hw - Reset hardware
341 * @hw: Pointer to the HW structure
342 */
pch_gbe_mac_reset_hw(struct pch_gbe_hw * hw)343 static void pch_gbe_mac_reset_hw(struct pch_gbe_hw *hw)
344 {
345 /* Read the MAC address. and store to the private data */
346 pch_gbe_mac_read_mac_addr(hw);
347 iowrite32(PCH_GBE_ALL_RST, &hw->reg->RESET);
348 iowrite32(PCH_GBE_MODE_GMII_ETHER, &hw->reg->MODE);
349 pch_gbe_wait_clr_bit(&hw->reg->RESET, PCH_GBE_ALL_RST);
350 /* Setup the receive addresses */
351 pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
352 return;
353 }
354
pch_gbe_disable_mac_rx(struct pch_gbe_hw * hw)355 static void pch_gbe_disable_mac_rx(struct pch_gbe_hw *hw)
356 {
357 u32 rctl;
358 /* Disables Receive MAC */
359 rctl = ioread32(&hw->reg->MAC_RX_EN);
360 iowrite32((rctl & ~PCH_GBE_MRE_MAC_RX_EN), &hw->reg->MAC_RX_EN);
361 }
362
pch_gbe_enable_mac_rx(struct pch_gbe_hw * hw)363 static void pch_gbe_enable_mac_rx(struct pch_gbe_hw *hw)
364 {
365 u32 rctl;
366 /* Enables Receive MAC */
367 rctl = ioread32(&hw->reg->MAC_RX_EN);
368 iowrite32((rctl | PCH_GBE_MRE_MAC_RX_EN), &hw->reg->MAC_RX_EN);
369 }
370
371 /**
372 * pch_gbe_mac_init_rx_addrs - Initialize receive address's
373 * @hw: Pointer to the HW structure
374 * @mar_count: Receive address registers
375 */
pch_gbe_mac_init_rx_addrs(struct pch_gbe_hw * hw,u16 mar_count)376 static void pch_gbe_mac_init_rx_addrs(struct pch_gbe_hw *hw, u16 mar_count)
377 {
378 u32 i;
379
380 /* Setup the receive address */
381 pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
382
383 /* Zero out the other receive addresses */
384 for (i = 1; i < mar_count; i++) {
385 iowrite32(0, &hw->reg->mac_adr[i].high);
386 iowrite32(0, &hw->reg->mac_adr[i].low);
387 }
388 iowrite32(0xFFFE, &hw->reg->ADDR_MASK);
389 /* wait busy */
390 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
391 }
392
393 /**
394 * pch_gbe_mac_force_mac_fc - Force the MAC's flow control settings
395 * @hw: Pointer to the HW structure
396 * Returns:
397 * 0: Successful.
398 * Negative value: Failed.
399 */
pch_gbe_mac_force_mac_fc(struct pch_gbe_hw * hw)400 s32 pch_gbe_mac_force_mac_fc(struct pch_gbe_hw *hw)
401 {
402 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
403 struct pch_gbe_mac_info *mac = &hw->mac;
404 u32 rx_fctrl;
405
406 netdev_dbg(adapter->netdev, "mac->fc = %u\n", mac->fc);
407
408 rx_fctrl = ioread32(&hw->reg->RX_FCTRL);
409
410 switch (mac->fc) {
411 case PCH_GBE_FC_NONE:
412 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
413 mac->tx_fc_enable = false;
414 break;
415 case PCH_GBE_FC_RX_PAUSE:
416 rx_fctrl |= PCH_GBE_FL_CTRL_EN;
417 mac->tx_fc_enable = false;
418 break;
419 case PCH_GBE_FC_TX_PAUSE:
420 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
421 mac->tx_fc_enable = true;
422 break;
423 case PCH_GBE_FC_FULL:
424 rx_fctrl |= PCH_GBE_FL_CTRL_EN;
425 mac->tx_fc_enable = true;
426 break;
427 default:
428 netdev_err(adapter->netdev,
429 "Flow control param set incorrectly\n");
430 return -EINVAL;
431 }
432 if (mac->link_duplex == DUPLEX_HALF)
433 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
434 iowrite32(rx_fctrl, &hw->reg->RX_FCTRL);
435 netdev_dbg(adapter->netdev,
436 "RX_FCTRL reg : 0x%08x mac->tx_fc_enable : %d\n",
437 ioread32(&hw->reg->RX_FCTRL), mac->tx_fc_enable);
438 return 0;
439 }
440
441 /**
442 * pch_gbe_mac_set_wol_event - Set wake-on-lan event
443 * @hw: Pointer to the HW structure
444 * @wu_evt: Wake up event
445 */
pch_gbe_mac_set_wol_event(struct pch_gbe_hw * hw,u32 wu_evt)446 static void pch_gbe_mac_set_wol_event(struct pch_gbe_hw *hw, u32 wu_evt)
447 {
448 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
449 u32 addr_mask;
450
451 netdev_dbg(adapter->netdev, "wu_evt : 0x%08x ADDR_MASK reg : 0x%08x\n",
452 wu_evt, ioread32(&hw->reg->ADDR_MASK));
453
454 if (wu_evt) {
455 /* Set Wake-On-Lan address mask */
456 addr_mask = ioread32(&hw->reg->ADDR_MASK);
457 iowrite32(addr_mask, &hw->reg->WOL_ADDR_MASK);
458 /* wait busy */
459 pch_gbe_wait_clr_bit(&hw->reg->WOL_ADDR_MASK, PCH_GBE_WLA_BUSY);
460 iowrite32(0, &hw->reg->WOL_ST);
461 iowrite32((wu_evt | PCH_GBE_WLC_WOL_MODE), &hw->reg->WOL_CTRL);
462 iowrite32(0x02, &hw->reg->TCPIP_ACC);
463 iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN);
464 } else {
465 iowrite32(0, &hw->reg->WOL_CTRL);
466 iowrite32(0, &hw->reg->WOL_ST);
467 }
468 return;
469 }
470
471 /**
472 * pch_gbe_mac_ctrl_miim - Control MIIM interface
473 * @hw: Pointer to the HW structure
474 * @addr: Address of PHY
475 * @dir: Operetion. (Write or Read)
476 * @reg: Access register of PHY
477 * @data: Write data.
478 *
479 * Returns: Read date.
480 */
pch_gbe_mac_ctrl_miim(struct pch_gbe_hw * hw,u32 addr,u32 dir,u32 reg,u16 data)481 u16 pch_gbe_mac_ctrl_miim(struct pch_gbe_hw *hw, u32 addr, u32 dir, u32 reg,
482 u16 data)
483 {
484 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
485 u32 data_out = 0;
486 unsigned int i;
487 unsigned long flags;
488
489 spin_lock_irqsave(&hw->miim_lock, flags);
490
491 for (i = 100; i; --i) {
492 if ((ioread32(&hw->reg->MIIM) & PCH_GBE_MIIM_OPER_READY))
493 break;
494 udelay(20);
495 }
496 if (i == 0) {
497 netdev_err(adapter->netdev, "pch-gbe.miim won't go Ready\n");
498 spin_unlock_irqrestore(&hw->miim_lock, flags);
499 return 0; /* No way to indicate timeout error */
500 }
501 iowrite32(((reg << PCH_GBE_MIIM_REG_ADDR_SHIFT) |
502 (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) |
503 dir | data), &hw->reg->MIIM);
504 for (i = 0; i < 100; i++) {
505 udelay(20);
506 data_out = ioread32(&hw->reg->MIIM);
507 if ((data_out & PCH_GBE_MIIM_OPER_READY))
508 break;
509 }
510 spin_unlock_irqrestore(&hw->miim_lock, flags);
511
512 netdev_dbg(adapter->netdev, "PHY %s: reg=%d, data=0x%04X\n",
513 dir == PCH_GBE_MIIM_OPER_READ ? "READ" : "WRITE", reg,
514 dir == PCH_GBE_MIIM_OPER_READ ? data_out : data);
515 return (u16) data_out;
516 }
517
518 /**
519 * pch_gbe_mac_set_pause_packet - Set pause packet
520 * @hw: Pointer to the HW structure
521 */
pch_gbe_mac_set_pause_packet(struct pch_gbe_hw * hw)522 static void pch_gbe_mac_set_pause_packet(struct pch_gbe_hw *hw)
523 {
524 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
525 unsigned long tmp2, tmp3;
526
527 /* Set Pause packet */
528 tmp2 = hw->mac.addr[1];
529 tmp2 = (tmp2 << 8) | hw->mac.addr[0];
530 tmp2 = PCH_GBE_PAUSE_PKT2_VALUE | (tmp2 << 16);
531
532 tmp3 = hw->mac.addr[5];
533 tmp3 = (tmp3 << 8) | hw->mac.addr[4];
534 tmp3 = (tmp3 << 8) | hw->mac.addr[3];
535 tmp3 = (tmp3 << 8) | hw->mac.addr[2];
536
537 iowrite32(PCH_GBE_PAUSE_PKT1_VALUE, &hw->reg->PAUSE_PKT1);
538 iowrite32(tmp2, &hw->reg->PAUSE_PKT2);
539 iowrite32(tmp3, &hw->reg->PAUSE_PKT3);
540 iowrite32(PCH_GBE_PAUSE_PKT4_VALUE, &hw->reg->PAUSE_PKT4);
541 iowrite32(PCH_GBE_PAUSE_PKT5_VALUE, &hw->reg->PAUSE_PKT5);
542
543 /* Transmit Pause Packet */
544 iowrite32(PCH_GBE_PS_PKT_RQ, &hw->reg->PAUSE_REQ);
545
546 netdev_dbg(adapter->netdev,
547 "PAUSE_PKT1-5 reg : 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
548 ioread32(&hw->reg->PAUSE_PKT1),
549 ioread32(&hw->reg->PAUSE_PKT2),
550 ioread32(&hw->reg->PAUSE_PKT3),
551 ioread32(&hw->reg->PAUSE_PKT4),
552 ioread32(&hw->reg->PAUSE_PKT5));
553
554 return;
555 }
556
557
558 /**
559 * pch_gbe_alloc_queues - Allocate memory for all rings
560 * @adapter: Board private structure to initialize
561 * Returns:
562 * 0: Successfully
563 * Negative value: Failed
564 */
pch_gbe_alloc_queues(struct pch_gbe_adapter * adapter)565 static int pch_gbe_alloc_queues(struct pch_gbe_adapter *adapter)
566 {
567 adapter->tx_ring = devm_kzalloc(&adapter->pdev->dev,
568 sizeof(*adapter->tx_ring), GFP_KERNEL);
569 if (!adapter->tx_ring)
570 return -ENOMEM;
571
572 adapter->rx_ring = devm_kzalloc(&adapter->pdev->dev,
573 sizeof(*adapter->rx_ring), GFP_KERNEL);
574 if (!adapter->rx_ring)
575 return -ENOMEM;
576 return 0;
577 }
578
579 /**
580 * pch_gbe_init_stats - Initialize status
581 * @adapter: Board private structure to initialize
582 */
pch_gbe_init_stats(struct pch_gbe_adapter * adapter)583 static void pch_gbe_init_stats(struct pch_gbe_adapter *adapter)
584 {
585 memset(&adapter->stats, 0, sizeof(adapter->stats));
586 return;
587 }
588
589 /**
590 * pch_gbe_init_phy - Initialize PHY
591 * @adapter: Board private structure to initialize
592 * Returns:
593 * 0: Successfully
594 * Negative value: Failed
595 */
pch_gbe_init_phy(struct pch_gbe_adapter * adapter)596 static int pch_gbe_init_phy(struct pch_gbe_adapter *adapter)
597 {
598 struct net_device *netdev = adapter->netdev;
599 u32 addr;
600 u16 bmcr, stat;
601
602 /* Discover phy addr by searching addrs in order {1,0,2,..., 31} */
603 for (addr = 0; addr < PCH_GBE_PHY_REGS_LEN; addr++) {
604 adapter->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr;
605 bmcr = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMCR);
606 stat = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMSR);
607 stat = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMSR);
608 if (!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0))))
609 break;
610 }
611 adapter->hw.phy.addr = adapter->mii.phy_id;
612 netdev_dbg(netdev, "phy_addr = %d\n", adapter->mii.phy_id);
613 if (addr == PCH_GBE_PHY_REGS_LEN)
614 return -EAGAIN;
615 /* Selected the phy and isolate the rest */
616 for (addr = 0; addr < PCH_GBE_PHY_REGS_LEN; addr++) {
617 if (addr != adapter->mii.phy_id) {
618 pch_gbe_mdio_write(netdev, addr, MII_BMCR,
619 BMCR_ISOLATE);
620 } else {
621 bmcr = pch_gbe_mdio_read(netdev, addr, MII_BMCR);
622 pch_gbe_mdio_write(netdev, addr, MII_BMCR,
623 bmcr & ~BMCR_ISOLATE);
624 }
625 }
626
627 /* MII setup */
628 adapter->mii.phy_id_mask = 0x1F;
629 adapter->mii.reg_num_mask = 0x1F;
630 adapter->mii.dev = adapter->netdev;
631 adapter->mii.mdio_read = pch_gbe_mdio_read;
632 adapter->mii.mdio_write = pch_gbe_mdio_write;
633 adapter->mii.supports_gmii = mii_check_gmii_support(&adapter->mii);
634 return 0;
635 }
636
637 /**
638 * pch_gbe_mdio_read - The read function for mii
639 * @netdev: Network interface device structure
640 * @addr: Phy ID
641 * @reg: Access location
642 * Returns:
643 * 0: Successfully
644 * Negative value: Failed
645 */
pch_gbe_mdio_read(struct net_device * netdev,int addr,int reg)646 static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg)
647 {
648 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
649 struct pch_gbe_hw *hw = &adapter->hw;
650
651 return pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_READ, reg,
652 (u16) 0);
653 }
654
655 /**
656 * pch_gbe_mdio_write - The write function for mii
657 * @netdev: Network interface device structure
658 * @addr: Phy ID (not used)
659 * @reg: Access location
660 * @data: Write data
661 */
pch_gbe_mdio_write(struct net_device * netdev,int addr,int reg,int data)662 static void pch_gbe_mdio_write(struct net_device *netdev,
663 int addr, int reg, int data)
664 {
665 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
666 struct pch_gbe_hw *hw = &adapter->hw;
667
668 pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_WRITE, reg, data);
669 }
670
671 /**
672 * pch_gbe_reset_task - Reset processing at the time of transmission timeout
673 * @work: Pointer of board private structure
674 */
pch_gbe_reset_task(struct work_struct * work)675 static void pch_gbe_reset_task(struct work_struct *work)
676 {
677 struct pch_gbe_adapter *adapter;
678 adapter = container_of(work, struct pch_gbe_adapter, reset_task);
679
680 rtnl_lock();
681 pch_gbe_reinit_locked(adapter);
682 rtnl_unlock();
683 }
684
685 /**
686 * pch_gbe_reinit_locked- Re-initialization
687 * @adapter: Board private structure
688 */
pch_gbe_reinit_locked(struct pch_gbe_adapter * adapter)689 void pch_gbe_reinit_locked(struct pch_gbe_adapter *adapter)
690 {
691 pch_gbe_down(adapter);
692 pch_gbe_up(adapter);
693 }
694
695 /**
696 * pch_gbe_reset - Reset GbE
697 * @adapter: Board private structure
698 */
pch_gbe_reset(struct pch_gbe_adapter * adapter)699 void pch_gbe_reset(struct pch_gbe_adapter *adapter)
700 {
701 struct net_device *netdev = adapter->netdev;
702 struct pch_gbe_hw *hw = &adapter->hw;
703 s32 ret_val;
704
705 pch_gbe_mac_reset_hw(hw);
706 /* reprogram multicast address register after reset */
707 pch_gbe_set_multi(netdev);
708 /* Setup the receive address. */
709 pch_gbe_mac_init_rx_addrs(hw, PCH_GBE_MAR_ENTRIES);
710
711 ret_val = pch_gbe_phy_get_id(hw);
712 if (ret_val) {
713 netdev_err(adapter->netdev, "pch_gbe_phy_get_id error\n");
714 return;
715 }
716 pch_gbe_phy_init_setting(hw);
717 /* Setup Mac interface option RGMII */
718 pch_gbe_phy_set_rgmii(hw);
719 }
720
721 /**
722 * pch_gbe_free_irq - Free an interrupt
723 * @adapter: Board private structure
724 */
pch_gbe_free_irq(struct pch_gbe_adapter * adapter)725 static void pch_gbe_free_irq(struct pch_gbe_adapter *adapter)
726 {
727 struct net_device *netdev = adapter->netdev;
728
729 free_irq(adapter->irq, netdev);
730 pci_free_irq_vectors(adapter->pdev);
731 }
732
733 /**
734 * pch_gbe_irq_disable - Mask off interrupt generation on the NIC
735 * @adapter: Board private structure
736 */
pch_gbe_irq_disable(struct pch_gbe_adapter * adapter)737 static void pch_gbe_irq_disable(struct pch_gbe_adapter *adapter)
738 {
739 struct pch_gbe_hw *hw = &adapter->hw;
740
741 atomic_inc(&adapter->irq_sem);
742 iowrite32(0, &hw->reg->INT_EN);
743 ioread32(&hw->reg->INT_ST);
744 synchronize_irq(adapter->irq);
745
746 netdev_dbg(adapter->netdev, "INT_EN reg : 0x%08x\n",
747 ioread32(&hw->reg->INT_EN));
748 }
749
750 /**
751 * pch_gbe_irq_enable - Enable default interrupt generation settings
752 * @adapter: Board private structure
753 */
pch_gbe_irq_enable(struct pch_gbe_adapter * adapter)754 static void pch_gbe_irq_enable(struct pch_gbe_adapter *adapter)
755 {
756 struct pch_gbe_hw *hw = &adapter->hw;
757
758 if (likely(atomic_dec_and_test(&adapter->irq_sem)))
759 iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN);
760 ioread32(&hw->reg->INT_ST);
761 netdev_dbg(adapter->netdev, "INT_EN reg : 0x%08x\n",
762 ioread32(&hw->reg->INT_EN));
763 }
764
765
766
767 /**
768 * pch_gbe_setup_tctl - configure the Transmit control registers
769 * @adapter: Board private structure
770 */
pch_gbe_setup_tctl(struct pch_gbe_adapter * adapter)771 static void pch_gbe_setup_tctl(struct pch_gbe_adapter *adapter)
772 {
773 struct pch_gbe_hw *hw = &adapter->hw;
774 u32 tx_mode, tcpip;
775
776 tx_mode = PCH_GBE_TM_LONG_PKT |
777 PCH_GBE_TM_ST_AND_FD |
778 PCH_GBE_TM_SHORT_PKT |
779 PCH_GBE_TM_TH_TX_STRT_8 |
780 PCH_GBE_TM_TH_ALM_EMP_4 | PCH_GBE_TM_TH_ALM_FULL_8;
781
782 iowrite32(tx_mode, &hw->reg->TX_MODE);
783
784 tcpip = ioread32(&hw->reg->TCPIP_ACC);
785 tcpip |= PCH_GBE_TX_TCPIPACC_EN;
786 iowrite32(tcpip, &hw->reg->TCPIP_ACC);
787 return;
788 }
789
790 /**
791 * pch_gbe_configure_tx - Configure Transmit Unit after Reset
792 * @adapter: Board private structure
793 */
pch_gbe_configure_tx(struct pch_gbe_adapter * adapter)794 static void pch_gbe_configure_tx(struct pch_gbe_adapter *adapter)
795 {
796 struct pch_gbe_hw *hw = &adapter->hw;
797 u32 tdba, tdlen, dctrl;
798
799 netdev_dbg(adapter->netdev, "dma addr = 0x%08llx size = 0x%08x\n",
800 (unsigned long long)adapter->tx_ring->dma,
801 adapter->tx_ring->size);
802
803 /* Setup the HW Tx Head and Tail descriptor pointers */
804 tdba = adapter->tx_ring->dma;
805 tdlen = adapter->tx_ring->size - 0x10;
806 iowrite32(tdba, &hw->reg->TX_DSC_BASE);
807 iowrite32(tdlen, &hw->reg->TX_DSC_SIZE);
808 iowrite32(tdba, &hw->reg->TX_DSC_SW_P);
809
810 /* Enables Transmission DMA */
811 dctrl = ioread32(&hw->reg->DMA_CTRL);
812 dctrl |= PCH_GBE_TX_DMA_EN;
813 iowrite32(dctrl, &hw->reg->DMA_CTRL);
814 }
815
816 /**
817 * pch_gbe_setup_rctl - Configure the receive control registers
818 * @adapter: Board private structure
819 */
pch_gbe_setup_rctl(struct pch_gbe_adapter * adapter)820 static void pch_gbe_setup_rctl(struct pch_gbe_adapter *adapter)
821 {
822 struct pch_gbe_hw *hw = &adapter->hw;
823 u32 rx_mode, tcpip;
824
825 rx_mode = PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN |
826 PCH_GBE_RH_ALM_EMP_4 | PCH_GBE_RH_ALM_FULL_4 | PCH_GBE_RH_RD_TRG_8;
827
828 iowrite32(rx_mode, &hw->reg->RX_MODE);
829
830 tcpip = ioread32(&hw->reg->TCPIP_ACC);
831
832 tcpip |= PCH_GBE_RX_TCPIPACC_OFF;
833 tcpip &= ~PCH_GBE_RX_TCPIPACC_EN;
834 iowrite32(tcpip, &hw->reg->TCPIP_ACC);
835 return;
836 }
837
838 /**
839 * pch_gbe_configure_rx - Configure Receive Unit after Reset
840 * @adapter: Board private structure
841 */
pch_gbe_configure_rx(struct pch_gbe_adapter * adapter)842 static void pch_gbe_configure_rx(struct pch_gbe_adapter *adapter)
843 {
844 struct pch_gbe_hw *hw = &adapter->hw;
845 u32 rdba, rdlen, rxdma;
846
847 netdev_dbg(adapter->netdev, "dma adr = 0x%08llx size = 0x%08x\n",
848 (unsigned long long)adapter->rx_ring->dma,
849 adapter->rx_ring->size);
850
851 pch_gbe_mac_force_mac_fc(hw);
852
853 pch_gbe_disable_mac_rx(hw);
854
855 /* Disables Receive DMA */
856 rxdma = ioread32(&hw->reg->DMA_CTRL);
857 rxdma &= ~PCH_GBE_RX_DMA_EN;
858 iowrite32(rxdma, &hw->reg->DMA_CTRL);
859
860 netdev_dbg(adapter->netdev,
861 "MAC_RX_EN reg = 0x%08x DMA_CTRL reg = 0x%08x\n",
862 ioread32(&hw->reg->MAC_RX_EN),
863 ioread32(&hw->reg->DMA_CTRL));
864
865 /* Setup the HW Rx Head and Tail Descriptor Pointers and
866 * the Base and Length of the Rx Descriptor Ring */
867 rdba = adapter->rx_ring->dma;
868 rdlen = adapter->rx_ring->size - 0x10;
869 iowrite32(rdba, &hw->reg->RX_DSC_BASE);
870 iowrite32(rdlen, &hw->reg->RX_DSC_SIZE);
871 iowrite32((rdba + rdlen), &hw->reg->RX_DSC_SW_P);
872 }
873
874 /**
875 * pch_gbe_unmap_and_free_tx_resource - Unmap and free tx socket buffer
876 * @adapter: Board private structure
877 * @buffer_info: Buffer information structure
878 */
pch_gbe_unmap_and_free_tx_resource(struct pch_gbe_adapter * adapter,struct pch_gbe_buffer * buffer_info)879 static void pch_gbe_unmap_and_free_tx_resource(
880 struct pch_gbe_adapter *adapter, struct pch_gbe_buffer *buffer_info)
881 {
882 if (buffer_info->mapped) {
883 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
884 buffer_info->length, DMA_TO_DEVICE);
885 buffer_info->mapped = false;
886 }
887 if (buffer_info->skb) {
888 dev_kfree_skb_any(buffer_info->skb);
889 buffer_info->skb = NULL;
890 }
891 }
892
893 /**
894 * pch_gbe_unmap_and_free_rx_resource - Unmap and free rx socket buffer
895 * @adapter: Board private structure
896 * @buffer_info: Buffer information structure
897 */
pch_gbe_unmap_and_free_rx_resource(struct pch_gbe_adapter * adapter,struct pch_gbe_buffer * buffer_info)898 static void pch_gbe_unmap_and_free_rx_resource(
899 struct pch_gbe_adapter *adapter,
900 struct pch_gbe_buffer *buffer_info)
901 {
902 if (buffer_info->mapped) {
903 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
904 buffer_info->length, DMA_FROM_DEVICE);
905 buffer_info->mapped = false;
906 }
907 if (buffer_info->skb) {
908 dev_kfree_skb_any(buffer_info->skb);
909 buffer_info->skb = NULL;
910 }
911 }
912
913 /**
914 * pch_gbe_clean_tx_ring - Free Tx Buffers
915 * @adapter: Board private structure
916 * @tx_ring: Ring to be cleaned
917 */
pch_gbe_clean_tx_ring(struct pch_gbe_adapter * adapter,struct pch_gbe_tx_ring * tx_ring)918 static void pch_gbe_clean_tx_ring(struct pch_gbe_adapter *adapter,
919 struct pch_gbe_tx_ring *tx_ring)
920 {
921 struct pch_gbe_hw *hw = &adapter->hw;
922 struct pch_gbe_buffer *buffer_info;
923 unsigned long size;
924 unsigned int i;
925
926 /* Free all the Tx ring sk_buffs */
927 for (i = 0; i < tx_ring->count; i++) {
928 buffer_info = &tx_ring->buffer_info[i];
929 pch_gbe_unmap_and_free_tx_resource(adapter, buffer_info);
930 }
931 netdev_dbg(adapter->netdev,
932 "call pch_gbe_unmap_and_free_tx_resource() %d count\n", i);
933
934 size = (unsigned long)sizeof(struct pch_gbe_buffer) * tx_ring->count;
935 memset(tx_ring->buffer_info, 0, size);
936
937 /* Zero out the descriptor ring */
938 memset(tx_ring->desc, 0, tx_ring->size);
939 tx_ring->next_to_use = 0;
940 tx_ring->next_to_clean = 0;
941 iowrite32(tx_ring->dma, &hw->reg->TX_DSC_HW_P);
942 iowrite32((tx_ring->size - 0x10), &hw->reg->TX_DSC_SIZE);
943 }
944
945 /**
946 * pch_gbe_clean_rx_ring - Free Rx Buffers
947 * @adapter: Board private structure
948 * @rx_ring: Ring to free buffers from
949 */
950 static void
pch_gbe_clean_rx_ring(struct pch_gbe_adapter * adapter,struct pch_gbe_rx_ring * rx_ring)951 pch_gbe_clean_rx_ring(struct pch_gbe_adapter *adapter,
952 struct pch_gbe_rx_ring *rx_ring)
953 {
954 struct pch_gbe_hw *hw = &adapter->hw;
955 struct pch_gbe_buffer *buffer_info;
956 unsigned long size;
957 unsigned int i;
958
959 /* Free all the Rx ring sk_buffs */
960 for (i = 0; i < rx_ring->count; i++) {
961 buffer_info = &rx_ring->buffer_info[i];
962 pch_gbe_unmap_and_free_rx_resource(adapter, buffer_info);
963 }
964 netdev_dbg(adapter->netdev,
965 "call pch_gbe_unmap_and_free_rx_resource() %d count\n", i);
966 size = (unsigned long)sizeof(struct pch_gbe_buffer) * rx_ring->count;
967 memset(rx_ring->buffer_info, 0, size);
968
969 /* Zero out the descriptor ring */
970 memset(rx_ring->desc, 0, rx_ring->size);
971 rx_ring->next_to_clean = 0;
972 rx_ring->next_to_use = 0;
973 iowrite32(rx_ring->dma, &hw->reg->RX_DSC_HW_P);
974 iowrite32((rx_ring->size - 0x10), &hw->reg->RX_DSC_SIZE);
975 }
976
pch_gbe_set_rgmii_ctrl(struct pch_gbe_adapter * adapter,u16 speed,u16 duplex)977 static void pch_gbe_set_rgmii_ctrl(struct pch_gbe_adapter *adapter, u16 speed,
978 u16 duplex)
979 {
980 struct pch_gbe_hw *hw = &adapter->hw;
981 unsigned long rgmii = 0;
982
983 /* Set the RGMII control. */
984 switch (speed) {
985 case SPEED_10:
986 rgmii = (PCH_GBE_RGMII_RATE_2_5M |
987 PCH_GBE_MAC_RGMII_CTRL_SETTING);
988 break;
989 case SPEED_100:
990 rgmii = (PCH_GBE_RGMII_RATE_25M |
991 PCH_GBE_MAC_RGMII_CTRL_SETTING);
992 break;
993 case SPEED_1000:
994 rgmii = (PCH_GBE_RGMII_RATE_125M |
995 PCH_GBE_MAC_RGMII_CTRL_SETTING);
996 break;
997 }
998 iowrite32(rgmii, &hw->reg->RGMII_CTRL);
999 }
pch_gbe_set_mode(struct pch_gbe_adapter * adapter,u16 speed,u16 duplex)1000 static void pch_gbe_set_mode(struct pch_gbe_adapter *adapter, u16 speed,
1001 u16 duplex)
1002 {
1003 struct net_device *netdev = adapter->netdev;
1004 struct pch_gbe_hw *hw = &adapter->hw;
1005 unsigned long mode = 0;
1006
1007 /* Set the communication mode */
1008 switch (speed) {
1009 case SPEED_10:
1010 mode = PCH_GBE_MODE_MII_ETHER;
1011 netdev->tx_queue_len = 10;
1012 break;
1013 case SPEED_100:
1014 mode = PCH_GBE_MODE_MII_ETHER;
1015 netdev->tx_queue_len = 100;
1016 break;
1017 case SPEED_1000:
1018 mode = PCH_GBE_MODE_GMII_ETHER;
1019 break;
1020 }
1021 if (duplex == DUPLEX_FULL)
1022 mode |= PCH_GBE_MODE_FULL_DUPLEX;
1023 else
1024 mode |= PCH_GBE_MODE_HALF_DUPLEX;
1025 iowrite32(mode, &hw->reg->MODE);
1026 }
1027
1028 /**
1029 * pch_gbe_watchdog - Watchdog process
1030 * @t: timer list containing a Board private structure
1031 */
pch_gbe_watchdog(struct timer_list * t)1032 static void pch_gbe_watchdog(struct timer_list *t)
1033 {
1034 struct pch_gbe_adapter *adapter = from_timer(adapter, t,
1035 watchdog_timer);
1036 struct net_device *netdev = adapter->netdev;
1037 struct pch_gbe_hw *hw = &adapter->hw;
1038
1039 netdev_dbg(netdev, "right now = %ld\n", jiffies);
1040
1041 pch_gbe_update_stats(adapter);
1042 if ((mii_link_ok(&adapter->mii)) && (!netif_carrier_ok(netdev))) {
1043 struct ethtool_cmd cmd = { .cmd = ETHTOOL_GSET };
1044 netdev->tx_queue_len = adapter->tx_queue_len;
1045 /* mii library handles link maintenance tasks */
1046 if (mii_ethtool_gset(&adapter->mii, &cmd)) {
1047 netdev_err(netdev, "ethtool get setting Error\n");
1048 mod_timer(&adapter->watchdog_timer,
1049 round_jiffies(jiffies +
1050 PCH_GBE_WATCHDOG_PERIOD));
1051 return;
1052 }
1053 hw->mac.link_speed = ethtool_cmd_speed(&cmd);
1054 hw->mac.link_duplex = cmd.duplex;
1055 /* Set the RGMII control. */
1056 pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed,
1057 hw->mac.link_duplex);
1058 /* Set the communication mode */
1059 pch_gbe_set_mode(adapter, hw->mac.link_speed,
1060 hw->mac.link_duplex);
1061 netdev_dbg(netdev,
1062 "Link is Up %d Mbps %s-Duplex\n",
1063 hw->mac.link_speed,
1064 cmd.duplex == DUPLEX_FULL ? "Full" : "Half");
1065 netif_carrier_on(netdev);
1066 netif_wake_queue(netdev);
1067 } else if ((!mii_link_ok(&adapter->mii)) &&
1068 (netif_carrier_ok(netdev))) {
1069 netdev_dbg(netdev, "NIC Link is Down\n");
1070 hw->mac.link_speed = SPEED_10;
1071 hw->mac.link_duplex = DUPLEX_HALF;
1072 netif_carrier_off(netdev);
1073 netif_stop_queue(netdev);
1074 }
1075 mod_timer(&adapter->watchdog_timer,
1076 round_jiffies(jiffies + PCH_GBE_WATCHDOG_PERIOD));
1077 }
1078
1079 /**
1080 * pch_gbe_tx_queue - Carry out queuing of the transmission data
1081 * @adapter: Board private structure
1082 * @tx_ring: Tx descriptor ring structure
1083 * @skb: Sockt buffer structure
1084 */
pch_gbe_tx_queue(struct pch_gbe_adapter * adapter,struct pch_gbe_tx_ring * tx_ring,struct sk_buff * skb)1085 static void pch_gbe_tx_queue(struct pch_gbe_adapter *adapter,
1086 struct pch_gbe_tx_ring *tx_ring,
1087 struct sk_buff *skb)
1088 {
1089 struct pch_gbe_hw *hw = &adapter->hw;
1090 struct pch_gbe_tx_desc *tx_desc;
1091 struct pch_gbe_buffer *buffer_info;
1092 struct sk_buff *tmp_skb;
1093 unsigned int frame_ctrl;
1094 unsigned int ring_num;
1095
1096 /*-- Set frame control --*/
1097 frame_ctrl = 0;
1098 if (unlikely(skb->len < PCH_GBE_SHORT_PKT))
1099 frame_ctrl |= PCH_GBE_TXD_CTRL_APAD;
1100 if (skb->ip_summed == CHECKSUM_NONE)
1101 frame_ctrl |= PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF;
1102
1103 /* Performs checksum processing */
1104 /*
1105 * It is because the hardware accelerator does not support a checksum,
1106 * when the received data size is less than 64 bytes.
1107 */
1108 if (skb->len < PCH_GBE_SHORT_PKT && skb->ip_summed != CHECKSUM_NONE) {
1109 frame_ctrl |= PCH_GBE_TXD_CTRL_APAD |
1110 PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF;
1111 if (skb->protocol == htons(ETH_P_IP)) {
1112 struct iphdr *iph = ip_hdr(skb);
1113 unsigned int offset;
1114 offset = skb_transport_offset(skb);
1115 if (iph->protocol == IPPROTO_TCP) {
1116 skb->csum = 0;
1117 tcp_hdr(skb)->check = 0;
1118 skb->csum = skb_checksum(skb, offset,
1119 skb->len - offset, 0);
1120 tcp_hdr(skb)->check =
1121 csum_tcpudp_magic(iph->saddr,
1122 iph->daddr,
1123 skb->len - offset,
1124 IPPROTO_TCP,
1125 skb->csum);
1126 } else if (iph->protocol == IPPROTO_UDP) {
1127 skb->csum = 0;
1128 udp_hdr(skb)->check = 0;
1129 skb->csum =
1130 skb_checksum(skb, offset,
1131 skb->len - offset, 0);
1132 udp_hdr(skb)->check =
1133 csum_tcpudp_magic(iph->saddr,
1134 iph->daddr,
1135 skb->len - offset,
1136 IPPROTO_UDP,
1137 skb->csum);
1138 }
1139 }
1140 }
1141
1142 ring_num = tx_ring->next_to_use;
1143 if (unlikely((ring_num + 1) == tx_ring->count))
1144 tx_ring->next_to_use = 0;
1145 else
1146 tx_ring->next_to_use = ring_num + 1;
1147
1148
1149 buffer_info = &tx_ring->buffer_info[ring_num];
1150 tmp_skb = buffer_info->skb;
1151
1152 /* [Header:14][payload] ---> [Header:14][paddong:2][payload] */
1153 memcpy(tmp_skb->data, skb->data, ETH_HLEN);
1154 tmp_skb->data[ETH_HLEN] = 0x00;
1155 tmp_skb->data[ETH_HLEN + 1] = 0x00;
1156 tmp_skb->len = skb->len;
1157 memcpy(&tmp_skb->data[ETH_HLEN + 2], &skb->data[ETH_HLEN],
1158 (skb->len - ETH_HLEN));
1159 /*-- Set Buffer information --*/
1160 buffer_info->length = tmp_skb->len;
1161 buffer_info->dma = dma_map_single(&adapter->pdev->dev, tmp_skb->data,
1162 buffer_info->length,
1163 DMA_TO_DEVICE);
1164 if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) {
1165 netdev_err(adapter->netdev, "TX DMA map failed\n");
1166 buffer_info->dma = 0;
1167 buffer_info->time_stamp = 0;
1168 tx_ring->next_to_use = ring_num;
1169 return;
1170 }
1171 buffer_info->mapped = true;
1172 buffer_info->time_stamp = jiffies;
1173
1174 /*-- Set Tx descriptor --*/
1175 tx_desc = PCH_GBE_TX_DESC(*tx_ring, ring_num);
1176 tx_desc->buffer_addr = (buffer_info->dma);
1177 tx_desc->length = (tmp_skb->len);
1178 tx_desc->tx_words_eob = ((tmp_skb->len + 3));
1179 tx_desc->tx_frame_ctrl = (frame_ctrl);
1180 tx_desc->gbec_status = (DSC_INIT16);
1181
1182 if (unlikely(++ring_num == tx_ring->count))
1183 ring_num = 0;
1184
1185 /* Update software pointer of TX descriptor */
1186 iowrite32(tx_ring->dma +
1187 (int)sizeof(struct pch_gbe_tx_desc) * ring_num,
1188 &hw->reg->TX_DSC_SW_P);
1189
1190 pch_tx_timestamp(adapter, skb);
1191
1192 dev_kfree_skb_any(skb);
1193 }
1194
1195 /**
1196 * pch_gbe_update_stats - Update the board statistics counters
1197 * @adapter: Board private structure
1198 */
pch_gbe_update_stats(struct pch_gbe_adapter * adapter)1199 void pch_gbe_update_stats(struct pch_gbe_adapter *adapter)
1200 {
1201 struct net_device *netdev = adapter->netdev;
1202 struct pci_dev *pdev = adapter->pdev;
1203 struct pch_gbe_hw_stats *stats = &adapter->stats;
1204 unsigned long flags;
1205
1206 /*
1207 * Prevent stats update while adapter is being reset, or if the pci
1208 * connection is down.
1209 */
1210 if ((pdev->error_state) && (pdev->error_state != pci_channel_io_normal))
1211 return;
1212
1213 spin_lock_irqsave(&adapter->stats_lock, flags);
1214
1215 /* Update device status "adapter->stats" */
1216 stats->rx_errors = stats->rx_crc_errors + stats->rx_frame_errors;
1217 stats->tx_errors = stats->tx_length_errors +
1218 stats->tx_aborted_errors +
1219 stats->tx_carrier_errors + stats->tx_timeout_count;
1220
1221 /* Update network device status "adapter->net_stats" */
1222 netdev->stats.rx_packets = stats->rx_packets;
1223 netdev->stats.rx_bytes = stats->rx_bytes;
1224 netdev->stats.rx_dropped = stats->rx_dropped;
1225 netdev->stats.tx_packets = stats->tx_packets;
1226 netdev->stats.tx_bytes = stats->tx_bytes;
1227 netdev->stats.tx_dropped = stats->tx_dropped;
1228 /* Fill out the OS statistics structure */
1229 netdev->stats.multicast = stats->multicast;
1230 netdev->stats.collisions = stats->collisions;
1231 /* Rx Errors */
1232 netdev->stats.rx_errors = stats->rx_errors;
1233 netdev->stats.rx_crc_errors = stats->rx_crc_errors;
1234 netdev->stats.rx_frame_errors = stats->rx_frame_errors;
1235 /* Tx Errors */
1236 netdev->stats.tx_errors = stats->tx_errors;
1237 netdev->stats.tx_aborted_errors = stats->tx_aborted_errors;
1238 netdev->stats.tx_carrier_errors = stats->tx_carrier_errors;
1239
1240 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1241 }
1242
pch_gbe_disable_dma_rx(struct pch_gbe_hw * hw)1243 static void pch_gbe_disable_dma_rx(struct pch_gbe_hw *hw)
1244 {
1245 u32 rxdma;
1246
1247 /* Disable Receive DMA */
1248 rxdma = ioread32(&hw->reg->DMA_CTRL);
1249 rxdma &= ~PCH_GBE_RX_DMA_EN;
1250 iowrite32(rxdma, &hw->reg->DMA_CTRL);
1251 }
1252
pch_gbe_enable_dma_rx(struct pch_gbe_hw * hw)1253 static void pch_gbe_enable_dma_rx(struct pch_gbe_hw *hw)
1254 {
1255 u32 rxdma;
1256
1257 /* Enables Receive DMA */
1258 rxdma = ioread32(&hw->reg->DMA_CTRL);
1259 rxdma |= PCH_GBE_RX_DMA_EN;
1260 iowrite32(rxdma, &hw->reg->DMA_CTRL);
1261 }
1262
1263 /**
1264 * pch_gbe_intr - Interrupt Handler
1265 * @irq: Interrupt number
1266 * @data: Pointer to a network interface device structure
1267 * Returns:
1268 * - IRQ_HANDLED: Our interrupt
1269 * - IRQ_NONE: Not our interrupt
1270 */
pch_gbe_intr(int irq,void * data)1271 static irqreturn_t pch_gbe_intr(int irq, void *data)
1272 {
1273 struct net_device *netdev = data;
1274 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1275 struct pch_gbe_hw *hw = &adapter->hw;
1276 u32 int_st;
1277 u32 int_en;
1278
1279 /* Check request status */
1280 int_st = ioread32(&hw->reg->INT_ST);
1281 int_st = int_st & ioread32(&hw->reg->INT_EN);
1282 /* When request status is no interruption factor */
1283 if (unlikely(!int_st))
1284 return IRQ_NONE; /* Not our interrupt. End processing. */
1285 netdev_dbg(netdev, "%s occur int_st = 0x%08x\n", __func__, int_st);
1286 if (int_st & PCH_GBE_INT_RX_FRAME_ERR)
1287 adapter->stats.intr_rx_frame_err_count++;
1288 if (int_st & PCH_GBE_INT_RX_FIFO_ERR)
1289 if (!adapter->rx_stop_flag) {
1290 adapter->stats.intr_rx_fifo_err_count++;
1291 netdev_dbg(netdev, "Rx fifo over run\n");
1292 adapter->rx_stop_flag = true;
1293 int_en = ioread32(&hw->reg->INT_EN);
1294 iowrite32((int_en & ~PCH_GBE_INT_RX_FIFO_ERR),
1295 &hw->reg->INT_EN);
1296 pch_gbe_disable_dma_rx(&adapter->hw);
1297 int_st |= ioread32(&hw->reg->INT_ST);
1298 int_st = int_st & ioread32(&hw->reg->INT_EN);
1299 }
1300 if (int_st & PCH_GBE_INT_RX_DMA_ERR)
1301 adapter->stats.intr_rx_dma_err_count++;
1302 if (int_st & PCH_GBE_INT_TX_FIFO_ERR)
1303 adapter->stats.intr_tx_fifo_err_count++;
1304 if (int_st & PCH_GBE_INT_TX_DMA_ERR)
1305 adapter->stats.intr_tx_dma_err_count++;
1306 if (int_st & PCH_GBE_INT_TCPIP_ERR)
1307 adapter->stats.intr_tcpip_err_count++;
1308 /* When Rx descriptor is empty */
1309 if ((int_st & PCH_GBE_INT_RX_DSC_EMP)) {
1310 adapter->stats.intr_rx_dsc_empty_count++;
1311 netdev_dbg(netdev, "Rx descriptor is empty\n");
1312 int_en = ioread32(&hw->reg->INT_EN);
1313 iowrite32((int_en & ~PCH_GBE_INT_RX_DSC_EMP), &hw->reg->INT_EN);
1314 if (hw->mac.tx_fc_enable) {
1315 /* Set Pause packet */
1316 pch_gbe_mac_set_pause_packet(hw);
1317 }
1318 }
1319
1320 /* When request status is Receive interruption */
1321 if ((int_st & (PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT)) ||
1322 (adapter->rx_stop_flag)) {
1323 if (likely(napi_schedule_prep(&adapter->napi))) {
1324 /* Enable only Rx Descriptor empty */
1325 atomic_inc(&adapter->irq_sem);
1326 int_en = ioread32(&hw->reg->INT_EN);
1327 int_en &=
1328 ~(PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT);
1329 iowrite32(int_en, &hw->reg->INT_EN);
1330 /* Start polling for NAPI */
1331 __napi_schedule(&adapter->napi);
1332 }
1333 }
1334 netdev_dbg(netdev, "return = 0x%08x INT_EN reg = 0x%08x\n",
1335 IRQ_HANDLED, ioread32(&hw->reg->INT_EN));
1336 return IRQ_HANDLED;
1337 }
1338
1339 /**
1340 * pch_gbe_alloc_rx_buffers - Replace used receive buffers; legacy & extended
1341 * @adapter: Board private structure
1342 * @rx_ring: Rx descriptor ring
1343 * @cleaned_count: Cleaned count
1344 */
1345 static void
pch_gbe_alloc_rx_buffers(struct pch_gbe_adapter * adapter,struct pch_gbe_rx_ring * rx_ring,int cleaned_count)1346 pch_gbe_alloc_rx_buffers(struct pch_gbe_adapter *adapter,
1347 struct pch_gbe_rx_ring *rx_ring, int cleaned_count)
1348 {
1349 struct net_device *netdev = adapter->netdev;
1350 struct pci_dev *pdev = adapter->pdev;
1351 struct pch_gbe_hw *hw = &adapter->hw;
1352 struct pch_gbe_rx_desc *rx_desc;
1353 struct pch_gbe_buffer *buffer_info;
1354 struct sk_buff *skb;
1355 unsigned int i;
1356 unsigned int bufsz;
1357
1358 bufsz = adapter->rx_buffer_len + NET_IP_ALIGN;
1359 i = rx_ring->next_to_use;
1360
1361 while ((cleaned_count--)) {
1362 buffer_info = &rx_ring->buffer_info[i];
1363 skb = netdev_alloc_skb(netdev, bufsz);
1364 if (unlikely(!skb)) {
1365 /* Better luck next round */
1366 adapter->stats.rx_alloc_buff_failed++;
1367 break;
1368 }
1369 /* align */
1370 skb_reserve(skb, NET_IP_ALIGN);
1371 buffer_info->skb = skb;
1372
1373 buffer_info->dma = dma_map_single(&pdev->dev,
1374 buffer_info->rx_buffer,
1375 buffer_info->length,
1376 DMA_FROM_DEVICE);
1377 if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) {
1378 dev_kfree_skb(skb);
1379 buffer_info->skb = NULL;
1380 buffer_info->dma = 0;
1381 adapter->stats.rx_alloc_buff_failed++;
1382 break; /* while !buffer_info->skb */
1383 }
1384 buffer_info->mapped = true;
1385 rx_desc = PCH_GBE_RX_DESC(*rx_ring, i);
1386 rx_desc->buffer_addr = (buffer_info->dma);
1387 rx_desc->gbec_status = DSC_INIT16;
1388
1389 netdev_dbg(netdev,
1390 "i = %d buffer_info->dma = 0x08%llx buffer_info->length = 0x%x\n",
1391 i, (unsigned long long)buffer_info->dma,
1392 buffer_info->length);
1393
1394 if (unlikely(++i == rx_ring->count))
1395 i = 0;
1396 }
1397 if (likely(rx_ring->next_to_use != i)) {
1398 rx_ring->next_to_use = i;
1399 if (unlikely(i-- == 0))
1400 i = (rx_ring->count - 1);
1401 iowrite32(rx_ring->dma +
1402 (int)sizeof(struct pch_gbe_rx_desc) * i,
1403 &hw->reg->RX_DSC_SW_P);
1404 }
1405 return;
1406 }
1407
1408 static int
pch_gbe_alloc_rx_buffers_pool(struct pch_gbe_adapter * adapter,struct pch_gbe_rx_ring * rx_ring,int cleaned_count)1409 pch_gbe_alloc_rx_buffers_pool(struct pch_gbe_adapter *adapter,
1410 struct pch_gbe_rx_ring *rx_ring, int cleaned_count)
1411 {
1412 struct pci_dev *pdev = adapter->pdev;
1413 struct pch_gbe_buffer *buffer_info;
1414 unsigned int i;
1415 unsigned int bufsz;
1416 unsigned int size;
1417
1418 bufsz = adapter->rx_buffer_len;
1419
1420 size = rx_ring->count * bufsz + PCH_GBE_RESERVE_MEMORY;
1421 rx_ring->rx_buff_pool =
1422 dma_alloc_coherent(&pdev->dev, size,
1423 &rx_ring->rx_buff_pool_logic, GFP_KERNEL);
1424 if (!rx_ring->rx_buff_pool)
1425 return -ENOMEM;
1426
1427 rx_ring->rx_buff_pool_size = size;
1428 for (i = 0; i < rx_ring->count; i++) {
1429 buffer_info = &rx_ring->buffer_info[i];
1430 buffer_info->rx_buffer = rx_ring->rx_buff_pool + bufsz * i;
1431 buffer_info->length = bufsz;
1432 }
1433 return 0;
1434 }
1435
1436 /**
1437 * pch_gbe_alloc_tx_buffers - Allocate transmit buffers
1438 * @adapter: Board private structure
1439 * @tx_ring: Tx descriptor ring
1440 */
pch_gbe_alloc_tx_buffers(struct pch_gbe_adapter * adapter,struct pch_gbe_tx_ring * tx_ring)1441 static void pch_gbe_alloc_tx_buffers(struct pch_gbe_adapter *adapter,
1442 struct pch_gbe_tx_ring *tx_ring)
1443 {
1444 struct pch_gbe_buffer *buffer_info;
1445 struct sk_buff *skb;
1446 unsigned int i;
1447 unsigned int bufsz;
1448 struct pch_gbe_tx_desc *tx_desc;
1449
1450 bufsz =
1451 adapter->hw.mac.max_frame_size + PCH_GBE_DMA_ALIGN + NET_IP_ALIGN;
1452
1453 for (i = 0; i < tx_ring->count; i++) {
1454 buffer_info = &tx_ring->buffer_info[i];
1455 skb = netdev_alloc_skb(adapter->netdev, bufsz);
1456 skb_reserve(skb, PCH_GBE_DMA_ALIGN);
1457 buffer_info->skb = skb;
1458 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1459 tx_desc->gbec_status = (DSC_INIT16);
1460 }
1461 return;
1462 }
1463
1464 /**
1465 * pch_gbe_clean_tx - Reclaim resources after transmit completes
1466 * @adapter: Board private structure
1467 * @tx_ring: Tx descriptor ring
1468 * Returns:
1469 * true: Cleaned the descriptor
1470 * false: Not cleaned the descriptor
1471 */
1472 static bool
pch_gbe_clean_tx(struct pch_gbe_adapter * adapter,struct pch_gbe_tx_ring * tx_ring)1473 pch_gbe_clean_tx(struct pch_gbe_adapter *adapter,
1474 struct pch_gbe_tx_ring *tx_ring)
1475 {
1476 struct pch_gbe_tx_desc *tx_desc;
1477 struct pch_gbe_buffer *buffer_info;
1478 struct sk_buff *skb;
1479 unsigned int i;
1480 unsigned int cleaned_count = 0;
1481 bool cleaned = false;
1482 int unused, thresh;
1483
1484 netdev_dbg(adapter->netdev, "next_to_clean : %d\n",
1485 tx_ring->next_to_clean);
1486
1487 i = tx_ring->next_to_clean;
1488 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1489 netdev_dbg(adapter->netdev, "gbec_status:0x%04x dma_status:0x%04x\n",
1490 tx_desc->gbec_status, tx_desc->dma_status);
1491
1492 unused = PCH_GBE_DESC_UNUSED(tx_ring);
1493 thresh = tx_ring->count - PCH_GBE_TX_WEIGHT;
1494 if ((tx_desc->gbec_status == DSC_INIT16) && (unused < thresh))
1495 { /* current marked clean, tx queue filling up, do extra clean */
1496 int j, k;
1497 if (unused < 8) { /* tx queue nearly full */
1498 netdev_dbg(adapter->netdev,
1499 "clean_tx: transmit queue warning (%x,%x) unused=%d\n",
1500 tx_ring->next_to_clean, tx_ring->next_to_use,
1501 unused);
1502 }
1503
1504 /* current marked clean, scan for more that need cleaning. */
1505 k = i;
1506 for (j = 0; j < PCH_GBE_TX_WEIGHT; j++)
1507 {
1508 tx_desc = PCH_GBE_TX_DESC(*tx_ring, k);
1509 if (tx_desc->gbec_status != DSC_INIT16) break; /*found*/
1510 if (++k >= tx_ring->count) k = 0; /*increment, wrap*/
1511 }
1512 if (j < PCH_GBE_TX_WEIGHT) {
1513 netdev_dbg(adapter->netdev,
1514 "clean_tx: unused=%d loops=%d found tx_desc[%x,%x:%x].gbec_status=%04x\n",
1515 unused, j, i, k, tx_ring->next_to_use,
1516 tx_desc->gbec_status);
1517 i = k; /*found one to clean, usu gbec_status==2000.*/
1518 }
1519 }
1520
1521 while ((tx_desc->gbec_status & DSC_INIT16) == 0x0000) {
1522 netdev_dbg(adapter->netdev, "gbec_status:0x%04x\n",
1523 tx_desc->gbec_status);
1524 buffer_info = &tx_ring->buffer_info[i];
1525 skb = buffer_info->skb;
1526 cleaned = true;
1527
1528 if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_ABT)) {
1529 adapter->stats.tx_aborted_errors++;
1530 netdev_err(adapter->netdev, "Transfer Abort Error\n");
1531 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_CRSER)
1532 ) {
1533 adapter->stats.tx_carrier_errors++;
1534 netdev_err(adapter->netdev,
1535 "Transfer Carrier Sense Error\n");
1536 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_EXCOL)
1537 ) {
1538 adapter->stats.tx_aborted_errors++;
1539 netdev_err(adapter->netdev,
1540 "Transfer Collision Abort Error\n");
1541 } else if ((tx_desc->gbec_status &
1542 (PCH_GBE_TXD_GMAC_STAT_SNGCOL |
1543 PCH_GBE_TXD_GMAC_STAT_MLTCOL))) {
1544 adapter->stats.collisions++;
1545 adapter->stats.tx_packets++;
1546 adapter->stats.tx_bytes += skb->len;
1547 netdev_dbg(adapter->netdev, "Transfer Collision\n");
1548 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_CMPLT)
1549 ) {
1550 adapter->stats.tx_packets++;
1551 adapter->stats.tx_bytes += skb->len;
1552 }
1553 if (buffer_info->mapped) {
1554 netdev_dbg(adapter->netdev,
1555 "unmap buffer_info->dma : %d\n", i);
1556 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1557 buffer_info->length, DMA_TO_DEVICE);
1558 buffer_info->mapped = false;
1559 }
1560 if (buffer_info->skb) {
1561 netdev_dbg(adapter->netdev,
1562 "trim buffer_info->skb : %d\n", i);
1563 skb_trim(buffer_info->skb, 0);
1564 }
1565 tx_desc->gbec_status = DSC_INIT16;
1566 if (unlikely(++i == tx_ring->count))
1567 i = 0;
1568 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1569
1570 /* weight of a sort for tx, to avoid endless transmit cleanup */
1571 if (cleaned_count++ == PCH_GBE_TX_WEIGHT) {
1572 cleaned = false;
1573 break;
1574 }
1575 }
1576 netdev_dbg(adapter->netdev,
1577 "called pch_gbe_unmap_and_free_tx_resource() %d count\n",
1578 cleaned_count);
1579 if (cleaned_count > 0) { /*skip this if nothing cleaned*/
1580 /* Recover from running out of Tx resources in xmit_frame */
1581 netif_tx_lock(adapter->netdev);
1582 if (unlikely(cleaned && (netif_queue_stopped(adapter->netdev))))
1583 {
1584 netif_wake_queue(adapter->netdev);
1585 adapter->stats.tx_restart_count++;
1586 netdev_dbg(adapter->netdev, "Tx wake queue\n");
1587 }
1588
1589 tx_ring->next_to_clean = i;
1590
1591 netdev_dbg(adapter->netdev, "next_to_clean : %d\n",
1592 tx_ring->next_to_clean);
1593 netif_tx_unlock(adapter->netdev);
1594 }
1595 return cleaned;
1596 }
1597
1598 /**
1599 * pch_gbe_clean_rx - Send received data up the network stack; legacy
1600 * @adapter: Board private structure
1601 * @rx_ring: Rx descriptor ring
1602 * @work_done: Completed count
1603 * @work_to_do: Request count
1604 * Returns:
1605 * true: Cleaned the descriptor
1606 * false: Not cleaned the descriptor
1607 */
1608 static bool
pch_gbe_clean_rx(struct pch_gbe_adapter * adapter,struct pch_gbe_rx_ring * rx_ring,int * work_done,int work_to_do)1609 pch_gbe_clean_rx(struct pch_gbe_adapter *adapter,
1610 struct pch_gbe_rx_ring *rx_ring,
1611 int *work_done, int work_to_do)
1612 {
1613 struct net_device *netdev = adapter->netdev;
1614 struct pci_dev *pdev = adapter->pdev;
1615 struct pch_gbe_buffer *buffer_info;
1616 struct pch_gbe_rx_desc *rx_desc;
1617 u32 length;
1618 unsigned int i;
1619 unsigned int cleaned_count = 0;
1620 bool cleaned = false;
1621 struct sk_buff *skb;
1622 u8 dma_status;
1623 u16 gbec_status;
1624 u32 tcp_ip_status;
1625
1626 i = rx_ring->next_to_clean;
1627
1628 while (*work_done < work_to_do) {
1629 /* Check Rx descriptor status */
1630 rx_desc = PCH_GBE_RX_DESC(*rx_ring, i);
1631 if (rx_desc->gbec_status == DSC_INIT16)
1632 break;
1633 cleaned = true;
1634 cleaned_count++;
1635
1636 dma_status = rx_desc->dma_status;
1637 gbec_status = rx_desc->gbec_status;
1638 tcp_ip_status = rx_desc->tcp_ip_status;
1639 rx_desc->gbec_status = DSC_INIT16;
1640 buffer_info = &rx_ring->buffer_info[i];
1641 skb = buffer_info->skb;
1642 buffer_info->skb = NULL;
1643
1644 /* unmap dma */
1645 dma_unmap_single(&pdev->dev, buffer_info->dma,
1646 buffer_info->length, DMA_FROM_DEVICE);
1647 buffer_info->mapped = false;
1648
1649 netdev_dbg(netdev,
1650 "RxDecNo = 0x%04x Status[DMA:0x%02x GBE:0x%04x TCP:0x%08x] BufInf = 0x%p\n",
1651 i, dma_status, gbec_status, tcp_ip_status,
1652 buffer_info);
1653 /* Error check */
1654 if (unlikely(gbec_status & PCH_GBE_RXD_GMAC_STAT_NOTOCTAL)) {
1655 adapter->stats.rx_frame_errors++;
1656 netdev_err(netdev, "Receive Not Octal Error\n");
1657 } else if (unlikely(gbec_status &
1658 PCH_GBE_RXD_GMAC_STAT_NBLERR)) {
1659 adapter->stats.rx_frame_errors++;
1660 netdev_err(netdev, "Receive Nibble Error\n");
1661 } else if (unlikely(gbec_status &
1662 PCH_GBE_RXD_GMAC_STAT_CRCERR)) {
1663 adapter->stats.rx_crc_errors++;
1664 netdev_err(netdev, "Receive CRC Error\n");
1665 } else {
1666 /* get receive length */
1667 /* length convert[-3], length includes FCS length */
1668 length = (rx_desc->rx_words_eob) - 3 - ETH_FCS_LEN;
1669 if (rx_desc->rx_words_eob & 0x02)
1670 length = length - 4;
1671 /*
1672 * buffer_info->rx_buffer: [Header:14][payload]
1673 * skb->data: [Reserve:2][Header:14][payload]
1674 */
1675 memcpy(skb->data, buffer_info->rx_buffer, length);
1676
1677 /* update status of driver */
1678 adapter->stats.rx_bytes += length;
1679 adapter->stats.rx_packets++;
1680 if ((gbec_status & PCH_GBE_RXD_GMAC_STAT_MARMLT))
1681 adapter->stats.multicast++;
1682 /* Write meta date of skb */
1683 skb_put(skb, length);
1684
1685 pch_rx_timestamp(adapter, skb);
1686
1687 skb->protocol = eth_type_trans(skb, netdev);
1688 if (tcp_ip_status & PCH_GBE_RXD_ACC_STAT_TCPIPOK)
1689 skb->ip_summed = CHECKSUM_UNNECESSARY;
1690 else
1691 skb->ip_summed = CHECKSUM_NONE;
1692
1693 napi_gro_receive(&adapter->napi, skb);
1694 (*work_done)++;
1695 netdev_dbg(netdev,
1696 "Receive skb->ip_summed: %d length: %d\n",
1697 skb->ip_summed, length);
1698 }
1699 /* return some buffers to hardware, one at a time is too slow */
1700 if (unlikely(cleaned_count >= PCH_GBE_RX_BUFFER_WRITE)) {
1701 pch_gbe_alloc_rx_buffers(adapter, rx_ring,
1702 cleaned_count);
1703 cleaned_count = 0;
1704 }
1705 if (++i == rx_ring->count)
1706 i = 0;
1707 }
1708 rx_ring->next_to_clean = i;
1709 if (cleaned_count)
1710 pch_gbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1711 return cleaned;
1712 }
1713
1714 /**
1715 * pch_gbe_setup_tx_resources - Allocate Tx resources (Descriptors)
1716 * @adapter: Board private structure
1717 * @tx_ring: Tx descriptor ring (for a specific queue) to setup
1718 * Returns:
1719 * 0: Successfully
1720 * Negative value: Failed
1721 */
pch_gbe_setup_tx_resources(struct pch_gbe_adapter * adapter,struct pch_gbe_tx_ring * tx_ring)1722 int pch_gbe_setup_tx_resources(struct pch_gbe_adapter *adapter,
1723 struct pch_gbe_tx_ring *tx_ring)
1724 {
1725 struct pci_dev *pdev = adapter->pdev;
1726 struct pch_gbe_tx_desc *tx_desc;
1727 int size;
1728 int desNo;
1729
1730 size = (int)sizeof(struct pch_gbe_buffer) * tx_ring->count;
1731 tx_ring->buffer_info = vzalloc(size);
1732 if (!tx_ring->buffer_info)
1733 return -ENOMEM;
1734
1735 tx_ring->size = tx_ring->count * (int)sizeof(struct pch_gbe_tx_desc);
1736
1737 tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size,
1738 &tx_ring->dma, GFP_KERNEL);
1739 if (!tx_ring->desc) {
1740 vfree(tx_ring->buffer_info);
1741 return -ENOMEM;
1742 }
1743
1744 tx_ring->next_to_use = 0;
1745 tx_ring->next_to_clean = 0;
1746
1747 for (desNo = 0; desNo < tx_ring->count; desNo++) {
1748 tx_desc = PCH_GBE_TX_DESC(*tx_ring, desNo);
1749 tx_desc->gbec_status = DSC_INIT16;
1750 }
1751 netdev_dbg(adapter->netdev,
1752 "tx_ring->desc = 0x%p tx_ring->dma = 0x%08llx next_to_clean = 0x%08x next_to_use = 0x%08x\n",
1753 tx_ring->desc, (unsigned long long)tx_ring->dma,
1754 tx_ring->next_to_clean, tx_ring->next_to_use);
1755 return 0;
1756 }
1757
1758 /**
1759 * pch_gbe_setup_rx_resources - Allocate Rx resources (Descriptors)
1760 * @adapter: Board private structure
1761 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
1762 * Returns:
1763 * 0: Successfully
1764 * Negative value: Failed
1765 */
pch_gbe_setup_rx_resources(struct pch_gbe_adapter * adapter,struct pch_gbe_rx_ring * rx_ring)1766 int pch_gbe_setup_rx_resources(struct pch_gbe_adapter *adapter,
1767 struct pch_gbe_rx_ring *rx_ring)
1768 {
1769 struct pci_dev *pdev = adapter->pdev;
1770 struct pch_gbe_rx_desc *rx_desc;
1771 int size;
1772 int desNo;
1773
1774 size = (int)sizeof(struct pch_gbe_buffer) * rx_ring->count;
1775 rx_ring->buffer_info = vzalloc(size);
1776 if (!rx_ring->buffer_info)
1777 return -ENOMEM;
1778
1779 rx_ring->size = rx_ring->count * (int)sizeof(struct pch_gbe_rx_desc);
1780 rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size,
1781 &rx_ring->dma, GFP_KERNEL);
1782 if (!rx_ring->desc) {
1783 vfree(rx_ring->buffer_info);
1784 return -ENOMEM;
1785 }
1786 rx_ring->next_to_clean = 0;
1787 rx_ring->next_to_use = 0;
1788 for (desNo = 0; desNo < rx_ring->count; desNo++) {
1789 rx_desc = PCH_GBE_RX_DESC(*rx_ring, desNo);
1790 rx_desc->gbec_status = DSC_INIT16;
1791 }
1792 netdev_dbg(adapter->netdev,
1793 "rx_ring->desc = 0x%p rx_ring->dma = 0x%08llx next_to_clean = 0x%08x next_to_use = 0x%08x\n",
1794 rx_ring->desc, (unsigned long long)rx_ring->dma,
1795 rx_ring->next_to_clean, rx_ring->next_to_use);
1796 return 0;
1797 }
1798
1799 /**
1800 * pch_gbe_free_tx_resources - Free Tx Resources
1801 * @adapter: Board private structure
1802 * @tx_ring: Tx descriptor ring for a specific queue
1803 */
pch_gbe_free_tx_resources(struct pch_gbe_adapter * adapter,struct pch_gbe_tx_ring * tx_ring)1804 void pch_gbe_free_tx_resources(struct pch_gbe_adapter *adapter,
1805 struct pch_gbe_tx_ring *tx_ring)
1806 {
1807 struct pci_dev *pdev = adapter->pdev;
1808
1809 pch_gbe_clean_tx_ring(adapter, tx_ring);
1810 vfree(tx_ring->buffer_info);
1811 tx_ring->buffer_info = NULL;
1812 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1813 tx_ring->desc = NULL;
1814 }
1815
1816 /**
1817 * pch_gbe_free_rx_resources - Free Rx Resources
1818 * @adapter: Board private structure
1819 * @rx_ring: Ring to clean the resources from
1820 */
pch_gbe_free_rx_resources(struct pch_gbe_adapter * adapter,struct pch_gbe_rx_ring * rx_ring)1821 void pch_gbe_free_rx_resources(struct pch_gbe_adapter *adapter,
1822 struct pch_gbe_rx_ring *rx_ring)
1823 {
1824 struct pci_dev *pdev = adapter->pdev;
1825
1826 pch_gbe_clean_rx_ring(adapter, rx_ring);
1827 vfree(rx_ring->buffer_info);
1828 rx_ring->buffer_info = NULL;
1829 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
1830 rx_ring->desc = NULL;
1831 }
1832
1833 /**
1834 * pch_gbe_request_irq - Allocate an interrupt line
1835 * @adapter: Board private structure
1836 * Returns:
1837 * 0: Successfully
1838 * Negative value: Failed
1839 */
pch_gbe_request_irq(struct pch_gbe_adapter * adapter)1840 static int pch_gbe_request_irq(struct pch_gbe_adapter *adapter)
1841 {
1842 struct net_device *netdev = adapter->netdev;
1843 int err;
1844
1845 err = pci_alloc_irq_vectors(adapter->pdev, 1, 1, PCI_IRQ_ALL_TYPES);
1846 if (err < 0)
1847 return err;
1848
1849 adapter->irq = pci_irq_vector(adapter->pdev, 0);
1850
1851 err = request_irq(adapter->irq, &pch_gbe_intr, IRQF_SHARED,
1852 netdev->name, netdev);
1853 if (err)
1854 netdev_err(netdev, "Unable to allocate interrupt Error: %d\n",
1855 err);
1856 netdev_dbg(netdev, "have_msi : %d return : 0x%04x\n",
1857 pci_dev_msi_enabled(adapter->pdev), err);
1858 return err;
1859 }
1860
1861 /**
1862 * pch_gbe_up - Up GbE network device
1863 * @adapter: Board private structure
1864 * Returns:
1865 * 0: Successfully
1866 * Negative value: Failed
1867 */
pch_gbe_up(struct pch_gbe_adapter * adapter)1868 int pch_gbe_up(struct pch_gbe_adapter *adapter)
1869 {
1870 struct net_device *netdev = adapter->netdev;
1871 struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring;
1872 struct pch_gbe_rx_ring *rx_ring = adapter->rx_ring;
1873 int err = -EINVAL;
1874
1875 /* Ensure we have a valid MAC */
1876 if (!is_valid_ether_addr(adapter->hw.mac.addr)) {
1877 netdev_err(netdev, "Error: Invalid MAC address\n");
1878 goto out;
1879 }
1880
1881 /* hardware has been reset, we need to reload some things */
1882 pch_gbe_set_multi(netdev);
1883
1884 pch_gbe_setup_tctl(adapter);
1885 pch_gbe_configure_tx(adapter);
1886 pch_gbe_setup_rctl(adapter);
1887 pch_gbe_configure_rx(adapter);
1888
1889 err = pch_gbe_request_irq(adapter);
1890 if (err) {
1891 netdev_err(netdev,
1892 "Error: can't bring device up - irq request failed\n");
1893 goto out;
1894 }
1895 err = pch_gbe_alloc_rx_buffers_pool(adapter, rx_ring, rx_ring->count);
1896 if (err) {
1897 netdev_err(netdev,
1898 "Error: can't bring device up - alloc rx buffers pool failed\n");
1899 goto freeirq;
1900 }
1901 pch_gbe_alloc_tx_buffers(adapter, tx_ring);
1902 pch_gbe_alloc_rx_buffers(adapter, rx_ring, rx_ring->count);
1903 adapter->tx_queue_len = netdev->tx_queue_len;
1904 pch_gbe_enable_dma_rx(&adapter->hw);
1905 pch_gbe_enable_mac_rx(&adapter->hw);
1906
1907 mod_timer(&adapter->watchdog_timer, jiffies);
1908
1909 napi_enable(&adapter->napi);
1910 pch_gbe_irq_enable(adapter);
1911 netif_start_queue(adapter->netdev);
1912
1913 return 0;
1914
1915 freeirq:
1916 pch_gbe_free_irq(adapter);
1917 out:
1918 return err;
1919 }
1920
1921 /**
1922 * pch_gbe_down - Down GbE network device
1923 * @adapter: Board private structure
1924 */
pch_gbe_down(struct pch_gbe_adapter * adapter)1925 void pch_gbe_down(struct pch_gbe_adapter *adapter)
1926 {
1927 struct net_device *netdev = adapter->netdev;
1928 struct pci_dev *pdev = adapter->pdev;
1929 struct pch_gbe_rx_ring *rx_ring = adapter->rx_ring;
1930
1931 /* signal that we're down so the interrupt handler does not
1932 * reschedule our watchdog timer */
1933 napi_disable(&adapter->napi);
1934 atomic_set(&adapter->irq_sem, 0);
1935
1936 pch_gbe_irq_disable(adapter);
1937 pch_gbe_free_irq(adapter);
1938
1939 del_timer_sync(&adapter->watchdog_timer);
1940
1941 netdev->tx_queue_len = adapter->tx_queue_len;
1942 netif_carrier_off(netdev);
1943 netif_stop_queue(netdev);
1944
1945 if ((pdev->error_state) && (pdev->error_state != pci_channel_io_normal))
1946 pch_gbe_reset(adapter);
1947 pch_gbe_clean_tx_ring(adapter, adapter->tx_ring);
1948 pch_gbe_clean_rx_ring(adapter, adapter->rx_ring);
1949
1950 pci_free_consistent(adapter->pdev, rx_ring->rx_buff_pool_size,
1951 rx_ring->rx_buff_pool, rx_ring->rx_buff_pool_logic);
1952 rx_ring->rx_buff_pool_logic = 0;
1953 rx_ring->rx_buff_pool_size = 0;
1954 rx_ring->rx_buff_pool = NULL;
1955 }
1956
1957 /**
1958 * pch_gbe_sw_init - Initialize general software structures (struct pch_gbe_adapter)
1959 * @adapter: Board private structure to initialize
1960 * Returns:
1961 * 0: Successfully
1962 * Negative value: Failed
1963 */
pch_gbe_sw_init(struct pch_gbe_adapter * adapter)1964 static int pch_gbe_sw_init(struct pch_gbe_adapter *adapter)
1965 {
1966 struct pch_gbe_hw *hw = &adapter->hw;
1967 struct net_device *netdev = adapter->netdev;
1968
1969 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_2048;
1970 hw->mac.max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1971 hw->mac.min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1972 hw->phy.reset_delay_us = PCH_GBE_PHY_RESET_DELAY_US;
1973
1974 if (pch_gbe_alloc_queues(adapter)) {
1975 netdev_err(netdev, "Unable to allocate memory for queues\n");
1976 return -ENOMEM;
1977 }
1978 spin_lock_init(&adapter->hw.miim_lock);
1979 spin_lock_init(&adapter->stats_lock);
1980 spin_lock_init(&adapter->ethtool_lock);
1981 atomic_set(&adapter->irq_sem, 0);
1982 pch_gbe_irq_disable(adapter);
1983
1984 pch_gbe_init_stats(adapter);
1985
1986 netdev_dbg(netdev,
1987 "rx_buffer_len : %d mac.min_frame_size : %d mac.max_frame_size : %d\n",
1988 (u32) adapter->rx_buffer_len,
1989 hw->mac.min_frame_size, hw->mac.max_frame_size);
1990 return 0;
1991 }
1992
1993 /**
1994 * pch_gbe_open - Called when a network interface is made active
1995 * @netdev: Network interface device structure
1996 * Returns:
1997 * 0: Successfully
1998 * Negative value: Failed
1999 */
pch_gbe_open(struct net_device * netdev)2000 static int pch_gbe_open(struct net_device *netdev)
2001 {
2002 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2003 struct pch_gbe_hw *hw = &adapter->hw;
2004 int err;
2005
2006 /* allocate transmit descriptors */
2007 err = pch_gbe_setup_tx_resources(adapter, adapter->tx_ring);
2008 if (err)
2009 goto err_setup_tx;
2010 /* allocate receive descriptors */
2011 err = pch_gbe_setup_rx_resources(adapter, adapter->rx_ring);
2012 if (err)
2013 goto err_setup_rx;
2014 pch_gbe_phy_power_up(hw);
2015 err = pch_gbe_up(adapter);
2016 if (err)
2017 goto err_up;
2018 netdev_dbg(netdev, "Success End\n");
2019 return 0;
2020
2021 err_up:
2022 if (!adapter->wake_up_evt)
2023 pch_gbe_phy_power_down(hw);
2024 pch_gbe_free_rx_resources(adapter, adapter->rx_ring);
2025 err_setup_rx:
2026 pch_gbe_free_tx_resources(adapter, adapter->tx_ring);
2027 err_setup_tx:
2028 pch_gbe_reset(adapter);
2029 netdev_err(netdev, "Error End\n");
2030 return err;
2031 }
2032
2033 /**
2034 * pch_gbe_stop - Disables a network interface
2035 * @netdev: Network interface device structure
2036 * Returns:
2037 * 0: Successfully
2038 */
pch_gbe_stop(struct net_device * netdev)2039 static int pch_gbe_stop(struct net_device *netdev)
2040 {
2041 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2042 struct pch_gbe_hw *hw = &adapter->hw;
2043
2044 pch_gbe_down(adapter);
2045 if (!adapter->wake_up_evt)
2046 pch_gbe_phy_power_down(hw);
2047 pch_gbe_free_tx_resources(adapter, adapter->tx_ring);
2048 pch_gbe_free_rx_resources(adapter, adapter->rx_ring);
2049 return 0;
2050 }
2051
2052 /**
2053 * pch_gbe_xmit_frame - Packet transmitting start
2054 * @skb: Socket buffer structure
2055 * @netdev: Network interface device structure
2056 * Returns:
2057 * - NETDEV_TX_OK: Normal end
2058 * - NETDEV_TX_BUSY: Error end
2059 */
pch_gbe_xmit_frame(struct sk_buff * skb,struct net_device * netdev)2060 static netdev_tx_t pch_gbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2061 {
2062 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2063 struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring;
2064
2065 if (unlikely(!PCH_GBE_DESC_UNUSED(tx_ring))) {
2066 netif_stop_queue(netdev);
2067 netdev_dbg(netdev,
2068 "Return : BUSY next_to use : 0x%08x next_to clean : 0x%08x\n",
2069 tx_ring->next_to_use, tx_ring->next_to_clean);
2070 return NETDEV_TX_BUSY;
2071 }
2072
2073 /* CRC,ITAG no support */
2074 pch_gbe_tx_queue(adapter, tx_ring, skb);
2075 return NETDEV_TX_OK;
2076 }
2077
2078 /**
2079 * pch_gbe_set_multi - Multicast and Promiscuous mode set
2080 * @netdev: Network interface device structure
2081 */
pch_gbe_set_multi(struct net_device * netdev)2082 static void pch_gbe_set_multi(struct net_device *netdev)
2083 {
2084 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2085 struct pch_gbe_hw *hw = &adapter->hw;
2086 struct netdev_hw_addr *ha;
2087 u32 rctl, adrmask;
2088 int mc_count, i;
2089
2090 netdev_dbg(netdev, "netdev->flags : 0x%08x\n", netdev->flags);
2091
2092 /* By default enable address & multicast filtering */
2093 rctl = ioread32(&hw->reg->RX_MODE);
2094 rctl |= PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN;
2095
2096 /* Promiscuous mode disables all hardware address filtering */
2097 if (netdev->flags & IFF_PROMISC)
2098 rctl &= ~(PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN);
2099
2100 /* If we want to monitor more multicast addresses than the hardware can
2101 * support then disable hardware multicast filtering.
2102 */
2103 mc_count = netdev_mc_count(netdev);
2104 if ((netdev->flags & IFF_ALLMULTI) || mc_count >= PCH_GBE_MAR_ENTRIES)
2105 rctl &= ~PCH_GBE_MLT_FIL_EN;
2106
2107 iowrite32(rctl, &hw->reg->RX_MODE);
2108
2109 /* If we're not using multicast filtering then there's no point
2110 * configuring the unused MAC address registers.
2111 */
2112 if (!(rctl & PCH_GBE_MLT_FIL_EN))
2113 return;
2114
2115 /* Load the first set of multicast addresses into MAC address registers
2116 * for use by hardware filtering.
2117 */
2118 i = 1;
2119 netdev_for_each_mc_addr(ha, netdev)
2120 pch_gbe_mac_mar_set(hw, ha->addr, i++);
2121
2122 /* If there are spare MAC registers, mask & clear them */
2123 for (; i < PCH_GBE_MAR_ENTRIES; i++) {
2124 /* Clear MAC address mask */
2125 adrmask = ioread32(&hw->reg->ADDR_MASK);
2126 iowrite32(adrmask | BIT(i), &hw->reg->ADDR_MASK);
2127 /* wait busy */
2128 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
2129 /* Clear MAC address */
2130 iowrite32(0, &hw->reg->mac_adr[i].high);
2131 iowrite32(0, &hw->reg->mac_adr[i].low);
2132 }
2133
2134 netdev_dbg(netdev,
2135 "RX_MODE reg(check bit31,30 ADD,MLT) : 0x%08x netdev->mc_count : 0x%08x\n",
2136 ioread32(&hw->reg->RX_MODE), mc_count);
2137 }
2138
2139 /**
2140 * pch_gbe_set_mac - Change the Ethernet Address of the NIC
2141 * @netdev: Network interface device structure
2142 * @addr: Pointer to an address structure
2143 * Returns:
2144 * 0: Successfully
2145 * -EADDRNOTAVAIL: Failed
2146 */
pch_gbe_set_mac(struct net_device * netdev,void * addr)2147 static int pch_gbe_set_mac(struct net_device *netdev, void *addr)
2148 {
2149 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2150 struct sockaddr *skaddr = addr;
2151 int ret_val;
2152
2153 if (!is_valid_ether_addr(skaddr->sa_data)) {
2154 ret_val = -EADDRNOTAVAIL;
2155 } else {
2156 memcpy(netdev->dev_addr, skaddr->sa_data, netdev->addr_len);
2157 memcpy(adapter->hw.mac.addr, skaddr->sa_data, netdev->addr_len);
2158 pch_gbe_mac_mar_set(&adapter->hw, adapter->hw.mac.addr, 0);
2159 ret_val = 0;
2160 }
2161 netdev_dbg(netdev, "ret_val : 0x%08x\n", ret_val);
2162 netdev_dbg(netdev, "dev_addr : %pM\n", netdev->dev_addr);
2163 netdev_dbg(netdev, "mac_addr : %pM\n", adapter->hw.mac.addr);
2164 netdev_dbg(netdev, "MAC_ADR1AB reg : 0x%08x 0x%08x\n",
2165 ioread32(&adapter->hw.reg->mac_adr[0].high),
2166 ioread32(&adapter->hw.reg->mac_adr[0].low));
2167 return ret_val;
2168 }
2169
2170 /**
2171 * pch_gbe_change_mtu - Change the Maximum Transfer Unit
2172 * @netdev: Network interface device structure
2173 * @new_mtu: New value for maximum frame size
2174 * Returns:
2175 * 0: Successfully
2176 * -EINVAL: Failed
2177 */
pch_gbe_change_mtu(struct net_device * netdev,int new_mtu)2178 static int pch_gbe_change_mtu(struct net_device *netdev, int new_mtu)
2179 {
2180 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2181 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
2182 unsigned long old_rx_buffer_len = adapter->rx_buffer_len;
2183 int err;
2184
2185 if (max_frame <= PCH_GBE_FRAME_SIZE_2048)
2186 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_2048;
2187 else if (max_frame <= PCH_GBE_FRAME_SIZE_4096)
2188 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_4096;
2189 else if (max_frame <= PCH_GBE_FRAME_SIZE_8192)
2190 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_8192;
2191 else
2192 adapter->rx_buffer_len = PCH_GBE_MAX_RX_BUFFER_SIZE;
2193
2194 if (netif_running(netdev)) {
2195 pch_gbe_down(adapter);
2196 err = pch_gbe_up(adapter);
2197 if (err) {
2198 adapter->rx_buffer_len = old_rx_buffer_len;
2199 pch_gbe_up(adapter);
2200 return err;
2201 } else {
2202 netdev->mtu = new_mtu;
2203 adapter->hw.mac.max_frame_size = max_frame;
2204 }
2205 } else {
2206 pch_gbe_reset(adapter);
2207 netdev->mtu = new_mtu;
2208 adapter->hw.mac.max_frame_size = max_frame;
2209 }
2210
2211 netdev_dbg(netdev,
2212 "max_frame : %d rx_buffer_len : %d mtu : %d max_frame_size : %d\n",
2213 max_frame, (u32) adapter->rx_buffer_len, netdev->mtu,
2214 adapter->hw.mac.max_frame_size);
2215 return 0;
2216 }
2217
2218 /**
2219 * pch_gbe_set_features - Reset device after features changed
2220 * @netdev: Network interface device structure
2221 * @features: New features
2222 * Returns:
2223 * 0: HW state updated successfully
2224 */
pch_gbe_set_features(struct net_device * netdev,netdev_features_t features)2225 static int pch_gbe_set_features(struct net_device *netdev,
2226 netdev_features_t features)
2227 {
2228 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2229 netdev_features_t changed = features ^ netdev->features;
2230
2231 if (!(changed & NETIF_F_RXCSUM))
2232 return 0;
2233
2234 if (netif_running(netdev))
2235 pch_gbe_reinit_locked(adapter);
2236 else
2237 pch_gbe_reset(adapter);
2238
2239 return 0;
2240 }
2241
2242 /**
2243 * pch_gbe_ioctl - Controls register through a MII interface
2244 * @netdev: Network interface device structure
2245 * @ifr: Pointer to ifr structure
2246 * @cmd: Control command
2247 * Returns:
2248 * 0: Successfully
2249 * Negative value: Failed
2250 */
pch_gbe_ioctl(struct net_device * netdev,struct ifreq * ifr,int cmd)2251 static int pch_gbe_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2252 {
2253 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2254
2255 netdev_dbg(netdev, "cmd : 0x%04x\n", cmd);
2256
2257 if (cmd == SIOCSHWTSTAMP)
2258 return hwtstamp_ioctl(netdev, ifr, cmd);
2259
2260 return generic_mii_ioctl(&adapter->mii, if_mii(ifr), cmd, NULL);
2261 }
2262
2263 /**
2264 * pch_gbe_tx_timeout - Respond to a Tx Hang
2265 * @netdev: Network interface device structure
2266 * @txqueue: index of hanging queue
2267 */
pch_gbe_tx_timeout(struct net_device * netdev,unsigned int txqueue)2268 static void pch_gbe_tx_timeout(struct net_device *netdev, unsigned int txqueue)
2269 {
2270 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2271
2272 /* Do the reset outside of interrupt context */
2273 adapter->stats.tx_timeout_count++;
2274 schedule_work(&adapter->reset_task);
2275 }
2276
2277 /**
2278 * pch_gbe_napi_poll - NAPI receive and transfer polling callback
2279 * @napi: Pointer of polling device struct
2280 * @budget: The maximum number of a packet
2281 * Returns:
2282 * false: Exit the polling mode
2283 * true: Continue the polling mode
2284 */
pch_gbe_napi_poll(struct napi_struct * napi,int budget)2285 static int pch_gbe_napi_poll(struct napi_struct *napi, int budget)
2286 {
2287 struct pch_gbe_adapter *adapter =
2288 container_of(napi, struct pch_gbe_adapter, napi);
2289 int work_done = 0;
2290 bool poll_end_flag = false;
2291 bool cleaned = false;
2292
2293 netdev_dbg(adapter->netdev, "budget : %d\n", budget);
2294
2295 pch_gbe_clean_rx(adapter, adapter->rx_ring, &work_done, budget);
2296 cleaned = pch_gbe_clean_tx(adapter, adapter->tx_ring);
2297
2298 if (cleaned)
2299 work_done = budget;
2300 /* If no Tx and not enough Rx work done,
2301 * exit the polling mode
2302 */
2303 if (work_done < budget)
2304 poll_end_flag = true;
2305
2306 if (poll_end_flag) {
2307 napi_complete_done(napi, work_done);
2308 pch_gbe_irq_enable(adapter);
2309 }
2310
2311 if (adapter->rx_stop_flag) {
2312 adapter->rx_stop_flag = false;
2313 pch_gbe_enable_dma_rx(&adapter->hw);
2314 }
2315
2316 netdev_dbg(adapter->netdev,
2317 "poll_end_flag : %d work_done : %d budget : %d\n",
2318 poll_end_flag, work_done, budget);
2319
2320 return work_done;
2321 }
2322
2323 #ifdef CONFIG_NET_POLL_CONTROLLER
2324 /**
2325 * pch_gbe_netpoll - Used by things like netconsole to send skbs
2326 * @netdev: Network interface device structure
2327 */
pch_gbe_netpoll(struct net_device * netdev)2328 static void pch_gbe_netpoll(struct net_device *netdev)
2329 {
2330 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2331
2332 disable_irq(adapter->irq);
2333 pch_gbe_intr(adapter->irq, netdev);
2334 enable_irq(adapter->irq);
2335 }
2336 #endif
2337
2338 static const struct net_device_ops pch_gbe_netdev_ops = {
2339 .ndo_open = pch_gbe_open,
2340 .ndo_stop = pch_gbe_stop,
2341 .ndo_start_xmit = pch_gbe_xmit_frame,
2342 .ndo_set_mac_address = pch_gbe_set_mac,
2343 .ndo_tx_timeout = pch_gbe_tx_timeout,
2344 .ndo_change_mtu = pch_gbe_change_mtu,
2345 .ndo_set_features = pch_gbe_set_features,
2346 .ndo_do_ioctl = pch_gbe_ioctl,
2347 .ndo_set_rx_mode = pch_gbe_set_multi,
2348 #ifdef CONFIG_NET_POLL_CONTROLLER
2349 .ndo_poll_controller = pch_gbe_netpoll,
2350 #endif
2351 };
2352
pch_gbe_io_error_detected(struct pci_dev * pdev,pci_channel_state_t state)2353 static pci_ers_result_t pch_gbe_io_error_detected(struct pci_dev *pdev,
2354 pci_channel_state_t state)
2355 {
2356 struct net_device *netdev = pci_get_drvdata(pdev);
2357 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2358
2359 netif_device_detach(netdev);
2360 if (netif_running(netdev))
2361 pch_gbe_down(adapter);
2362 pci_disable_device(pdev);
2363 /* Request a slot slot reset. */
2364 return PCI_ERS_RESULT_NEED_RESET;
2365 }
2366
pch_gbe_io_slot_reset(struct pci_dev * pdev)2367 static pci_ers_result_t pch_gbe_io_slot_reset(struct pci_dev *pdev)
2368 {
2369 struct net_device *netdev = pci_get_drvdata(pdev);
2370 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2371 struct pch_gbe_hw *hw = &adapter->hw;
2372
2373 if (pci_enable_device(pdev)) {
2374 netdev_err(netdev, "Cannot re-enable PCI device after reset\n");
2375 return PCI_ERS_RESULT_DISCONNECT;
2376 }
2377 pci_set_master(pdev);
2378 pci_enable_wake(pdev, PCI_D0, 0);
2379 pch_gbe_phy_power_up(hw);
2380 pch_gbe_reset(adapter);
2381 /* Clear wake up status */
2382 pch_gbe_mac_set_wol_event(hw, 0);
2383
2384 return PCI_ERS_RESULT_RECOVERED;
2385 }
2386
pch_gbe_io_resume(struct pci_dev * pdev)2387 static void pch_gbe_io_resume(struct pci_dev *pdev)
2388 {
2389 struct net_device *netdev = pci_get_drvdata(pdev);
2390 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2391
2392 if (netif_running(netdev)) {
2393 if (pch_gbe_up(adapter)) {
2394 netdev_dbg(netdev,
2395 "can't bring device back up after reset\n");
2396 return;
2397 }
2398 }
2399 netif_device_attach(netdev);
2400 }
2401
__pch_gbe_suspend(struct pci_dev * pdev)2402 static int __pch_gbe_suspend(struct pci_dev *pdev)
2403 {
2404 struct net_device *netdev = pci_get_drvdata(pdev);
2405 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2406 struct pch_gbe_hw *hw = &adapter->hw;
2407 u32 wufc = adapter->wake_up_evt;
2408 int retval = 0;
2409
2410 netif_device_detach(netdev);
2411 if (netif_running(netdev))
2412 pch_gbe_down(adapter);
2413 if (wufc) {
2414 pch_gbe_set_multi(netdev);
2415 pch_gbe_setup_rctl(adapter);
2416 pch_gbe_configure_rx(adapter);
2417 pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed,
2418 hw->mac.link_duplex);
2419 pch_gbe_set_mode(adapter, hw->mac.link_speed,
2420 hw->mac.link_duplex);
2421 pch_gbe_mac_set_wol_event(hw, wufc);
2422 pci_disable_device(pdev);
2423 } else {
2424 pch_gbe_phy_power_down(hw);
2425 pch_gbe_mac_set_wol_event(hw, wufc);
2426 pci_disable_device(pdev);
2427 }
2428 return retval;
2429 }
2430
2431 #ifdef CONFIG_PM
pch_gbe_suspend(struct device * device)2432 static int pch_gbe_suspend(struct device *device)
2433 {
2434 struct pci_dev *pdev = to_pci_dev(device);
2435
2436 return __pch_gbe_suspend(pdev);
2437 }
2438
pch_gbe_resume(struct device * device)2439 static int pch_gbe_resume(struct device *device)
2440 {
2441 struct pci_dev *pdev = to_pci_dev(device);
2442 struct net_device *netdev = pci_get_drvdata(pdev);
2443 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2444 struct pch_gbe_hw *hw = &adapter->hw;
2445 u32 err;
2446
2447 err = pci_enable_device(pdev);
2448 if (err) {
2449 netdev_err(netdev, "Cannot enable PCI device from suspend\n");
2450 return err;
2451 }
2452 pci_set_master(pdev);
2453 pch_gbe_phy_power_up(hw);
2454 pch_gbe_reset(adapter);
2455 /* Clear wake on lan control and status */
2456 pch_gbe_mac_set_wol_event(hw, 0);
2457
2458 if (netif_running(netdev))
2459 pch_gbe_up(adapter);
2460 netif_device_attach(netdev);
2461
2462 return 0;
2463 }
2464 #endif /* CONFIG_PM */
2465
pch_gbe_shutdown(struct pci_dev * pdev)2466 static void pch_gbe_shutdown(struct pci_dev *pdev)
2467 {
2468 __pch_gbe_suspend(pdev);
2469 if (system_state == SYSTEM_POWER_OFF) {
2470 pci_wake_from_d3(pdev, true);
2471 pci_set_power_state(pdev, PCI_D3hot);
2472 }
2473 }
2474
pch_gbe_remove(struct pci_dev * pdev)2475 static void pch_gbe_remove(struct pci_dev *pdev)
2476 {
2477 struct net_device *netdev = pci_get_drvdata(pdev);
2478 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2479
2480 cancel_work_sync(&adapter->reset_task);
2481 unregister_netdev(netdev);
2482
2483 pch_gbe_phy_hw_reset(&adapter->hw);
2484
2485 free_netdev(netdev);
2486 }
2487
pch_gbe_probe(struct pci_dev * pdev,const struct pci_device_id * pci_id)2488 static int pch_gbe_probe(struct pci_dev *pdev,
2489 const struct pci_device_id *pci_id)
2490 {
2491 struct net_device *netdev;
2492 struct pch_gbe_adapter *adapter;
2493 int ret;
2494
2495 ret = pcim_enable_device(pdev);
2496 if (ret)
2497 return ret;
2498
2499 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
2500 || pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
2501 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2502 if (ret) {
2503 ret = pci_set_consistent_dma_mask(pdev,
2504 DMA_BIT_MASK(32));
2505 if (ret) {
2506 dev_err(&pdev->dev, "ERR: No usable DMA "
2507 "configuration, aborting\n");
2508 return ret;
2509 }
2510 }
2511 }
2512
2513 ret = pcim_iomap_regions(pdev, 1 << PCH_GBE_PCI_BAR, pci_name(pdev));
2514 if (ret) {
2515 dev_err(&pdev->dev,
2516 "ERR: Can't reserve PCI I/O and memory resources\n");
2517 return ret;
2518 }
2519 pci_set_master(pdev);
2520
2521 netdev = alloc_etherdev((int)sizeof(struct pch_gbe_adapter));
2522 if (!netdev)
2523 return -ENOMEM;
2524 SET_NETDEV_DEV(netdev, &pdev->dev);
2525
2526 pci_set_drvdata(pdev, netdev);
2527 adapter = netdev_priv(netdev);
2528 adapter->netdev = netdev;
2529 adapter->pdev = pdev;
2530 adapter->hw.back = adapter;
2531 adapter->hw.reg = pcim_iomap_table(pdev)[PCH_GBE_PCI_BAR];
2532
2533 adapter->pdata = (struct pch_gbe_privdata *)pci_id->driver_data;
2534 if (adapter->pdata && adapter->pdata->platform_init) {
2535 ret = adapter->pdata->platform_init(pdev);
2536 if (ret)
2537 goto err_free_netdev;
2538 }
2539
2540 adapter->ptp_pdev =
2541 pci_get_domain_bus_and_slot(pci_domain_nr(adapter->pdev->bus),
2542 adapter->pdev->bus->number,
2543 PCI_DEVFN(12, 4));
2544
2545 netdev->netdev_ops = &pch_gbe_netdev_ops;
2546 netdev->watchdog_timeo = PCH_GBE_WATCHDOG_PERIOD;
2547 netif_napi_add(netdev, &adapter->napi,
2548 pch_gbe_napi_poll, PCH_GBE_RX_WEIGHT);
2549 netdev->hw_features = NETIF_F_RXCSUM |
2550 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2551 netdev->features = netdev->hw_features;
2552 pch_gbe_set_ethtool_ops(netdev);
2553
2554 /* MTU range: 46 - 10300 */
2555 netdev->min_mtu = ETH_ZLEN - ETH_HLEN;
2556 netdev->max_mtu = PCH_GBE_MAX_JUMBO_FRAME_SIZE -
2557 (ETH_HLEN + ETH_FCS_LEN);
2558
2559 pch_gbe_mac_load_mac_addr(&adapter->hw);
2560 pch_gbe_mac_reset_hw(&adapter->hw);
2561
2562 /* setup the private structure */
2563 ret = pch_gbe_sw_init(adapter);
2564 if (ret)
2565 goto err_free_netdev;
2566
2567 /* Initialize PHY */
2568 ret = pch_gbe_init_phy(adapter);
2569 if (ret) {
2570 dev_err(&pdev->dev, "PHY initialize error\n");
2571 goto err_free_adapter;
2572 }
2573
2574 /* Read the MAC address. and store to the private data */
2575 ret = pch_gbe_mac_read_mac_addr(&adapter->hw);
2576 if (ret) {
2577 dev_err(&pdev->dev, "MAC address Read Error\n");
2578 goto err_free_adapter;
2579 }
2580
2581 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
2582 if (!is_valid_ether_addr(netdev->dev_addr)) {
2583 /*
2584 * If the MAC is invalid (or just missing), display a warning
2585 * but do not abort setting up the device. pch_gbe_up will
2586 * prevent the interface from being brought up until a valid MAC
2587 * is set.
2588 */
2589 dev_err(&pdev->dev, "Invalid MAC address, "
2590 "interface disabled.\n");
2591 }
2592 timer_setup(&adapter->watchdog_timer, pch_gbe_watchdog, 0);
2593
2594 INIT_WORK(&adapter->reset_task, pch_gbe_reset_task);
2595
2596 pch_gbe_check_options(adapter);
2597
2598 /* initialize the wol settings based on the eeprom settings */
2599 adapter->wake_up_evt = PCH_GBE_WL_INIT_SETTING;
2600 dev_info(&pdev->dev, "MAC address : %pM\n", netdev->dev_addr);
2601
2602 /* reset the hardware with the new settings */
2603 pch_gbe_reset(adapter);
2604
2605 ret = register_netdev(netdev);
2606 if (ret)
2607 goto err_free_adapter;
2608 /* tell the stack to leave us alone until pch_gbe_open() is called */
2609 netif_carrier_off(netdev);
2610 netif_stop_queue(netdev);
2611
2612 dev_dbg(&pdev->dev, "PCH Network Connection\n");
2613
2614 /* Disable hibernation on certain platforms */
2615 if (adapter->pdata && adapter->pdata->phy_disable_hibernate)
2616 pch_gbe_phy_disable_hibernate(&adapter->hw);
2617
2618 device_set_wakeup_enable(&pdev->dev, 1);
2619 return 0;
2620
2621 err_free_adapter:
2622 pch_gbe_phy_hw_reset(&adapter->hw);
2623 err_free_netdev:
2624 free_netdev(netdev);
2625 return ret;
2626 }
2627
2628 /* The AR803X PHY on the MinnowBoard requires a physical pin to be toggled to
2629 * ensure it is awake for probe and init. Request the line and reset the PHY.
2630 */
pch_gbe_minnow_platform_init(struct pci_dev * pdev)2631 static int pch_gbe_minnow_platform_init(struct pci_dev *pdev)
2632 {
2633 unsigned long flags = GPIOF_OUT_INIT_HIGH;
2634 unsigned gpio = MINNOW_PHY_RESET_GPIO;
2635 int ret;
2636
2637 ret = devm_gpio_request_one(&pdev->dev, gpio, flags,
2638 "minnow_phy_reset");
2639 if (ret) {
2640 dev_err(&pdev->dev,
2641 "ERR: Can't request PHY reset GPIO line '%d'\n", gpio);
2642 return ret;
2643 }
2644
2645 gpio_set_value(gpio, 0);
2646 usleep_range(1250, 1500);
2647 gpio_set_value(gpio, 1);
2648 usleep_range(1250, 1500);
2649
2650 return ret;
2651 }
2652
2653 static struct pch_gbe_privdata pch_gbe_minnow_privdata = {
2654 .phy_tx_clk_delay = true,
2655 .phy_disable_hibernate = true,
2656 .platform_init = pch_gbe_minnow_platform_init,
2657 };
2658
2659 static const struct pci_device_id pch_gbe_pcidev_id[] = {
2660 {.vendor = PCI_VENDOR_ID_INTEL,
2661 .device = PCI_DEVICE_ID_INTEL_IOH1_GBE,
2662 .subvendor = PCI_VENDOR_ID_CIRCUITCO,
2663 .subdevice = PCI_SUBSYSTEM_ID_CIRCUITCO_MINNOWBOARD,
2664 .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2665 .class_mask = (0xFFFF00),
2666 .driver_data = (kernel_ulong_t)&pch_gbe_minnow_privdata
2667 },
2668 {.vendor = PCI_VENDOR_ID_INTEL,
2669 .device = PCI_DEVICE_ID_INTEL_IOH1_GBE,
2670 .subvendor = PCI_ANY_ID,
2671 .subdevice = PCI_ANY_ID,
2672 .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2673 .class_mask = (0xFFFF00)
2674 },
2675 {.vendor = PCI_VENDOR_ID_ROHM,
2676 .device = PCI_DEVICE_ID_ROHM_ML7223_GBE,
2677 .subvendor = PCI_ANY_ID,
2678 .subdevice = PCI_ANY_ID,
2679 .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2680 .class_mask = (0xFFFF00)
2681 },
2682 {.vendor = PCI_VENDOR_ID_ROHM,
2683 .device = PCI_DEVICE_ID_ROHM_ML7831_GBE,
2684 .subvendor = PCI_ANY_ID,
2685 .subdevice = PCI_ANY_ID,
2686 .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2687 .class_mask = (0xFFFF00)
2688 },
2689 /* required last entry */
2690 {0}
2691 };
2692
2693 #ifdef CONFIG_PM
2694 static const struct dev_pm_ops pch_gbe_pm_ops = {
2695 .suspend = pch_gbe_suspend,
2696 .resume = pch_gbe_resume,
2697 .freeze = pch_gbe_suspend,
2698 .thaw = pch_gbe_resume,
2699 .poweroff = pch_gbe_suspend,
2700 .restore = pch_gbe_resume,
2701 };
2702 #endif
2703
2704 static const struct pci_error_handlers pch_gbe_err_handler = {
2705 .error_detected = pch_gbe_io_error_detected,
2706 .slot_reset = pch_gbe_io_slot_reset,
2707 .resume = pch_gbe_io_resume
2708 };
2709
2710 static struct pci_driver pch_gbe_driver = {
2711 .name = KBUILD_MODNAME,
2712 .id_table = pch_gbe_pcidev_id,
2713 .probe = pch_gbe_probe,
2714 .remove = pch_gbe_remove,
2715 #ifdef CONFIG_PM
2716 .driver.pm = &pch_gbe_pm_ops,
2717 #endif
2718 .shutdown = pch_gbe_shutdown,
2719 .err_handler = &pch_gbe_err_handler
2720 };
2721 module_pci_driver(pch_gbe_driver);
2722
2723 MODULE_DESCRIPTION("EG20T PCH Gigabit ethernet Driver");
2724 MODULE_AUTHOR("LAPIS SEMICONDUCTOR, <tshimizu818@gmail.com>");
2725 MODULE_LICENSE("GPL");
2726 MODULE_VERSION(DRV_VERSION);
2727 MODULE_DEVICE_TABLE(pci, pch_gbe_pcidev_id);
2728
2729 /* pch_gbe_main.c */
2730