1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2020, Intel Corporation
3 */
4
5 #include <linux/clk-provider.h>
6 #include <linux/pci.h>
7 #include <linux/dmi.h>
8 #include "dwmac-intel.h"
9 #include "dwmac4.h"
10 #include "stmmac.h"
11
12 struct intel_priv_data {
13 int mdio_adhoc_addr; /* mdio address for serdes & etc */
14 };
15
16 /* This struct is used to associate PCI Function of MAC controller on a board,
17 * discovered via DMI, with the address of PHY connected to the MAC. The
18 * negative value of the address means that MAC controller is not connected
19 * with PHY.
20 */
21 struct stmmac_pci_func_data {
22 unsigned int func;
23 int phy_addr;
24 };
25
26 struct stmmac_pci_dmi_data {
27 const struct stmmac_pci_func_data *func;
28 size_t nfuncs;
29 };
30
31 struct stmmac_pci_info {
32 int (*setup)(struct pci_dev *pdev, struct plat_stmmacenet_data *plat);
33 };
34
stmmac_pci_find_phy_addr(struct pci_dev * pdev,const struct dmi_system_id * dmi_list)35 static int stmmac_pci_find_phy_addr(struct pci_dev *pdev,
36 const struct dmi_system_id *dmi_list)
37 {
38 const struct stmmac_pci_func_data *func_data;
39 const struct stmmac_pci_dmi_data *dmi_data;
40 const struct dmi_system_id *dmi_id;
41 int func = PCI_FUNC(pdev->devfn);
42 size_t n;
43
44 dmi_id = dmi_first_match(dmi_list);
45 if (!dmi_id)
46 return -ENODEV;
47
48 dmi_data = dmi_id->driver_data;
49 func_data = dmi_data->func;
50
51 for (n = 0; n < dmi_data->nfuncs; n++, func_data++)
52 if (func_data->func == func)
53 return func_data->phy_addr;
54
55 return -ENODEV;
56 }
57
serdes_status_poll(struct stmmac_priv * priv,int phyaddr,int phyreg,u32 mask,u32 val)58 static int serdes_status_poll(struct stmmac_priv *priv, int phyaddr,
59 int phyreg, u32 mask, u32 val)
60 {
61 unsigned int retries = 10;
62 int val_rd;
63
64 do {
65 val_rd = mdiobus_read(priv->mii, phyaddr, phyreg);
66 if ((val_rd & mask) == (val & mask))
67 return 0;
68 udelay(POLL_DELAY_US);
69 } while (--retries);
70
71 return -ETIMEDOUT;
72 }
73
intel_serdes_powerup(struct net_device * ndev,void * priv_data)74 static int intel_serdes_powerup(struct net_device *ndev, void *priv_data)
75 {
76 struct intel_priv_data *intel_priv = priv_data;
77 struct stmmac_priv *priv = netdev_priv(ndev);
78 int serdes_phy_addr = 0;
79 u32 data = 0;
80
81 if (!intel_priv->mdio_adhoc_addr)
82 return 0;
83
84 serdes_phy_addr = intel_priv->mdio_adhoc_addr;
85
86 /* assert clk_req */
87 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
88 data |= SERDES_PLL_CLK;
89 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
90
91 /* check for clk_ack assertion */
92 data = serdes_status_poll(priv, serdes_phy_addr,
93 SERDES_GSR0,
94 SERDES_PLL_CLK,
95 SERDES_PLL_CLK);
96
97 if (data) {
98 dev_err(priv->device, "Serdes PLL clk request timeout\n");
99 return data;
100 }
101
102 /* assert lane reset */
103 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
104 data |= SERDES_RST;
105 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
106
107 /* check for assert lane reset reflection */
108 data = serdes_status_poll(priv, serdes_phy_addr,
109 SERDES_GSR0,
110 SERDES_RST,
111 SERDES_RST);
112
113 if (data) {
114 dev_err(priv->device, "Serdes assert lane reset timeout\n");
115 return data;
116 }
117
118 /* move power state to P0 */
119 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
120
121 data &= ~SERDES_PWR_ST_MASK;
122 data |= SERDES_PWR_ST_P0 << SERDES_PWR_ST_SHIFT;
123
124 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
125
126 /* Check for P0 state */
127 data = serdes_status_poll(priv, serdes_phy_addr,
128 SERDES_GSR0,
129 SERDES_PWR_ST_MASK,
130 SERDES_PWR_ST_P0 << SERDES_PWR_ST_SHIFT);
131
132 if (data) {
133 dev_err(priv->device, "Serdes power state P0 timeout.\n");
134 return data;
135 }
136
137 return 0;
138 }
139
intel_serdes_powerdown(struct net_device * ndev,void * intel_data)140 static void intel_serdes_powerdown(struct net_device *ndev, void *intel_data)
141 {
142 struct intel_priv_data *intel_priv = intel_data;
143 struct stmmac_priv *priv = netdev_priv(ndev);
144 int serdes_phy_addr = 0;
145 u32 data = 0;
146
147 if (!intel_priv->mdio_adhoc_addr)
148 return;
149
150 serdes_phy_addr = intel_priv->mdio_adhoc_addr;
151
152 /* move power state to P3 */
153 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
154
155 data &= ~SERDES_PWR_ST_MASK;
156 data |= SERDES_PWR_ST_P3 << SERDES_PWR_ST_SHIFT;
157
158 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
159
160 /* Check for P3 state */
161 data = serdes_status_poll(priv, serdes_phy_addr,
162 SERDES_GSR0,
163 SERDES_PWR_ST_MASK,
164 SERDES_PWR_ST_P3 << SERDES_PWR_ST_SHIFT);
165
166 if (data) {
167 dev_err(priv->device, "Serdes power state P3 timeout\n");
168 return;
169 }
170
171 /* de-assert clk_req */
172 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
173 data &= ~SERDES_PLL_CLK;
174 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
175
176 /* check for clk_ack de-assert */
177 data = serdes_status_poll(priv, serdes_phy_addr,
178 SERDES_GSR0,
179 SERDES_PLL_CLK,
180 (u32)~SERDES_PLL_CLK);
181
182 if (data) {
183 dev_err(priv->device, "Serdes PLL clk de-assert timeout\n");
184 return;
185 }
186
187 /* de-assert lane reset */
188 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
189 data &= ~SERDES_RST;
190 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
191
192 /* check for de-assert lane reset reflection */
193 data = serdes_status_poll(priv, serdes_phy_addr,
194 SERDES_GSR0,
195 SERDES_RST,
196 (u32)~SERDES_RST);
197
198 if (data) {
199 dev_err(priv->device, "Serdes de-assert lane reset timeout\n");
200 return;
201 }
202 }
203
common_default_data(struct plat_stmmacenet_data * plat)204 static void common_default_data(struct plat_stmmacenet_data *plat)
205 {
206 plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */
207 plat->has_gmac = 1;
208 plat->force_sf_dma_mode = 1;
209
210 plat->mdio_bus_data->needs_reset = true;
211
212 /* Set default value for multicast hash bins */
213 plat->multicast_filter_bins = HASH_TABLE_SIZE;
214
215 /* Set default value for unicast filter entries */
216 plat->unicast_filter_entries = 1;
217
218 /* Set the maxmtu to a default of JUMBO_LEN */
219 plat->maxmtu = JUMBO_LEN;
220
221 /* Set default number of RX and TX queues to use */
222 plat->tx_queues_to_use = 1;
223 plat->rx_queues_to_use = 1;
224
225 /* Disable Priority config by default */
226 plat->tx_queues_cfg[0].use_prio = false;
227 plat->rx_queues_cfg[0].use_prio = false;
228
229 /* Disable RX queues routing by default */
230 plat->rx_queues_cfg[0].pkt_route = 0x0;
231 }
232
intel_mgbe_common_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)233 static int intel_mgbe_common_data(struct pci_dev *pdev,
234 struct plat_stmmacenet_data *plat)
235 {
236 char clk_name[20];
237 int ret;
238 int i;
239
240 plat->phy_addr = -1;
241 plat->clk_csr = 5;
242 plat->has_gmac = 0;
243 plat->has_gmac4 = 1;
244 plat->force_sf_dma_mode = 0;
245 plat->tso_en = 1;
246
247 plat->rx_sched_algorithm = MTL_RX_ALGORITHM_SP;
248
249 for (i = 0; i < plat->rx_queues_to_use; i++) {
250 plat->rx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB;
251 plat->rx_queues_cfg[i].chan = i;
252
253 /* Disable Priority config by default */
254 plat->rx_queues_cfg[i].use_prio = false;
255
256 /* Disable RX queues routing by default */
257 plat->rx_queues_cfg[i].pkt_route = 0x0;
258 }
259
260 for (i = 0; i < plat->tx_queues_to_use; i++) {
261 plat->tx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB;
262
263 /* Disable Priority config by default */
264 plat->tx_queues_cfg[i].use_prio = false;
265 }
266
267 /* FIFO size is 4096 bytes for 1 tx/rx queue */
268 plat->tx_fifo_size = plat->tx_queues_to_use * 4096;
269 plat->rx_fifo_size = plat->rx_queues_to_use * 4096;
270
271 plat->tx_sched_algorithm = MTL_TX_ALGORITHM_WRR;
272 plat->tx_queues_cfg[0].weight = 0x09;
273 plat->tx_queues_cfg[1].weight = 0x0A;
274 plat->tx_queues_cfg[2].weight = 0x0B;
275 plat->tx_queues_cfg[3].weight = 0x0C;
276 plat->tx_queues_cfg[4].weight = 0x0D;
277 plat->tx_queues_cfg[5].weight = 0x0E;
278 plat->tx_queues_cfg[6].weight = 0x0F;
279 plat->tx_queues_cfg[7].weight = 0x10;
280
281 plat->dma_cfg->pbl = 32;
282 plat->dma_cfg->pblx8 = true;
283 plat->dma_cfg->fixed_burst = 0;
284 plat->dma_cfg->mixed_burst = 0;
285 plat->dma_cfg->aal = 0;
286
287 plat->axi = devm_kzalloc(&pdev->dev, sizeof(*plat->axi),
288 GFP_KERNEL);
289 if (!plat->axi)
290 return -ENOMEM;
291
292 plat->axi->axi_lpi_en = 0;
293 plat->axi->axi_xit_frm = 0;
294 plat->axi->axi_wr_osr_lmt = 1;
295 plat->axi->axi_rd_osr_lmt = 1;
296 plat->axi->axi_blen[0] = 4;
297 plat->axi->axi_blen[1] = 8;
298 plat->axi->axi_blen[2] = 16;
299
300 plat->ptp_max_adj = plat->clk_ptp_rate;
301 plat->eee_usecs_rate = plat->clk_ptp_rate;
302
303 /* Set system clock */
304 sprintf(clk_name, "%s-%s", "stmmac", pci_name(pdev));
305
306 plat->stmmac_clk = clk_register_fixed_rate(&pdev->dev,
307 clk_name, NULL, 0,
308 plat->clk_ptp_rate);
309
310 if (IS_ERR(plat->stmmac_clk)) {
311 dev_warn(&pdev->dev, "Fail to register stmmac-clk\n");
312 plat->stmmac_clk = NULL;
313 }
314
315 ret = clk_prepare_enable(plat->stmmac_clk);
316 if (ret) {
317 clk_unregister_fixed_rate(plat->stmmac_clk);
318 return ret;
319 }
320
321 /* Set default value for multicast hash bins */
322 plat->multicast_filter_bins = HASH_TABLE_SIZE;
323
324 /* Set default value for unicast filter entries */
325 plat->unicast_filter_entries = 1;
326
327 /* Set the maxmtu to a default of JUMBO_LEN */
328 plat->maxmtu = JUMBO_LEN;
329
330 plat->vlan_fail_q_en = true;
331
332 /* Use the last Rx queue */
333 plat->vlan_fail_q = plat->rx_queues_to_use - 1;
334
335 return 0;
336 }
337
ehl_common_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)338 static int ehl_common_data(struct pci_dev *pdev,
339 struct plat_stmmacenet_data *plat)
340 {
341 plat->rx_queues_to_use = 8;
342 plat->tx_queues_to_use = 8;
343 plat->clk_ptp_rate = 200000000;
344
345 return intel_mgbe_common_data(pdev, plat);
346 }
347
ehl_sgmii_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)348 static int ehl_sgmii_data(struct pci_dev *pdev,
349 struct plat_stmmacenet_data *plat)
350 {
351 plat->bus_id = 1;
352 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
353
354 plat->serdes_powerup = intel_serdes_powerup;
355 plat->serdes_powerdown = intel_serdes_powerdown;
356
357 return ehl_common_data(pdev, plat);
358 }
359
360 static struct stmmac_pci_info ehl_sgmii1g_info = {
361 .setup = ehl_sgmii_data,
362 };
363
ehl_rgmii_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)364 static int ehl_rgmii_data(struct pci_dev *pdev,
365 struct plat_stmmacenet_data *plat)
366 {
367 plat->bus_id = 1;
368 plat->phy_interface = PHY_INTERFACE_MODE_RGMII;
369
370 return ehl_common_data(pdev, plat);
371 }
372
373 static struct stmmac_pci_info ehl_rgmii1g_info = {
374 .setup = ehl_rgmii_data,
375 };
376
ehl_pse0_common_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)377 static int ehl_pse0_common_data(struct pci_dev *pdev,
378 struct plat_stmmacenet_data *plat)
379 {
380 plat->bus_id = 2;
381 plat->addr64 = 32;
382 return ehl_common_data(pdev, plat);
383 }
384
ehl_pse0_rgmii1g_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)385 static int ehl_pse0_rgmii1g_data(struct pci_dev *pdev,
386 struct plat_stmmacenet_data *plat)
387 {
388 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID;
389 return ehl_pse0_common_data(pdev, plat);
390 }
391
392 static struct stmmac_pci_info ehl_pse0_rgmii1g_info = {
393 .setup = ehl_pse0_rgmii1g_data,
394 };
395
ehl_pse0_sgmii1g_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)396 static int ehl_pse0_sgmii1g_data(struct pci_dev *pdev,
397 struct plat_stmmacenet_data *plat)
398 {
399 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
400 plat->serdes_powerup = intel_serdes_powerup;
401 plat->serdes_powerdown = intel_serdes_powerdown;
402 return ehl_pse0_common_data(pdev, plat);
403 }
404
405 static struct stmmac_pci_info ehl_pse0_sgmii1g_info = {
406 .setup = ehl_pse0_sgmii1g_data,
407 };
408
ehl_pse1_common_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)409 static int ehl_pse1_common_data(struct pci_dev *pdev,
410 struct plat_stmmacenet_data *plat)
411 {
412 plat->bus_id = 3;
413 plat->addr64 = 32;
414 return ehl_common_data(pdev, plat);
415 }
416
ehl_pse1_rgmii1g_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)417 static int ehl_pse1_rgmii1g_data(struct pci_dev *pdev,
418 struct plat_stmmacenet_data *plat)
419 {
420 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID;
421 return ehl_pse1_common_data(pdev, plat);
422 }
423
424 static struct stmmac_pci_info ehl_pse1_rgmii1g_info = {
425 .setup = ehl_pse1_rgmii1g_data,
426 };
427
ehl_pse1_sgmii1g_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)428 static int ehl_pse1_sgmii1g_data(struct pci_dev *pdev,
429 struct plat_stmmacenet_data *plat)
430 {
431 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
432 plat->serdes_powerup = intel_serdes_powerup;
433 plat->serdes_powerdown = intel_serdes_powerdown;
434 return ehl_pse1_common_data(pdev, plat);
435 }
436
437 static struct stmmac_pci_info ehl_pse1_sgmii1g_info = {
438 .setup = ehl_pse1_sgmii1g_data,
439 };
440
tgl_common_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)441 static int tgl_common_data(struct pci_dev *pdev,
442 struct plat_stmmacenet_data *plat)
443 {
444 plat->rx_queues_to_use = 6;
445 plat->tx_queues_to_use = 4;
446 plat->clk_ptp_rate = 200000000;
447
448 return intel_mgbe_common_data(pdev, plat);
449 }
450
tgl_sgmii_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)451 static int tgl_sgmii_data(struct pci_dev *pdev,
452 struct plat_stmmacenet_data *plat)
453 {
454 plat->bus_id = 1;
455 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
456 plat->serdes_powerup = intel_serdes_powerup;
457 plat->serdes_powerdown = intel_serdes_powerdown;
458 return tgl_common_data(pdev, plat);
459 }
460
461 static struct stmmac_pci_info tgl_sgmii1g_info = {
462 .setup = tgl_sgmii_data,
463 };
464
465 static const struct stmmac_pci_func_data galileo_stmmac_func_data[] = {
466 {
467 .func = 6,
468 .phy_addr = 1,
469 },
470 };
471
472 static const struct stmmac_pci_dmi_data galileo_stmmac_dmi_data = {
473 .func = galileo_stmmac_func_data,
474 .nfuncs = ARRAY_SIZE(galileo_stmmac_func_data),
475 };
476
477 static const struct stmmac_pci_func_data iot2040_stmmac_func_data[] = {
478 {
479 .func = 6,
480 .phy_addr = 1,
481 },
482 {
483 .func = 7,
484 .phy_addr = 1,
485 },
486 };
487
488 static const struct stmmac_pci_dmi_data iot2040_stmmac_dmi_data = {
489 .func = iot2040_stmmac_func_data,
490 .nfuncs = ARRAY_SIZE(iot2040_stmmac_func_data),
491 };
492
493 static const struct dmi_system_id quark_pci_dmi[] = {
494 {
495 .matches = {
496 DMI_EXACT_MATCH(DMI_BOARD_NAME, "Galileo"),
497 },
498 .driver_data = (void *)&galileo_stmmac_dmi_data,
499 },
500 {
501 .matches = {
502 DMI_EXACT_MATCH(DMI_BOARD_NAME, "GalileoGen2"),
503 },
504 .driver_data = (void *)&galileo_stmmac_dmi_data,
505 },
506 /* There are 2 types of SIMATIC IOT2000: IOT2020 and IOT2040.
507 * The asset tag "6ES7647-0AA00-0YA2" is only for IOT2020 which
508 * has only one pci network device while other asset tags are
509 * for IOT2040 which has two.
510 */
511 {
512 .matches = {
513 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"),
514 DMI_EXACT_MATCH(DMI_BOARD_ASSET_TAG,
515 "6ES7647-0AA00-0YA2"),
516 },
517 .driver_data = (void *)&galileo_stmmac_dmi_data,
518 },
519 {
520 .matches = {
521 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"),
522 },
523 .driver_data = (void *)&iot2040_stmmac_dmi_data,
524 },
525 {}
526 };
527
quark_default_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)528 static int quark_default_data(struct pci_dev *pdev,
529 struct plat_stmmacenet_data *plat)
530 {
531 int ret;
532
533 /* Set common default data first */
534 common_default_data(plat);
535
536 /* Refuse to load the driver and register net device if MAC controller
537 * does not connect to any PHY interface.
538 */
539 ret = stmmac_pci_find_phy_addr(pdev, quark_pci_dmi);
540 if (ret < 0) {
541 /* Return error to the caller on DMI enabled boards. */
542 if (dmi_get_system_info(DMI_BOARD_NAME))
543 return ret;
544
545 /* Galileo boards with old firmware don't support DMI. We always
546 * use 1 here as PHY address, so at least the first found MAC
547 * controller would be probed.
548 */
549 ret = 1;
550 }
551
552 plat->bus_id = pci_dev_id(pdev);
553 plat->phy_addr = ret;
554 plat->phy_interface = PHY_INTERFACE_MODE_RMII;
555
556 plat->dma_cfg->pbl = 16;
557 plat->dma_cfg->pblx8 = true;
558 plat->dma_cfg->fixed_burst = 1;
559 /* AXI (TODO) */
560
561 return 0;
562 }
563
564 static const struct stmmac_pci_info quark_info = {
565 .setup = quark_default_data,
566 };
567
568 /**
569 * intel_eth_pci_probe
570 *
571 * @pdev: pci device pointer
572 * @id: pointer to table of device id/id's.
573 *
574 * Description: This probing function gets called for all PCI devices which
575 * match the ID table and are not "owned" by other driver yet. This function
576 * gets passed a "struct pci_dev *" for each device whose entry in the ID table
577 * matches the device. The probe functions returns zero when the driver choose
578 * to take "ownership" of the device or an error code(-ve no) otherwise.
579 */
intel_eth_pci_probe(struct pci_dev * pdev,const struct pci_device_id * id)580 static int intel_eth_pci_probe(struct pci_dev *pdev,
581 const struct pci_device_id *id)
582 {
583 struct stmmac_pci_info *info = (struct stmmac_pci_info *)id->driver_data;
584 struct intel_priv_data *intel_priv;
585 struct plat_stmmacenet_data *plat;
586 struct stmmac_resources res;
587 int ret;
588
589 intel_priv = devm_kzalloc(&pdev->dev, sizeof(*intel_priv), GFP_KERNEL);
590 if (!intel_priv)
591 return -ENOMEM;
592
593 plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL);
594 if (!plat)
595 return -ENOMEM;
596
597 plat->mdio_bus_data = devm_kzalloc(&pdev->dev,
598 sizeof(*plat->mdio_bus_data),
599 GFP_KERNEL);
600 if (!plat->mdio_bus_data)
601 return -ENOMEM;
602
603 plat->dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg),
604 GFP_KERNEL);
605 if (!plat->dma_cfg)
606 return -ENOMEM;
607
608 /* Enable pci device */
609 ret = pci_enable_device(pdev);
610 if (ret) {
611 dev_err(&pdev->dev, "%s: ERROR: failed to enable device\n",
612 __func__);
613 return ret;
614 }
615
616 ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev));
617 if (ret)
618 return ret;
619
620 pci_set_master(pdev);
621
622 plat->bsp_priv = intel_priv;
623 intel_priv->mdio_adhoc_addr = 0x15;
624
625 ret = info->setup(pdev, plat);
626 if (ret)
627 return ret;
628
629 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
630 if (ret < 0)
631 return ret;
632
633 memset(&res, 0, sizeof(res));
634 res.addr = pcim_iomap_table(pdev)[0];
635 res.wol_irq = pci_irq_vector(pdev, 0);
636 res.irq = pci_irq_vector(pdev, 0);
637
638 if (plat->eee_usecs_rate > 0) {
639 u32 tx_lpi_usec;
640
641 tx_lpi_usec = (plat->eee_usecs_rate / 1000000) - 1;
642 writel(tx_lpi_usec, res.addr + GMAC_1US_TIC_COUNTER);
643 }
644
645 ret = stmmac_dvr_probe(&pdev->dev, plat, &res);
646 if (ret) {
647 pci_free_irq_vectors(pdev);
648 clk_disable_unprepare(plat->stmmac_clk);
649 clk_unregister_fixed_rate(plat->stmmac_clk);
650 }
651
652 return ret;
653 }
654
655 /**
656 * intel_eth_pci_remove
657 *
658 * @pdev: platform device pointer
659 * Description: this function calls the main to free the net resources
660 * and releases the PCI resources.
661 */
intel_eth_pci_remove(struct pci_dev * pdev)662 static void intel_eth_pci_remove(struct pci_dev *pdev)
663 {
664 struct net_device *ndev = dev_get_drvdata(&pdev->dev);
665 struct stmmac_priv *priv = netdev_priv(ndev);
666
667 stmmac_dvr_remove(&pdev->dev);
668
669 pci_free_irq_vectors(pdev);
670
671 clk_unregister_fixed_rate(priv->plat->stmmac_clk);
672
673 pcim_iounmap_regions(pdev, BIT(0));
674
675 pci_disable_device(pdev);
676 }
677
intel_eth_pci_suspend(struct device * dev)678 static int __maybe_unused intel_eth_pci_suspend(struct device *dev)
679 {
680 struct pci_dev *pdev = to_pci_dev(dev);
681 int ret;
682
683 ret = stmmac_suspend(dev);
684 if (ret)
685 return ret;
686
687 ret = pci_save_state(pdev);
688 if (ret)
689 return ret;
690
691 pci_disable_device(pdev);
692 pci_wake_from_d3(pdev, true);
693 return 0;
694 }
695
intel_eth_pci_resume(struct device * dev)696 static int __maybe_unused intel_eth_pci_resume(struct device *dev)
697 {
698 struct pci_dev *pdev = to_pci_dev(dev);
699 int ret;
700
701 pci_restore_state(pdev);
702 pci_set_power_state(pdev, PCI_D0);
703
704 ret = pci_enable_device(pdev);
705 if (ret)
706 return ret;
707
708 pci_set_master(pdev);
709
710 return stmmac_resume(dev);
711 }
712
713 static SIMPLE_DEV_PM_OPS(intel_eth_pm_ops, intel_eth_pci_suspend,
714 intel_eth_pci_resume);
715
716 #define PCI_DEVICE_ID_INTEL_QUARK_ID 0x0937
717 #define PCI_DEVICE_ID_INTEL_EHL_RGMII1G_ID 0x4b30
718 #define PCI_DEVICE_ID_INTEL_EHL_SGMII1G_ID 0x4b31
719 #define PCI_DEVICE_ID_INTEL_EHL_SGMII2G5_ID 0x4b32
720 /* Intel(R) Programmable Services Engine (Intel(R) PSE) consist of 2 MAC
721 * which are named PSE0 and PSE1
722 */
723 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G_ID 0x4ba0
724 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G_ID 0x4ba1
725 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII2G5_ID 0x4ba2
726 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G_ID 0x4bb0
727 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G_ID 0x4bb1
728 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII2G5_ID 0x4bb2
729 #define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_0_ID 0x43ac
730 #define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_1_ID 0x43a2
731 #define PCI_DEVICE_ID_INTEL_TGL_SGMII1G_ID 0xa0ac
732
733 static const struct pci_device_id intel_eth_pci_id_table[] = {
734 { PCI_DEVICE_DATA(INTEL, QUARK_ID, &quark_info) },
735 { PCI_DEVICE_DATA(INTEL, EHL_RGMII1G_ID, &ehl_rgmii1g_info) },
736 { PCI_DEVICE_DATA(INTEL, EHL_SGMII1G_ID, &ehl_sgmii1g_info) },
737 { PCI_DEVICE_DATA(INTEL, EHL_SGMII2G5_ID, &ehl_sgmii1g_info) },
738 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_RGMII1G_ID, &ehl_pse0_rgmii1g_info) },
739 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII1G_ID, &ehl_pse0_sgmii1g_info) },
740 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII2G5_ID, &ehl_pse0_sgmii1g_info) },
741 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_RGMII1G_ID, &ehl_pse1_rgmii1g_info) },
742 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII1G_ID, &ehl_pse1_sgmii1g_info) },
743 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII2G5_ID, &ehl_pse1_sgmii1g_info) },
744 { PCI_DEVICE_DATA(INTEL, TGL_SGMII1G_ID, &tgl_sgmii1g_info) },
745 { PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_0_ID, &tgl_sgmii1g_info) },
746 { PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_1_ID, &tgl_sgmii1g_info) },
747 {}
748 };
749 MODULE_DEVICE_TABLE(pci, intel_eth_pci_id_table);
750
751 static struct pci_driver intel_eth_pci_driver = {
752 .name = "intel-eth-pci",
753 .id_table = intel_eth_pci_id_table,
754 .probe = intel_eth_pci_probe,
755 .remove = intel_eth_pci_remove,
756 .driver = {
757 .pm = &intel_eth_pm_ops,
758 },
759 };
760
761 module_pci_driver(intel_eth_pci_driver);
762
763 MODULE_DESCRIPTION("INTEL 10/100/1000 Ethernet PCI driver");
764 MODULE_AUTHOR("Voon Weifeng <weifeng.voon@intel.com>");
765 MODULE_LICENSE("GPL v2");
766