1 // SPDX-License-Identifier: GPL-2.0
2 /* Driver for the Texas Instruments DP83822, DP83825 and DP83826 PHYs.
3 *
4 * Copyright (C) 2017 Texas Instruments Inc.
5 */
6
7 #include <linux/ethtool.h>
8 #include <linux/etherdevice.h>
9 #include <linux/kernel.h>
10 #include <linux/mii.h>
11 #include <linux/module.h>
12 #include <linux/of.h>
13 #include <linux/phy.h>
14 #include <linux/netdevice.h>
15
16 #define DP83822_PHY_ID 0x2000a240
17 #define DP83825S_PHY_ID 0x2000a140
18 #define DP83825I_PHY_ID 0x2000a150
19 #define DP83825CM_PHY_ID 0x2000a160
20 #define DP83825CS_PHY_ID 0x2000a170
21 #define DP83826C_PHY_ID 0x2000a130
22 #define DP83826NC_PHY_ID 0x2000a110
23
24 #define DP83822_DEVADDR 0x1f
25
26 #define MII_DP83822_CTRL_2 0x0a
27 #define MII_DP83822_PHYSTS 0x10
28 #define MII_DP83822_PHYSCR 0x11
29 #define MII_DP83822_MISR1 0x12
30 #define MII_DP83822_MISR2 0x13
31 #define MII_DP83822_FCSCR 0x14
32 #define MII_DP83822_RCSR 0x17
33 #define MII_DP83822_RESET_CTRL 0x1f
34 #define MII_DP83822_GENCFG 0x465
35 #define MII_DP83822_SOR1 0x467
36
37 /* GENCFG */
38 #define DP83822_SIG_DET_LOW BIT(0)
39
40 /* Control Register 2 bits */
41 #define DP83822_FX_ENABLE BIT(14)
42
43 #define DP83822_HW_RESET BIT(15)
44 #define DP83822_SW_RESET BIT(14)
45
46 /* PHY STS bits */
47 #define DP83822_PHYSTS_DUPLEX BIT(2)
48 #define DP83822_PHYSTS_10 BIT(1)
49 #define DP83822_PHYSTS_LINK BIT(0)
50
51 /* PHYSCR Register Fields */
52 #define DP83822_PHYSCR_INT_OE BIT(0) /* Interrupt Output Enable */
53 #define DP83822_PHYSCR_INTEN BIT(1) /* Interrupt Enable */
54
55 /* MISR1 bits */
56 #define DP83822_RX_ERR_HF_INT_EN BIT(0)
57 #define DP83822_FALSE_CARRIER_HF_INT_EN BIT(1)
58 #define DP83822_ANEG_COMPLETE_INT_EN BIT(2)
59 #define DP83822_DUP_MODE_CHANGE_INT_EN BIT(3)
60 #define DP83822_SPEED_CHANGED_INT_EN BIT(4)
61 #define DP83822_LINK_STAT_INT_EN BIT(5)
62 #define DP83822_ENERGY_DET_INT_EN BIT(6)
63 #define DP83822_LINK_QUAL_INT_EN BIT(7)
64
65 /* MISR2 bits */
66 #define DP83822_JABBER_DET_INT_EN BIT(0)
67 #define DP83822_WOL_PKT_INT_EN BIT(1)
68 #define DP83822_SLEEP_MODE_INT_EN BIT(2)
69 #define DP83822_MDI_XOVER_INT_EN BIT(3)
70 #define DP83822_LB_FIFO_INT_EN BIT(4)
71 #define DP83822_PAGE_RX_INT_EN BIT(5)
72 #define DP83822_ANEG_ERR_INT_EN BIT(6)
73 #define DP83822_EEE_ERROR_CHANGE_INT_EN BIT(7)
74
75 /* INT_STAT1 bits */
76 #define DP83822_WOL_INT_EN BIT(4)
77 #define DP83822_WOL_INT_STAT BIT(12)
78
79 #define MII_DP83822_RXSOP1 0x04a5
80 #define MII_DP83822_RXSOP2 0x04a6
81 #define MII_DP83822_RXSOP3 0x04a7
82
83 /* WoL Registers */
84 #define MII_DP83822_WOL_CFG 0x04a0
85 #define MII_DP83822_WOL_STAT 0x04a1
86 #define MII_DP83822_WOL_DA1 0x04a2
87 #define MII_DP83822_WOL_DA2 0x04a3
88 #define MII_DP83822_WOL_DA3 0x04a4
89
90 /* WoL bits */
91 #define DP83822_WOL_MAGIC_EN BIT(0)
92 #define DP83822_WOL_SECURE_ON BIT(5)
93 #define DP83822_WOL_EN BIT(7)
94 #define DP83822_WOL_INDICATION_SEL BIT(8)
95 #define DP83822_WOL_CLR_INDICATION BIT(11)
96
97 /* RSCR bits */
98 #define DP83822_RX_CLK_SHIFT BIT(12)
99 #define DP83822_TX_CLK_SHIFT BIT(11)
100
101 /* SOR1 mode */
102 #define DP83822_STRAP_MODE1 0
103 #define DP83822_STRAP_MODE2 BIT(0)
104 #define DP83822_STRAP_MODE3 BIT(1)
105 #define DP83822_STRAP_MODE4 GENMASK(1, 0)
106
107 #define DP83822_COL_STRAP_MASK GENMASK(11, 10)
108 #define DP83822_COL_SHIFT 10
109 #define DP83822_RX_ER_STR_MASK GENMASK(9, 8)
110 #define DP83822_RX_ER_SHIFT 8
111
112 #define MII_DP83822_FIBER_ADVERTISE (ADVERTISED_TP | ADVERTISED_MII | \
113 ADVERTISED_FIBRE | \
114 ADVERTISED_Pause | ADVERTISED_Asym_Pause)
115
116 struct dp83822_private {
117 bool fx_signal_det_low;
118 int fx_enabled;
119 u16 fx_sd_enable;
120 };
121
dp83822_ack_interrupt(struct phy_device * phydev)122 static int dp83822_ack_interrupt(struct phy_device *phydev)
123 {
124 int err;
125
126 err = phy_read(phydev, MII_DP83822_MISR1);
127 if (err < 0)
128 return err;
129
130 err = phy_read(phydev, MII_DP83822_MISR2);
131 if (err < 0)
132 return err;
133
134 return 0;
135 }
136
dp83822_set_wol(struct phy_device * phydev,struct ethtool_wolinfo * wol)137 static int dp83822_set_wol(struct phy_device *phydev,
138 struct ethtool_wolinfo *wol)
139 {
140 struct net_device *ndev = phydev->attached_dev;
141 u16 value;
142 const u8 *mac;
143
144 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE)) {
145 mac = (const u8 *)ndev->dev_addr;
146
147 if (!is_valid_ether_addr(mac))
148 return -EINVAL;
149
150 /* MAC addresses start with byte 5, but stored in mac[0].
151 * 822 PHYs store bytes 4|5, 2|3, 0|1
152 */
153 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA1,
154 (mac[1] << 8) | mac[0]);
155 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA2,
156 (mac[3] << 8) | mac[2]);
157 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA3,
158 (mac[5] << 8) | mac[4]);
159
160 value = phy_read_mmd(phydev, DP83822_DEVADDR,
161 MII_DP83822_WOL_CFG);
162 if (wol->wolopts & WAKE_MAGIC)
163 value |= DP83822_WOL_MAGIC_EN;
164 else
165 value &= ~DP83822_WOL_MAGIC_EN;
166
167 if (wol->wolopts & WAKE_MAGICSECURE) {
168 phy_write_mmd(phydev, DP83822_DEVADDR,
169 MII_DP83822_RXSOP1,
170 (wol->sopass[1] << 8) | wol->sopass[0]);
171 phy_write_mmd(phydev, DP83822_DEVADDR,
172 MII_DP83822_RXSOP2,
173 (wol->sopass[3] << 8) | wol->sopass[2]);
174 phy_write_mmd(phydev, DP83822_DEVADDR,
175 MII_DP83822_RXSOP3,
176 (wol->sopass[5] << 8) | wol->sopass[4]);
177 value |= DP83822_WOL_SECURE_ON;
178 } else {
179 value &= ~DP83822_WOL_SECURE_ON;
180 }
181
182 /* Clear any pending WoL interrupt */
183 phy_read(phydev, MII_DP83822_MISR2);
184
185 value |= DP83822_WOL_EN | DP83822_WOL_INDICATION_SEL |
186 DP83822_WOL_CLR_INDICATION;
187
188 return phy_write_mmd(phydev, DP83822_DEVADDR,
189 MII_DP83822_WOL_CFG, value);
190 } else {
191 return phy_clear_bits_mmd(phydev, DP83822_DEVADDR,
192 MII_DP83822_WOL_CFG, DP83822_WOL_EN);
193 }
194 }
195
dp83822_get_wol(struct phy_device * phydev,struct ethtool_wolinfo * wol)196 static void dp83822_get_wol(struct phy_device *phydev,
197 struct ethtool_wolinfo *wol)
198 {
199 int value;
200 u16 sopass_val;
201
202 wol->supported = (WAKE_MAGIC | WAKE_MAGICSECURE);
203 wol->wolopts = 0;
204
205 value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG);
206
207 if (value & DP83822_WOL_MAGIC_EN)
208 wol->wolopts |= WAKE_MAGIC;
209
210 if (value & DP83822_WOL_SECURE_ON) {
211 sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR,
212 MII_DP83822_RXSOP1);
213 wol->sopass[0] = (sopass_val & 0xff);
214 wol->sopass[1] = (sopass_val >> 8);
215
216 sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR,
217 MII_DP83822_RXSOP2);
218 wol->sopass[2] = (sopass_val & 0xff);
219 wol->sopass[3] = (sopass_val >> 8);
220
221 sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR,
222 MII_DP83822_RXSOP3);
223 wol->sopass[4] = (sopass_val & 0xff);
224 wol->sopass[5] = (sopass_val >> 8);
225
226 wol->wolopts |= WAKE_MAGICSECURE;
227 }
228
229 /* WoL is not enabled so set wolopts to 0 */
230 if (!(value & DP83822_WOL_EN))
231 wol->wolopts = 0;
232 }
233
dp83822_config_intr(struct phy_device * phydev)234 static int dp83822_config_intr(struct phy_device *phydev)
235 {
236 struct dp83822_private *dp83822 = phydev->priv;
237 int misr_status;
238 int physcr_status;
239 int err;
240
241 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
242 misr_status = phy_read(phydev, MII_DP83822_MISR1);
243 if (misr_status < 0)
244 return misr_status;
245
246 misr_status |= (DP83822_RX_ERR_HF_INT_EN |
247 DP83822_FALSE_CARRIER_HF_INT_EN |
248 DP83822_LINK_STAT_INT_EN |
249 DP83822_ENERGY_DET_INT_EN |
250 DP83822_LINK_QUAL_INT_EN);
251
252 if (!dp83822->fx_enabled)
253 misr_status |= DP83822_ANEG_COMPLETE_INT_EN |
254 DP83822_DUP_MODE_CHANGE_INT_EN |
255 DP83822_SPEED_CHANGED_INT_EN;
256
257
258 err = phy_write(phydev, MII_DP83822_MISR1, misr_status);
259 if (err < 0)
260 return err;
261
262 misr_status = phy_read(phydev, MII_DP83822_MISR2);
263 if (misr_status < 0)
264 return misr_status;
265
266 misr_status |= (DP83822_JABBER_DET_INT_EN |
267 DP83822_SLEEP_MODE_INT_EN |
268 DP83822_LB_FIFO_INT_EN |
269 DP83822_PAGE_RX_INT_EN |
270 DP83822_EEE_ERROR_CHANGE_INT_EN);
271
272 if (!dp83822->fx_enabled)
273 misr_status |= DP83822_MDI_XOVER_INT_EN |
274 DP83822_ANEG_ERR_INT_EN |
275 DP83822_WOL_PKT_INT_EN;
276
277 err = phy_write(phydev, MII_DP83822_MISR2, misr_status);
278 if (err < 0)
279 return err;
280
281 physcr_status = phy_read(phydev, MII_DP83822_PHYSCR);
282 if (physcr_status < 0)
283 return physcr_status;
284
285 physcr_status |= DP83822_PHYSCR_INT_OE | DP83822_PHYSCR_INTEN;
286
287 } else {
288 err = phy_write(phydev, MII_DP83822_MISR1, 0);
289 if (err < 0)
290 return err;
291
292 err = phy_write(phydev, MII_DP83822_MISR1, 0);
293 if (err < 0)
294 return err;
295
296 physcr_status = phy_read(phydev, MII_DP83822_PHYSCR);
297 if (physcr_status < 0)
298 return physcr_status;
299
300 physcr_status &= ~DP83822_PHYSCR_INTEN;
301 }
302
303 return phy_write(phydev, MII_DP83822_PHYSCR, physcr_status);
304 }
305
dp8382x_disable_wol(struct phy_device * phydev)306 static int dp8382x_disable_wol(struct phy_device *phydev)
307 {
308 return phy_clear_bits_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG,
309 DP83822_WOL_EN | DP83822_WOL_MAGIC_EN |
310 DP83822_WOL_SECURE_ON);
311 }
312
dp83822_read_status(struct phy_device * phydev)313 static int dp83822_read_status(struct phy_device *phydev)
314 {
315 struct dp83822_private *dp83822 = phydev->priv;
316 int status = phy_read(phydev, MII_DP83822_PHYSTS);
317 int ctrl2;
318 int ret;
319
320 if (dp83822->fx_enabled) {
321 if (status & DP83822_PHYSTS_LINK) {
322 phydev->speed = SPEED_UNKNOWN;
323 phydev->duplex = DUPLEX_UNKNOWN;
324 } else {
325 ctrl2 = phy_read(phydev, MII_DP83822_CTRL_2);
326 if (ctrl2 < 0)
327 return ctrl2;
328
329 if (!(ctrl2 & DP83822_FX_ENABLE)) {
330 ret = phy_write(phydev, MII_DP83822_CTRL_2,
331 DP83822_FX_ENABLE | ctrl2);
332 if (ret < 0)
333 return ret;
334 }
335 }
336 }
337
338 ret = genphy_read_status(phydev);
339 if (ret)
340 return ret;
341
342 if (status < 0)
343 return status;
344
345 if (status & DP83822_PHYSTS_DUPLEX)
346 phydev->duplex = DUPLEX_FULL;
347 else
348 phydev->duplex = DUPLEX_HALF;
349
350 if (status & DP83822_PHYSTS_10)
351 phydev->speed = SPEED_10;
352 else
353 phydev->speed = SPEED_100;
354
355 return 0;
356 }
357
dp83822_config_init(struct phy_device * phydev)358 static int dp83822_config_init(struct phy_device *phydev)
359 {
360 struct dp83822_private *dp83822 = phydev->priv;
361 struct device *dev = &phydev->mdio.dev;
362 int rgmii_delay;
363 s32 rx_int_delay;
364 s32 tx_int_delay;
365 int err = 0;
366 int bmcr;
367
368 if (phy_interface_is_rgmii(phydev)) {
369 rx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0,
370 true);
371
372 if (rx_int_delay <= 0)
373 rgmii_delay = 0;
374 else
375 rgmii_delay = DP83822_RX_CLK_SHIFT;
376
377 tx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0,
378 false);
379 if (tx_int_delay <= 0)
380 rgmii_delay &= ~DP83822_TX_CLK_SHIFT;
381 else
382 rgmii_delay |= DP83822_TX_CLK_SHIFT;
383
384 if (rgmii_delay) {
385 err = phy_set_bits_mmd(phydev, DP83822_DEVADDR,
386 MII_DP83822_RCSR, rgmii_delay);
387 if (err)
388 return err;
389 }
390 }
391
392 if (dp83822->fx_enabled) {
393 err = phy_modify(phydev, MII_DP83822_CTRL_2,
394 DP83822_FX_ENABLE, 1);
395 if (err < 0)
396 return err;
397
398 /* Only allow advertising what this PHY supports */
399 linkmode_and(phydev->advertising, phydev->advertising,
400 phydev->supported);
401
402 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
403 phydev->supported);
404 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
405 phydev->advertising);
406 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT,
407 phydev->supported);
408 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT,
409 phydev->supported);
410 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT,
411 phydev->advertising);
412 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT,
413 phydev->advertising);
414
415 /* Auto neg is not supported in fiber mode */
416 bmcr = phy_read(phydev, MII_BMCR);
417 if (bmcr < 0)
418 return bmcr;
419
420 if (bmcr & BMCR_ANENABLE) {
421 err = phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0);
422 if (err < 0)
423 return err;
424 }
425 phydev->autoneg = AUTONEG_DISABLE;
426 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
427 phydev->supported);
428 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
429 phydev->advertising);
430
431 /* Setup fiber advertisement */
432 err = phy_modify_changed(phydev, MII_ADVERTISE,
433 MII_DP83822_FIBER_ADVERTISE,
434 MII_DP83822_FIBER_ADVERTISE);
435
436 if (err < 0)
437 return err;
438
439 if (dp83822->fx_signal_det_low) {
440 err = phy_set_bits_mmd(phydev, DP83822_DEVADDR,
441 MII_DP83822_GENCFG,
442 DP83822_SIG_DET_LOW);
443 if (err)
444 return err;
445 }
446 }
447 return dp8382x_disable_wol(phydev);
448 }
449
dp8382x_config_init(struct phy_device * phydev)450 static int dp8382x_config_init(struct phy_device *phydev)
451 {
452 return dp8382x_disable_wol(phydev);
453 }
454
dp83822_phy_reset(struct phy_device * phydev)455 static int dp83822_phy_reset(struct phy_device *phydev)
456 {
457 int err;
458
459 err = phy_write(phydev, MII_DP83822_RESET_CTRL, DP83822_SW_RESET);
460 if (err < 0)
461 return err;
462
463 return phydev->drv->config_init(phydev);
464 }
465
466 #ifdef CONFIG_OF_MDIO
dp83822_of_init(struct phy_device * phydev)467 static int dp83822_of_init(struct phy_device *phydev)
468 {
469 struct dp83822_private *dp83822 = phydev->priv;
470 struct device *dev = &phydev->mdio.dev;
471
472 /* Signal detection for the PHY is only enabled if the FX_EN and the
473 * SD_EN pins are strapped. Signal detection can only enabled if FX_EN
474 * is strapped otherwise signal detection is disabled for the PHY.
475 */
476 if (dp83822->fx_enabled && dp83822->fx_sd_enable)
477 dp83822->fx_signal_det_low = device_property_present(dev,
478 "ti,link-loss-low");
479 if (!dp83822->fx_enabled)
480 dp83822->fx_enabled = device_property_present(dev,
481 "ti,fiber-mode");
482
483 return 0;
484 }
485 #else
dp83822_of_init(struct phy_device * phydev)486 static int dp83822_of_init(struct phy_device *phydev)
487 {
488 return 0;
489 }
490 #endif /* CONFIG_OF_MDIO */
491
dp83822_read_straps(struct phy_device * phydev)492 static int dp83822_read_straps(struct phy_device *phydev)
493 {
494 struct dp83822_private *dp83822 = phydev->priv;
495 int fx_enabled, fx_sd_enable;
496 int val;
497
498 val = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_SOR1);
499 if (val < 0)
500 return val;
501
502 fx_enabled = (val & DP83822_COL_STRAP_MASK) >> DP83822_COL_SHIFT;
503 if (fx_enabled == DP83822_STRAP_MODE2 ||
504 fx_enabled == DP83822_STRAP_MODE3)
505 dp83822->fx_enabled = 1;
506
507 if (dp83822->fx_enabled) {
508 fx_sd_enable = (val & DP83822_RX_ER_STR_MASK) >> DP83822_RX_ER_SHIFT;
509 if (fx_sd_enable == DP83822_STRAP_MODE3 ||
510 fx_sd_enable == DP83822_STRAP_MODE4)
511 dp83822->fx_sd_enable = 1;
512 }
513
514 return 0;
515 }
516
dp83822_probe(struct phy_device * phydev)517 static int dp83822_probe(struct phy_device *phydev)
518 {
519 struct dp83822_private *dp83822;
520 int ret;
521
522 dp83822 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83822),
523 GFP_KERNEL);
524 if (!dp83822)
525 return -ENOMEM;
526
527 phydev->priv = dp83822;
528
529 ret = dp83822_read_straps(phydev);
530 if (ret)
531 return ret;
532
533 dp83822_of_init(phydev);
534
535 if (dp83822->fx_enabled)
536 phydev->port = PORT_FIBRE;
537
538 return 0;
539 }
540
dp83822_suspend(struct phy_device * phydev)541 static int dp83822_suspend(struct phy_device *phydev)
542 {
543 int value;
544
545 value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG);
546
547 if (!(value & DP83822_WOL_EN))
548 genphy_suspend(phydev);
549
550 return 0;
551 }
552
dp83822_resume(struct phy_device * phydev)553 static int dp83822_resume(struct phy_device *phydev)
554 {
555 int value;
556
557 genphy_resume(phydev);
558
559 value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG);
560
561 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG, value |
562 DP83822_WOL_CLR_INDICATION);
563
564 return 0;
565 }
566
567 #define DP83822_PHY_DRIVER(_id, _name) \
568 { \
569 PHY_ID_MATCH_MODEL(_id), \
570 .name = (_name), \
571 /* PHY_BASIC_FEATURES */ \
572 .probe = dp83822_probe, \
573 .soft_reset = dp83822_phy_reset, \
574 .config_init = dp83822_config_init, \
575 .read_status = dp83822_read_status, \
576 .get_wol = dp83822_get_wol, \
577 .set_wol = dp83822_set_wol, \
578 .ack_interrupt = dp83822_ack_interrupt, \
579 .config_intr = dp83822_config_intr, \
580 .suspend = dp83822_suspend, \
581 .resume = dp83822_resume, \
582 }
583
584 #define DP8382X_PHY_DRIVER(_id, _name) \
585 { \
586 PHY_ID_MATCH_MODEL(_id), \
587 .name = (_name), \
588 /* PHY_BASIC_FEATURES */ \
589 .soft_reset = dp83822_phy_reset, \
590 .config_init = dp8382x_config_init, \
591 .get_wol = dp83822_get_wol, \
592 .set_wol = dp83822_set_wol, \
593 .ack_interrupt = dp83822_ack_interrupt, \
594 .config_intr = dp83822_config_intr, \
595 .suspend = dp83822_suspend, \
596 .resume = dp83822_resume, \
597 }
598
599 static struct phy_driver dp83822_driver[] = {
600 DP83822_PHY_DRIVER(DP83822_PHY_ID, "TI DP83822"),
601 DP8382X_PHY_DRIVER(DP83825I_PHY_ID, "TI DP83825I"),
602 DP8382X_PHY_DRIVER(DP83826C_PHY_ID, "TI DP83826C"),
603 DP8382X_PHY_DRIVER(DP83826NC_PHY_ID, "TI DP83826NC"),
604 DP8382X_PHY_DRIVER(DP83825S_PHY_ID, "TI DP83825S"),
605 DP8382X_PHY_DRIVER(DP83825CM_PHY_ID, "TI DP83825M"),
606 DP8382X_PHY_DRIVER(DP83825CS_PHY_ID, "TI DP83825CS"),
607 };
608 module_phy_driver(dp83822_driver);
609
610 static struct mdio_device_id __maybe_unused dp83822_tbl[] = {
611 { DP83822_PHY_ID, 0xfffffff0 },
612 { DP83825I_PHY_ID, 0xfffffff0 },
613 { DP83826C_PHY_ID, 0xfffffff0 },
614 { DP83826NC_PHY_ID, 0xfffffff0 },
615 { DP83825S_PHY_ID, 0xfffffff0 },
616 { DP83825CM_PHY_ID, 0xfffffff0 },
617 { DP83825CS_PHY_ID, 0xfffffff0 },
618 { },
619 };
620 MODULE_DEVICE_TABLE(mdio, dp83822_tbl);
621
622 MODULE_DESCRIPTION("Texas Instruments DP83822 PHY driver");
623 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
624 MODULE_LICENSE("GPL v2");
625