1 /*
2 * PMC-Sierra SPCv/ve 8088/8089 SAS/SATA based host adapters driver
3 *
4 * Copyright (c) 2008-2009 PMC-Sierra, Inc.,
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
25 *
26 * NO WARRANTY
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGES.
38 *
39 */
40 #include <linux/slab.h>
41 #include "pm8001_sas.h"
42 #include "pm80xx_hwi.h"
43 #include "pm8001_chips.h"
44 #include "pm8001_ctl.h"
45
46 #define SMP_DIRECT 1
47 #define SMP_INDIRECT 2
48
49
pm80xx_bar4_shift(struct pm8001_hba_info * pm8001_ha,u32 shift_value)50 int pm80xx_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shift_value)
51 {
52 u32 reg_val;
53 unsigned long start;
54 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, shift_value);
55 /* confirm the setting is written */
56 start = jiffies + HZ; /* 1 sec */
57 do {
58 reg_val = pm8001_cr32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER);
59 } while ((reg_val != shift_value) && time_before(jiffies, start));
60 if (reg_val != shift_value) {
61 pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:MEMBASE_II_SHIFT_REGISTER = 0x%x\n",
62 reg_val);
63 return -1;
64 }
65 return 0;
66 }
67
pm80xx_pci_mem_copy(struct pm8001_hba_info * pm8001_ha,u32 soffset,const void * destination,u32 dw_count,u32 bus_base_number)68 static void pm80xx_pci_mem_copy(struct pm8001_hba_info *pm8001_ha, u32 soffset,
69 const void *destination,
70 u32 dw_count, u32 bus_base_number)
71 {
72 u32 index, value, offset;
73 u32 *destination1;
74 destination1 = (u32 *)destination;
75
76 for (index = 0; index < dw_count; index += 4, destination1++) {
77 offset = (soffset + index);
78 if (offset < (64 * 1024)) {
79 value = pm8001_cr32(pm8001_ha, bus_base_number, offset);
80 *destination1 = cpu_to_le32(value);
81 }
82 }
83 return;
84 }
85
pm80xx_get_fatal_dump(struct device * cdev,struct device_attribute * attr,char * buf)86 ssize_t pm80xx_get_fatal_dump(struct device *cdev,
87 struct device_attribute *attr, char *buf)
88 {
89 struct Scsi_Host *shost = class_to_shost(cdev);
90 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
91 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
92 void __iomem *fatal_table_address = pm8001_ha->fatal_tbl_addr;
93 u32 accum_len , reg_val, index, *temp;
94 u32 status = 1;
95 unsigned long start;
96 u8 *direct_data;
97 char *fatal_error_data = buf;
98 u32 length_to_read;
99 u32 offset;
100
101 pm8001_ha->forensic_info.data_buf.direct_data = buf;
102 if (pm8001_ha->chip_id == chip_8001) {
103 pm8001_ha->forensic_info.data_buf.direct_data +=
104 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
105 "Not supported for SPC controller");
106 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
107 (char *)buf;
108 }
109 /* initialize variables for very first call from host application */
110 if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) {
111 pm8001_dbg(pm8001_ha, IO,
112 "forensic_info TYPE_NON_FATAL..............\n");
113 direct_data = (u8 *)fatal_error_data;
114 pm8001_ha->forensic_info.data_type = TYPE_NON_FATAL;
115 pm8001_ha->forensic_info.data_buf.direct_len = SYSFS_OFFSET;
116 pm8001_ha->forensic_info.data_buf.direct_offset = 0;
117 pm8001_ha->forensic_info.data_buf.read_len = 0;
118 pm8001_ha->forensic_preserved_accumulated_transfer = 0;
119
120 /* Write signature to fatal dump table */
121 pm8001_mw32(fatal_table_address,
122 MPI_FATAL_EDUMP_TABLE_SIGNATURE, 0x1234abcd);
123
124 pm8001_ha->forensic_info.data_buf.direct_data = direct_data;
125 pm8001_dbg(pm8001_ha, IO, "ossaHwCB: status1 %d\n", status);
126 pm8001_dbg(pm8001_ha, IO, "ossaHwCB: read_len 0x%x\n",
127 pm8001_ha->forensic_info.data_buf.read_len);
128 pm8001_dbg(pm8001_ha, IO, "ossaHwCB: direct_len 0x%x\n",
129 pm8001_ha->forensic_info.data_buf.direct_len);
130 pm8001_dbg(pm8001_ha, IO, "ossaHwCB: direct_offset 0x%x\n",
131 pm8001_ha->forensic_info.data_buf.direct_offset);
132 }
133 if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) {
134 /* start to get data */
135 /* Program the MEMBASE II Shifting Register with 0x00.*/
136 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
137 pm8001_ha->fatal_forensic_shift_offset);
138 pm8001_ha->forensic_last_offset = 0;
139 pm8001_ha->forensic_fatal_step = 0;
140 pm8001_ha->fatal_bar_loc = 0;
141 }
142
143 /* Read until accum_len is retrived */
144 accum_len = pm8001_mr32(fatal_table_address,
145 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN);
146 /* Determine length of data between previously stored transfer length
147 * and current accumulated transfer length
148 */
149 length_to_read =
150 accum_len - pm8001_ha->forensic_preserved_accumulated_transfer;
151 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: accum_len 0x%x\n",
152 accum_len);
153 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: length_to_read 0x%x\n",
154 length_to_read);
155 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: last_offset 0x%x\n",
156 pm8001_ha->forensic_last_offset);
157 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: read_len 0x%x\n",
158 pm8001_ha->forensic_info.data_buf.read_len);
159 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv:: direct_len 0x%x\n",
160 pm8001_ha->forensic_info.data_buf.direct_len);
161 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv:: direct_offset 0x%x\n",
162 pm8001_ha->forensic_info.data_buf.direct_offset);
163
164 /* If accumulated length failed to read correctly fail the attempt.*/
165 if (accum_len == 0xFFFFFFFF) {
166 pm8001_dbg(pm8001_ha, IO,
167 "Possible PCI issue 0x%x not expected\n",
168 accum_len);
169 return status;
170 }
171 /* If accumulated length is zero fail the attempt */
172 if (accum_len == 0) {
173 pm8001_ha->forensic_info.data_buf.direct_data +=
174 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
175 "%08x ", 0xFFFFFFFF);
176 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
177 (char *)buf;
178 }
179 /* Accumulated length is good so start capturing the first data */
180 temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr;
181 if (pm8001_ha->forensic_fatal_step == 0) {
182 moreData:
183 /* If data to read is less than SYSFS_OFFSET then reduce the
184 * length of dataLen
185 */
186 if (pm8001_ha->forensic_last_offset + SYSFS_OFFSET
187 > length_to_read) {
188 pm8001_ha->forensic_info.data_buf.direct_len =
189 length_to_read -
190 pm8001_ha->forensic_last_offset;
191 } else {
192 pm8001_ha->forensic_info.data_buf.direct_len =
193 SYSFS_OFFSET;
194 }
195 if (pm8001_ha->forensic_info.data_buf.direct_data) {
196 /* Data is in bar, copy to host memory */
197 pm80xx_pci_mem_copy(pm8001_ha,
198 pm8001_ha->fatal_bar_loc,
199 pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr,
200 pm8001_ha->forensic_info.data_buf.direct_len, 1);
201 }
202 pm8001_ha->fatal_bar_loc +=
203 pm8001_ha->forensic_info.data_buf.direct_len;
204 pm8001_ha->forensic_info.data_buf.direct_offset +=
205 pm8001_ha->forensic_info.data_buf.direct_len;
206 pm8001_ha->forensic_last_offset +=
207 pm8001_ha->forensic_info.data_buf.direct_len;
208 pm8001_ha->forensic_info.data_buf.read_len =
209 pm8001_ha->forensic_info.data_buf.direct_len;
210
211 if (pm8001_ha->forensic_last_offset >= length_to_read) {
212 pm8001_ha->forensic_info.data_buf.direct_data +=
213 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
214 "%08x ", 3);
215 for (index = 0; index <
216 (pm8001_ha->forensic_info.data_buf.direct_len
217 / 4); index++) {
218 pm8001_ha->forensic_info.data_buf.direct_data +=
219 sprintf(
220 pm8001_ha->forensic_info.data_buf.direct_data,
221 "%08x ", *(temp + index));
222 }
223
224 pm8001_ha->fatal_bar_loc = 0;
225 pm8001_ha->forensic_fatal_step = 1;
226 pm8001_ha->fatal_forensic_shift_offset = 0;
227 pm8001_ha->forensic_last_offset = 0;
228 status = 0;
229 offset = (int)
230 ((char *)pm8001_ha->forensic_info.data_buf.direct_data
231 - (char *)buf);
232 pm8001_dbg(pm8001_ha, IO,
233 "get_fatal_spcv:return1 0x%x\n", offset);
234 return (char *)pm8001_ha->
235 forensic_info.data_buf.direct_data -
236 (char *)buf;
237 }
238 if (pm8001_ha->fatal_bar_loc < (64 * 1024)) {
239 pm8001_ha->forensic_info.data_buf.direct_data +=
240 sprintf(pm8001_ha->
241 forensic_info.data_buf.direct_data,
242 "%08x ", 2);
243 for (index = 0; index <
244 (pm8001_ha->forensic_info.data_buf.direct_len
245 / 4); index++) {
246 pm8001_ha->forensic_info.data_buf.direct_data
247 += sprintf(pm8001_ha->
248 forensic_info.data_buf.direct_data,
249 "%08x ", *(temp + index));
250 }
251 status = 0;
252 offset = (int)
253 ((char *)pm8001_ha->forensic_info.data_buf.direct_data
254 - (char *)buf);
255 pm8001_dbg(pm8001_ha, IO,
256 "get_fatal_spcv:return2 0x%x\n", offset);
257 return (char *)pm8001_ha->
258 forensic_info.data_buf.direct_data -
259 (char *)buf;
260 }
261
262 /* Increment the MEMBASE II Shifting Register value by 0x100.*/
263 pm8001_ha->forensic_info.data_buf.direct_data +=
264 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
265 "%08x ", 2);
266 for (index = 0; index <
267 (pm8001_ha->forensic_info.data_buf.direct_len
268 / 4) ; index++) {
269 pm8001_ha->forensic_info.data_buf.direct_data +=
270 sprintf(pm8001_ha->
271 forensic_info.data_buf.direct_data,
272 "%08x ", *(temp + index));
273 }
274 pm8001_ha->fatal_forensic_shift_offset += 0x100;
275 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
276 pm8001_ha->fatal_forensic_shift_offset);
277 pm8001_ha->fatal_bar_loc = 0;
278 status = 0;
279 offset = (int)
280 ((char *)pm8001_ha->forensic_info.data_buf.direct_data
281 - (char *)buf);
282 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: return3 0x%x\n",
283 offset);
284 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
285 (char *)buf;
286 }
287 if (pm8001_ha->forensic_fatal_step == 1) {
288 /* store previous accumulated length before triggering next
289 * accumulated length update
290 */
291 pm8001_ha->forensic_preserved_accumulated_transfer =
292 pm8001_mr32(fatal_table_address,
293 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN);
294
295 /* continue capturing the fatal log until Dump status is 0x3 */
296 if (pm8001_mr32(fatal_table_address,
297 MPI_FATAL_EDUMP_TABLE_STATUS) <
298 MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) {
299
300 /* reset fddstat bit by writing to zero*/
301 pm8001_mw32(fatal_table_address,
302 MPI_FATAL_EDUMP_TABLE_STATUS, 0x0);
303
304 /* set dump control value to '1' so that new data will
305 * be transferred to shared memory
306 */
307 pm8001_mw32(fatal_table_address,
308 MPI_FATAL_EDUMP_TABLE_HANDSHAKE,
309 MPI_FATAL_EDUMP_HANDSHAKE_RDY);
310
311 /*Poll FDDHSHK until clear */
312 start = jiffies + (2 * HZ); /* 2 sec */
313
314 do {
315 reg_val = pm8001_mr32(fatal_table_address,
316 MPI_FATAL_EDUMP_TABLE_HANDSHAKE);
317 } while ((reg_val) && time_before(jiffies, start));
318
319 if (reg_val != 0) {
320 pm8001_dbg(pm8001_ha, FAIL,
321 "TIMEOUT:MPI_FATAL_EDUMP_TABLE_HDSHAKE 0x%x\n",
322 reg_val);
323 /* Fail the dump if a timeout occurs */
324 pm8001_ha->forensic_info.data_buf.direct_data +=
325 sprintf(
326 pm8001_ha->forensic_info.data_buf.direct_data,
327 "%08x ", 0xFFFFFFFF);
328 return((char *)
329 pm8001_ha->forensic_info.data_buf.direct_data
330 - (char *)buf);
331 }
332 /* Poll status register until set to 2 or
333 * 3 for up to 2 seconds
334 */
335 start = jiffies + (2 * HZ); /* 2 sec */
336
337 do {
338 reg_val = pm8001_mr32(fatal_table_address,
339 MPI_FATAL_EDUMP_TABLE_STATUS);
340 } while (((reg_val != 2) && (reg_val != 3)) &&
341 time_before(jiffies, start));
342
343 if (reg_val < 2) {
344 pm8001_dbg(pm8001_ha, FAIL,
345 "TIMEOUT:MPI_FATAL_EDUMP_TABLE_STATUS = 0x%x\n",
346 reg_val);
347 /* Fail the dump if a timeout occurs */
348 pm8001_ha->forensic_info.data_buf.direct_data +=
349 sprintf(
350 pm8001_ha->forensic_info.data_buf.direct_data,
351 "%08x ", 0xFFFFFFFF);
352 pm8001_cw32(pm8001_ha, 0,
353 MEMBASE_II_SHIFT_REGISTER,
354 pm8001_ha->fatal_forensic_shift_offset);
355 }
356 /* Read the next block of the debug data.*/
357 length_to_read = pm8001_mr32(fatal_table_address,
358 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN) -
359 pm8001_ha->forensic_preserved_accumulated_transfer;
360 if (length_to_read != 0x0) {
361 pm8001_ha->forensic_fatal_step = 0;
362 goto moreData;
363 } else {
364 pm8001_ha->forensic_info.data_buf.direct_data +=
365 sprintf(
366 pm8001_ha->forensic_info.data_buf.direct_data,
367 "%08x ", 4);
368 pm8001_ha->forensic_info.data_buf.read_len
369 = 0xFFFFFFFF;
370 pm8001_ha->forensic_info.data_buf.direct_len
371 = 0;
372 pm8001_ha->forensic_info.data_buf.direct_offset
373 = 0;
374 pm8001_ha->forensic_info.data_buf.read_len = 0;
375 }
376 }
377 }
378 offset = (int)((char *)pm8001_ha->forensic_info.data_buf.direct_data
379 - (char *)buf);
380 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: return4 0x%x\n", offset);
381 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
382 (char *)buf;
383 }
384
385 /* pm80xx_get_non_fatal_dump - dump the nonfatal data from the dma
386 * location by the firmware.
387 */
pm80xx_get_non_fatal_dump(struct device * cdev,struct device_attribute * attr,char * buf)388 ssize_t pm80xx_get_non_fatal_dump(struct device *cdev,
389 struct device_attribute *attr, char *buf)
390 {
391 struct Scsi_Host *shost = class_to_shost(cdev);
392 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
393 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
394 void __iomem *nonfatal_table_address = pm8001_ha->fatal_tbl_addr;
395 u32 accum_len = 0;
396 u32 total_len = 0;
397 u32 reg_val = 0;
398 u32 *temp = NULL;
399 u32 index = 0;
400 u32 output_length;
401 unsigned long start = 0;
402 char *buf_copy = buf;
403
404 temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr;
405 if (++pm8001_ha->non_fatal_count == 1) {
406 if (pm8001_ha->chip_id == chip_8001) {
407 snprintf(pm8001_ha->forensic_info.data_buf.direct_data,
408 PAGE_SIZE, "Not supported for SPC controller");
409 return 0;
410 }
411 pm8001_dbg(pm8001_ha, IO, "forensic_info TYPE_NON_FATAL...\n");
412 /*
413 * Step 1: Write the host buffer parameters in the MPI Fatal and
414 * Non-Fatal Error Dump Capture Table.This is the buffer
415 * where debug data will be DMAed to.
416 */
417 pm8001_mw32(nonfatal_table_address,
418 MPI_FATAL_EDUMP_TABLE_LO_OFFSET,
419 pm8001_ha->memoryMap.region[FORENSIC_MEM].phys_addr_lo);
420
421 pm8001_mw32(nonfatal_table_address,
422 MPI_FATAL_EDUMP_TABLE_HI_OFFSET,
423 pm8001_ha->memoryMap.region[FORENSIC_MEM].phys_addr_hi);
424
425 pm8001_mw32(nonfatal_table_address,
426 MPI_FATAL_EDUMP_TABLE_LENGTH, SYSFS_OFFSET);
427
428 /* Optionally, set the DUMPCTRL bit to 1 if the host
429 * keeps sending active I/Os while capturing the non-fatal
430 * debug data. Otherwise, leave this bit set to zero
431 */
432 pm8001_mw32(nonfatal_table_address,
433 MPI_FATAL_EDUMP_TABLE_HANDSHAKE, MPI_FATAL_EDUMP_HANDSHAKE_RDY);
434
435 /*
436 * Step 2: Clear Accumulative Length of Debug Data Transferred
437 * [ACCDDLEN] field in the MPI Fatal and Non-Fatal Error Dump
438 * Capture Table to zero.
439 */
440 pm8001_mw32(nonfatal_table_address,
441 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN, 0);
442
443 /* initiallize previous accumulated length to 0 */
444 pm8001_ha->forensic_preserved_accumulated_transfer = 0;
445 pm8001_ha->non_fatal_read_length = 0;
446 }
447
448 total_len = pm8001_mr32(nonfatal_table_address,
449 MPI_FATAL_EDUMP_TABLE_TOTAL_LEN);
450 /*
451 * Step 3:Clear Fatal/Non-Fatal Debug Data Transfer Status [FDDTSTAT]
452 * field and then request that the SPCv controller transfer the debug
453 * data by setting bit 7 of the Inbound Doorbell Set Register.
454 */
455 pm8001_mw32(nonfatal_table_address, MPI_FATAL_EDUMP_TABLE_STATUS, 0);
456 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET,
457 SPCv_MSGU_CFG_TABLE_NONFATAL_DUMP);
458
459 /*
460 * Step 4.1: Read back the Inbound Doorbell Set Register (by polling for
461 * 2 seconds) until register bit 7 is cleared.
462 * This step only indicates the request is accepted by the controller.
463 */
464 start = jiffies + (2 * HZ); /* 2 sec */
465 do {
466 reg_val = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET) &
467 SPCv_MSGU_CFG_TABLE_NONFATAL_DUMP;
468 } while ((reg_val != 0) && time_before(jiffies, start));
469
470 /* Step 4.2: To check the completion of the transfer, poll the Fatal/Non
471 * Fatal Debug Data Transfer Status [FDDTSTAT] field for 2 seconds in
472 * the MPI Fatal and Non-Fatal Error Dump Capture Table.
473 */
474 start = jiffies + (2 * HZ); /* 2 sec */
475 do {
476 reg_val = pm8001_mr32(nonfatal_table_address,
477 MPI_FATAL_EDUMP_TABLE_STATUS);
478 } while ((!reg_val) && time_before(jiffies, start));
479
480 if ((reg_val == 0x00) ||
481 (reg_val == MPI_FATAL_EDUMP_TABLE_STAT_DMA_FAILED) ||
482 (reg_val > MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE)) {
483 pm8001_ha->non_fatal_read_length = 0;
484 buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 0xFFFFFFFF);
485 pm8001_ha->non_fatal_count = 0;
486 return (buf_copy - buf);
487 } else if (reg_val ==
488 MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_MORE_DATA) {
489 buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 2);
490 } else if ((reg_val == MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) ||
491 (pm8001_ha->non_fatal_read_length >= total_len)) {
492 pm8001_ha->non_fatal_read_length = 0;
493 buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 4);
494 pm8001_ha->non_fatal_count = 0;
495 }
496 accum_len = pm8001_mr32(nonfatal_table_address,
497 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN);
498 output_length = accum_len -
499 pm8001_ha->forensic_preserved_accumulated_transfer;
500
501 for (index = 0; index < output_length/4; index++)
502 buf_copy += snprintf(buf_copy, PAGE_SIZE,
503 "%08x ", *(temp+index));
504
505 pm8001_ha->non_fatal_read_length += output_length;
506
507 /* store current accumulated length to use in next iteration as
508 * the previous accumulated length
509 */
510 pm8001_ha->forensic_preserved_accumulated_transfer = accum_len;
511 return (buf_copy - buf);
512 }
513
514 /**
515 * read_main_config_table - read the configure table and save it.
516 * @pm8001_ha: our hba card information
517 */
read_main_config_table(struct pm8001_hba_info * pm8001_ha)518 static void read_main_config_table(struct pm8001_hba_info *pm8001_ha)
519 {
520 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
521
522 pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature =
523 pm8001_mr32(address, MAIN_SIGNATURE_OFFSET);
524 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev =
525 pm8001_mr32(address, MAIN_INTERFACE_REVISION);
526 pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev =
527 pm8001_mr32(address, MAIN_FW_REVISION);
528 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io =
529 pm8001_mr32(address, MAIN_MAX_OUTSTANDING_IO_OFFSET);
530 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_sgl =
531 pm8001_mr32(address, MAIN_MAX_SGL_OFFSET);
532 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ctrl_cap_flag =
533 pm8001_mr32(address, MAIN_CNTRL_CAP_OFFSET);
534 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset =
535 pm8001_mr32(address, MAIN_GST_OFFSET);
536 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset =
537 pm8001_mr32(address, MAIN_IBQ_OFFSET);
538 pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset =
539 pm8001_mr32(address, MAIN_OBQ_OFFSET);
540
541 /* read Error Dump Offset and Length */
542 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset0 =
543 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
544 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length0 =
545 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
546 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset1 =
547 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
548 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length1 =
549 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
550
551 /* read GPIO LED settings from the configuration table */
552 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping =
553 pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET);
554
555 /* read analog Setting offset from the configuration table */
556 pm8001_ha->main_cfg_tbl.pm80xx_tbl.analog_setup_table_offset =
557 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
558
559 pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset =
560 pm8001_mr32(address, MAIN_INT_VECTOR_TABLE_OFFSET);
561 pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset =
562 pm8001_mr32(address, MAIN_SAS_PHY_ATTR_TABLE_OFFSET);
563 /* read port recover and reset timeout */
564 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer =
565 pm8001_mr32(address, MAIN_PORT_RECOVERY_TIMER);
566 /* read ILA and inactive firmware version */
567 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ila_version =
568 pm8001_mr32(address, MAIN_MPI_ILA_RELEASE_TYPE);
569 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inc_fw_version =
570 pm8001_mr32(address, MAIN_MPI_INACTIVE_FW_VERSION);
571
572 pm8001_dbg(pm8001_ha, DEV,
573 "Main cfg table: sign:%x interface rev:%x fw_rev:%x\n",
574 pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature,
575 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev,
576 pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev);
577
578 pm8001_dbg(pm8001_ha, DEV,
579 "table offset: gst:%x iq:%x oq:%x int vec:%x phy attr:%x\n",
580 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset,
581 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset,
582 pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset,
583 pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset,
584 pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset);
585
586 pm8001_dbg(pm8001_ha, DEV,
587 "Main cfg table; ila rev:%x Inactive fw rev:%x\n",
588 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ila_version,
589 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inc_fw_version);
590 }
591
592 /**
593 * read_general_status_table - read the general status table and save it.
594 * @pm8001_ha: our hba card information
595 */
read_general_status_table(struct pm8001_hba_info * pm8001_ha)596 static void read_general_status_table(struct pm8001_hba_info *pm8001_ha)
597 {
598 void __iomem *address = pm8001_ha->general_stat_tbl_addr;
599 pm8001_ha->gs_tbl.pm80xx_tbl.gst_len_mpistate =
600 pm8001_mr32(address, GST_GSTLEN_MPIS_OFFSET);
601 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state0 =
602 pm8001_mr32(address, GST_IQ_FREEZE_STATE0_OFFSET);
603 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state1 =
604 pm8001_mr32(address, GST_IQ_FREEZE_STATE1_OFFSET);
605 pm8001_ha->gs_tbl.pm80xx_tbl.msgu_tcnt =
606 pm8001_mr32(address, GST_MSGUTCNT_OFFSET);
607 pm8001_ha->gs_tbl.pm80xx_tbl.iop_tcnt =
608 pm8001_mr32(address, GST_IOPTCNT_OFFSET);
609 pm8001_ha->gs_tbl.pm80xx_tbl.gpio_input_val =
610 pm8001_mr32(address, GST_GPIO_INPUT_VAL);
611 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[0] =
612 pm8001_mr32(address, GST_RERRINFO_OFFSET0);
613 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[1] =
614 pm8001_mr32(address, GST_RERRINFO_OFFSET1);
615 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[2] =
616 pm8001_mr32(address, GST_RERRINFO_OFFSET2);
617 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[3] =
618 pm8001_mr32(address, GST_RERRINFO_OFFSET3);
619 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[4] =
620 pm8001_mr32(address, GST_RERRINFO_OFFSET4);
621 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[5] =
622 pm8001_mr32(address, GST_RERRINFO_OFFSET5);
623 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[6] =
624 pm8001_mr32(address, GST_RERRINFO_OFFSET6);
625 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[7] =
626 pm8001_mr32(address, GST_RERRINFO_OFFSET7);
627 }
628 /**
629 * read_phy_attr_table - read the phy attribute table and save it.
630 * @pm8001_ha: our hba card information
631 */
read_phy_attr_table(struct pm8001_hba_info * pm8001_ha)632 static void read_phy_attr_table(struct pm8001_hba_info *pm8001_ha)
633 {
634 void __iomem *address = pm8001_ha->pspa_q_tbl_addr;
635 pm8001_ha->phy_attr_table.phystart1_16[0] =
636 pm8001_mr32(address, PSPA_PHYSTATE0_OFFSET);
637 pm8001_ha->phy_attr_table.phystart1_16[1] =
638 pm8001_mr32(address, PSPA_PHYSTATE1_OFFSET);
639 pm8001_ha->phy_attr_table.phystart1_16[2] =
640 pm8001_mr32(address, PSPA_PHYSTATE2_OFFSET);
641 pm8001_ha->phy_attr_table.phystart1_16[3] =
642 pm8001_mr32(address, PSPA_PHYSTATE3_OFFSET);
643 pm8001_ha->phy_attr_table.phystart1_16[4] =
644 pm8001_mr32(address, PSPA_PHYSTATE4_OFFSET);
645 pm8001_ha->phy_attr_table.phystart1_16[5] =
646 pm8001_mr32(address, PSPA_PHYSTATE5_OFFSET);
647 pm8001_ha->phy_attr_table.phystart1_16[6] =
648 pm8001_mr32(address, PSPA_PHYSTATE6_OFFSET);
649 pm8001_ha->phy_attr_table.phystart1_16[7] =
650 pm8001_mr32(address, PSPA_PHYSTATE7_OFFSET);
651 pm8001_ha->phy_attr_table.phystart1_16[8] =
652 pm8001_mr32(address, PSPA_PHYSTATE8_OFFSET);
653 pm8001_ha->phy_attr_table.phystart1_16[9] =
654 pm8001_mr32(address, PSPA_PHYSTATE9_OFFSET);
655 pm8001_ha->phy_attr_table.phystart1_16[10] =
656 pm8001_mr32(address, PSPA_PHYSTATE10_OFFSET);
657 pm8001_ha->phy_attr_table.phystart1_16[11] =
658 pm8001_mr32(address, PSPA_PHYSTATE11_OFFSET);
659 pm8001_ha->phy_attr_table.phystart1_16[12] =
660 pm8001_mr32(address, PSPA_PHYSTATE12_OFFSET);
661 pm8001_ha->phy_attr_table.phystart1_16[13] =
662 pm8001_mr32(address, PSPA_PHYSTATE13_OFFSET);
663 pm8001_ha->phy_attr_table.phystart1_16[14] =
664 pm8001_mr32(address, PSPA_PHYSTATE14_OFFSET);
665 pm8001_ha->phy_attr_table.phystart1_16[15] =
666 pm8001_mr32(address, PSPA_PHYSTATE15_OFFSET);
667
668 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[0] =
669 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID0_OFFSET);
670 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[1] =
671 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID1_OFFSET);
672 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[2] =
673 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID2_OFFSET);
674 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[3] =
675 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID3_OFFSET);
676 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[4] =
677 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID4_OFFSET);
678 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[5] =
679 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID5_OFFSET);
680 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[6] =
681 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID6_OFFSET);
682 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[7] =
683 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID7_OFFSET);
684 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[8] =
685 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID8_OFFSET);
686 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[9] =
687 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID9_OFFSET);
688 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[10] =
689 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID10_OFFSET);
690 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[11] =
691 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID11_OFFSET);
692 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[12] =
693 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID12_OFFSET);
694 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[13] =
695 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID13_OFFSET);
696 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[14] =
697 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID14_OFFSET);
698 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[15] =
699 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID15_OFFSET);
700
701 }
702
703 /**
704 * read_inbnd_queue_table - read the inbound queue table and save it.
705 * @pm8001_ha: our hba card information
706 */
read_inbnd_queue_table(struct pm8001_hba_info * pm8001_ha)707 static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
708 {
709 int i;
710 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
711 for (i = 0; i < PM8001_MAX_INB_NUM; i++) {
712 u32 offset = i * 0x20;
713 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
714 get_pci_bar_index(pm8001_mr32(address,
715 (offset + IB_PIPCI_BAR)));
716 pm8001_ha->inbnd_q_tbl[i].pi_offset =
717 pm8001_mr32(address, (offset + IB_PIPCI_BAR_OFFSET));
718 }
719 }
720
721 /**
722 * read_outbnd_queue_table - read the outbound queue table and save it.
723 * @pm8001_ha: our hba card information
724 */
read_outbnd_queue_table(struct pm8001_hba_info * pm8001_ha)725 static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
726 {
727 int i;
728 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
729 for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) {
730 u32 offset = i * 0x24;
731 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
732 get_pci_bar_index(pm8001_mr32(address,
733 (offset + OB_CIPCI_BAR)));
734 pm8001_ha->outbnd_q_tbl[i].ci_offset =
735 pm8001_mr32(address, (offset + OB_CIPCI_BAR_OFFSET));
736 }
737 }
738
739 /**
740 * init_default_table_values - init the default table.
741 * @pm8001_ha: our hba card information
742 */
init_default_table_values(struct pm8001_hba_info * pm8001_ha)743 static void init_default_table_values(struct pm8001_hba_info *pm8001_ha)
744 {
745 int i;
746 u32 offsetib, offsetob;
747 void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
748 void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
749 u32 ib_offset = pm8001_ha->ib_offset;
750 u32 ob_offset = pm8001_ha->ob_offset;
751 u32 ci_offset = pm8001_ha->ci_offset;
752 u32 pi_offset = pm8001_ha->pi_offset;
753
754 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr =
755 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
756 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr =
757 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
758 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size =
759 PM8001_EVENT_LOG_SIZE;
760 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity = 0x01;
761 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr =
762 pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
763 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr =
764 pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
765 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size =
766 PM8001_EVENT_LOG_SIZE;
767 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity = 0x01;
768 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt = 0x01;
769
770 /* Disable end to end CRC checking */
771 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump = (0x1 << 16);
772
773 for (i = 0; i < pm8001_ha->max_q_num; i++) {
774 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt =
775 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30);
776 pm8001_ha->inbnd_q_tbl[i].upper_base_addr =
777 pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_hi;
778 pm8001_ha->inbnd_q_tbl[i].lower_base_addr =
779 pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_lo;
780 pm8001_ha->inbnd_q_tbl[i].base_virt =
781 (u8 *)pm8001_ha->memoryMap.region[ib_offset + i].virt_ptr;
782 pm8001_ha->inbnd_q_tbl[i].total_length =
783 pm8001_ha->memoryMap.region[ib_offset + i].total_len;
784 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr =
785 pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_hi;
786 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr =
787 pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_lo;
788 pm8001_ha->inbnd_q_tbl[i].ci_virt =
789 pm8001_ha->memoryMap.region[ci_offset + i].virt_ptr;
790 offsetib = i * 0x20;
791 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
792 get_pci_bar_index(pm8001_mr32(addressib,
793 (offsetib + 0x14)));
794 pm8001_ha->inbnd_q_tbl[i].pi_offset =
795 pm8001_mr32(addressib, (offsetib + 0x18));
796 pm8001_ha->inbnd_q_tbl[i].producer_idx = 0;
797 pm8001_ha->inbnd_q_tbl[i].consumer_index = 0;
798
799 pm8001_dbg(pm8001_ha, DEV,
800 "IQ %d pi_bar 0x%x pi_offset 0x%x\n", i,
801 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar,
802 pm8001_ha->inbnd_q_tbl[i].pi_offset);
803 }
804 for (i = 0; i < pm8001_ha->max_q_num; i++) {
805 pm8001_ha->outbnd_q_tbl[i].element_size_cnt =
806 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30);
807 pm8001_ha->outbnd_q_tbl[i].upper_base_addr =
808 pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_hi;
809 pm8001_ha->outbnd_q_tbl[i].lower_base_addr =
810 pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_lo;
811 pm8001_ha->outbnd_q_tbl[i].base_virt =
812 (u8 *)pm8001_ha->memoryMap.region[ob_offset + i].virt_ptr;
813 pm8001_ha->outbnd_q_tbl[i].total_length =
814 pm8001_ha->memoryMap.region[ob_offset + i].total_len;
815 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr =
816 pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_hi;
817 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr =
818 pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_lo;
819 /* interrupt vector based on oq */
820 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay = (i << 24);
821 pm8001_ha->outbnd_q_tbl[i].pi_virt =
822 pm8001_ha->memoryMap.region[pi_offset + i].virt_ptr;
823 offsetob = i * 0x24;
824 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
825 get_pci_bar_index(pm8001_mr32(addressob,
826 offsetob + 0x14));
827 pm8001_ha->outbnd_q_tbl[i].ci_offset =
828 pm8001_mr32(addressob, (offsetob + 0x18));
829 pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0;
830 pm8001_ha->outbnd_q_tbl[i].producer_index = 0;
831
832 pm8001_dbg(pm8001_ha, DEV,
833 "OQ %d ci_bar 0x%x ci_offset 0x%x\n", i,
834 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar,
835 pm8001_ha->outbnd_q_tbl[i].ci_offset);
836 }
837 }
838
839 /**
840 * update_main_config_table - update the main default table to the HBA.
841 * @pm8001_ha: our hba card information
842 */
update_main_config_table(struct pm8001_hba_info * pm8001_ha)843 static void update_main_config_table(struct pm8001_hba_info *pm8001_ha)
844 {
845 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
846 pm8001_mw32(address, MAIN_IQNPPD_HPPD_OFFSET,
847 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_q_nppd_hppd);
848 pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_HI,
849 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr);
850 pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_LO,
851 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr);
852 pm8001_mw32(address, MAIN_EVENT_LOG_BUFF_SIZE,
853 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size);
854 pm8001_mw32(address, MAIN_EVENT_LOG_OPTION,
855 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity);
856 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_HI,
857 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr);
858 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_LO,
859 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr);
860 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_BUFF_SIZE,
861 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size);
862 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_OPTION,
863 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity);
864 /* Update Fatal error interrupt vector */
865 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt |=
866 ((pm8001_ha->max_q_num - 1) << 8);
867 pm8001_mw32(address, MAIN_FATAL_ERROR_INTERRUPT,
868 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt);
869 pm8001_dbg(pm8001_ha, DEV,
870 "Updated Fatal error interrupt vector 0x%x\n",
871 pm8001_mr32(address, MAIN_FATAL_ERROR_INTERRUPT));
872
873 pm8001_mw32(address, MAIN_EVENT_CRC_CHECK,
874 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump);
875
876 /* SPCv specific */
877 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping &= 0xCFFFFFFF;
878 /* Set GPIOLED to 0x2 for LED indicator */
879 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping |= 0x20000000;
880 pm8001_mw32(address, MAIN_GPIO_LED_FLAGS_OFFSET,
881 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping);
882 pm8001_dbg(pm8001_ha, DEV,
883 "Programming DW 0x21 in main cfg table with 0x%x\n",
884 pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET));
885
886 pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER,
887 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer);
888 pm8001_mw32(address, MAIN_INT_REASSERTION_DELAY,
889 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interrupt_reassertion_delay);
890
891 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &= 0xffff0000;
892 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |=
893 PORT_RECOVERY_TIMEOUT;
894 if (pm8001_ha->chip_id == chip_8006) {
895 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &=
896 0x0000ffff;
897 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |=
898 CHIP_8006_PORT_RECOVERY_TIMEOUT;
899 }
900 pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER,
901 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer);
902 }
903
904 /**
905 * update_inbnd_queue_table - update the inbound queue table to the HBA.
906 * @pm8001_ha: our hba card information
907 * @number: entry in the queue
908 */
update_inbnd_queue_table(struct pm8001_hba_info * pm8001_ha,int number)909 static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
910 int number)
911 {
912 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
913 u16 offset = number * 0x20;
914 pm8001_mw32(address, offset + IB_PROPERITY_OFFSET,
915 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
916 pm8001_mw32(address, offset + IB_BASE_ADDR_HI_OFFSET,
917 pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
918 pm8001_mw32(address, offset + IB_BASE_ADDR_LO_OFFSET,
919 pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
920 pm8001_mw32(address, offset + IB_CI_BASE_ADDR_HI_OFFSET,
921 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
922 pm8001_mw32(address, offset + IB_CI_BASE_ADDR_LO_OFFSET,
923 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
924
925 pm8001_dbg(pm8001_ha, DEV,
926 "IQ %d: Element pri size 0x%x\n",
927 number,
928 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
929
930 pm8001_dbg(pm8001_ha, DEV,
931 "IQ upr base addr 0x%x IQ lwr base addr 0x%x\n",
932 pm8001_ha->inbnd_q_tbl[number].upper_base_addr,
933 pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
934
935 pm8001_dbg(pm8001_ha, DEV,
936 "CI upper base addr 0x%x CI lower base addr 0x%x\n",
937 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr,
938 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
939 }
940
941 /**
942 * update_outbnd_queue_table - update the outbound queue table to the HBA.
943 * @pm8001_ha: our hba card information
944 * @number: entry in the queue
945 */
update_outbnd_queue_table(struct pm8001_hba_info * pm8001_ha,int number)946 static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
947 int number)
948 {
949 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
950 u16 offset = number * 0x24;
951 pm8001_mw32(address, offset + OB_PROPERITY_OFFSET,
952 pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
953 pm8001_mw32(address, offset + OB_BASE_ADDR_HI_OFFSET,
954 pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
955 pm8001_mw32(address, offset + OB_BASE_ADDR_LO_OFFSET,
956 pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
957 pm8001_mw32(address, offset + OB_PI_BASE_ADDR_HI_OFFSET,
958 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
959 pm8001_mw32(address, offset + OB_PI_BASE_ADDR_LO_OFFSET,
960 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
961 pm8001_mw32(address, offset + OB_INTERRUPT_COALES_OFFSET,
962 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
963
964 pm8001_dbg(pm8001_ha, DEV,
965 "OQ %d: Element pri size 0x%x\n",
966 number,
967 pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
968
969 pm8001_dbg(pm8001_ha, DEV,
970 "OQ upr base addr 0x%x OQ lwr base addr 0x%x\n",
971 pm8001_ha->outbnd_q_tbl[number].upper_base_addr,
972 pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
973
974 pm8001_dbg(pm8001_ha, DEV,
975 "PI upper base addr 0x%x PI lower base addr 0x%x\n",
976 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr,
977 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
978 }
979
980 /**
981 * mpi_init_check - check firmware initialization status.
982 * @pm8001_ha: our hba card information
983 */
mpi_init_check(struct pm8001_hba_info * pm8001_ha)984 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
985 {
986 u32 max_wait_count;
987 u32 value;
988 u32 gst_len_mpistate;
989
990 /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
991 table is updated */
992 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_UPDATE);
993 /* wait until Inbound DoorBell Clear Register toggled */
994 if (IS_SPCV_12G(pm8001_ha->pdev)) {
995 max_wait_count = SPCV_DOORBELL_CLEAR_TIMEOUT;
996 } else {
997 max_wait_count = SPC_DOORBELL_CLEAR_TIMEOUT;
998 }
999 do {
1000 udelay(1);
1001 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
1002 value &= SPCv_MSGU_CFG_TABLE_UPDATE;
1003 } while ((value != 0) && (--max_wait_count));
1004
1005 if (!max_wait_count) {
1006 /* additional check */
1007 pm8001_dbg(pm8001_ha, FAIL,
1008 "Inb doorbell clear not toggled[value:%x]\n",
1009 value);
1010 return -EBUSY;
1011 }
1012 /* check the MPI-State for initialization upto 100ms*/
1013 max_wait_count = 100 * 1000;/* 100 msec */
1014 do {
1015 udelay(1);
1016 gst_len_mpistate =
1017 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
1018 GST_GSTLEN_MPIS_OFFSET);
1019 } while ((GST_MPI_STATE_INIT !=
1020 (gst_len_mpistate & GST_MPI_STATE_MASK)) && (--max_wait_count));
1021 if (!max_wait_count)
1022 return -EBUSY;
1023
1024 /* check MPI Initialization error */
1025 gst_len_mpistate = gst_len_mpistate >> 16;
1026 if (0x0000 != gst_len_mpistate)
1027 return -EBUSY;
1028
1029 return 0;
1030 }
1031
1032 /**
1033 * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
1034 * @pm8001_ha: our hba card information
1035 */
check_fw_ready(struct pm8001_hba_info * pm8001_ha)1036 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
1037 {
1038 u32 value;
1039 u32 max_wait_count;
1040 u32 max_wait_time;
1041 int ret = 0;
1042
1043 /* reset / PCIe ready */
1044 max_wait_time = max_wait_count = 100 * 1000; /* 100 milli sec */
1045 do {
1046 udelay(1);
1047 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1048 } while ((value == 0xFFFFFFFF) && (--max_wait_count));
1049
1050 /* check ila status */
1051 max_wait_time = max_wait_count = 1000 * 1000; /* 1000 milli sec */
1052 do {
1053 udelay(1);
1054 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1055 } while (((value & SCRATCH_PAD_ILA_READY) !=
1056 SCRATCH_PAD_ILA_READY) && (--max_wait_count));
1057 if (!max_wait_count)
1058 ret = -1;
1059 else {
1060 pm8001_dbg(pm8001_ha, MSG,
1061 " ila ready status in %d millisec\n",
1062 (max_wait_time - max_wait_count));
1063 }
1064
1065 /* check RAAE status */
1066 max_wait_time = max_wait_count = 1800 * 1000; /* 1800 milli sec */
1067 do {
1068 udelay(1);
1069 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1070 } while (((value & SCRATCH_PAD_RAAE_READY) !=
1071 SCRATCH_PAD_RAAE_READY) && (--max_wait_count));
1072 if (!max_wait_count)
1073 ret = -1;
1074 else {
1075 pm8001_dbg(pm8001_ha, MSG,
1076 " raae ready status in %d millisec\n",
1077 (max_wait_time - max_wait_count));
1078 }
1079
1080 /* check iop0 status */
1081 max_wait_time = max_wait_count = 600 * 1000; /* 600 milli sec */
1082 do {
1083 udelay(1);
1084 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1085 } while (((value & SCRATCH_PAD_IOP0_READY) != SCRATCH_PAD_IOP0_READY) &&
1086 (--max_wait_count));
1087 if (!max_wait_count)
1088 ret = -1;
1089 else {
1090 pm8001_dbg(pm8001_ha, MSG,
1091 " iop0 ready status in %d millisec\n",
1092 (max_wait_time - max_wait_count));
1093 }
1094
1095 /* check iop1 status only for 16 port controllers */
1096 if ((pm8001_ha->chip_id != chip_8008) &&
1097 (pm8001_ha->chip_id != chip_8009)) {
1098 /* 200 milli sec */
1099 max_wait_time = max_wait_count = 200 * 1000;
1100 do {
1101 udelay(1);
1102 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1103 } while (((value & SCRATCH_PAD_IOP1_READY) !=
1104 SCRATCH_PAD_IOP1_READY) && (--max_wait_count));
1105 if (!max_wait_count)
1106 ret = -1;
1107 else {
1108 pm8001_dbg(pm8001_ha, MSG,
1109 "iop1 ready status in %d millisec\n",
1110 (max_wait_time - max_wait_count));
1111 }
1112 }
1113
1114 return ret;
1115 }
1116
init_pci_device_addresses(struct pm8001_hba_info * pm8001_ha)1117 static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
1118 {
1119 void __iomem *base_addr;
1120 u32 value;
1121 u32 offset;
1122 u32 pcibar;
1123 u32 pcilogic;
1124
1125 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
1126 offset = value & 0x03FFFFFF; /* scratch pad 0 TBL address */
1127
1128 pm8001_dbg(pm8001_ha, DEV, "Scratchpad 0 Offset: 0x%x value 0x%x\n",
1129 offset, value);
1130 pcilogic = (value & 0xFC000000) >> 26;
1131 pcibar = get_pci_bar_index(pcilogic);
1132 pm8001_dbg(pm8001_ha, INIT, "Scratchpad 0 PCI BAR: %d\n", pcibar);
1133 pm8001_ha->main_cfg_tbl_addr = base_addr =
1134 pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
1135 pm8001_ha->general_stat_tbl_addr =
1136 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x18) &
1137 0xFFFFFF);
1138 pm8001_ha->inbnd_q_tbl_addr =
1139 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C) &
1140 0xFFFFFF);
1141 pm8001_ha->outbnd_q_tbl_addr =
1142 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x20) &
1143 0xFFFFFF);
1144 pm8001_ha->ivt_tbl_addr =
1145 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C) &
1146 0xFFFFFF);
1147 pm8001_ha->pspa_q_tbl_addr =
1148 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x90) &
1149 0xFFFFFF);
1150 pm8001_ha->fatal_tbl_addr =
1151 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0xA0) &
1152 0xFFFFFF);
1153
1154 pm8001_dbg(pm8001_ha, INIT, "GST OFFSET 0x%x\n",
1155 pm8001_cr32(pm8001_ha, pcibar, offset + 0x18));
1156 pm8001_dbg(pm8001_ha, INIT, "INBND OFFSET 0x%x\n",
1157 pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C));
1158 pm8001_dbg(pm8001_ha, INIT, "OBND OFFSET 0x%x\n",
1159 pm8001_cr32(pm8001_ha, pcibar, offset + 0x20));
1160 pm8001_dbg(pm8001_ha, INIT, "IVT OFFSET 0x%x\n",
1161 pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C));
1162 pm8001_dbg(pm8001_ha, INIT, "PSPA OFFSET 0x%x\n",
1163 pm8001_cr32(pm8001_ha, pcibar, offset + 0x90));
1164 pm8001_dbg(pm8001_ha, INIT, "addr - main cfg %p general status %p\n",
1165 pm8001_ha->main_cfg_tbl_addr,
1166 pm8001_ha->general_stat_tbl_addr);
1167 pm8001_dbg(pm8001_ha, INIT, "addr - inbnd %p obnd %p\n",
1168 pm8001_ha->inbnd_q_tbl_addr,
1169 pm8001_ha->outbnd_q_tbl_addr);
1170 pm8001_dbg(pm8001_ha, INIT, "addr - pspa %p ivt %p\n",
1171 pm8001_ha->pspa_q_tbl_addr,
1172 pm8001_ha->ivt_tbl_addr);
1173 }
1174
1175 /**
1176 * pm80xx_set_thermal_config - support the thermal configuration
1177 * @pm8001_ha: our hba card information.
1178 */
1179 int
pm80xx_set_thermal_config(struct pm8001_hba_info * pm8001_ha)1180 pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha)
1181 {
1182 struct set_ctrl_cfg_req payload;
1183 struct inbound_queue_table *circularQ;
1184 int rc;
1185 u32 tag;
1186 u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
1187 u32 page_code;
1188
1189 memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
1190 rc = pm8001_tag_alloc(pm8001_ha, &tag);
1191 if (rc)
1192 return -1;
1193
1194 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1195 payload.tag = cpu_to_le32(tag);
1196
1197 if (IS_SPCV_12G(pm8001_ha->pdev))
1198 page_code = THERMAL_PAGE_CODE_7H;
1199 else
1200 page_code = THERMAL_PAGE_CODE_8H;
1201
1202 payload.cfg_pg[0] = (THERMAL_LOG_ENABLE << 9) |
1203 (THERMAL_ENABLE << 8) | page_code;
1204 payload.cfg_pg[1] = (LTEMPHIL << 24) | (RTEMPHIL << 8);
1205
1206 pm8001_dbg(pm8001_ha, DEV,
1207 "Setting up thermal config. cfg_pg 0 0x%x cfg_pg 1 0x%x\n",
1208 payload.cfg_pg[0], payload.cfg_pg[1]);
1209
1210 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
1211 sizeof(payload), 0);
1212 if (rc)
1213 pm8001_tag_free(pm8001_ha, tag);
1214 return rc;
1215
1216 }
1217
1218 /**
1219 * pm80xx_set_sas_protocol_timer_config - support the SAS Protocol
1220 * Timer configuration page
1221 * @pm8001_ha: our hba card information.
1222 */
1223 static int
pm80xx_set_sas_protocol_timer_config(struct pm8001_hba_info * pm8001_ha)1224 pm80xx_set_sas_protocol_timer_config(struct pm8001_hba_info *pm8001_ha)
1225 {
1226 struct set_ctrl_cfg_req payload;
1227 struct inbound_queue_table *circularQ;
1228 SASProtocolTimerConfig_t SASConfigPage;
1229 int rc;
1230 u32 tag;
1231 u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
1232
1233 memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
1234 memset(&SASConfigPage, 0, sizeof(SASProtocolTimerConfig_t));
1235
1236 rc = pm8001_tag_alloc(pm8001_ha, &tag);
1237
1238 if (rc)
1239 return -1;
1240
1241 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1242 payload.tag = cpu_to_le32(tag);
1243
1244 SASConfigPage.pageCode = SAS_PROTOCOL_TIMER_CONFIG_PAGE;
1245 SASConfigPage.MST_MSI = 3 << 15;
1246 SASConfigPage.STP_SSP_MCT_TMO = (STP_MCT_TMO << 16) | SSP_MCT_TMO;
1247 SASConfigPage.STP_FRM_TMO = (SAS_MAX_OPEN_TIME << 24) |
1248 (SMP_MAX_CONN_TIMER << 16) | STP_FRM_TIMER;
1249 SASConfigPage.STP_IDLE_TMO = STP_IDLE_TIME;
1250
1251 if (SASConfigPage.STP_IDLE_TMO > 0x3FFFFFF)
1252 SASConfigPage.STP_IDLE_TMO = 0x3FFFFFF;
1253
1254
1255 SASConfigPage.OPNRJT_RTRY_INTVL = (SAS_MFD << 16) |
1256 SAS_OPNRJT_RTRY_INTVL;
1257 SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO = (SAS_DOPNRJT_RTRY_TMO << 16)
1258 | SAS_COPNRJT_RTRY_TMO;
1259 SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR = (SAS_DOPNRJT_RTRY_THR << 16)
1260 | SAS_COPNRJT_RTRY_THR;
1261 SASConfigPage.MAX_AIP = SAS_MAX_AIP;
1262
1263 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.pageCode 0x%08x\n",
1264 SASConfigPage.pageCode);
1265 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.MST_MSI 0x%08x\n",
1266 SASConfigPage.MST_MSI);
1267 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.STP_SSP_MCT_TMO 0x%08x\n",
1268 SASConfigPage.STP_SSP_MCT_TMO);
1269 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.STP_FRM_TMO 0x%08x\n",
1270 SASConfigPage.STP_FRM_TMO);
1271 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.STP_IDLE_TMO 0x%08x\n",
1272 SASConfigPage.STP_IDLE_TMO);
1273 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.OPNRJT_RTRY_INTVL 0x%08x\n",
1274 SASConfigPage.OPNRJT_RTRY_INTVL);
1275 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO 0x%08x\n",
1276 SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO);
1277 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR 0x%08x\n",
1278 SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR);
1279 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.MAX_AIP 0x%08x\n",
1280 SASConfigPage.MAX_AIP);
1281
1282 memcpy(&payload.cfg_pg, &SASConfigPage,
1283 sizeof(SASProtocolTimerConfig_t));
1284
1285 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
1286 sizeof(payload), 0);
1287 if (rc)
1288 pm8001_tag_free(pm8001_ha, tag);
1289
1290 return rc;
1291 }
1292
1293 /**
1294 * pm80xx_get_encrypt_info - Check for encryption
1295 * @pm8001_ha: our hba card information.
1296 */
1297 static int
pm80xx_get_encrypt_info(struct pm8001_hba_info * pm8001_ha)1298 pm80xx_get_encrypt_info(struct pm8001_hba_info *pm8001_ha)
1299 {
1300 u32 scratch3_value;
1301 int ret = -1;
1302
1303 /* Read encryption status from SCRATCH PAD 3 */
1304 scratch3_value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
1305
1306 if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
1307 SCRATCH_PAD3_ENC_READY) {
1308 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
1309 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
1310 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1311 SCRATCH_PAD3_SMF_ENABLED)
1312 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1313 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1314 SCRATCH_PAD3_SMA_ENABLED)
1315 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1316 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1317 SCRATCH_PAD3_SMB_ENABLED)
1318 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1319 pm8001_ha->encrypt_info.status = 0;
1320 pm8001_dbg(pm8001_ha, INIT,
1321 "Encryption: SCRATCH_PAD3_ENC_READY 0x%08X.Cipher mode 0x%x Sec mode 0x%x status 0x%x\n",
1322 scratch3_value,
1323 pm8001_ha->encrypt_info.cipher_mode,
1324 pm8001_ha->encrypt_info.sec_mode,
1325 pm8001_ha->encrypt_info.status);
1326 ret = 0;
1327 } else if ((scratch3_value & SCRATCH_PAD3_ENC_READY) ==
1328 SCRATCH_PAD3_ENC_DISABLED) {
1329 pm8001_dbg(pm8001_ha, INIT,
1330 "Encryption: SCRATCH_PAD3_ENC_DISABLED 0x%08X\n",
1331 scratch3_value);
1332 pm8001_ha->encrypt_info.status = 0xFFFFFFFF;
1333 pm8001_ha->encrypt_info.cipher_mode = 0;
1334 pm8001_ha->encrypt_info.sec_mode = 0;
1335 ret = 0;
1336 } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
1337 SCRATCH_PAD3_ENC_DIS_ERR) {
1338 pm8001_ha->encrypt_info.status =
1339 (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
1340 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
1341 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
1342 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1343 SCRATCH_PAD3_SMF_ENABLED)
1344 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1345 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1346 SCRATCH_PAD3_SMA_ENABLED)
1347 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1348 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1349 SCRATCH_PAD3_SMB_ENABLED)
1350 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1351 pm8001_dbg(pm8001_ha, INIT,
1352 "Encryption: SCRATCH_PAD3_DIS_ERR 0x%08X.Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
1353 scratch3_value,
1354 pm8001_ha->encrypt_info.cipher_mode,
1355 pm8001_ha->encrypt_info.sec_mode,
1356 pm8001_ha->encrypt_info.status);
1357 } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
1358 SCRATCH_PAD3_ENC_ENA_ERR) {
1359
1360 pm8001_ha->encrypt_info.status =
1361 (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
1362 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
1363 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
1364 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1365 SCRATCH_PAD3_SMF_ENABLED)
1366 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1367 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1368 SCRATCH_PAD3_SMA_ENABLED)
1369 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1370 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1371 SCRATCH_PAD3_SMB_ENABLED)
1372 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1373
1374 pm8001_dbg(pm8001_ha, INIT,
1375 "Encryption: SCRATCH_PAD3_ENA_ERR 0x%08X.Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
1376 scratch3_value,
1377 pm8001_ha->encrypt_info.cipher_mode,
1378 pm8001_ha->encrypt_info.sec_mode,
1379 pm8001_ha->encrypt_info.status);
1380 }
1381 return ret;
1382 }
1383
1384 /**
1385 * pm80xx_encrypt_update - update flash with encryption informtion
1386 * @pm8001_ha: our hba card information.
1387 */
pm80xx_encrypt_update(struct pm8001_hba_info * pm8001_ha)1388 static int pm80xx_encrypt_update(struct pm8001_hba_info *pm8001_ha)
1389 {
1390 struct kek_mgmt_req payload;
1391 struct inbound_queue_table *circularQ;
1392 int rc;
1393 u32 tag;
1394 u32 opc = OPC_INB_KEK_MANAGEMENT;
1395
1396 memset(&payload, 0, sizeof(struct kek_mgmt_req));
1397 rc = pm8001_tag_alloc(pm8001_ha, &tag);
1398 if (rc)
1399 return -1;
1400
1401 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1402 payload.tag = cpu_to_le32(tag);
1403 /* Currently only one key is used. New KEK index is 1.
1404 * Current KEK index is 1. Store KEK to NVRAM is 1.
1405 */
1406 payload.new_curidx_ksop = ((1 << 24) | (1 << 16) | (1 << 8) |
1407 KEK_MGMT_SUBOP_KEYCARDUPDATE);
1408
1409 pm8001_dbg(pm8001_ha, DEV,
1410 "Saving Encryption info to flash. payload 0x%x\n",
1411 payload.new_curidx_ksop);
1412
1413 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
1414 sizeof(payload), 0);
1415 if (rc)
1416 pm8001_tag_free(pm8001_ha, tag);
1417
1418 return rc;
1419 }
1420
1421 /**
1422 * pm8001_chip_init - the main init function that initialize whole PM8001 chip.
1423 * @pm8001_ha: our hba card information
1424 */
pm80xx_chip_init(struct pm8001_hba_info * pm8001_ha)1425 static int pm80xx_chip_init(struct pm8001_hba_info *pm8001_ha)
1426 {
1427 int ret;
1428 u8 i = 0;
1429
1430 /* check the firmware status */
1431 if (-1 == check_fw_ready(pm8001_ha)) {
1432 pm8001_dbg(pm8001_ha, FAIL, "Firmware is not ready!\n");
1433 return -EBUSY;
1434 }
1435
1436 /* Initialize the controller fatal error flag */
1437 pm8001_ha->controller_fatal_error = false;
1438
1439 /* Initialize pci space address eg: mpi offset */
1440 init_pci_device_addresses(pm8001_ha);
1441 init_default_table_values(pm8001_ha);
1442 read_main_config_table(pm8001_ha);
1443 read_general_status_table(pm8001_ha);
1444 read_inbnd_queue_table(pm8001_ha);
1445 read_outbnd_queue_table(pm8001_ha);
1446 read_phy_attr_table(pm8001_ha);
1447
1448 /* update main config table ,inbound table and outbound table */
1449 update_main_config_table(pm8001_ha);
1450 for (i = 0; i < pm8001_ha->max_q_num; i++) {
1451 update_inbnd_queue_table(pm8001_ha, i);
1452 update_outbnd_queue_table(pm8001_ha, i);
1453 }
1454 /* notify firmware update finished and check initialization status */
1455 if (0 == mpi_init_check(pm8001_ha)) {
1456 pm8001_dbg(pm8001_ha, INIT, "MPI initialize successful!\n");
1457 } else
1458 return -EBUSY;
1459
1460 /* send SAS protocol timer configuration page to FW */
1461 ret = pm80xx_set_sas_protocol_timer_config(pm8001_ha);
1462
1463 /* Check for encryption */
1464 if (pm8001_ha->chip->encrypt) {
1465 pm8001_dbg(pm8001_ha, INIT, "Checking for encryption\n");
1466 ret = pm80xx_get_encrypt_info(pm8001_ha);
1467 if (ret == -1) {
1468 pm8001_dbg(pm8001_ha, INIT, "Encryption error !!\n");
1469 if (pm8001_ha->encrypt_info.status == 0x81) {
1470 pm8001_dbg(pm8001_ha, INIT,
1471 "Encryption enabled with error.Saving encryption key to flash\n");
1472 pm80xx_encrypt_update(pm8001_ha);
1473 }
1474 }
1475 }
1476 return 0;
1477 }
1478
mpi_uninit_check(struct pm8001_hba_info * pm8001_ha)1479 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
1480 {
1481 u32 max_wait_count;
1482 u32 value;
1483 u32 gst_len_mpistate;
1484 init_pci_device_addresses(pm8001_ha);
1485 /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
1486 table is stop */
1487 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_RESET);
1488
1489 /* wait until Inbound DoorBell Clear Register toggled */
1490 if (IS_SPCV_12G(pm8001_ha->pdev)) {
1491 max_wait_count = 30 * 1000 * 1000; /* 30 sec */
1492 } else {
1493 max_wait_count = 15 * 1000 * 1000; /* 15 sec */
1494 }
1495 do {
1496 udelay(1);
1497 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
1498 value &= SPCv_MSGU_CFG_TABLE_RESET;
1499 } while ((value != 0) && (--max_wait_count));
1500
1501 if (!max_wait_count) {
1502 pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:IBDB value/=%x\n", value);
1503 return -1;
1504 }
1505
1506 /* check the MPI-State for termination in progress */
1507 /* wait until Inbound DoorBell Clear Register toggled */
1508 max_wait_count = 2 * 1000 * 1000; /* 2 sec for spcv/ve */
1509 do {
1510 udelay(1);
1511 gst_len_mpistate =
1512 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
1513 GST_GSTLEN_MPIS_OFFSET);
1514 if (GST_MPI_STATE_UNINIT ==
1515 (gst_len_mpistate & GST_MPI_STATE_MASK))
1516 break;
1517 } while (--max_wait_count);
1518 if (!max_wait_count) {
1519 pm8001_dbg(pm8001_ha, FAIL, " TIME OUT MPI State = 0x%x\n",
1520 gst_len_mpistate & GST_MPI_STATE_MASK);
1521 return -1;
1522 }
1523
1524 return 0;
1525 }
1526
1527 /**
1528 * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all
1529 * the FW register status to the originated status.
1530 * @pm8001_ha: our hba card information
1531 */
1532
1533 static int
pm80xx_chip_soft_rst(struct pm8001_hba_info * pm8001_ha)1534 pm80xx_chip_soft_rst(struct pm8001_hba_info *pm8001_ha)
1535 {
1536 u32 regval;
1537 u32 bootloader_state;
1538 u32 ibutton0, ibutton1;
1539
1540 /* Process MPI table uninitialization only if FW is ready */
1541 if (!pm8001_ha->controller_fatal_error) {
1542 /* Check if MPI is in ready state to reset */
1543 if (mpi_uninit_check(pm8001_ha) != 0) {
1544 u32 r0 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
1545 u32 r1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1546 u32 r2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
1547 u32 r3 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
1548 pm8001_dbg(pm8001_ha, FAIL,
1549 "MPI state is not ready scratch: %x:%x:%x:%x\n",
1550 r0, r1, r2, r3);
1551 /* if things aren't ready but the bootloader is ok then
1552 * try the reset anyway.
1553 */
1554 if (r1 & SCRATCH_PAD1_BOOTSTATE_MASK)
1555 return -1;
1556 }
1557 }
1558 /* checked for reset register normal state; 0x0 */
1559 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
1560 pm8001_dbg(pm8001_ha, INIT, "reset register before write : 0x%x\n",
1561 regval);
1562
1563 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, SPCv_NORMAL_RESET_VALUE);
1564 msleep(500);
1565
1566 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
1567 pm8001_dbg(pm8001_ha, INIT, "reset register after write 0x%x\n",
1568 regval);
1569
1570 if ((regval & SPCv_SOFT_RESET_READ_MASK) ==
1571 SPCv_SOFT_RESET_NORMAL_RESET_OCCURED) {
1572 pm8001_dbg(pm8001_ha, MSG,
1573 " soft reset successful [regval: 0x%x]\n",
1574 regval);
1575 } else {
1576 pm8001_dbg(pm8001_ha, MSG,
1577 " soft reset failed [regval: 0x%x]\n",
1578 regval);
1579
1580 /* check bootloader is successfully executed or in HDA mode */
1581 bootloader_state =
1582 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
1583 SCRATCH_PAD1_BOOTSTATE_MASK;
1584
1585 if (bootloader_state == SCRATCH_PAD1_BOOTSTATE_HDA_SEEPROM) {
1586 pm8001_dbg(pm8001_ha, MSG,
1587 "Bootloader state - HDA mode SEEPROM\n");
1588 } else if (bootloader_state ==
1589 SCRATCH_PAD1_BOOTSTATE_HDA_BOOTSTRAP) {
1590 pm8001_dbg(pm8001_ha, MSG,
1591 "Bootloader state - HDA mode Bootstrap Pin\n");
1592 } else if (bootloader_state ==
1593 SCRATCH_PAD1_BOOTSTATE_HDA_SOFTRESET) {
1594 pm8001_dbg(pm8001_ha, MSG,
1595 "Bootloader state - HDA mode soft reset\n");
1596 } else if (bootloader_state ==
1597 SCRATCH_PAD1_BOOTSTATE_CRIT_ERROR) {
1598 pm8001_dbg(pm8001_ha, MSG,
1599 "Bootloader state-HDA mode critical error\n");
1600 }
1601 return -EBUSY;
1602 }
1603
1604 /* check the firmware status after reset */
1605 if (-1 == check_fw_ready(pm8001_ha)) {
1606 pm8001_dbg(pm8001_ha, FAIL, "Firmware is not ready!\n");
1607 /* check iButton feature support for motherboard controller */
1608 if (pm8001_ha->pdev->subsystem_vendor !=
1609 PCI_VENDOR_ID_ADAPTEC2 &&
1610 pm8001_ha->pdev->subsystem_vendor !=
1611 PCI_VENDOR_ID_ATTO &&
1612 pm8001_ha->pdev->subsystem_vendor != 0) {
1613 ibutton0 = pm8001_cr32(pm8001_ha, 0,
1614 MSGU_HOST_SCRATCH_PAD_6);
1615 ibutton1 = pm8001_cr32(pm8001_ha, 0,
1616 MSGU_HOST_SCRATCH_PAD_7);
1617 if (!ibutton0 && !ibutton1) {
1618 pm8001_dbg(pm8001_ha, FAIL,
1619 "iButton Feature is not Available!!!\n");
1620 return -EBUSY;
1621 }
1622 if (ibutton0 == 0xdeadbeef && ibutton1 == 0xdeadbeef) {
1623 pm8001_dbg(pm8001_ha, FAIL,
1624 "CRC Check for iButton Feature Failed!!!\n");
1625 return -EBUSY;
1626 }
1627 }
1628 }
1629 pm8001_dbg(pm8001_ha, INIT, "SPCv soft reset Complete\n");
1630 return 0;
1631 }
1632
pm80xx_hw_chip_rst(struct pm8001_hba_info * pm8001_ha)1633 static void pm80xx_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
1634 {
1635 u32 i;
1636
1637 pm8001_dbg(pm8001_ha, INIT, "chip reset start\n");
1638
1639 /* do SPCv chip reset. */
1640 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, 0x11);
1641 pm8001_dbg(pm8001_ha, INIT, "SPC soft reset Complete\n");
1642
1643 /* Check this ..whether delay is required or no */
1644 /* delay 10 usec */
1645 udelay(10);
1646
1647 /* wait for 20 msec until the firmware gets reloaded */
1648 i = 20;
1649 do {
1650 mdelay(1);
1651 } while ((--i) != 0);
1652
1653 pm8001_dbg(pm8001_ha, INIT, "chip reset finished\n");
1654 }
1655
1656 /**
1657 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1658 * @pm8001_ha: our hba card information
1659 */
1660 static void
pm80xx_chip_intx_interrupt_enable(struct pm8001_hba_info * pm8001_ha)1661 pm80xx_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1662 {
1663 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1664 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1665 }
1666
1667 /**
1668 * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1669 * @pm8001_ha: our hba card information
1670 */
1671 static void
pm80xx_chip_intx_interrupt_disable(struct pm8001_hba_info * pm8001_ha)1672 pm80xx_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1673 {
1674 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, ODMR_MASK_ALL);
1675 }
1676
1677 /**
1678 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1679 * @pm8001_ha: our hba card information
1680 * @vec: interrupt number to enable
1681 */
1682 static void
pm80xx_chip_interrupt_enable(struct pm8001_hba_info * pm8001_ha,u8 vec)1683 pm80xx_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1684 {
1685 #ifdef PM8001_USE_MSIX
1686 u32 mask;
1687 mask = (u32)(1 << vec);
1688
1689 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, (u32)(mask & 0xFFFFFFFF));
1690 return;
1691 #endif
1692 pm80xx_chip_intx_interrupt_enable(pm8001_ha);
1693
1694 }
1695
1696 /**
1697 * pm8001_chip_interrupt_disable- disable PM8001 chip interrupt
1698 * @pm8001_ha: our hba card information
1699 * @vec: interrupt number to disable
1700 */
1701 static void
pm80xx_chip_interrupt_disable(struct pm8001_hba_info * pm8001_ha,u8 vec)1702 pm80xx_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1703 {
1704 #ifdef PM8001_USE_MSIX
1705 u32 mask;
1706 if (vec == 0xFF)
1707 mask = 0xFFFFFFFF;
1708 else
1709 mask = (u32)(1 << vec);
1710 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, (u32)(mask & 0xFFFFFFFF));
1711 return;
1712 #endif
1713 pm80xx_chip_intx_interrupt_disable(pm8001_ha);
1714 }
1715
pm80xx_send_abort_all(struct pm8001_hba_info * pm8001_ha,struct pm8001_device * pm8001_ha_dev)1716 static void pm80xx_send_abort_all(struct pm8001_hba_info *pm8001_ha,
1717 struct pm8001_device *pm8001_ha_dev)
1718 {
1719 int res;
1720 u32 ccb_tag;
1721 struct pm8001_ccb_info *ccb;
1722 struct sas_task *task = NULL;
1723 struct task_abort_req task_abort;
1724 struct inbound_queue_table *circularQ;
1725 u32 opc = OPC_INB_SATA_ABORT;
1726 int ret;
1727
1728 if (!pm8001_ha_dev) {
1729 pm8001_dbg(pm8001_ha, FAIL, "dev is null\n");
1730 return;
1731 }
1732
1733 task = sas_alloc_slow_task(GFP_ATOMIC);
1734
1735 if (!task) {
1736 pm8001_dbg(pm8001_ha, FAIL, "cannot allocate task\n");
1737 return;
1738 }
1739
1740 task->task_done = pm8001_task_done;
1741
1742 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1743 if (res) {
1744 sas_free_task(task);
1745 return;
1746 }
1747
1748 ccb = &pm8001_ha->ccb_info[ccb_tag];
1749 ccb->device = pm8001_ha_dev;
1750 ccb->ccb_tag = ccb_tag;
1751 ccb->task = task;
1752
1753 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1754
1755 memset(&task_abort, 0, sizeof(task_abort));
1756 task_abort.abort_all = cpu_to_le32(1);
1757 task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1758 task_abort.tag = cpu_to_le32(ccb_tag);
1759
1760 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort,
1761 sizeof(task_abort), 0);
1762 pm8001_dbg(pm8001_ha, FAIL, "Executing abort task end\n");
1763 if (ret) {
1764 sas_free_task(task);
1765 pm8001_tag_free(pm8001_ha, ccb_tag);
1766 }
1767 }
1768
pm80xx_send_read_log(struct pm8001_hba_info * pm8001_ha,struct pm8001_device * pm8001_ha_dev)1769 static void pm80xx_send_read_log(struct pm8001_hba_info *pm8001_ha,
1770 struct pm8001_device *pm8001_ha_dev)
1771 {
1772 struct sata_start_req sata_cmd;
1773 int res;
1774 u32 ccb_tag;
1775 struct pm8001_ccb_info *ccb;
1776 struct sas_task *task = NULL;
1777 struct host_to_dev_fis fis;
1778 struct domain_device *dev;
1779 struct inbound_queue_table *circularQ;
1780 u32 opc = OPC_INB_SATA_HOST_OPSTART;
1781
1782 task = sas_alloc_slow_task(GFP_ATOMIC);
1783
1784 if (!task) {
1785 pm8001_dbg(pm8001_ha, FAIL, "cannot allocate task !!!\n");
1786 return;
1787 }
1788 task->task_done = pm8001_task_done;
1789
1790 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1791 if (res) {
1792 sas_free_task(task);
1793 pm8001_dbg(pm8001_ha, FAIL, "cannot allocate tag !!!\n");
1794 return;
1795 }
1796
1797 /* allocate domain device by ourselves as libsas
1798 * is not going to provide any
1799 */
1800 dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC);
1801 if (!dev) {
1802 sas_free_task(task);
1803 pm8001_tag_free(pm8001_ha, ccb_tag);
1804 pm8001_dbg(pm8001_ha, FAIL,
1805 "Domain device cannot be allocated\n");
1806 return;
1807 }
1808
1809 task->dev = dev;
1810 task->dev->lldd_dev = pm8001_ha_dev;
1811
1812 ccb = &pm8001_ha->ccb_info[ccb_tag];
1813 ccb->device = pm8001_ha_dev;
1814 ccb->ccb_tag = ccb_tag;
1815 ccb->task = task;
1816 ccb->n_elem = 0;
1817 pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG;
1818 pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG;
1819
1820 memset(&sata_cmd, 0, sizeof(sata_cmd));
1821 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1822
1823 /* construct read log FIS */
1824 memset(&fis, 0, sizeof(struct host_to_dev_fis));
1825 fis.fis_type = 0x27;
1826 fis.flags = 0x80;
1827 fis.command = ATA_CMD_READ_LOG_EXT;
1828 fis.lbal = 0x10;
1829 fis.sector_count = 0x1;
1830
1831 sata_cmd.tag = cpu_to_le32(ccb_tag);
1832 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1833 sata_cmd.ncqtag_atap_dir_m_dad |= ((0x1 << 7) | (0x5 << 9));
1834 memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis));
1835
1836 res = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd,
1837 sizeof(sata_cmd), 0);
1838 pm8001_dbg(pm8001_ha, FAIL, "Executing read log end\n");
1839 if (res) {
1840 sas_free_task(task);
1841 pm8001_tag_free(pm8001_ha, ccb_tag);
1842 kfree(dev);
1843 }
1844 }
1845
1846 /**
1847 * mpi_ssp_completion- process the event that FW response to the SSP request.
1848 * @pm8001_ha: our hba card information
1849 * @piomb: the message contents of this outbound message.
1850 *
1851 * When FW has completed a ssp request for example a IO request, after it has
1852 * filled the SG data with the data, it will trigger this event represent
1853 * that he has finished the job,please check the coresponding buffer.
1854 * So we will tell the caller who maybe waiting the result to tell upper layer
1855 * that the task has been finished.
1856 */
1857 static void
mpi_ssp_completion(struct pm8001_hba_info * pm8001_ha,void * piomb)1858 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb)
1859 {
1860 struct sas_task *t;
1861 struct pm8001_ccb_info *ccb;
1862 unsigned long flags;
1863 u32 status;
1864 u32 param;
1865 u32 tag;
1866 struct ssp_completion_resp *psspPayload;
1867 struct task_status_struct *ts;
1868 struct ssp_response_iu *iu;
1869 struct pm8001_device *pm8001_dev;
1870 psspPayload = (struct ssp_completion_resp *)(piomb + 4);
1871 status = le32_to_cpu(psspPayload->status);
1872 tag = le32_to_cpu(psspPayload->tag);
1873 ccb = &pm8001_ha->ccb_info[tag];
1874 if ((status == IO_ABORTED) && ccb->open_retry) {
1875 /* Being completed by another */
1876 ccb->open_retry = 0;
1877 return;
1878 }
1879 pm8001_dev = ccb->device;
1880 param = le32_to_cpu(psspPayload->param);
1881 t = ccb->task;
1882
1883 if (status && status != IO_UNDERFLOW)
1884 pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", status);
1885 if (unlikely(!t || !t->lldd_task || !t->dev))
1886 return;
1887 ts = &t->task_status;
1888
1889 pm8001_dbg(pm8001_ha, DEV,
1890 "tag::0x%x, status::0x%x task::0x%p\n", tag, status, t);
1891
1892 /* Print sas address of IO failed device */
1893 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
1894 (status != IO_UNDERFLOW))
1895 pm8001_dbg(pm8001_ha, FAIL, "SAS Address of IO Failure Drive:%016llx\n",
1896 SAS_ADDR(t->dev->sas_addr));
1897
1898 switch (status) {
1899 case IO_SUCCESS:
1900 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS ,param = 0x%x\n",
1901 param);
1902 if (param == 0) {
1903 ts->resp = SAS_TASK_COMPLETE;
1904 ts->stat = SAM_STAT_GOOD;
1905 } else {
1906 ts->resp = SAS_TASK_COMPLETE;
1907 ts->stat = SAS_PROTO_RESPONSE;
1908 ts->residual = param;
1909 iu = &psspPayload->ssp_resp_iu;
1910 sas_ssp_task_response(pm8001_ha->dev, t, iu);
1911 }
1912 if (pm8001_dev)
1913 atomic_dec(&pm8001_dev->running_req);
1914 break;
1915 case IO_ABORTED:
1916 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n");
1917 ts->resp = SAS_TASK_COMPLETE;
1918 ts->stat = SAS_ABORTED_TASK;
1919 if (pm8001_dev)
1920 atomic_dec(&pm8001_dev->running_req);
1921 break;
1922 case IO_UNDERFLOW:
1923 /* SSP Completion with error */
1924 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW ,param = 0x%x\n",
1925 param);
1926 ts->resp = SAS_TASK_COMPLETE;
1927 ts->stat = SAS_DATA_UNDERRUN;
1928 ts->residual = param;
1929 if (pm8001_dev)
1930 atomic_dec(&pm8001_dev->running_req);
1931 break;
1932 case IO_NO_DEVICE:
1933 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n");
1934 ts->resp = SAS_TASK_UNDELIVERED;
1935 ts->stat = SAS_PHY_DOWN;
1936 if (pm8001_dev)
1937 atomic_dec(&pm8001_dev->running_req);
1938 break;
1939 case IO_XFER_ERROR_BREAK:
1940 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
1941 ts->resp = SAS_TASK_COMPLETE;
1942 ts->stat = SAS_OPEN_REJECT;
1943 /* Force the midlayer to retry */
1944 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1945 if (pm8001_dev)
1946 atomic_dec(&pm8001_dev->running_req);
1947 break;
1948 case IO_XFER_ERROR_PHY_NOT_READY:
1949 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
1950 ts->resp = SAS_TASK_COMPLETE;
1951 ts->stat = SAS_OPEN_REJECT;
1952 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1953 if (pm8001_dev)
1954 atomic_dec(&pm8001_dev->running_req);
1955 break;
1956 case IO_XFER_ERROR_INVALID_SSP_RSP_FRAME:
1957 pm8001_dbg(pm8001_ha, IO,
1958 "IO_XFER_ERROR_INVALID_SSP_RSP_FRAME\n");
1959 ts->resp = SAS_TASK_COMPLETE;
1960 ts->stat = SAS_OPEN_REJECT;
1961 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1962 if (pm8001_dev)
1963 atomic_dec(&pm8001_dev->running_req);
1964 break;
1965 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1966 pm8001_dbg(pm8001_ha, IO,
1967 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
1968 ts->resp = SAS_TASK_COMPLETE;
1969 ts->stat = SAS_OPEN_REJECT;
1970 ts->open_rej_reason = SAS_OREJ_EPROTO;
1971 if (pm8001_dev)
1972 atomic_dec(&pm8001_dev->running_req);
1973 break;
1974 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1975 pm8001_dbg(pm8001_ha, IO,
1976 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
1977 ts->resp = SAS_TASK_COMPLETE;
1978 ts->stat = SAS_OPEN_REJECT;
1979 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1980 if (pm8001_dev)
1981 atomic_dec(&pm8001_dev->running_req);
1982 break;
1983 case IO_OPEN_CNX_ERROR_BREAK:
1984 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
1985 ts->resp = SAS_TASK_COMPLETE;
1986 ts->stat = SAS_OPEN_REJECT;
1987 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1988 if (pm8001_dev)
1989 atomic_dec(&pm8001_dev->running_req);
1990 break;
1991 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1992 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
1993 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
1994 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
1995 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
1996 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
1997 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
1998 ts->resp = SAS_TASK_COMPLETE;
1999 ts->stat = SAS_OPEN_REJECT;
2000 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2001 if (!t->uldd_task)
2002 pm8001_handle_event(pm8001_ha,
2003 pm8001_dev,
2004 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2005 break;
2006 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2007 pm8001_dbg(pm8001_ha, IO,
2008 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2009 ts->resp = SAS_TASK_COMPLETE;
2010 ts->stat = SAS_OPEN_REJECT;
2011 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2012 if (pm8001_dev)
2013 atomic_dec(&pm8001_dev->running_req);
2014 break;
2015 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2016 pm8001_dbg(pm8001_ha, IO,
2017 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2018 ts->resp = SAS_TASK_COMPLETE;
2019 ts->stat = SAS_OPEN_REJECT;
2020 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2021 if (pm8001_dev)
2022 atomic_dec(&pm8001_dev->running_req);
2023 break;
2024 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2025 pm8001_dbg(pm8001_ha, IO,
2026 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2027 ts->resp = SAS_TASK_UNDELIVERED;
2028 ts->stat = SAS_OPEN_REJECT;
2029 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2030 if (pm8001_dev)
2031 atomic_dec(&pm8001_dev->running_req);
2032 break;
2033 case IO_XFER_ERROR_NAK_RECEIVED:
2034 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2035 ts->resp = SAS_TASK_COMPLETE;
2036 ts->stat = SAS_OPEN_REJECT;
2037 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2038 if (pm8001_dev)
2039 atomic_dec(&pm8001_dev->running_req);
2040 break;
2041 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2042 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n");
2043 ts->resp = SAS_TASK_COMPLETE;
2044 ts->stat = SAS_NAK_R_ERR;
2045 if (pm8001_dev)
2046 atomic_dec(&pm8001_dev->running_req);
2047 break;
2048 case IO_XFER_ERROR_DMA:
2049 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n");
2050 ts->resp = SAS_TASK_COMPLETE;
2051 ts->stat = SAS_OPEN_REJECT;
2052 if (pm8001_dev)
2053 atomic_dec(&pm8001_dev->running_req);
2054 break;
2055 case IO_XFER_OPEN_RETRY_TIMEOUT:
2056 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2057 ts->resp = SAS_TASK_COMPLETE;
2058 ts->stat = SAS_OPEN_REJECT;
2059 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2060 if (pm8001_dev)
2061 atomic_dec(&pm8001_dev->running_req);
2062 break;
2063 case IO_XFER_ERROR_OFFSET_MISMATCH:
2064 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n");
2065 ts->resp = SAS_TASK_COMPLETE;
2066 ts->stat = SAS_OPEN_REJECT;
2067 if (pm8001_dev)
2068 atomic_dec(&pm8001_dev->running_req);
2069 break;
2070 case IO_PORT_IN_RESET:
2071 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n");
2072 ts->resp = SAS_TASK_COMPLETE;
2073 ts->stat = SAS_OPEN_REJECT;
2074 if (pm8001_dev)
2075 atomic_dec(&pm8001_dev->running_req);
2076 break;
2077 case IO_DS_NON_OPERATIONAL:
2078 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n");
2079 ts->resp = SAS_TASK_COMPLETE;
2080 ts->stat = SAS_OPEN_REJECT;
2081 if (!t->uldd_task)
2082 pm8001_handle_event(pm8001_ha,
2083 pm8001_dev,
2084 IO_DS_NON_OPERATIONAL);
2085 break;
2086 case IO_DS_IN_RECOVERY:
2087 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n");
2088 ts->resp = SAS_TASK_COMPLETE;
2089 ts->stat = SAS_OPEN_REJECT;
2090 if (pm8001_dev)
2091 atomic_dec(&pm8001_dev->running_req);
2092 break;
2093 case IO_TM_TAG_NOT_FOUND:
2094 pm8001_dbg(pm8001_ha, IO, "IO_TM_TAG_NOT_FOUND\n");
2095 ts->resp = SAS_TASK_COMPLETE;
2096 ts->stat = SAS_OPEN_REJECT;
2097 if (pm8001_dev)
2098 atomic_dec(&pm8001_dev->running_req);
2099 break;
2100 case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
2101 pm8001_dbg(pm8001_ha, IO, "IO_SSP_EXT_IU_ZERO_LEN_ERROR\n");
2102 ts->resp = SAS_TASK_COMPLETE;
2103 ts->stat = SAS_OPEN_REJECT;
2104 if (pm8001_dev)
2105 atomic_dec(&pm8001_dev->running_req);
2106 break;
2107 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2108 pm8001_dbg(pm8001_ha, IO,
2109 "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n");
2110 ts->resp = SAS_TASK_COMPLETE;
2111 ts->stat = SAS_OPEN_REJECT;
2112 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2113 if (pm8001_dev)
2114 atomic_dec(&pm8001_dev->running_req);
2115 break;
2116 default:
2117 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status);
2118 /* not allowed case. Therefore, return failed status */
2119 ts->resp = SAS_TASK_COMPLETE;
2120 ts->stat = SAS_OPEN_REJECT;
2121 if (pm8001_dev)
2122 atomic_dec(&pm8001_dev->running_req);
2123 break;
2124 }
2125 pm8001_dbg(pm8001_ha, IO, "scsi_status = 0x%x\n ",
2126 psspPayload->ssp_resp_iu.status);
2127 spin_lock_irqsave(&t->task_state_lock, flags);
2128 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2129 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2130 t->task_state_flags |= SAS_TASK_STATE_DONE;
2131 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2132 spin_unlock_irqrestore(&t->task_state_lock, flags);
2133 pm8001_dbg(pm8001_ha, FAIL,
2134 "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
2135 t, status, ts->resp, ts->stat);
2136 if (t->slow_task)
2137 complete(&t->slow_task->completion);
2138 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2139 } else {
2140 spin_unlock_irqrestore(&t->task_state_lock, flags);
2141 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2142 mb();/* in order to force CPU ordering */
2143 t->task_done(t);
2144 }
2145 }
2146
2147 /*See the comments for mpi_ssp_completion */
mpi_ssp_event(struct pm8001_hba_info * pm8001_ha,void * piomb)2148 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
2149 {
2150 struct sas_task *t;
2151 unsigned long flags;
2152 struct task_status_struct *ts;
2153 struct pm8001_ccb_info *ccb;
2154 struct pm8001_device *pm8001_dev;
2155 struct ssp_event_resp *psspPayload =
2156 (struct ssp_event_resp *)(piomb + 4);
2157 u32 event = le32_to_cpu(psspPayload->event);
2158 u32 tag = le32_to_cpu(psspPayload->tag);
2159 u32 port_id = le32_to_cpu(psspPayload->port_id);
2160
2161 ccb = &pm8001_ha->ccb_info[tag];
2162 t = ccb->task;
2163 pm8001_dev = ccb->device;
2164 if (event)
2165 pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", event);
2166 if (unlikely(!t || !t->lldd_task || !t->dev))
2167 return;
2168 ts = &t->task_status;
2169 pm8001_dbg(pm8001_ha, IOERR, "port_id:0x%x, tag:0x%x, event:0x%x\n",
2170 port_id, tag, event);
2171 switch (event) {
2172 case IO_OVERFLOW:
2173 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n");
2174 ts->resp = SAS_TASK_COMPLETE;
2175 ts->stat = SAS_DATA_OVERRUN;
2176 ts->residual = 0;
2177 if (pm8001_dev)
2178 atomic_dec(&pm8001_dev->running_req);
2179 break;
2180 case IO_XFER_ERROR_BREAK:
2181 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2182 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK);
2183 return;
2184 case IO_XFER_ERROR_PHY_NOT_READY:
2185 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2186 ts->resp = SAS_TASK_COMPLETE;
2187 ts->stat = SAS_OPEN_REJECT;
2188 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2189 break;
2190 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2191 pm8001_dbg(pm8001_ha, IO,
2192 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2193 ts->resp = SAS_TASK_COMPLETE;
2194 ts->stat = SAS_OPEN_REJECT;
2195 ts->open_rej_reason = SAS_OREJ_EPROTO;
2196 break;
2197 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2198 pm8001_dbg(pm8001_ha, IO,
2199 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2200 ts->resp = SAS_TASK_COMPLETE;
2201 ts->stat = SAS_OPEN_REJECT;
2202 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2203 break;
2204 case IO_OPEN_CNX_ERROR_BREAK:
2205 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2206 ts->resp = SAS_TASK_COMPLETE;
2207 ts->stat = SAS_OPEN_REJECT;
2208 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2209 break;
2210 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2211 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2212 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2213 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2214 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2215 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2216 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2217 ts->resp = SAS_TASK_COMPLETE;
2218 ts->stat = SAS_OPEN_REJECT;
2219 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2220 if (!t->uldd_task)
2221 pm8001_handle_event(pm8001_ha,
2222 pm8001_dev,
2223 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2224 break;
2225 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2226 pm8001_dbg(pm8001_ha, IO,
2227 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2228 ts->resp = SAS_TASK_COMPLETE;
2229 ts->stat = SAS_OPEN_REJECT;
2230 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2231 break;
2232 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2233 pm8001_dbg(pm8001_ha, IO,
2234 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2235 ts->resp = SAS_TASK_COMPLETE;
2236 ts->stat = SAS_OPEN_REJECT;
2237 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2238 break;
2239 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2240 pm8001_dbg(pm8001_ha, IO,
2241 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2242 ts->resp = SAS_TASK_COMPLETE;
2243 ts->stat = SAS_OPEN_REJECT;
2244 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2245 break;
2246 case IO_XFER_ERROR_NAK_RECEIVED:
2247 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2248 ts->resp = SAS_TASK_COMPLETE;
2249 ts->stat = SAS_OPEN_REJECT;
2250 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2251 break;
2252 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2253 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n");
2254 ts->resp = SAS_TASK_COMPLETE;
2255 ts->stat = SAS_NAK_R_ERR;
2256 break;
2257 case IO_XFER_OPEN_RETRY_TIMEOUT:
2258 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2259 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT);
2260 return;
2261 case IO_XFER_ERROR_UNEXPECTED_PHASE:
2262 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n");
2263 ts->resp = SAS_TASK_COMPLETE;
2264 ts->stat = SAS_DATA_OVERRUN;
2265 break;
2266 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2267 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n");
2268 ts->resp = SAS_TASK_COMPLETE;
2269 ts->stat = SAS_DATA_OVERRUN;
2270 break;
2271 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2272 pm8001_dbg(pm8001_ha, IO,
2273 "IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n");
2274 ts->resp = SAS_TASK_COMPLETE;
2275 ts->stat = SAS_DATA_OVERRUN;
2276 break;
2277 case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
2278 pm8001_dbg(pm8001_ha, IO,
2279 "IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n");
2280 ts->resp = SAS_TASK_COMPLETE;
2281 ts->stat = SAS_DATA_OVERRUN;
2282 break;
2283 case IO_XFER_ERROR_OFFSET_MISMATCH:
2284 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n");
2285 ts->resp = SAS_TASK_COMPLETE;
2286 ts->stat = SAS_DATA_OVERRUN;
2287 break;
2288 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2289 pm8001_dbg(pm8001_ha, IO,
2290 "IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n");
2291 ts->resp = SAS_TASK_COMPLETE;
2292 ts->stat = SAS_DATA_OVERRUN;
2293 break;
2294 case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
2295 pm8001_dbg(pm8001_ha, IOERR,
2296 "IO_XFR_ERROR_INTERNAL_CRC_ERROR\n");
2297 /* TBC: used default set values */
2298 ts->resp = SAS_TASK_COMPLETE;
2299 ts->stat = SAS_DATA_OVERRUN;
2300 break;
2301 case IO_XFER_CMD_FRAME_ISSUED:
2302 pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n");
2303 return;
2304 default:
2305 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", event);
2306 /* not allowed case. Therefore, return failed status */
2307 ts->resp = SAS_TASK_COMPLETE;
2308 ts->stat = SAS_DATA_OVERRUN;
2309 break;
2310 }
2311 spin_lock_irqsave(&t->task_state_lock, flags);
2312 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2313 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2314 t->task_state_flags |= SAS_TASK_STATE_DONE;
2315 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2316 spin_unlock_irqrestore(&t->task_state_lock, flags);
2317 pm8001_dbg(pm8001_ha, FAIL,
2318 "task 0x%p done with event 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
2319 t, event, ts->resp, ts->stat);
2320 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2321 } else {
2322 spin_unlock_irqrestore(&t->task_state_lock, flags);
2323 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2324 mb();/* in order to force CPU ordering */
2325 t->task_done(t);
2326 }
2327 }
2328
2329 /*See the comments for mpi_ssp_completion */
2330 static void
mpi_sata_completion(struct pm8001_hba_info * pm8001_ha,void * piomb)2331 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2332 {
2333 struct sas_task *t;
2334 struct pm8001_ccb_info *ccb;
2335 u32 param;
2336 u32 status;
2337 u32 tag;
2338 int i, j;
2339 u8 sata_addr_low[4];
2340 u32 temp_sata_addr_low, temp_sata_addr_hi;
2341 u8 sata_addr_hi[4];
2342 struct sata_completion_resp *psataPayload;
2343 struct task_status_struct *ts;
2344 struct ata_task_resp *resp ;
2345 u32 *sata_resp;
2346 struct pm8001_device *pm8001_dev;
2347 unsigned long flags;
2348
2349 psataPayload = (struct sata_completion_resp *)(piomb + 4);
2350 status = le32_to_cpu(psataPayload->status);
2351 tag = le32_to_cpu(psataPayload->tag);
2352
2353 if (!tag) {
2354 pm8001_dbg(pm8001_ha, FAIL, "tag null\n");
2355 return;
2356 }
2357 ccb = &pm8001_ha->ccb_info[tag];
2358 param = le32_to_cpu(psataPayload->param);
2359 if (ccb) {
2360 t = ccb->task;
2361 pm8001_dev = ccb->device;
2362 } else {
2363 pm8001_dbg(pm8001_ha, FAIL, "ccb null\n");
2364 return;
2365 }
2366
2367 if (t) {
2368 if (t->dev && (t->dev->lldd_dev))
2369 pm8001_dev = t->dev->lldd_dev;
2370 } else {
2371 pm8001_dbg(pm8001_ha, FAIL, "task null\n");
2372 return;
2373 }
2374
2375 if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG))
2376 && unlikely(!t || !t->lldd_task || !t->dev)) {
2377 pm8001_dbg(pm8001_ha, FAIL, "task or dev null\n");
2378 return;
2379 }
2380
2381 ts = &t->task_status;
2382 if (!ts) {
2383 pm8001_dbg(pm8001_ha, FAIL, "ts null\n");
2384 return;
2385 }
2386
2387 if (unlikely(status))
2388 pm8001_dbg(pm8001_ha, IOERR,
2389 "status:0x%x, tag:0x%x, task::0x%p\n",
2390 status, tag, t);
2391
2392 /* Print sas address of IO failed device */
2393 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
2394 (status != IO_UNDERFLOW)) {
2395 if (!((t->dev->parent) &&
2396 (dev_is_expander(t->dev->parent->dev_type)))) {
2397 for (i = 0 , j = 4; i <= 3 && j <= 7; i++ , j++)
2398 sata_addr_low[i] = pm8001_ha->sas_addr[j];
2399 for (i = 0 , j = 0; i <= 3 && j <= 3; i++ , j++)
2400 sata_addr_hi[i] = pm8001_ha->sas_addr[j];
2401 memcpy(&temp_sata_addr_low, sata_addr_low,
2402 sizeof(sata_addr_low));
2403 memcpy(&temp_sata_addr_hi, sata_addr_hi,
2404 sizeof(sata_addr_hi));
2405 temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff)
2406 |((temp_sata_addr_hi << 8) &
2407 0xff0000) |
2408 ((temp_sata_addr_hi >> 8)
2409 & 0xff00) |
2410 ((temp_sata_addr_hi << 24) &
2411 0xff000000));
2412 temp_sata_addr_low = ((((temp_sata_addr_low >> 24)
2413 & 0xff) |
2414 ((temp_sata_addr_low << 8)
2415 & 0xff0000) |
2416 ((temp_sata_addr_low >> 8)
2417 & 0xff00) |
2418 ((temp_sata_addr_low << 24)
2419 & 0xff000000)) +
2420 pm8001_dev->attached_phy +
2421 0x10);
2422 pm8001_dbg(pm8001_ha, FAIL,
2423 "SAS Address of IO Failure Drive:%08x%08x\n",
2424 temp_sata_addr_hi,
2425 temp_sata_addr_low);
2426
2427 } else {
2428 pm8001_dbg(pm8001_ha, FAIL,
2429 "SAS Address of IO Failure Drive:%016llx\n",
2430 SAS_ADDR(t->dev->sas_addr));
2431 }
2432 }
2433 switch (status) {
2434 case IO_SUCCESS:
2435 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n");
2436 if (param == 0) {
2437 ts->resp = SAS_TASK_COMPLETE;
2438 ts->stat = SAM_STAT_GOOD;
2439 /* check if response is for SEND READ LOG */
2440 if (pm8001_dev &&
2441 (pm8001_dev->id & NCQ_READ_LOG_FLAG)) {
2442 /* set new bit for abort_all */
2443 pm8001_dev->id |= NCQ_ABORT_ALL_FLAG;
2444 /* clear bit for read log */
2445 pm8001_dev->id = pm8001_dev->id & 0x7FFFFFFF;
2446 pm80xx_send_abort_all(pm8001_ha, pm8001_dev);
2447 /* Free the tag */
2448 pm8001_tag_free(pm8001_ha, tag);
2449 sas_free_task(t);
2450 return;
2451 }
2452 } else {
2453 u8 len;
2454 ts->resp = SAS_TASK_COMPLETE;
2455 ts->stat = SAS_PROTO_RESPONSE;
2456 ts->residual = param;
2457 pm8001_dbg(pm8001_ha, IO,
2458 "SAS_PROTO_RESPONSE len = %d\n",
2459 param);
2460 sata_resp = &psataPayload->sata_resp[0];
2461 resp = (struct ata_task_resp *)ts->buf;
2462 if (t->ata_task.dma_xfer == 0 &&
2463 t->data_dir == DMA_FROM_DEVICE) {
2464 len = sizeof(struct pio_setup_fis);
2465 pm8001_dbg(pm8001_ha, IO,
2466 "PIO read len = %d\n", len);
2467 } else if (t->ata_task.use_ncq) {
2468 len = sizeof(struct set_dev_bits_fis);
2469 pm8001_dbg(pm8001_ha, IO, "FPDMA len = %d\n",
2470 len);
2471 } else {
2472 len = sizeof(struct dev_to_host_fis);
2473 pm8001_dbg(pm8001_ha, IO, "other len = %d\n",
2474 len);
2475 }
2476 if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
2477 resp->frame_len = len;
2478 memcpy(&resp->ending_fis[0], sata_resp, len);
2479 ts->buf_valid_size = sizeof(*resp);
2480 } else
2481 pm8001_dbg(pm8001_ha, IO,
2482 "response too large\n");
2483 }
2484 if (pm8001_dev)
2485 atomic_dec(&pm8001_dev->running_req);
2486 break;
2487 case IO_ABORTED:
2488 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n");
2489 ts->resp = SAS_TASK_COMPLETE;
2490 ts->stat = SAS_ABORTED_TASK;
2491 if (pm8001_dev)
2492 atomic_dec(&pm8001_dev->running_req);
2493 break;
2494 /* following cases are to do cases */
2495 case IO_UNDERFLOW:
2496 /* SATA Completion with error */
2497 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW param = %d\n", param);
2498 ts->resp = SAS_TASK_COMPLETE;
2499 ts->stat = SAS_DATA_UNDERRUN;
2500 ts->residual = param;
2501 if (pm8001_dev)
2502 atomic_dec(&pm8001_dev->running_req);
2503 break;
2504 case IO_NO_DEVICE:
2505 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n");
2506 ts->resp = SAS_TASK_UNDELIVERED;
2507 ts->stat = SAS_PHY_DOWN;
2508 if (pm8001_dev)
2509 atomic_dec(&pm8001_dev->running_req);
2510 break;
2511 case IO_XFER_ERROR_BREAK:
2512 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2513 ts->resp = SAS_TASK_COMPLETE;
2514 ts->stat = SAS_INTERRUPTED;
2515 if (pm8001_dev)
2516 atomic_dec(&pm8001_dev->running_req);
2517 break;
2518 case IO_XFER_ERROR_PHY_NOT_READY:
2519 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2520 ts->resp = SAS_TASK_COMPLETE;
2521 ts->stat = SAS_OPEN_REJECT;
2522 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2523 if (pm8001_dev)
2524 atomic_dec(&pm8001_dev->running_req);
2525 break;
2526 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2527 pm8001_dbg(pm8001_ha, IO,
2528 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2529 ts->resp = SAS_TASK_COMPLETE;
2530 ts->stat = SAS_OPEN_REJECT;
2531 ts->open_rej_reason = SAS_OREJ_EPROTO;
2532 if (pm8001_dev)
2533 atomic_dec(&pm8001_dev->running_req);
2534 break;
2535 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2536 pm8001_dbg(pm8001_ha, IO,
2537 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2538 ts->resp = SAS_TASK_COMPLETE;
2539 ts->stat = SAS_OPEN_REJECT;
2540 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2541 if (pm8001_dev)
2542 atomic_dec(&pm8001_dev->running_req);
2543 break;
2544 case IO_OPEN_CNX_ERROR_BREAK:
2545 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2546 ts->resp = SAS_TASK_COMPLETE;
2547 ts->stat = SAS_OPEN_REJECT;
2548 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2549 if (pm8001_dev)
2550 atomic_dec(&pm8001_dev->running_req);
2551 break;
2552 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2553 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2554 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2555 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2556 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2557 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2558 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2559 ts->resp = SAS_TASK_COMPLETE;
2560 ts->stat = SAS_DEV_NO_RESPONSE;
2561 if (!t->uldd_task) {
2562 pm8001_handle_event(pm8001_ha,
2563 pm8001_dev,
2564 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2565 ts->resp = SAS_TASK_UNDELIVERED;
2566 ts->stat = SAS_QUEUE_FULL;
2567 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2568 return;
2569 }
2570 break;
2571 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2572 pm8001_dbg(pm8001_ha, IO,
2573 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2574 ts->resp = SAS_TASK_UNDELIVERED;
2575 ts->stat = SAS_OPEN_REJECT;
2576 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2577 if (!t->uldd_task) {
2578 pm8001_handle_event(pm8001_ha,
2579 pm8001_dev,
2580 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2581 ts->resp = SAS_TASK_UNDELIVERED;
2582 ts->stat = SAS_QUEUE_FULL;
2583 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2584 return;
2585 }
2586 break;
2587 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2588 pm8001_dbg(pm8001_ha, IO,
2589 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2590 ts->resp = SAS_TASK_COMPLETE;
2591 ts->stat = SAS_OPEN_REJECT;
2592 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2593 if (pm8001_dev)
2594 atomic_dec(&pm8001_dev->running_req);
2595 break;
2596 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
2597 pm8001_dbg(pm8001_ha, IO,
2598 "IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n");
2599 ts->resp = SAS_TASK_COMPLETE;
2600 ts->stat = SAS_DEV_NO_RESPONSE;
2601 if (!t->uldd_task) {
2602 pm8001_handle_event(pm8001_ha,
2603 pm8001_dev,
2604 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
2605 ts->resp = SAS_TASK_UNDELIVERED;
2606 ts->stat = SAS_QUEUE_FULL;
2607 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2608 return;
2609 }
2610 break;
2611 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2612 pm8001_dbg(pm8001_ha, IO,
2613 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2614 ts->resp = SAS_TASK_COMPLETE;
2615 ts->stat = SAS_OPEN_REJECT;
2616 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2617 if (pm8001_dev)
2618 atomic_dec(&pm8001_dev->running_req);
2619 break;
2620 case IO_XFER_ERROR_NAK_RECEIVED:
2621 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2622 ts->resp = SAS_TASK_COMPLETE;
2623 ts->stat = SAS_NAK_R_ERR;
2624 if (pm8001_dev)
2625 atomic_dec(&pm8001_dev->running_req);
2626 break;
2627 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2628 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n");
2629 ts->resp = SAS_TASK_COMPLETE;
2630 ts->stat = SAS_NAK_R_ERR;
2631 if (pm8001_dev)
2632 atomic_dec(&pm8001_dev->running_req);
2633 break;
2634 case IO_XFER_ERROR_DMA:
2635 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n");
2636 ts->resp = SAS_TASK_COMPLETE;
2637 ts->stat = SAS_ABORTED_TASK;
2638 if (pm8001_dev)
2639 atomic_dec(&pm8001_dev->running_req);
2640 break;
2641 case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
2642 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_SATA_LINK_TIMEOUT\n");
2643 ts->resp = SAS_TASK_UNDELIVERED;
2644 ts->stat = SAS_DEV_NO_RESPONSE;
2645 if (pm8001_dev)
2646 atomic_dec(&pm8001_dev->running_req);
2647 break;
2648 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2649 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n");
2650 ts->resp = SAS_TASK_COMPLETE;
2651 ts->stat = SAS_DATA_UNDERRUN;
2652 if (pm8001_dev)
2653 atomic_dec(&pm8001_dev->running_req);
2654 break;
2655 case IO_XFER_OPEN_RETRY_TIMEOUT:
2656 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2657 ts->resp = SAS_TASK_COMPLETE;
2658 ts->stat = SAS_OPEN_TO;
2659 if (pm8001_dev)
2660 atomic_dec(&pm8001_dev->running_req);
2661 break;
2662 case IO_PORT_IN_RESET:
2663 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n");
2664 ts->resp = SAS_TASK_COMPLETE;
2665 ts->stat = SAS_DEV_NO_RESPONSE;
2666 if (pm8001_dev)
2667 atomic_dec(&pm8001_dev->running_req);
2668 break;
2669 case IO_DS_NON_OPERATIONAL:
2670 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n");
2671 ts->resp = SAS_TASK_COMPLETE;
2672 ts->stat = SAS_DEV_NO_RESPONSE;
2673 if (!t->uldd_task) {
2674 pm8001_handle_event(pm8001_ha, pm8001_dev,
2675 IO_DS_NON_OPERATIONAL);
2676 ts->resp = SAS_TASK_UNDELIVERED;
2677 ts->stat = SAS_QUEUE_FULL;
2678 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2679 return;
2680 }
2681 break;
2682 case IO_DS_IN_RECOVERY:
2683 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n");
2684 ts->resp = SAS_TASK_COMPLETE;
2685 ts->stat = SAS_DEV_NO_RESPONSE;
2686 if (pm8001_dev)
2687 atomic_dec(&pm8001_dev->running_req);
2688 break;
2689 case IO_DS_IN_ERROR:
2690 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_ERROR\n");
2691 ts->resp = SAS_TASK_COMPLETE;
2692 ts->stat = SAS_DEV_NO_RESPONSE;
2693 if (!t->uldd_task) {
2694 pm8001_handle_event(pm8001_ha, pm8001_dev,
2695 IO_DS_IN_ERROR);
2696 ts->resp = SAS_TASK_UNDELIVERED;
2697 ts->stat = SAS_QUEUE_FULL;
2698 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2699 return;
2700 }
2701 break;
2702 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2703 pm8001_dbg(pm8001_ha, IO,
2704 "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n");
2705 ts->resp = SAS_TASK_COMPLETE;
2706 ts->stat = SAS_OPEN_REJECT;
2707 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2708 if (pm8001_dev)
2709 atomic_dec(&pm8001_dev->running_req);
2710 break;
2711 default:
2712 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status);
2713 /* not allowed case. Therefore, return failed status */
2714 ts->resp = SAS_TASK_COMPLETE;
2715 ts->stat = SAS_DEV_NO_RESPONSE;
2716 if (pm8001_dev)
2717 atomic_dec(&pm8001_dev->running_req);
2718 break;
2719 }
2720 spin_lock_irqsave(&t->task_state_lock, flags);
2721 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2722 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2723 t->task_state_flags |= SAS_TASK_STATE_DONE;
2724 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2725 spin_unlock_irqrestore(&t->task_state_lock, flags);
2726 pm8001_dbg(pm8001_ha, FAIL,
2727 "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
2728 t, status, ts->resp, ts->stat);
2729 if (t->slow_task)
2730 complete(&t->slow_task->completion);
2731 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2732 } else {
2733 spin_unlock_irqrestore(&t->task_state_lock, flags);
2734 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2735 }
2736 }
2737
2738 /*See the comments for mpi_ssp_completion */
mpi_sata_event(struct pm8001_hba_info * pm8001_ha,void * piomb)2739 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
2740 {
2741 struct sas_task *t;
2742 struct task_status_struct *ts;
2743 struct pm8001_ccb_info *ccb;
2744 struct pm8001_device *pm8001_dev;
2745 struct sata_event_resp *psataPayload =
2746 (struct sata_event_resp *)(piomb + 4);
2747 u32 event = le32_to_cpu(psataPayload->event);
2748 u32 tag = le32_to_cpu(psataPayload->tag);
2749 u32 port_id = le32_to_cpu(psataPayload->port_id);
2750 u32 dev_id = le32_to_cpu(psataPayload->device_id);
2751 unsigned long flags;
2752
2753 ccb = &pm8001_ha->ccb_info[tag];
2754
2755 if (ccb) {
2756 t = ccb->task;
2757 pm8001_dev = ccb->device;
2758 } else {
2759 pm8001_dbg(pm8001_ha, FAIL, "No CCB !!!. returning\n");
2760 return;
2761 }
2762 if (event)
2763 pm8001_dbg(pm8001_ha, FAIL, "SATA EVENT 0x%x\n", event);
2764
2765 /* Check if this is NCQ error */
2766 if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) {
2767 /* find device using device id */
2768 pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id);
2769 /* send read log extension */
2770 if (pm8001_dev)
2771 pm80xx_send_read_log(pm8001_ha, pm8001_dev);
2772 return;
2773 }
2774
2775 if (unlikely(!t || !t->lldd_task || !t->dev)) {
2776 pm8001_dbg(pm8001_ha, FAIL, "task or dev null\n");
2777 return;
2778 }
2779
2780 ts = &t->task_status;
2781 pm8001_dbg(pm8001_ha, IOERR, "port_id:0x%x, tag:0x%x, event:0x%x\n",
2782 port_id, tag, event);
2783 switch (event) {
2784 case IO_OVERFLOW:
2785 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n");
2786 ts->resp = SAS_TASK_COMPLETE;
2787 ts->stat = SAS_DATA_OVERRUN;
2788 ts->residual = 0;
2789 if (pm8001_dev)
2790 atomic_dec(&pm8001_dev->running_req);
2791 break;
2792 case IO_XFER_ERROR_BREAK:
2793 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2794 ts->resp = SAS_TASK_COMPLETE;
2795 ts->stat = SAS_INTERRUPTED;
2796 break;
2797 case IO_XFER_ERROR_PHY_NOT_READY:
2798 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2799 ts->resp = SAS_TASK_COMPLETE;
2800 ts->stat = SAS_OPEN_REJECT;
2801 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2802 break;
2803 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2804 pm8001_dbg(pm8001_ha, IO,
2805 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2806 ts->resp = SAS_TASK_COMPLETE;
2807 ts->stat = SAS_OPEN_REJECT;
2808 ts->open_rej_reason = SAS_OREJ_EPROTO;
2809 break;
2810 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2811 pm8001_dbg(pm8001_ha, IO,
2812 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2813 ts->resp = SAS_TASK_COMPLETE;
2814 ts->stat = SAS_OPEN_REJECT;
2815 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2816 break;
2817 case IO_OPEN_CNX_ERROR_BREAK:
2818 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2819 ts->resp = SAS_TASK_COMPLETE;
2820 ts->stat = SAS_OPEN_REJECT;
2821 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2822 break;
2823 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2824 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2825 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2826 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2827 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2828 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2829 pm8001_dbg(pm8001_ha, FAIL,
2830 "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2831 ts->resp = SAS_TASK_UNDELIVERED;
2832 ts->stat = SAS_DEV_NO_RESPONSE;
2833 if (!t->uldd_task) {
2834 pm8001_handle_event(pm8001_ha,
2835 pm8001_dev,
2836 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2837 ts->resp = SAS_TASK_COMPLETE;
2838 ts->stat = SAS_QUEUE_FULL;
2839 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2840 return;
2841 }
2842 break;
2843 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2844 pm8001_dbg(pm8001_ha, IO,
2845 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2846 ts->resp = SAS_TASK_UNDELIVERED;
2847 ts->stat = SAS_OPEN_REJECT;
2848 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2849 break;
2850 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2851 pm8001_dbg(pm8001_ha, IO,
2852 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2853 ts->resp = SAS_TASK_COMPLETE;
2854 ts->stat = SAS_OPEN_REJECT;
2855 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2856 break;
2857 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2858 pm8001_dbg(pm8001_ha, IO,
2859 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2860 ts->resp = SAS_TASK_COMPLETE;
2861 ts->stat = SAS_OPEN_REJECT;
2862 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2863 break;
2864 case IO_XFER_ERROR_NAK_RECEIVED:
2865 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2866 ts->resp = SAS_TASK_COMPLETE;
2867 ts->stat = SAS_NAK_R_ERR;
2868 break;
2869 case IO_XFER_ERROR_PEER_ABORTED:
2870 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PEER_ABORTED\n");
2871 ts->resp = SAS_TASK_COMPLETE;
2872 ts->stat = SAS_NAK_R_ERR;
2873 break;
2874 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2875 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n");
2876 ts->resp = SAS_TASK_COMPLETE;
2877 ts->stat = SAS_DATA_UNDERRUN;
2878 break;
2879 case IO_XFER_OPEN_RETRY_TIMEOUT:
2880 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2881 ts->resp = SAS_TASK_COMPLETE;
2882 ts->stat = SAS_OPEN_TO;
2883 break;
2884 case IO_XFER_ERROR_UNEXPECTED_PHASE:
2885 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n");
2886 ts->resp = SAS_TASK_COMPLETE;
2887 ts->stat = SAS_OPEN_TO;
2888 break;
2889 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2890 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n");
2891 ts->resp = SAS_TASK_COMPLETE;
2892 ts->stat = SAS_OPEN_TO;
2893 break;
2894 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2895 pm8001_dbg(pm8001_ha, IO,
2896 "IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n");
2897 ts->resp = SAS_TASK_COMPLETE;
2898 ts->stat = SAS_OPEN_TO;
2899 break;
2900 case IO_XFER_ERROR_OFFSET_MISMATCH:
2901 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n");
2902 ts->resp = SAS_TASK_COMPLETE;
2903 ts->stat = SAS_OPEN_TO;
2904 break;
2905 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2906 pm8001_dbg(pm8001_ha, IO,
2907 "IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n");
2908 ts->resp = SAS_TASK_COMPLETE;
2909 ts->stat = SAS_OPEN_TO;
2910 break;
2911 case IO_XFER_CMD_FRAME_ISSUED:
2912 pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n");
2913 break;
2914 case IO_XFER_PIO_SETUP_ERROR:
2915 pm8001_dbg(pm8001_ha, IO, "IO_XFER_PIO_SETUP_ERROR\n");
2916 ts->resp = SAS_TASK_COMPLETE;
2917 ts->stat = SAS_OPEN_TO;
2918 break;
2919 case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
2920 pm8001_dbg(pm8001_ha, FAIL,
2921 "IO_XFR_ERROR_INTERNAL_CRC_ERROR\n");
2922 /* TBC: used default set values */
2923 ts->resp = SAS_TASK_COMPLETE;
2924 ts->stat = SAS_OPEN_TO;
2925 break;
2926 case IO_XFER_DMA_ACTIVATE_TIMEOUT:
2927 pm8001_dbg(pm8001_ha, FAIL, "IO_XFR_DMA_ACTIVATE_TIMEOUT\n");
2928 /* TBC: used default set values */
2929 ts->resp = SAS_TASK_COMPLETE;
2930 ts->stat = SAS_OPEN_TO;
2931 break;
2932 default:
2933 pm8001_dbg(pm8001_ha, IO, "Unknown status 0x%x\n", event);
2934 /* not allowed case. Therefore, return failed status */
2935 ts->resp = SAS_TASK_COMPLETE;
2936 ts->stat = SAS_OPEN_TO;
2937 break;
2938 }
2939 spin_lock_irqsave(&t->task_state_lock, flags);
2940 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2941 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2942 t->task_state_flags |= SAS_TASK_STATE_DONE;
2943 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2944 spin_unlock_irqrestore(&t->task_state_lock, flags);
2945 pm8001_dbg(pm8001_ha, FAIL,
2946 "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
2947 t, event, ts->resp, ts->stat);
2948 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2949 } else {
2950 spin_unlock_irqrestore(&t->task_state_lock, flags);
2951 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2952 }
2953 }
2954
2955 /*See the comments for mpi_ssp_completion */
2956 static void
mpi_smp_completion(struct pm8001_hba_info * pm8001_ha,void * piomb)2957 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2958 {
2959 u32 param, i;
2960 struct sas_task *t;
2961 struct pm8001_ccb_info *ccb;
2962 unsigned long flags;
2963 u32 status;
2964 u32 tag;
2965 struct smp_completion_resp *psmpPayload;
2966 struct task_status_struct *ts;
2967 struct pm8001_device *pm8001_dev;
2968 char *pdma_respaddr = NULL;
2969
2970 psmpPayload = (struct smp_completion_resp *)(piomb + 4);
2971 status = le32_to_cpu(psmpPayload->status);
2972 tag = le32_to_cpu(psmpPayload->tag);
2973
2974 ccb = &pm8001_ha->ccb_info[tag];
2975 param = le32_to_cpu(psmpPayload->param);
2976 t = ccb->task;
2977 ts = &t->task_status;
2978 pm8001_dev = ccb->device;
2979 if (status)
2980 pm8001_dbg(pm8001_ha, FAIL, "smp IO status 0x%x\n", status);
2981 if (unlikely(!t || !t->lldd_task || !t->dev))
2982 return;
2983
2984 pm8001_dbg(pm8001_ha, DEV, "tag::0x%x status::0x%x\n", tag, status);
2985
2986 switch (status) {
2987
2988 case IO_SUCCESS:
2989 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n");
2990 ts->resp = SAS_TASK_COMPLETE;
2991 ts->stat = SAM_STAT_GOOD;
2992 if (pm8001_dev)
2993 atomic_dec(&pm8001_dev->running_req);
2994 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
2995 pm8001_dbg(pm8001_ha, IO,
2996 "DIRECT RESPONSE Length:%d\n",
2997 param);
2998 pdma_respaddr = (char *)(phys_to_virt(cpu_to_le64
2999 ((u64)sg_dma_address
3000 (&t->smp_task.smp_resp))));
3001 for (i = 0; i < param; i++) {
3002 *(pdma_respaddr+i) = psmpPayload->_r_a[i];
3003 pm8001_dbg(pm8001_ha, IO,
3004 "SMP Byte%d DMA data 0x%x psmp 0x%x\n",
3005 i, *(pdma_respaddr + i),
3006 psmpPayload->_r_a[i]);
3007 }
3008 }
3009 break;
3010 case IO_ABORTED:
3011 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB\n");
3012 ts->resp = SAS_TASK_COMPLETE;
3013 ts->stat = SAS_ABORTED_TASK;
3014 if (pm8001_dev)
3015 atomic_dec(&pm8001_dev->running_req);
3016 break;
3017 case IO_OVERFLOW:
3018 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n");
3019 ts->resp = SAS_TASK_COMPLETE;
3020 ts->stat = SAS_DATA_OVERRUN;
3021 ts->residual = 0;
3022 if (pm8001_dev)
3023 atomic_dec(&pm8001_dev->running_req);
3024 break;
3025 case IO_NO_DEVICE:
3026 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n");
3027 ts->resp = SAS_TASK_COMPLETE;
3028 ts->stat = SAS_PHY_DOWN;
3029 break;
3030 case IO_ERROR_HW_TIMEOUT:
3031 pm8001_dbg(pm8001_ha, IO, "IO_ERROR_HW_TIMEOUT\n");
3032 ts->resp = SAS_TASK_COMPLETE;
3033 ts->stat = SAM_STAT_BUSY;
3034 break;
3035 case IO_XFER_ERROR_BREAK:
3036 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
3037 ts->resp = SAS_TASK_COMPLETE;
3038 ts->stat = SAM_STAT_BUSY;
3039 break;
3040 case IO_XFER_ERROR_PHY_NOT_READY:
3041 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
3042 ts->resp = SAS_TASK_COMPLETE;
3043 ts->stat = SAM_STAT_BUSY;
3044 break;
3045 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
3046 pm8001_dbg(pm8001_ha, IO,
3047 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
3048 ts->resp = SAS_TASK_COMPLETE;
3049 ts->stat = SAS_OPEN_REJECT;
3050 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
3051 break;
3052 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
3053 pm8001_dbg(pm8001_ha, IO,
3054 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
3055 ts->resp = SAS_TASK_COMPLETE;
3056 ts->stat = SAS_OPEN_REJECT;
3057 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
3058 break;
3059 case IO_OPEN_CNX_ERROR_BREAK:
3060 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
3061 ts->resp = SAS_TASK_COMPLETE;
3062 ts->stat = SAS_OPEN_REJECT;
3063 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
3064 break;
3065 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
3066 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
3067 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
3068 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
3069 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
3070 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
3071 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
3072 ts->resp = SAS_TASK_COMPLETE;
3073 ts->stat = SAS_OPEN_REJECT;
3074 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
3075 pm8001_handle_event(pm8001_ha,
3076 pm8001_dev,
3077 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
3078 break;
3079 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
3080 pm8001_dbg(pm8001_ha, IO,
3081 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
3082 ts->resp = SAS_TASK_COMPLETE;
3083 ts->stat = SAS_OPEN_REJECT;
3084 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
3085 break;
3086 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
3087 pm8001_dbg(pm8001_ha, IO,
3088 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
3089 ts->resp = SAS_TASK_COMPLETE;
3090 ts->stat = SAS_OPEN_REJECT;
3091 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
3092 break;
3093 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
3094 pm8001_dbg(pm8001_ha, IO,
3095 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
3096 ts->resp = SAS_TASK_COMPLETE;
3097 ts->stat = SAS_OPEN_REJECT;
3098 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
3099 break;
3100 case IO_XFER_ERROR_RX_FRAME:
3101 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_RX_FRAME\n");
3102 ts->resp = SAS_TASK_COMPLETE;
3103 ts->stat = SAS_DEV_NO_RESPONSE;
3104 break;
3105 case IO_XFER_OPEN_RETRY_TIMEOUT:
3106 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
3107 ts->resp = SAS_TASK_COMPLETE;
3108 ts->stat = SAS_OPEN_REJECT;
3109 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3110 break;
3111 case IO_ERROR_INTERNAL_SMP_RESOURCE:
3112 pm8001_dbg(pm8001_ha, IO, "IO_ERROR_INTERNAL_SMP_RESOURCE\n");
3113 ts->resp = SAS_TASK_COMPLETE;
3114 ts->stat = SAS_QUEUE_FULL;
3115 break;
3116 case IO_PORT_IN_RESET:
3117 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n");
3118 ts->resp = SAS_TASK_COMPLETE;
3119 ts->stat = SAS_OPEN_REJECT;
3120 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3121 break;
3122 case IO_DS_NON_OPERATIONAL:
3123 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n");
3124 ts->resp = SAS_TASK_COMPLETE;
3125 ts->stat = SAS_DEV_NO_RESPONSE;
3126 break;
3127 case IO_DS_IN_RECOVERY:
3128 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n");
3129 ts->resp = SAS_TASK_COMPLETE;
3130 ts->stat = SAS_OPEN_REJECT;
3131 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3132 break;
3133 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
3134 pm8001_dbg(pm8001_ha, IO,
3135 "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n");
3136 ts->resp = SAS_TASK_COMPLETE;
3137 ts->stat = SAS_OPEN_REJECT;
3138 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3139 break;
3140 default:
3141 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status);
3142 ts->resp = SAS_TASK_COMPLETE;
3143 ts->stat = SAS_DEV_NO_RESPONSE;
3144 /* not allowed case. Therefore, return failed status */
3145 break;
3146 }
3147 spin_lock_irqsave(&t->task_state_lock, flags);
3148 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
3149 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
3150 t->task_state_flags |= SAS_TASK_STATE_DONE;
3151 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
3152 spin_unlock_irqrestore(&t->task_state_lock, flags);
3153 pm8001_dbg(pm8001_ha, FAIL,
3154 "task 0x%p done with io_status 0x%x resp 0x%xstat 0x%x but aborted by upper layer!\n",
3155 t, status, ts->resp, ts->stat);
3156 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
3157 } else {
3158 spin_unlock_irqrestore(&t->task_state_lock, flags);
3159 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
3160 mb();/* in order to force CPU ordering */
3161 t->task_done(t);
3162 }
3163 }
3164
3165 /**
3166 * pm80xx_hw_event_ack_req- For PM8001,some events need to acknowage to FW.
3167 * @pm8001_ha: our hba card information
3168 * @Qnum: the outbound queue message number.
3169 * @SEA: source of event to ack
3170 * @port_id: port id.
3171 * @phyId: phy id.
3172 * @param0: parameter 0.
3173 * @param1: parameter 1.
3174 */
pm80xx_hw_event_ack_req(struct pm8001_hba_info * pm8001_ha,u32 Qnum,u32 SEA,u32 port_id,u32 phyId,u32 param0,u32 param1)3175 static void pm80xx_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
3176 u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
3177 {
3178 struct hw_event_ack_req payload;
3179 u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
3180
3181 struct inbound_queue_table *circularQ;
3182
3183 memset((u8 *)&payload, 0, sizeof(payload));
3184 circularQ = &pm8001_ha->inbnd_q_tbl[Qnum];
3185 payload.tag = cpu_to_le32(1);
3186 payload.phyid_sea_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
3187 ((phyId & 0xFF) << 24) | (port_id & 0xFF));
3188 payload.param0 = cpu_to_le32(param0);
3189 payload.param1 = cpu_to_le32(param1);
3190 pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
3191 sizeof(payload), 0);
3192 }
3193
3194 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
3195 u32 phyId, u32 phy_op);
3196
hw_event_port_recover(struct pm8001_hba_info * pm8001_ha,void * piomb)3197 static void hw_event_port_recover(struct pm8001_hba_info *pm8001_ha,
3198 void *piomb)
3199 {
3200 struct hw_event_resp *pPayload = (struct hw_event_resp *)(piomb + 4);
3201 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3202 u8 phy_id = (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3203 u32 lr_status_evt_portid =
3204 le32_to_cpu(pPayload->lr_status_evt_portid);
3205 u8 deviceType = pPayload->sas_identify.dev_type;
3206 u8 link_rate = (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
3207 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3208 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3209 struct pm8001_port *port = &pm8001_ha->port[port_id];
3210
3211 if (deviceType == SAS_END_DEVICE) {
3212 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id,
3213 PHY_NOTIFY_ENABLE_SPINUP);
3214 }
3215
3216 port->wide_port_phymap |= (1U << phy_id);
3217 pm8001_get_lrate_mode(phy, link_rate);
3218 phy->sas_phy.oob_mode = SAS_OOB_MODE;
3219 phy->phy_state = PHY_STATE_LINK_UP_SPCV;
3220 phy->phy_attached = 1;
3221 }
3222
3223 /**
3224 * hw_event_sas_phy_up -FW tells me a SAS phy up event.
3225 * @pm8001_ha: our hba card information
3226 * @piomb: IO message buffer
3227 */
3228 static void
hw_event_sas_phy_up(struct pm8001_hba_info * pm8001_ha,void * piomb)3229 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3230 {
3231 struct hw_event_resp *pPayload =
3232 (struct hw_event_resp *)(piomb + 4);
3233 u32 lr_status_evt_portid =
3234 le32_to_cpu(pPayload->lr_status_evt_portid);
3235 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3236
3237 u8 link_rate =
3238 (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
3239 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3240 u8 phy_id =
3241 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3242 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
3243
3244 struct pm8001_port *port = &pm8001_ha->port[port_id];
3245 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3246 unsigned long flags;
3247 u8 deviceType = pPayload->sas_identify.dev_type;
3248 port->port_state = portstate;
3249 port->wide_port_phymap |= (1U << phy_id);
3250 phy->phy_state = PHY_STATE_LINK_UP_SPCV;
3251 pm8001_dbg(pm8001_ha, MSG,
3252 "portid:%d; phyid:%d; linkrate:%d; portstate:%x; devicetype:%x\n",
3253 port_id, phy_id, link_rate, portstate, deviceType);
3254
3255 switch (deviceType) {
3256 case SAS_PHY_UNUSED:
3257 pm8001_dbg(pm8001_ha, MSG, "device type no device.\n");
3258 break;
3259 case SAS_END_DEVICE:
3260 pm8001_dbg(pm8001_ha, MSG, "end device.\n");
3261 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id,
3262 PHY_NOTIFY_ENABLE_SPINUP);
3263 port->port_attached = 1;
3264 pm8001_get_lrate_mode(phy, link_rate);
3265 break;
3266 case SAS_EDGE_EXPANDER_DEVICE:
3267 pm8001_dbg(pm8001_ha, MSG, "expander device.\n");
3268 port->port_attached = 1;
3269 pm8001_get_lrate_mode(phy, link_rate);
3270 break;
3271 case SAS_FANOUT_EXPANDER_DEVICE:
3272 pm8001_dbg(pm8001_ha, MSG, "fanout expander device.\n");
3273 port->port_attached = 1;
3274 pm8001_get_lrate_mode(phy, link_rate);
3275 break;
3276 default:
3277 pm8001_dbg(pm8001_ha, DEVIO, "unknown device type(%x)\n",
3278 deviceType);
3279 break;
3280 }
3281 phy->phy_type |= PORT_TYPE_SAS;
3282 phy->identify.device_type = deviceType;
3283 phy->phy_attached = 1;
3284 if (phy->identify.device_type == SAS_END_DEVICE)
3285 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
3286 else if (phy->identify.device_type != SAS_PHY_UNUSED)
3287 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
3288 phy->sas_phy.oob_mode = SAS_OOB_MODE;
3289 sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
3290 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3291 memcpy(phy->frame_rcvd, &pPayload->sas_identify,
3292 sizeof(struct sas_identify_frame)-4);
3293 phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
3294 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3295 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3296 if (pm8001_ha->flags == PM8001F_RUN_TIME)
3297 mdelay(200); /* delay a moment to wait for disk to spin up */
3298 pm8001_bytes_dmaed(pm8001_ha, phy_id);
3299 }
3300
3301 /**
3302 * hw_event_sata_phy_up -FW tells me a SATA phy up event.
3303 * @pm8001_ha: our hba card information
3304 * @piomb: IO message buffer
3305 */
3306 static void
hw_event_sata_phy_up(struct pm8001_hba_info * pm8001_ha,void * piomb)3307 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3308 {
3309 struct hw_event_resp *pPayload =
3310 (struct hw_event_resp *)(piomb + 4);
3311 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3312 u32 lr_status_evt_portid =
3313 le32_to_cpu(pPayload->lr_status_evt_portid);
3314 u8 link_rate =
3315 (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
3316 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3317 u8 phy_id =
3318 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3319
3320 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
3321
3322 struct pm8001_port *port = &pm8001_ha->port[port_id];
3323 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3324 unsigned long flags;
3325 pm8001_dbg(pm8001_ha, DEVIO,
3326 "port id %d, phy id %d link_rate %d portstate 0x%x\n",
3327 port_id, phy_id, link_rate, portstate);
3328
3329 port->port_state = portstate;
3330 phy->phy_state = PHY_STATE_LINK_UP_SPCV;
3331 port->port_attached = 1;
3332 pm8001_get_lrate_mode(phy, link_rate);
3333 phy->phy_type |= PORT_TYPE_SATA;
3334 phy->phy_attached = 1;
3335 phy->sas_phy.oob_mode = SATA_OOB_MODE;
3336 sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
3337 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3338 memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
3339 sizeof(struct dev_to_host_fis));
3340 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
3341 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
3342 phy->identify.device_type = SAS_SATA_DEV;
3343 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3344 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3345 pm8001_bytes_dmaed(pm8001_ha, phy_id);
3346 }
3347
3348 /**
3349 * hw_event_phy_down -we should notify the libsas the phy is down.
3350 * @pm8001_ha: our hba card information
3351 * @piomb: IO message buffer
3352 */
3353 static void
hw_event_phy_down(struct pm8001_hba_info * pm8001_ha,void * piomb)3354 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
3355 {
3356 struct hw_event_resp *pPayload =
3357 (struct hw_event_resp *)(piomb + 4);
3358
3359 u32 lr_status_evt_portid =
3360 le32_to_cpu(pPayload->lr_status_evt_portid);
3361 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3362 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3363 u8 phy_id =
3364 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3365 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
3366
3367 struct pm8001_port *port = &pm8001_ha->port[port_id];
3368 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3369 u32 port_sata = (phy->phy_type & PORT_TYPE_SATA);
3370 port->port_state = portstate;
3371 phy->identify.device_type = 0;
3372 phy->phy_attached = 0;
3373 switch (portstate) {
3374 case PORT_VALID:
3375 break;
3376 case PORT_INVALID:
3377 pm8001_dbg(pm8001_ha, MSG, " PortInvalid portID %d\n",
3378 port_id);
3379 pm8001_dbg(pm8001_ha, MSG,
3380 " Last phy Down and port invalid\n");
3381 if (port_sata) {
3382 phy->phy_type = 0;
3383 port->port_attached = 0;
3384 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3385 port_id, phy_id, 0, 0);
3386 }
3387 sas_phy_disconnected(&phy->sas_phy);
3388 break;
3389 case PORT_IN_RESET:
3390 pm8001_dbg(pm8001_ha, MSG, " Port In Reset portID %d\n",
3391 port_id);
3392 break;
3393 case PORT_NOT_ESTABLISHED:
3394 pm8001_dbg(pm8001_ha, MSG,
3395 " Phy Down and PORT_NOT_ESTABLISHED\n");
3396 port->port_attached = 0;
3397 break;
3398 case PORT_LOSTCOMM:
3399 pm8001_dbg(pm8001_ha, MSG, " Phy Down and PORT_LOSTCOMM\n");
3400 pm8001_dbg(pm8001_ha, MSG,
3401 " Last phy Down and port invalid\n");
3402 if (port_sata) {
3403 port->port_attached = 0;
3404 phy->phy_type = 0;
3405 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3406 port_id, phy_id, 0, 0);
3407 }
3408 sas_phy_disconnected(&phy->sas_phy);
3409 break;
3410 default:
3411 port->port_attached = 0;
3412 pm8001_dbg(pm8001_ha, DEVIO,
3413 " Phy Down and(default) = 0x%x\n",
3414 portstate);
3415 break;
3416
3417 }
3418 if (port_sata && (portstate != PORT_IN_RESET))
3419 sas_notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL);
3420 }
3421
mpi_phy_start_resp(struct pm8001_hba_info * pm8001_ha,void * piomb)3422 static int mpi_phy_start_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3423 {
3424 struct phy_start_resp *pPayload =
3425 (struct phy_start_resp *)(piomb + 4);
3426 u32 status =
3427 le32_to_cpu(pPayload->status);
3428 u32 phy_id =
3429 le32_to_cpu(pPayload->phyid);
3430 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3431
3432 pm8001_dbg(pm8001_ha, INIT,
3433 "phy start resp status:0x%x, phyid:0x%x\n",
3434 status, phy_id);
3435 if (status == 0)
3436 phy->phy_state = PHY_LINK_DOWN;
3437
3438 if (pm8001_ha->flags == PM8001F_RUN_TIME &&
3439 phy->enable_completion != NULL) {
3440 complete(phy->enable_completion);
3441 phy->enable_completion = NULL;
3442 }
3443 return 0;
3444
3445 }
3446
3447 /**
3448 * mpi_thermal_hw_event -The hw event has come.
3449 * @pm8001_ha: our hba card information
3450 * @piomb: IO message buffer
3451 */
mpi_thermal_hw_event(struct pm8001_hba_info * pm8001_ha,void * piomb)3452 static int mpi_thermal_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3453 {
3454 struct thermal_hw_event *pPayload =
3455 (struct thermal_hw_event *)(piomb + 4);
3456
3457 u32 thermal_event = le32_to_cpu(pPayload->thermal_event);
3458 u32 rht_lht = le32_to_cpu(pPayload->rht_lht);
3459
3460 if (thermal_event & 0x40) {
3461 pm8001_dbg(pm8001_ha, IO,
3462 "Thermal Event: Local high temperature violated!\n");
3463 pm8001_dbg(pm8001_ha, IO,
3464 "Thermal Event: Measured local high temperature %d\n",
3465 ((rht_lht & 0xFF00) >> 8));
3466 }
3467 if (thermal_event & 0x10) {
3468 pm8001_dbg(pm8001_ha, IO,
3469 "Thermal Event: Remote high temperature violated!\n");
3470 pm8001_dbg(pm8001_ha, IO,
3471 "Thermal Event: Measured remote high temperature %d\n",
3472 ((rht_lht & 0xFF000000) >> 24));
3473 }
3474 return 0;
3475 }
3476
3477 /**
3478 * mpi_hw_event -The hw event has come.
3479 * @pm8001_ha: our hba card information
3480 * @piomb: IO message buffer
3481 */
mpi_hw_event(struct pm8001_hba_info * pm8001_ha,void * piomb)3482 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3483 {
3484 unsigned long flags, i;
3485 struct hw_event_resp *pPayload =
3486 (struct hw_event_resp *)(piomb + 4);
3487 u32 lr_status_evt_portid =
3488 le32_to_cpu(pPayload->lr_status_evt_portid);
3489 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3490 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3491 u8 phy_id =
3492 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3493 u16 eventType =
3494 (u16)((lr_status_evt_portid & 0x00FFFF00) >> 8);
3495 u8 status =
3496 (u8)((lr_status_evt_portid & 0x0F000000) >> 24);
3497 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3498 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3499 struct pm8001_port *port = &pm8001_ha->port[port_id];
3500 struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
3501 pm8001_dbg(pm8001_ha, DEV,
3502 "portid:%d phyid:%d event:0x%x status:0x%x\n",
3503 port_id, phy_id, eventType, status);
3504
3505 switch (eventType) {
3506
3507 case HW_EVENT_SAS_PHY_UP:
3508 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_START_STATUS\n");
3509 hw_event_sas_phy_up(pm8001_ha, piomb);
3510 break;
3511 case HW_EVENT_SATA_PHY_UP:
3512 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_SATA_PHY_UP\n");
3513 hw_event_sata_phy_up(pm8001_ha, piomb);
3514 break;
3515 case HW_EVENT_SATA_SPINUP_HOLD:
3516 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_SATA_SPINUP_HOLD\n");
3517 sas_notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD);
3518 break;
3519 case HW_EVENT_PHY_DOWN:
3520 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_DOWN\n");
3521 hw_event_phy_down(pm8001_ha, piomb);
3522 if (pm8001_ha->reset_in_progress) {
3523 pm8001_dbg(pm8001_ha, MSG, "Reset in progress\n");
3524 return 0;
3525 }
3526 phy->phy_attached = 0;
3527 phy->phy_state = PHY_LINK_DISABLE;
3528 break;
3529 case HW_EVENT_PORT_INVALID:
3530 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_INVALID\n");
3531 sas_phy_disconnected(sas_phy);
3532 phy->phy_attached = 0;
3533 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3534 break;
3535 /* the broadcast change primitive received, tell the LIBSAS this event
3536 to revalidate the sas domain*/
3537 case HW_EVENT_BROADCAST_CHANGE:
3538 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_CHANGE\n");
3539 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
3540 port_id, phy_id, 1, 0);
3541 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3542 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
3543 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3544 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3545 break;
3546 case HW_EVENT_PHY_ERROR:
3547 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_ERROR\n");
3548 sas_phy_disconnected(&phy->sas_phy);
3549 phy->phy_attached = 0;
3550 sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR);
3551 break;
3552 case HW_EVENT_BROADCAST_EXP:
3553 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_EXP\n");
3554 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3555 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
3556 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3557 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3558 break;
3559 case HW_EVENT_LINK_ERR_INVALID_DWORD:
3560 pm8001_dbg(pm8001_ha, MSG,
3561 "HW_EVENT_LINK_ERR_INVALID_DWORD\n");
3562 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3563 HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
3564 break;
3565 case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
3566 pm8001_dbg(pm8001_ha, MSG,
3567 "HW_EVENT_LINK_ERR_DISPARITY_ERROR\n");
3568 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3569 HW_EVENT_LINK_ERR_DISPARITY_ERROR,
3570 port_id, phy_id, 0, 0);
3571 break;
3572 case HW_EVENT_LINK_ERR_CODE_VIOLATION:
3573 pm8001_dbg(pm8001_ha, MSG,
3574 "HW_EVENT_LINK_ERR_CODE_VIOLATION\n");
3575 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3576 HW_EVENT_LINK_ERR_CODE_VIOLATION,
3577 port_id, phy_id, 0, 0);
3578 break;
3579 case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
3580 pm8001_dbg(pm8001_ha, MSG,
3581 "HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n");
3582 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3583 HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
3584 port_id, phy_id, 0, 0);
3585 break;
3586 case HW_EVENT_MALFUNCTION:
3587 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_MALFUNCTION\n");
3588 break;
3589 case HW_EVENT_BROADCAST_SES:
3590 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_SES\n");
3591 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3592 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
3593 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3594 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3595 break;
3596 case HW_EVENT_INBOUND_CRC_ERROR:
3597 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_INBOUND_CRC_ERROR\n");
3598 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3599 HW_EVENT_INBOUND_CRC_ERROR,
3600 port_id, phy_id, 0, 0);
3601 break;
3602 case HW_EVENT_HARD_RESET_RECEIVED:
3603 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_HARD_RESET_RECEIVED\n");
3604 sas_notify_port_event(sas_phy, PORTE_HARD_RESET);
3605 break;
3606 case HW_EVENT_ID_FRAME_TIMEOUT:
3607 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_ID_FRAME_TIMEOUT\n");
3608 sas_phy_disconnected(sas_phy);
3609 phy->phy_attached = 0;
3610 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3611 break;
3612 case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
3613 pm8001_dbg(pm8001_ha, MSG,
3614 "HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n");
3615 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3616 HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
3617 port_id, phy_id, 0, 0);
3618 sas_phy_disconnected(sas_phy);
3619 phy->phy_attached = 0;
3620 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3621 break;
3622 case HW_EVENT_PORT_RESET_TIMER_TMO:
3623 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RESET_TIMER_TMO\n");
3624 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3625 port_id, phy_id, 0, 0);
3626 sas_phy_disconnected(sas_phy);
3627 phy->phy_attached = 0;
3628 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3629 if (pm8001_ha->phy[phy_id].reset_completion) {
3630 pm8001_ha->phy[phy_id].port_reset_status =
3631 PORT_RESET_TMO;
3632 complete(pm8001_ha->phy[phy_id].reset_completion);
3633 pm8001_ha->phy[phy_id].reset_completion = NULL;
3634 }
3635 break;
3636 case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
3637 pm8001_dbg(pm8001_ha, MSG,
3638 "HW_EVENT_PORT_RECOVERY_TIMER_TMO\n");
3639 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3640 HW_EVENT_PORT_RECOVERY_TIMER_TMO,
3641 port_id, phy_id, 0, 0);
3642 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
3643 if (port->wide_port_phymap & (1 << i)) {
3644 phy = &pm8001_ha->phy[i];
3645 sas_notify_phy_event(&phy->sas_phy,
3646 PHYE_LOSS_OF_SIGNAL);
3647 port->wide_port_phymap &= ~(1 << i);
3648 }
3649 }
3650 break;
3651 case HW_EVENT_PORT_RECOVER:
3652 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RECOVER\n");
3653 hw_event_port_recover(pm8001_ha, piomb);
3654 break;
3655 case HW_EVENT_PORT_RESET_COMPLETE:
3656 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RESET_COMPLETE\n");
3657 if (pm8001_ha->phy[phy_id].reset_completion) {
3658 pm8001_ha->phy[phy_id].port_reset_status =
3659 PORT_RESET_SUCCESS;
3660 complete(pm8001_ha->phy[phy_id].reset_completion);
3661 pm8001_ha->phy[phy_id].reset_completion = NULL;
3662 }
3663 break;
3664 case EVENT_BROADCAST_ASYNCH_EVENT:
3665 pm8001_dbg(pm8001_ha, MSG, "EVENT_BROADCAST_ASYNCH_EVENT\n");
3666 break;
3667 default:
3668 pm8001_dbg(pm8001_ha, DEVIO, "Unknown event type 0x%x\n",
3669 eventType);
3670 break;
3671 }
3672 return 0;
3673 }
3674
3675 /**
3676 * mpi_phy_stop_resp - SPCv specific
3677 * @pm8001_ha: our hba card information
3678 * @piomb: IO message buffer
3679 */
mpi_phy_stop_resp(struct pm8001_hba_info * pm8001_ha,void * piomb)3680 static int mpi_phy_stop_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3681 {
3682 struct phy_stop_resp *pPayload =
3683 (struct phy_stop_resp *)(piomb + 4);
3684 u32 status =
3685 le32_to_cpu(pPayload->status);
3686 u32 phyid =
3687 le32_to_cpu(pPayload->phyid) & 0xFF;
3688 struct pm8001_phy *phy = &pm8001_ha->phy[phyid];
3689 pm8001_dbg(pm8001_ha, MSG, "phy:0x%x status:0x%x\n",
3690 phyid, status);
3691 if (status == PHY_STOP_SUCCESS ||
3692 status == PHY_STOP_ERR_DEVICE_ATTACHED)
3693 phy->phy_state = PHY_LINK_DISABLE;
3694 return 0;
3695 }
3696
3697 /**
3698 * mpi_set_controller_config_resp - SPCv specific
3699 * @pm8001_ha: our hba card information
3700 * @piomb: IO message buffer
3701 */
mpi_set_controller_config_resp(struct pm8001_hba_info * pm8001_ha,void * piomb)3702 static int mpi_set_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
3703 void *piomb)
3704 {
3705 struct set_ctrl_cfg_resp *pPayload =
3706 (struct set_ctrl_cfg_resp *)(piomb + 4);
3707 u32 status = le32_to_cpu(pPayload->status);
3708 u32 err_qlfr_pgcd = le32_to_cpu(pPayload->err_qlfr_pgcd);
3709
3710 pm8001_dbg(pm8001_ha, MSG,
3711 "SET CONTROLLER RESP: status 0x%x qlfr_pgcd 0x%x\n",
3712 status, err_qlfr_pgcd);
3713
3714 return 0;
3715 }
3716
3717 /**
3718 * mpi_get_controller_config_resp - SPCv specific
3719 * @pm8001_ha: our hba card information
3720 * @piomb: IO message buffer
3721 */
mpi_get_controller_config_resp(struct pm8001_hba_info * pm8001_ha,void * piomb)3722 static int mpi_get_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
3723 void *piomb)
3724 {
3725 pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n");
3726
3727 return 0;
3728 }
3729
3730 /**
3731 * mpi_get_phy_profile_resp - SPCv specific
3732 * @pm8001_ha: our hba card information
3733 * @piomb: IO message buffer
3734 */
mpi_get_phy_profile_resp(struct pm8001_hba_info * pm8001_ha,void * piomb)3735 static int mpi_get_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
3736 void *piomb)
3737 {
3738 pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n");
3739
3740 return 0;
3741 }
3742
3743 /**
3744 * mpi_flash_op_ext_resp - SPCv specific
3745 * @pm8001_ha: our hba card information
3746 * @piomb: IO message buffer
3747 */
mpi_flash_op_ext_resp(struct pm8001_hba_info * pm8001_ha,void * piomb)3748 static int mpi_flash_op_ext_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3749 {
3750 pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n");
3751
3752 return 0;
3753 }
3754
3755 /**
3756 * mpi_set_phy_profile_resp - SPCv specific
3757 * @pm8001_ha: our hba card information
3758 * @piomb: IO message buffer
3759 */
mpi_set_phy_profile_resp(struct pm8001_hba_info * pm8001_ha,void * piomb)3760 static int mpi_set_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
3761 void *piomb)
3762 {
3763 u32 tag;
3764 u8 page_code;
3765 int rc = 0;
3766 struct set_phy_profile_resp *pPayload =
3767 (struct set_phy_profile_resp *)(piomb + 4);
3768 u32 ppc_phyid = le32_to_cpu(pPayload->ppc_phyid);
3769 u32 status = le32_to_cpu(pPayload->status);
3770
3771 tag = le32_to_cpu(pPayload->tag);
3772 page_code = (u8)((ppc_phyid & 0xFF00) >> 8);
3773 if (status) {
3774 /* status is FAILED */
3775 pm8001_dbg(pm8001_ha, FAIL,
3776 "PhyProfile command failed with status 0x%08X\n",
3777 status);
3778 rc = -1;
3779 } else {
3780 if (page_code != SAS_PHY_ANALOG_SETTINGS_PAGE) {
3781 pm8001_dbg(pm8001_ha, FAIL, "Invalid page code 0x%X\n",
3782 page_code);
3783 rc = -1;
3784 }
3785 }
3786 pm8001_tag_free(pm8001_ha, tag);
3787 return rc;
3788 }
3789
3790 /**
3791 * mpi_kek_management_resp - SPCv specific
3792 * @pm8001_ha: our hba card information
3793 * @piomb: IO message buffer
3794 */
mpi_kek_management_resp(struct pm8001_hba_info * pm8001_ha,void * piomb)3795 static int mpi_kek_management_resp(struct pm8001_hba_info *pm8001_ha,
3796 void *piomb)
3797 {
3798 struct kek_mgmt_resp *pPayload = (struct kek_mgmt_resp *)(piomb + 4);
3799
3800 u32 status = le32_to_cpu(pPayload->status);
3801 u32 kidx_new_curr_ksop = le32_to_cpu(pPayload->kidx_new_curr_ksop);
3802 u32 err_qlfr = le32_to_cpu(pPayload->err_qlfr);
3803
3804 pm8001_dbg(pm8001_ha, MSG,
3805 "KEK MGMT RESP. Status 0x%x idx_ksop 0x%x err_qlfr 0x%x\n",
3806 status, kidx_new_curr_ksop, err_qlfr);
3807
3808 return 0;
3809 }
3810
3811 /**
3812 * mpi_dek_management_resp - SPCv specific
3813 * @pm8001_ha: our hba card information
3814 * @piomb: IO message buffer
3815 */
mpi_dek_management_resp(struct pm8001_hba_info * pm8001_ha,void * piomb)3816 static int mpi_dek_management_resp(struct pm8001_hba_info *pm8001_ha,
3817 void *piomb)
3818 {
3819 pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n");
3820
3821 return 0;
3822 }
3823
3824 /**
3825 * ssp_coalesced_comp_resp - SPCv specific
3826 * @pm8001_ha: our hba card information
3827 * @piomb: IO message buffer
3828 */
ssp_coalesced_comp_resp(struct pm8001_hba_info * pm8001_ha,void * piomb)3829 static int ssp_coalesced_comp_resp(struct pm8001_hba_info *pm8001_ha,
3830 void *piomb)
3831 {
3832 pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n");
3833
3834 return 0;
3835 }
3836
3837 /**
3838 * process_one_iomb - process one outbound Queue memory block
3839 * @pm8001_ha: our hba card information
3840 * @piomb: IO message buffer
3841 */
process_one_iomb(struct pm8001_hba_info * pm8001_ha,void * piomb)3842 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb)
3843 {
3844 __le32 pHeader = *(__le32 *)piomb;
3845 u32 opc = (u32)((le32_to_cpu(pHeader)) & 0xFFF);
3846
3847 switch (opc) {
3848 case OPC_OUB_ECHO:
3849 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_ECHO\n");
3850 break;
3851 case OPC_OUB_HW_EVENT:
3852 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_HW_EVENT\n");
3853 mpi_hw_event(pm8001_ha, piomb);
3854 break;
3855 case OPC_OUB_THERM_HW_EVENT:
3856 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_THERMAL_EVENT\n");
3857 mpi_thermal_hw_event(pm8001_ha, piomb);
3858 break;
3859 case OPC_OUB_SSP_COMP:
3860 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_COMP\n");
3861 mpi_ssp_completion(pm8001_ha, piomb);
3862 break;
3863 case OPC_OUB_SMP_COMP:
3864 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SMP_COMP\n");
3865 mpi_smp_completion(pm8001_ha, piomb);
3866 break;
3867 case OPC_OUB_LOCAL_PHY_CNTRL:
3868 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_LOCAL_PHY_CNTRL\n");
3869 pm8001_mpi_local_phy_ctl(pm8001_ha, piomb);
3870 break;
3871 case OPC_OUB_DEV_REGIST:
3872 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_REGIST\n");
3873 pm8001_mpi_reg_resp(pm8001_ha, piomb);
3874 break;
3875 case OPC_OUB_DEREG_DEV:
3876 pm8001_dbg(pm8001_ha, MSG, "unregister the device\n");
3877 pm8001_mpi_dereg_resp(pm8001_ha, piomb);
3878 break;
3879 case OPC_OUB_GET_DEV_HANDLE:
3880 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_DEV_HANDLE\n");
3881 break;
3882 case OPC_OUB_SATA_COMP:
3883 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_COMP\n");
3884 mpi_sata_completion(pm8001_ha, piomb);
3885 break;
3886 case OPC_OUB_SATA_EVENT:
3887 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_EVENT\n");
3888 mpi_sata_event(pm8001_ha, piomb);
3889 break;
3890 case OPC_OUB_SSP_EVENT:
3891 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_EVENT\n");
3892 mpi_ssp_event(pm8001_ha, piomb);
3893 break;
3894 case OPC_OUB_DEV_HANDLE_ARRIV:
3895 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_HANDLE_ARRIV\n");
3896 /*This is for target*/
3897 break;
3898 case OPC_OUB_SSP_RECV_EVENT:
3899 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_RECV_EVENT\n");
3900 /*This is for target*/
3901 break;
3902 case OPC_OUB_FW_FLASH_UPDATE:
3903 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_FW_FLASH_UPDATE\n");
3904 pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb);
3905 break;
3906 case OPC_OUB_GPIO_RESPONSE:
3907 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GPIO_RESPONSE\n");
3908 break;
3909 case OPC_OUB_GPIO_EVENT:
3910 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GPIO_EVENT\n");
3911 break;
3912 case OPC_OUB_GENERAL_EVENT:
3913 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GENERAL_EVENT\n");
3914 pm8001_mpi_general_event(pm8001_ha, piomb);
3915 break;
3916 case OPC_OUB_SSP_ABORT_RSP:
3917 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_ABORT_RSP\n");
3918 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3919 break;
3920 case OPC_OUB_SATA_ABORT_RSP:
3921 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_ABORT_RSP\n");
3922 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3923 break;
3924 case OPC_OUB_SAS_DIAG_MODE_START_END:
3925 pm8001_dbg(pm8001_ha, MSG,
3926 "OPC_OUB_SAS_DIAG_MODE_START_END\n");
3927 break;
3928 case OPC_OUB_SAS_DIAG_EXECUTE:
3929 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_DIAG_EXECUTE\n");
3930 break;
3931 case OPC_OUB_GET_TIME_STAMP:
3932 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_TIME_STAMP\n");
3933 break;
3934 case OPC_OUB_SAS_HW_EVENT_ACK:
3935 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_HW_EVENT_ACK\n");
3936 break;
3937 case OPC_OUB_PORT_CONTROL:
3938 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_PORT_CONTROL\n");
3939 break;
3940 case OPC_OUB_SMP_ABORT_RSP:
3941 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SMP_ABORT_RSP\n");
3942 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3943 break;
3944 case OPC_OUB_GET_NVMD_DATA:
3945 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_NVMD_DATA\n");
3946 pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb);
3947 break;
3948 case OPC_OUB_SET_NVMD_DATA:
3949 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_NVMD_DATA\n");
3950 pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb);
3951 break;
3952 case OPC_OUB_DEVICE_HANDLE_REMOVAL:
3953 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEVICE_HANDLE_REMOVAL\n");
3954 break;
3955 case OPC_OUB_SET_DEVICE_STATE:
3956 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_DEVICE_STATE\n");
3957 pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb);
3958 break;
3959 case OPC_OUB_GET_DEVICE_STATE:
3960 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_DEVICE_STATE\n");
3961 break;
3962 case OPC_OUB_SET_DEV_INFO:
3963 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_DEV_INFO\n");
3964 break;
3965 /* spcv specifc commands */
3966 case OPC_OUB_PHY_START_RESP:
3967 pm8001_dbg(pm8001_ha, MSG,
3968 "OPC_OUB_PHY_START_RESP opcode:%x\n", opc);
3969 mpi_phy_start_resp(pm8001_ha, piomb);
3970 break;
3971 case OPC_OUB_PHY_STOP_RESP:
3972 pm8001_dbg(pm8001_ha, MSG,
3973 "OPC_OUB_PHY_STOP_RESP opcode:%x\n", opc);
3974 mpi_phy_stop_resp(pm8001_ha, piomb);
3975 break;
3976 case OPC_OUB_SET_CONTROLLER_CONFIG:
3977 pm8001_dbg(pm8001_ha, MSG,
3978 "OPC_OUB_SET_CONTROLLER_CONFIG opcode:%x\n", opc);
3979 mpi_set_controller_config_resp(pm8001_ha, piomb);
3980 break;
3981 case OPC_OUB_GET_CONTROLLER_CONFIG:
3982 pm8001_dbg(pm8001_ha, MSG,
3983 "OPC_OUB_GET_CONTROLLER_CONFIG opcode:%x\n", opc);
3984 mpi_get_controller_config_resp(pm8001_ha, piomb);
3985 break;
3986 case OPC_OUB_GET_PHY_PROFILE:
3987 pm8001_dbg(pm8001_ha, MSG,
3988 "OPC_OUB_GET_PHY_PROFILE opcode:%x\n", opc);
3989 mpi_get_phy_profile_resp(pm8001_ha, piomb);
3990 break;
3991 case OPC_OUB_FLASH_OP_EXT:
3992 pm8001_dbg(pm8001_ha, MSG,
3993 "OPC_OUB_FLASH_OP_EXT opcode:%x\n", opc);
3994 mpi_flash_op_ext_resp(pm8001_ha, piomb);
3995 break;
3996 case OPC_OUB_SET_PHY_PROFILE:
3997 pm8001_dbg(pm8001_ha, MSG,
3998 "OPC_OUB_SET_PHY_PROFILE opcode:%x\n", opc);
3999 mpi_set_phy_profile_resp(pm8001_ha, piomb);
4000 break;
4001 case OPC_OUB_KEK_MANAGEMENT_RESP:
4002 pm8001_dbg(pm8001_ha, MSG,
4003 "OPC_OUB_KEK_MANAGEMENT_RESP opcode:%x\n", opc);
4004 mpi_kek_management_resp(pm8001_ha, piomb);
4005 break;
4006 case OPC_OUB_DEK_MANAGEMENT_RESP:
4007 pm8001_dbg(pm8001_ha, MSG,
4008 "OPC_OUB_DEK_MANAGEMENT_RESP opcode:%x\n", opc);
4009 mpi_dek_management_resp(pm8001_ha, piomb);
4010 break;
4011 case OPC_OUB_SSP_COALESCED_COMP_RESP:
4012 pm8001_dbg(pm8001_ha, MSG,
4013 "OPC_OUB_SSP_COALESCED_COMP_RESP opcode:%x\n", opc);
4014 ssp_coalesced_comp_resp(pm8001_ha, piomb);
4015 break;
4016 default:
4017 pm8001_dbg(pm8001_ha, DEVIO,
4018 "Unknown outbound Queue IOMB OPC = 0x%x\n", opc);
4019 break;
4020 }
4021 }
4022
print_scratchpad_registers(struct pm8001_hba_info * pm8001_ha)4023 static void print_scratchpad_registers(struct pm8001_hba_info *pm8001_ha)
4024 {
4025 pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_0: 0x%x\n",
4026 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0));
4027 pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_1:0x%x\n",
4028 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1));
4029 pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_2: 0x%x\n",
4030 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2));
4031 pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_3: 0x%x\n",
4032 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3));
4033 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_0: 0x%x\n",
4034 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0));
4035 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_1: 0x%x\n",
4036 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_1));
4037 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_2: 0x%x\n",
4038 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_2));
4039 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_3: 0x%x\n",
4040 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_3));
4041 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_4: 0x%x\n",
4042 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_4));
4043 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_5: 0x%x\n",
4044 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_5));
4045 pm8001_dbg(pm8001_ha, FAIL, "MSGU_RSVD_SCRATCH_PAD_0: 0x%x\n",
4046 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_6));
4047 pm8001_dbg(pm8001_ha, FAIL, "MSGU_RSVD_SCRATCH_PAD_1: 0x%x\n",
4048 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_7));
4049 }
4050
process_oq(struct pm8001_hba_info * pm8001_ha,u8 vec)4051 static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec)
4052 {
4053 struct outbound_queue_table *circularQ;
4054 void *pMsg1 = NULL;
4055 u8 bc;
4056 u32 ret = MPI_IO_STATUS_FAIL;
4057 unsigned long flags;
4058 u32 regval;
4059
4060 if (vec == (pm8001_ha->max_q_num - 1)) {
4061 regval = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
4062 if ((regval & SCRATCH_PAD_MIPSALL_READY) !=
4063 SCRATCH_PAD_MIPSALL_READY) {
4064 pm8001_ha->controller_fatal_error = true;
4065 pm8001_dbg(pm8001_ha, FAIL,
4066 "Firmware Fatal error! Regval:0x%x\n",
4067 regval);
4068 print_scratchpad_registers(pm8001_ha);
4069 return ret;
4070 }
4071 }
4072 spin_lock_irqsave(&pm8001_ha->lock, flags);
4073 circularQ = &pm8001_ha->outbnd_q_tbl[vec];
4074 do {
4075 /* spurious interrupt during setup if kexec-ing and
4076 * driver doing a doorbell access w/ the pre-kexec oq
4077 * interrupt setup.
4078 */
4079 if (!circularQ->pi_virt)
4080 break;
4081 ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
4082 if (MPI_IO_STATUS_SUCCESS == ret) {
4083 /* process the outbound message */
4084 process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4));
4085 /* free the message from the outbound circular buffer */
4086 pm8001_mpi_msg_free_set(pm8001_ha, pMsg1,
4087 circularQ, bc);
4088 }
4089 if (MPI_IO_STATUS_BUSY == ret) {
4090 /* Update the producer index from SPC */
4091 circularQ->producer_index =
4092 cpu_to_le32(pm8001_read_32(circularQ->pi_virt));
4093 if (le32_to_cpu(circularQ->producer_index) ==
4094 circularQ->consumer_idx)
4095 /* OQ is empty */
4096 break;
4097 }
4098 } while (1);
4099 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
4100 return ret;
4101 }
4102
4103 /* DMA_... to our direction translation. */
4104 static const u8 data_dir_flags[] = {
4105 [DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT, /* UNSPECIFIED */
4106 [DMA_TO_DEVICE] = DATA_DIR_OUT, /* OUTBOUND */
4107 [DMA_FROM_DEVICE] = DATA_DIR_IN, /* INBOUND */
4108 [DMA_NONE] = DATA_DIR_NONE, /* NO TRANSFER */
4109 };
4110
build_smp_cmd(u32 deviceID,__le32 hTag,struct smp_req * psmp_cmd,int mode,int length)4111 static void build_smp_cmd(u32 deviceID, __le32 hTag,
4112 struct smp_req *psmp_cmd, int mode, int length)
4113 {
4114 psmp_cmd->tag = hTag;
4115 psmp_cmd->device_id = cpu_to_le32(deviceID);
4116 if (mode == SMP_DIRECT) {
4117 length = length - 4; /* subtract crc */
4118 psmp_cmd->len_ip_ir = cpu_to_le32(length << 16);
4119 } else {
4120 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
4121 }
4122 }
4123
4124 /**
4125 * pm8001_chip_smp_req - send a SMP task to FW
4126 * @pm8001_ha: our hba card information.
4127 * @ccb: the ccb information this request used.
4128 */
pm80xx_chip_smp_req(struct pm8001_hba_info * pm8001_ha,struct pm8001_ccb_info * ccb)4129 static int pm80xx_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
4130 struct pm8001_ccb_info *ccb)
4131 {
4132 int elem, rc;
4133 struct sas_task *task = ccb->task;
4134 struct domain_device *dev = task->dev;
4135 struct pm8001_device *pm8001_dev = dev->lldd_dev;
4136 struct scatterlist *sg_req, *sg_resp;
4137 u32 req_len, resp_len;
4138 struct smp_req smp_cmd;
4139 u32 opc;
4140 struct inbound_queue_table *circularQ;
4141 char *preq_dma_addr = NULL;
4142 __le64 tmp_addr;
4143 u32 i, length;
4144
4145 memset(&smp_cmd, 0, sizeof(smp_cmd));
4146 /*
4147 * DMA-map SMP request, response buffers
4148 */
4149 sg_req = &task->smp_task.smp_req;
4150 elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, DMA_TO_DEVICE);
4151 if (!elem)
4152 return -ENOMEM;
4153 req_len = sg_dma_len(sg_req);
4154
4155 sg_resp = &task->smp_task.smp_resp;
4156 elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, DMA_FROM_DEVICE);
4157 if (!elem) {
4158 rc = -ENOMEM;
4159 goto err_out;
4160 }
4161 resp_len = sg_dma_len(sg_resp);
4162 /* must be in dwords */
4163 if ((req_len & 0x3) || (resp_len & 0x3)) {
4164 rc = -EINVAL;
4165 goto err_out_2;
4166 }
4167
4168 opc = OPC_INB_SMP_REQUEST;
4169 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4170 smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
4171
4172 length = sg_req->length;
4173 pm8001_dbg(pm8001_ha, IO, "SMP Frame Length %d\n", sg_req->length);
4174 if (!(length - 8))
4175 pm8001_ha->smp_exp_mode = SMP_DIRECT;
4176 else
4177 pm8001_ha->smp_exp_mode = SMP_INDIRECT;
4178
4179
4180 tmp_addr = cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req));
4181 preq_dma_addr = (char *)phys_to_virt(tmp_addr);
4182
4183 /* INDIRECT MODE command settings. Use DMA */
4184 if (pm8001_ha->smp_exp_mode == SMP_INDIRECT) {
4185 pm8001_dbg(pm8001_ha, IO, "SMP REQUEST INDIRECT MODE\n");
4186 /* for SPCv indirect mode. Place the top 4 bytes of
4187 * SMP Request header here. */
4188 for (i = 0; i < 4; i++)
4189 smp_cmd.smp_req16[i] = *(preq_dma_addr + i);
4190 /* exclude top 4 bytes for SMP req header */
4191 smp_cmd.long_smp_req.long_req_addr =
4192 cpu_to_le64((u64)sg_dma_address
4193 (&task->smp_task.smp_req) + 4);
4194 /* exclude 4 bytes for SMP req header and CRC */
4195 smp_cmd.long_smp_req.long_req_size =
4196 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-8);
4197 smp_cmd.long_smp_req.long_resp_addr =
4198 cpu_to_le64((u64)sg_dma_address
4199 (&task->smp_task.smp_resp));
4200 smp_cmd.long_smp_req.long_resp_size =
4201 cpu_to_le32((u32)sg_dma_len
4202 (&task->smp_task.smp_resp)-4);
4203 } else { /* DIRECT MODE */
4204 smp_cmd.long_smp_req.long_req_addr =
4205 cpu_to_le64((u64)sg_dma_address
4206 (&task->smp_task.smp_req));
4207 smp_cmd.long_smp_req.long_req_size =
4208 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
4209 smp_cmd.long_smp_req.long_resp_addr =
4210 cpu_to_le64((u64)sg_dma_address
4211 (&task->smp_task.smp_resp));
4212 smp_cmd.long_smp_req.long_resp_size =
4213 cpu_to_le32
4214 ((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
4215 }
4216 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
4217 pm8001_dbg(pm8001_ha, IO, "SMP REQUEST DIRECT MODE\n");
4218 for (i = 0; i < length; i++)
4219 if (i < 16) {
4220 smp_cmd.smp_req16[i] = *(preq_dma_addr+i);
4221 pm8001_dbg(pm8001_ha, IO,
4222 "Byte[%d]:%x (DMA data:%x)\n",
4223 i, smp_cmd.smp_req16[i],
4224 *(preq_dma_addr));
4225 } else {
4226 smp_cmd.smp_req[i] = *(preq_dma_addr+i);
4227 pm8001_dbg(pm8001_ha, IO,
4228 "Byte[%d]:%x (DMA data:%x)\n",
4229 i, smp_cmd.smp_req[i],
4230 *(preq_dma_addr));
4231 }
4232 }
4233
4234 build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag,
4235 &smp_cmd, pm8001_ha->smp_exp_mode, length);
4236 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &smp_cmd,
4237 sizeof(smp_cmd), 0);
4238 if (rc)
4239 goto err_out_2;
4240 return 0;
4241
4242 err_out_2:
4243 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
4244 DMA_FROM_DEVICE);
4245 err_out:
4246 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
4247 DMA_TO_DEVICE);
4248 return rc;
4249 }
4250
check_enc_sas_cmd(struct sas_task * task)4251 static int check_enc_sas_cmd(struct sas_task *task)
4252 {
4253 u8 cmd = task->ssp_task.cmd->cmnd[0];
4254
4255 if (cmd == READ_10 || cmd == WRITE_10 || cmd == WRITE_VERIFY)
4256 return 1;
4257 else
4258 return 0;
4259 }
4260
check_enc_sat_cmd(struct sas_task * task)4261 static int check_enc_sat_cmd(struct sas_task *task)
4262 {
4263 int ret = 0;
4264 switch (task->ata_task.fis.command) {
4265 case ATA_CMD_FPDMA_READ:
4266 case ATA_CMD_READ_EXT:
4267 case ATA_CMD_READ:
4268 case ATA_CMD_FPDMA_WRITE:
4269 case ATA_CMD_WRITE_EXT:
4270 case ATA_CMD_WRITE:
4271 case ATA_CMD_PIO_READ:
4272 case ATA_CMD_PIO_READ_EXT:
4273 case ATA_CMD_PIO_WRITE:
4274 case ATA_CMD_PIO_WRITE_EXT:
4275 ret = 1;
4276 break;
4277 default:
4278 ret = 0;
4279 break;
4280 }
4281 return ret;
4282 }
4283
4284 /**
4285 * pm80xx_chip_ssp_io_req - send a SSP task to FW
4286 * @pm8001_ha: our hba card information.
4287 * @ccb: the ccb information this request used.
4288 */
pm80xx_chip_ssp_io_req(struct pm8001_hba_info * pm8001_ha,struct pm8001_ccb_info * ccb)4289 static int pm80xx_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
4290 struct pm8001_ccb_info *ccb)
4291 {
4292 struct sas_task *task = ccb->task;
4293 struct domain_device *dev = task->dev;
4294 struct pm8001_device *pm8001_dev = dev->lldd_dev;
4295 struct ssp_ini_io_start_req ssp_cmd;
4296 u32 tag = ccb->ccb_tag;
4297 int ret;
4298 u64 phys_addr, start_addr, end_addr;
4299 u32 end_addr_high, end_addr_low;
4300 struct inbound_queue_table *circularQ;
4301 u32 q_index, cpu_id;
4302 u32 opc = OPC_INB_SSPINIIOSTART;
4303 memset(&ssp_cmd, 0, sizeof(ssp_cmd));
4304 memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
4305 /* data address domain added for spcv; set to 0 by host,
4306 * used internally by controller
4307 * 0 for SAS 1.1 and SAS 2.0 compatible TLR
4308 */
4309 ssp_cmd.dad_dir_m_tlr =
4310 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);
4311 ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4312 ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4313 ssp_cmd.tag = cpu_to_le32(tag);
4314 if (task->ssp_task.enable_first_burst)
4315 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80;
4316 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3);
4317 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
4318 memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd,
4319 task->ssp_task.cmd->cmd_len);
4320 cpu_id = smp_processor_id();
4321 q_index = (u32) (cpu_id) % (pm8001_ha->max_q_num);
4322 circularQ = &pm8001_ha->inbnd_q_tbl[q_index];
4323
4324 /* Check if encryption is set */
4325 if (pm8001_ha->chip->encrypt &&
4326 !(pm8001_ha->encrypt_info.status) && check_enc_sas_cmd(task)) {
4327 pm8001_dbg(pm8001_ha, IO,
4328 "Encryption enabled.Sending Encrypt SAS command 0x%x\n",
4329 task->ssp_task.cmd->cmnd[0]);
4330 opc = OPC_INB_SSP_INI_DIF_ENC_IO;
4331 /* enable encryption. 0 for SAS 1.1 and SAS 2.0 compatible TLR*/
4332 ssp_cmd.dad_dir_m_tlr = cpu_to_le32
4333 ((data_dir_flags[task->data_dir] << 8) | 0x20 | 0x0);
4334
4335 /* fill in PRD (scatter/gather) table, if any */
4336 if (task->num_scatter > 1) {
4337 pm8001_chip_make_sg(task->scatter,
4338 ccb->n_elem, ccb->buf_prd);
4339 phys_addr = ccb->ccb_dma_handle;
4340 ssp_cmd.enc_addr_low =
4341 cpu_to_le32(lower_32_bits(phys_addr));
4342 ssp_cmd.enc_addr_high =
4343 cpu_to_le32(upper_32_bits(phys_addr));
4344 ssp_cmd.enc_esgl = cpu_to_le32(1<<31);
4345 } else if (task->num_scatter == 1) {
4346 u64 dma_addr = sg_dma_address(task->scatter);
4347 ssp_cmd.enc_addr_low =
4348 cpu_to_le32(lower_32_bits(dma_addr));
4349 ssp_cmd.enc_addr_high =
4350 cpu_to_le32(upper_32_bits(dma_addr));
4351 ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4352 ssp_cmd.enc_esgl = 0;
4353 /* Check 4G Boundary */
4354 start_addr = cpu_to_le64(dma_addr);
4355 end_addr = (start_addr + ssp_cmd.enc_len) - 1;
4356 end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4357 end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4358 if (end_addr_high != ssp_cmd.enc_addr_high) {
4359 pm8001_dbg(pm8001_ha, FAIL,
4360 "The sg list address start_addr=0x%016llx data_len=0x%x end_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n",
4361 start_addr, ssp_cmd.enc_len,
4362 end_addr_high, end_addr_low);
4363 pm8001_chip_make_sg(task->scatter, 1,
4364 ccb->buf_prd);
4365 phys_addr = ccb->ccb_dma_handle;
4366 ssp_cmd.enc_addr_low =
4367 cpu_to_le32(lower_32_bits(phys_addr));
4368 ssp_cmd.enc_addr_high =
4369 cpu_to_le32(upper_32_bits(phys_addr));
4370 ssp_cmd.enc_esgl = cpu_to_le32(1<<31);
4371 }
4372 } else if (task->num_scatter == 0) {
4373 ssp_cmd.enc_addr_low = 0;
4374 ssp_cmd.enc_addr_high = 0;
4375 ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4376 ssp_cmd.enc_esgl = 0;
4377 }
4378 /* XTS mode. All other fields are 0 */
4379 ssp_cmd.key_cmode = 0x6 << 4;
4380 /* set tweak values. Should be the start lba */
4381 ssp_cmd.twk_val0 = cpu_to_le32((task->ssp_task.cmd->cmnd[2] << 24) |
4382 (task->ssp_task.cmd->cmnd[3] << 16) |
4383 (task->ssp_task.cmd->cmnd[4] << 8) |
4384 (task->ssp_task.cmd->cmnd[5]));
4385 } else {
4386 pm8001_dbg(pm8001_ha, IO,
4387 "Sending Normal SAS command 0x%x inb q %x\n",
4388 task->ssp_task.cmd->cmnd[0], q_index);
4389 /* fill in PRD (scatter/gather) table, if any */
4390 if (task->num_scatter > 1) {
4391 pm8001_chip_make_sg(task->scatter, ccb->n_elem,
4392 ccb->buf_prd);
4393 phys_addr = ccb->ccb_dma_handle;
4394 ssp_cmd.addr_low =
4395 cpu_to_le32(lower_32_bits(phys_addr));
4396 ssp_cmd.addr_high =
4397 cpu_to_le32(upper_32_bits(phys_addr));
4398 ssp_cmd.esgl = cpu_to_le32(1<<31);
4399 } else if (task->num_scatter == 1) {
4400 u64 dma_addr = sg_dma_address(task->scatter);
4401 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr));
4402 ssp_cmd.addr_high =
4403 cpu_to_le32(upper_32_bits(dma_addr));
4404 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4405 ssp_cmd.esgl = 0;
4406 /* Check 4G Boundary */
4407 start_addr = cpu_to_le64(dma_addr);
4408 end_addr = (start_addr + ssp_cmd.len) - 1;
4409 end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4410 end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4411 if (end_addr_high != ssp_cmd.addr_high) {
4412 pm8001_dbg(pm8001_ha, FAIL,
4413 "The sg list address start_addr=0x%016llx data_len=0x%x end_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n",
4414 start_addr, ssp_cmd.len,
4415 end_addr_high, end_addr_low);
4416 pm8001_chip_make_sg(task->scatter, 1,
4417 ccb->buf_prd);
4418 phys_addr = ccb->ccb_dma_handle;
4419 ssp_cmd.addr_low =
4420 cpu_to_le32(lower_32_bits(phys_addr));
4421 ssp_cmd.addr_high =
4422 cpu_to_le32(upper_32_bits(phys_addr));
4423 ssp_cmd.esgl = cpu_to_le32(1<<31);
4424 }
4425 } else if (task->num_scatter == 0) {
4426 ssp_cmd.addr_low = 0;
4427 ssp_cmd.addr_high = 0;
4428 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4429 ssp_cmd.esgl = 0;
4430 }
4431 }
4432 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
4433 &ssp_cmd, sizeof(ssp_cmd), q_index);
4434 return ret;
4435 }
4436
pm80xx_chip_sata_req(struct pm8001_hba_info * pm8001_ha,struct pm8001_ccb_info * ccb)4437 static int pm80xx_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
4438 struct pm8001_ccb_info *ccb)
4439 {
4440 struct sas_task *task = ccb->task;
4441 struct domain_device *dev = task->dev;
4442 struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
4443 u32 tag = ccb->ccb_tag;
4444 int ret;
4445 u32 q_index, cpu_id;
4446 struct sata_start_req sata_cmd;
4447 u32 hdr_tag, ncg_tag = 0;
4448 u64 phys_addr, start_addr, end_addr;
4449 u32 end_addr_high, end_addr_low;
4450 u32 ATAP = 0x0;
4451 u32 dir;
4452 struct inbound_queue_table *circularQ;
4453 unsigned long flags;
4454 u32 opc = OPC_INB_SATA_HOST_OPSTART;
4455 memset(&sata_cmd, 0, sizeof(sata_cmd));
4456 cpu_id = smp_processor_id();
4457 q_index = (u32) (cpu_id) % (pm8001_ha->max_q_num);
4458 circularQ = &pm8001_ha->inbnd_q_tbl[q_index];
4459
4460 if (task->data_dir == DMA_NONE) {
4461 ATAP = 0x04; /* no data*/
4462 pm8001_dbg(pm8001_ha, IO, "no data\n");
4463 } else if (likely(!task->ata_task.device_control_reg_update)) {
4464 if (task->ata_task.dma_xfer) {
4465 ATAP = 0x06; /* DMA */
4466 pm8001_dbg(pm8001_ha, IO, "DMA\n");
4467 } else {
4468 ATAP = 0x05; /* PIO*/
4469 pm8001_dbg(pm8001_ha, IO, "PIO\n");
4470 }
4471 if (task->ata_task.use_ncq &&
4472 dev->sata_dev.class != ATA_DEV_ATAPI) {
4473 ATAP = 0x07; /* FPDMA */
4474 pm8001_dbg(pm8001_ha, IO, "FPDMA\n");
4475 }
4476 }
4477 if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) {
4478 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
4479 ncg_tag = hdr_tag;
4480 }
4481 dir = data_dir_flags[task->data_dir] << 8;
4482 sata_cmd.tag = cpu_to_le32(tag);
4483 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
4484 sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4485
4486 sata_cmd.sata_fis = task->ata_task.fis;
4487 if (likely(!task->ata_task.device_control_reg_update))
4488 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
4489 sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */
4490
4491 /* Check if encryption is set */
4492 if (pm8001_ha->chip->encrypt &&
4493 !(pm8001_ha->encrypt_info.status) && check_enc_sat_cmd(task)) {
4494 pm8001_dbg(pm8001_ha, IO,
4495 "Encryption enabled.Sending Encrypt SATA cmd 0x%x\n",
4496 sata_cmd.sata_fis.command);
4497 opc = OPC_INB_SATA_DIF_ENC_IO;
4498
4499 /* set encryption bit */
4500 sata_cmd.ncqtag_atap_dir_m_dad =
4501 cpu_to_le32(((ncg_tag & 0xff)<<16)|
4502 ((ATAP & 0x3f) << 10) | 0x20 | dir);
4503 /* dad (bit 0-1) is 0 */
4504 /* fill in PRD (scatter/gather) table, if any */
4505 if (task->num_scatter > 1) {
4506 pm8001_chip_make_sg(task->scatter,
4507 ccb->n_elem, ccb->buf_prd);
4508 phys_addr = ccb->ccb_dma_handle;
4509 sata_cmd.enc_addr_low = lower_32_bits(phys_addr);
4510 sata_cmd.enc_addr_high = upper_32_bits(phys_addr);
4511 sata_cmd.enc_esgl = cpu_to_le32(1 << 31);
4512 } else if (task->num_scatter == 1) {
4513 u64 dma_addr = sg_dma_address(task->scatter);
4514 sata_cmd.enc_addr_low = lower_32_bits(dma_addr);
4515 sata_cmd.enc_addr_high = upper_32_bits(dma_addr);
4516 sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4517 sata_cmd.enc_esgl = 0;
4518 /* Check 4G Boundary */
4519 start_addr = cpu_to_le64(dma_addr);
4520 end_addr = (start_addr + sata_cmd.enc_len) - 1;
4521 end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4522 end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4523 if (end_addr_high != sata_cmd.enc_addr_high) {
4524 pm8001_dbg(pm8001_ha, FAIL,
4525 "The sg list address start_addr=0x%016llx data_len=0x%x end_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n",
4526 start_addr, sata_cmd.enc_len,
4527 end_addr_high, end_addr_low);
4528 pm8001_chip_make_sg(task->scatter, 1,
4529 ccb->buf_prd);
4530 phys_addr = ccb->ccb_dma_handle;
4531 sata_cmd.enc_addr_low =
4532 lower_32_bits(phys_addr);
4533 sata_cmd.enc_addr_high =
4534 upper_32_bits(phys_addr);
4535 sata_cmd.enc_esgl =
4536 cpu_to_le32(1 << 31);
4537 }
4538 } else if (task->num_scatter == 0) {
4539 sata_cmd.enc_addr_low = 0;
4540 sata_cmd.enc_addr_high = 0;
4541 sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4542 sata_cmd.enc_esgl = 0;
4543 }
4544 /* XTS mode. All other fields are 0 */
4545 sata_cmd.key_index_mode = 0x6 << 4;
4546 /* set tweak values. Should be the start lba */
4547 sata_cmd.twk_val0 =
4548 cpu_to_le32((sata_cmd.sata_fis.lbal_exp << 24) |
4549 (sata_cmd.sata_fis.lbah << 16) |
4550 (sata_cmd.sata_fis.lbam << 8) |
4551 (sata_cmd.sata_fis.lbal));
4552 sata_cmd.twk_val1 =
4553 cpu_to_le32((sata_cmd.sata_fis.lbah_exp << 8) |
4554 (sata_cmd.sata_fis.lbam_exp));
4555 } else {
4556 pm8001_dbg(pm8001_ha, IO,
4557 "Sending Normal SATA command 0x%x inb %x\n",
4558 sata_cmd.sata_fis.command, q_index);
4559 /* dad (bit 0-1) is 0 */
4560 sata_cmd.ncqtag_atap_dir_m_dad =
4561 cpu_to_le32(((ncg_tag & 0xff)<<16) |
4562 ((ATAP & 0x3f) << 10) | dir);
4563
4564 /* fill in PRD (scatter/gather) table, if any */
4565 if (task->num_scatter > 1) {
4566 pm8001_chip_make_sg(task->scatter,
4567 ccb->n_elem, ccb->buf_prd);
4568 phys_addr = ccb->ccb_dma_handle;
4569 sata_cmd.addr_low = lower_32_bits(phys_addr);
4570 sata_cmd.addr_high = upper_32_bits(phys_addr);
4571 sata_cmd.esgl = cpu_to_le32(1 << 31);
4572 } else if (task->num_scatter == 1) {
4573 u64 dma_addr = sg_dma_address(task->scatter);
4574 sata_cmd.addr_low = lower_32_bits(dma_addr);
4575 sata_cmd.addr_high = upper_32_bits(dma_addr);
4576 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4577 sata_cmd.esgl = 0;
4578 /* Check 4G Boundary */
4579 start_addr = cpu_to_le64(dma_addr);
4580 end_addr = (start_addr + sata_cmd.len) - 1;
4581 end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4582 end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4583 if (end_addr_high != sata_cmd.addr_high) {
4584 pm8001_dbg(pm8001_ha, FAIL,
4585 "The sg list address start_addr=0x%016llx data_len=0x%xend_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n",
4586 start_addr, sata_cmd.len,
4587 end_addr_high, end_addr_low);
4588 pm8001_chip_make_sg(task->scatter, 1,
4589 ccb->buf_prd);
4590 phys_addr = ccb->ccb_dma_handle;
4591 sata_cmd.addr_low =
4592 lower_32_bits(phys_addr);
4593 sata_cmd.addr_high =
4594 upper_32_bits(phys_addr);
4595 sata_cmd.esgl = cpu_to_le32(1 << 31);
4596 }
4597 } else if (task->num_scatter == 0) {
4598 sata_cmd.addr_low = 0;
4599 sata_cmd.addr_high = 0;
4600 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4601 sata_cmd.esgl = 0;
4602 }
4603 /* scsi cdb */
4604 sata_cmd.atapi_scsi_cdb[0] =
4605 cpu_to_le32(((task->ata_task.atapi_packet[0]) |
4606 (task->ata_task.atapi_packet[1] << 8) |
4607 (task->ata_task.atapi_packet[2] << 16) |
4608 (task->ata_task.atapi_packet[3] << 24)));
4609 sata_cmd.atapi_scsi_cdb[1] =
4610 cpu_to_le32(((task->ata_task.atapi_packet[4]) |
4611 (task->ata_task.atapi_packet[5] << 8) |
4612 (task->ata_task.atapi_packet[6] << 16) |
4613 (task->ata_task.atapi_packet[7] << 24)));
4614 sata_cmd.atapi_scsi_cdb[2] =
4615 cpu_to_le32(((task->ata_task.atapi_packet[8]) |
4616 (task->ata_task.atapi_packet[9] << 8) |
4617 (task->ata_task.atapi_packet[10] << 16) |
4618 (task->ata_task.atapi_packet[11] << 24)));
4619 sata_cmd.atapi_scsi_cdb[3] =
4620 cpu_to_le32(((task->ata_task.atapi_packet[12]) |
4621 (task->ata_task.atapi_packet[13] << 8) |
4622 (task->ata_task.atapi_packet[14] << 16) |
4623 (task->ata_task.atapi_packet[15] << 24)));
4624 }
4625
4626 /* Check for read log for failed drive and return */
4627 if (sata_cmd.sata_fis.command == 0x2f) {
4628 if (pm8001_ha_dev && ((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) ||
4629 (pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) ||
4630 (pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) {
4631 struct task_status_struct *ts;
4632
4633 pm8001_ha_dev->id &= 0xDFFFFFFF;
4634 ts = &task->task_status;
4635
4636 spin_lock_irqsave(&task->task_state_lock, flags);
4637 ts->resp = SAS_TASK_COMPLETE;
4638 ts->stat = SAM_STAT_GOOD;
4639 task->task_state_flags &= ~SAS_TASK_STATE_PENDING;
4640 task->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
4641 task->task_state_flags |= SAS_TASK_STATE_DONE;
4642 if (unlikely((task->task_state_flags &
4643 SAS_TASK_STATE_ABORTED))) {
4644 spin_unlock_irqrestore(&task->task_state_lock,
4645 flags);
4646 pm8001_dbg(pm8001_ha, FAIL,
4647 "task 0x%p resp 0x%x stat 0x%x but aborted by upper layer\n",
4648 task, ts->resp,
4649 ts->stat);
4650 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
4651 return 0;
4652 } else {
4653 spin_unlock_irqrestore(&task->task_state_lock,
4654 flags);
4655 pm8001_ccb_task_free_done(pm8001_ha, task,
4656 ccb, tag);
4657 atomic_dec(&pm8001_ha_dev->running_req);
4658 return 0;
4659 }
4660 }
4661 }
4662 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
4663 &sata_cmd, sizeof(sata_cmd), q_index);
4664 return ret;
4665 }
4666
4667 /**
4668 * pm80xx_chip_phy_start_req - start phy via PHY_START COMMAND
4669 * @pm8001_ha: our hba card information.
4670 * @phy_id: the phy id which we wanted to start up.
4671 */
4672 static int
pm80xx_chip_phy_start_req(struct pm8001_hba_info * pm8001_ha,u8 phy_id)4673 pm80xx_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
4674 {
4675 struct phy_start_req payload;
4676 struct inbound_queue_table *circularQ;
4677 int ret;
4678 u32 tag = 0x01;
4679 u32 opcode = OPC_INB_PHYSTART;
4680 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4681 memset(&payload, 0, sizeof(payload));
4682 payload.tag = cpu_to_le32(tag);
4683
4684 pm8001_dbg(pm8001_ha, INIT, "PHY START REQ for phy_id %d\n", phy_id);
4685
4686 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4687 LINKMODE_AUTO | pm8001_ha->link_rate | phy_id);
4688 /* SSC Disable and SAS Analog ST configuration */
4689 /**
4690 payload.ase_sh_lm_slr_phyid =
4691 cpu_to_le32(SSC_DISABLE_30 | SAS_ASE | SPINHOLD_DISABLE |
4692 LINKMODE_AUTO | LINKRATE_15 | LINKRATE_30 | LINKRATE_60 |
4693 phy_id);
4694 Have to add "SAS PHY Analog Setup SPASTI 1 Byte" Based on need
4695 **/
4696
4697 payload.sas_identify.dev_type = SAS_END_DEVICE;
4698 payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
4699 memcpy(payload.sas_identify.sas_addr,
4700 &pm8001_ha->sas_addr, SAS_ADDR_SIZE);
4701 payload.sas_identify.phy_id = phy_id;
4702 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload,
4703 sizeof(payload), 0);
4704 return ret;
4705 }
4706
4707 /**
4708 * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND
4709 * @pm8001_ha: our hba card information.
4710 * @phy_id: the phy id which we wanted to start up.
4711 */
pm80xx_chip_phy_stop_req(struct pm8001_hba_info * pm8001_ha,u8 phy_id)4712 static int pm80xx_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
4713 u8 phy_id)
4714 {
4715 struct phy_stop_req payload;
4716 struct inbound_queue_table *circularQ;
4717 int ret;
4718 u32 tag = 0x01;
4719 u32 opcode = OPC_INB_PHYSTOP;
4720 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4721 memset(&payload, 0, sizeof(payload));
4722 payload.tag = cpu_to_le32(tag);
4723 payload.phy_id = cpu_to_le32(phy_id);
4724 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload,
4725 sizeof(payload), 0);
4726 return ret;
4727 }
4728
4729 /*
4730 * see comments on pm8001_mpi_reg_resp.
4731 */
pm80xx_chip_reg_dev_req(struct pm8001_hba_info * pm8001_ha,struct pm8001_device * pm8001_dev,u32 flag)4732 static int pm80xx_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
4733 struct pm8001_device *pm8001_dev, u32 flag)
4734 {
4735 struct reg_dev_req payload;
4736 u32 opc;
4737 u32 stp_sspsmp_sata = 0x4;
4738 struct inbound_queue_table *circularQ;
4739 u32 linkrate, phy_id;
4740 int rc, tag = 0xdeadbeef;
4741 struct pm8001_ccb_info *ccb;
4742 u8 retryFlag = 0x1;
4743 u16 firstBurstSize = 0;
4744 u16 ITNT = 2000;
4745 struct domain_device *dev = pm8001_dev->sas_device;
4746 struct domain_device *parent_dev = dev->parent;
4747 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4748
4749 memset(&payload, 0, sizeof(payload));
4750 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4751 if (rc)
4752 return rc;
4753 ccb = &pm8001_ha->ccb_info[tag];
4754 ccb->device = pm8001_dev;
4755 ccb->ccb_tag = tag;
4756 payload.tag = cpu_to_le32(tag);
4757
4758 if (flag == 1) {
4759 stp_sspsmp_sata = 0x02; /*direct attached sata */
4760 } else {
4761 if (pm8001_dev->dev_type == SAS_SATA_DEV)
4762 stp_sspsmp_sata = 0x00; /* stp*/
4763 else if (pm8001_dev->dev_type == SAS_END_DEVICE ||
4764 pm8001_dev->dev_type == SAS_EDGE_EXPANDER_DEVICE ||
4765 pm8001_dev->dev_type == SAS_FANOUT_EXPANDER_DEVICE)
4766 stp_sspsmp_sata = 0x01; /*ssp or smp*/
4767 }
4768 if (parent_dev && dev_is_expander(parent_dev->dev_type))
4769 phy_id = parent_dev->ex_dev.ex_phy->phy_id;
4770 else
4771 phy_id = pm8001_dev->attached_phy;
4772
4773 opc = OPC_INB_REG_DEV;
4774
4775 linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
4776 pm8001_dev->sas_device->linkrate : dev->port->linkrate;
4777
4778 payload.phyid_portid =
4779 cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0xFF) |
4780 ((phy_id & 0xFF) << 8));
4781
4782 payload.dtype_dlr_mcn_ir_retry = cpu_to_le32((retryFlag & 0x01) |
4783 ((linkrate & 0x0F) << 24) |
4784 ((stp_sspsmp_sata & 0x03) << 28));
4785 payload.firstburstsize_ITNexustimeout =
4786 cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
4787
4788 memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr,
4789 SAS_ADDR_SIZE);
4790
4791 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
4792 sizeof(payload), 0);
4793 if (rc)
4794 pm8001_tag_free(pm8001_ha, tag);
4795
4796 return rc;
4797 }
4798
4799 /**
4800 * pm80xx_chip_phy_ctl_req - support the local phy operation
4801 * @pm8001_ha: our hba card information.
4802 * @phyId: the phy id which we wanted to operate
4803 * @phy_op: phy operation to request
4804 */
pm80xx_chip_phy_ctl_req(struct pm8001_hba_info * pm8001_ha,u32 phyId,u32 phy_op)4805 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
4806 u32 phyId, u32 phy_op)
4807 {
4808 u32 tag;
4809 int rc;
4810 struct local_phy_ctl_req payload;
4811 struct inbound_queue_table *circularQ;
4812 u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
4813 memset(&payload, 0, sizeof(payload));
4814 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4815 if (rc)
4816 return rc;
4817 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4818 payload.tag = cpu_to_le32(tag);
4819 payload.phyop_phyid =
4820 cpu_to_le32(((phy_op & 0xFF) << 8) | (phyId & 0xFF));
4821 return pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
4822 sizeof(payload), 0);
4823 }
4824
pm80xx_chip_is_our_interrupt(struct pm8001_hba_info * pm8001_ha)4825 static u32 pm80xx_chip_is_our_interrupt(struct pm8001_hba_info *pm8001_ha)
4826 {
4827 #ifdef PM8001_USE_MSIX
4828 return 1;
4829 #else
4830 u32 value;
4831
4832 value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
4833 if (value)
4834 return 1;
4835 return 0;
4836 #endif
4837 }
4838
4839 /**
4840 * pm8001_chip_isr - PM8001 isr handler.
4841 * @pm8001_ha: our hba card information.
4842 * @vec: irq number.
4843 */
4844 static irqreturn_t
pm80xx_chip_isr(struct pm8001_hba_info * pm8001_ha,u8 vec)4845 pm80xx_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec)
4846 {
4847 pm80xx_chip_interrupt_disable(pm8001_ha, vec);
4848 pm8001_dbg(pm8001_ha, DEVIO,
4849 "irq vec %d, ODMR:0x%x\n",
4850 vec, pm8001_cr32(pm8001_ha, 0, 0x30));
4851 process_oq(pm8001_ha, vec);
4852 pm80xx_chip_interrupt_enable(pm8001_ha, vec);
4853 return IRQ_HANDLED;
4854 }
4855
mpi_set_phy_profile_req(struct pm8001_hba_info * pm8001_ha,u32 operation,u32 phyid,u32 length,u32 * buf)4856 static void mpi_set_phy_profile_req(struct pm8001_hba_info *pm8001_ha,
4857 u32 operation, u32 phyid,
4858 u32 length, u32 *buf)
4859 {
4860 u32 tag , i, j = 0;
4861 int rc;
4862 struct set_phy_profile_req payload;
4863 struct inbound_queue_table *circularQ;
4864 u32 opc = OPC_INB_SET_PHY_PROFILE;
4865
4866 memset(&payload, 0, sizeof(payload));
4867 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4868 if (rc)
4869 pm8001_dbg(pm8001_ha, FAIL, "Invalid tag\n");
4870 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4871 payload.tag = cpu_to_le32(tag);
4872 payload.ppc_phyid = (((operation & 0xF) << 8) | (phyid & 0xFF));
4873 pm8001_dbg(pm8001_ha, INIT,
4874 " phy profile command for phy %x ,length is %d\n",
4875 payload.ppc_phyid, length);
4876 for (i = length; i < (length + PHY_DWORD_LENGTH - 1); i++) {
4877 payload.reserved[j] = cpu_to_le32(*((u32 *)buf + i));
4878 j++;
4879 }
4880 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
4881 sizeof(payload), 0);
4882 if (rc)
4883 pm8001_tag_free(pm8001_ha, tag);
4884 }
4885
pm8001_set_phy_profile(struct pm8001_hba_info * pm8001_ha,u32 length,u8 * buf)4886 void pm8001_set_phy_profile(struct pm8001_hba_info *pm8001_ha,
4887 u32 length, u8 *buf)
4888 {
4889 u32 i;
4890
4891 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
4892 mpi_set_phy_profile_req(pm8001_ha,
4893 SAS_PHY_ANALOG_SETTINGS_PAGE, i, length, (u32 *)buf);
4894 length = length + PHY_DWORD_LENGTH;
4895 }
4896 pm8001_dbg(pm8001_ha, INIT, "phy settings completed\n");
4897 }
4898
pm8001_set_phy_profile_single(struct pm8001_hba_info * pm8001_ha,u32 phy,u32 length,u32 * buf)4899 void pm8001_set_phy_profile_single(struct pm8001_hba_info *pm8001_ha,
4900 u32 phy, u32 length, u32 *buf)
4901 {
4902 u32 tag, opc;
4903 int rc, i;
4904 struct set_phy_profile_req payload;
4905 struct inbound_queue_table *circularQ;
4906
4907 memset(&payload, 0, sizeof(payload));
4908
4909 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4910 if (rc)
4911 pm8001_dbg(pm8001_ha, INIT, "Invalid tag\n");
4912
4913 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4914 opc = OPC_INB_SET_PHY_PROFILE;
4915
4916 payload.tag = cpu_to_le32(tag);
4917 payload.ppc_phyid = (((SAS_PHY_ANALOG_SETTINGS_PAGE & 0xF) << 8)
4918 | (phy & 0xFF));
4919
4920 for (i = 0; i < length; i++)
4921 payload.reserved[i] = cpu_to_le32(*(buf + i));
4922
4923 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
4924 sizeof(payload), 0);
4925 if (rc)
4926 pm8001_tag_free(pm8001_ha, tag);
4927
4928 pm8001_dbg(pm8001_ha, INIT, "PHY %d settings applied\n", phy);
4929 }
4930 const struct pm8001_dispatch pm8001_80xx_dispatch = {
4931 .name = "pmc80xx",
4932 .chip_init = pm80xx_chip_init,
4933 .chip_soft_rst = pm80xx_chip_soft_rst,
4934 .chip_rst = pm80xx_hw_chip_rst,
4935 .chip_iounmap = pm8001_chip_iounmap,
4936 .isr = pm80xx_chip_isr,
4937 .is_our_interrupt = pm80xx_chip_is_our_interrupt,
4938 .isr_process_oq = process_oq,
4939 .interrupt_enable = pm80xx_chip_interrupt_enable,
4940 .interrupt_disable = pm80xx_chip_interrupt_disable,
4941 .make_prd = pm8001_chip_make_sg,
4942 .smp_req = pm80xx_chip_smp_req,
4943 .ssp_io_req = pm80xx_chip_ssp_io_req,
4944 .sata_req = pm80xx_chip_sata_req,
4945 .phy_start_req = pm80xx_chip_phy_start_req,
4946 .phy_stop_req = pm80xx_chip_phy_stop_req,
4947 .reg_dev_req = pm80xx_chip_reg_dev_req,
4948 .dereg_dev_req = pm8001_chip_dereg_dev_req,
4949 .phy_ctl_req = pm80xx_chip_phy_ctl_req,
4950 .task_abort = pm8001_chip_abort_task,
4951 .ssp_tm_req = pm8001_chip_ssp_tm_req,
4952 .get_nvmd_req = pm8001_chip_get_nvmd_req,
4953 .set_nvmd_req = pm8001_chip_set_nvmd_req,
4954 .fw_flash_update_req = pm8001_chip_fw_flash_update_req,
4955 .set_dev_state_req = pm8001_chip_set_dev_state_req,
4956 };
4957