1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2013-2016, Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/acpi.h>
7 #include <linux/time.h>
8 #include <linux/of.h>
9 #include <linux/platform_device.h>
10 #include <linux/phy/phy.h>
11 #include <linux/gpio/consumer.h>
12 #include <linux/reset-controller.h>
13 #include <linux/devfreq.h>
14
15 #include "ufshcd.h"
16 #include "ufshcd-pltfrm.h"
17 #include "unipro.h"
18 #include "ufs-qcom.h"
19 #include "ufshci.h"
20 #include "ufs_quirks.h"
21 #define UFS_QCOM_DEFAULT_DBG_PRINT_EN \
22 (UFS_QCOM_DBG_PRINT_REGS_EN | UFS_QCOM_DBG_PRINT_TEST_BUS_EN)
23
24 enum {
25 TSTBUS_UAWM,
26 TSTBUS_UARM,
27 TSTBUS_TXUC,
28 TSTBUS_RXUC,
29 TSTBUS_DFC,
30 TSTBUS_TRLUT,
31 TSTBUS_TMRLUT,
32 TSTBUS_OCSC,
33 TSTBUS_UTP_HCI,
34 TSTBUS_COMBINED,
35 TSTBUS_WRAPPER,
36 TSTBUS_UNIPRO,
37 TSTBUS_MAX,
38 };
39
40 static struct ufs_qcom_host *ufs_qcom_hosts[MAX_UFS_QCOM_HOSTS];
41
42 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host);
43 static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba,
44 u32 clk_cycles);
45
rcdev_to_ufs_host(struct reset_controller_dev * rcd)46 static struct ufs_qcom_host *rcdev_to_ufs_host(struct reset_controller_dev *rcd)
47 {
48 return container_of(rcd, struct ufs_qcom_host, rcdev);
49 }
50
ufs_qcom_dump_regs_wrapper(struct ufs_hba * hba,int offset,int len,const char * prefix,void * priv)51 static void ufs_qcom_dump_regs_wrapper(struct ufs_hba *hba, int offset, int len,
52 const char *prefix, void *priv)
53 {
54 ufshcd_dump_regs(hba, offset, len * 4, prefix);
55 }
56
ufs_qcom_get_connected_tx_lanes(struct ufs_hba * hba,u32 * tx_lanes)57 static int ufs_qcom_get_connected_tx_lanes(struct ufs_hba *hba, u32 *tx_lanes)
58 {
59 int err = 0;
60
61 err = ufshcd_dme_get(hba,
62 UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), tx_lanes);
63 if (err)
64 dev_err(hba->dev, "%s: couldn't read PA_CONNECTEDTXDATALANES %d\n",
65 __func__, err);
66
67 return err;
68 }
69
ufs_qcom_host_clk_get(struct device * dev,const char * name,struct clk ** clk_out,bool optional)70 static int ufs_qcom_host_clk_get(struct device *dev,
71 const char *name, struct clk **clk_out, bool optional)
72 {
73 struct clk *clk;
74 int err = 0;
75
76 clk = devm_clk_get(dev, name);
77 if (!IS_ERR(clk)) {
78 *clk_out = clk;
79 return 0;
80 }
81
82 err = PTR_ERR(clk);
83
84 if (optional && err == -ENOENT) {
85 *clk_out = NULL;
86 return 0;
87 }
88
89 if (err != -EPROBE_DEFER)
90 dev_err(dev, "failed to get %s err %d\n", name, err);
91
92 return err;
93 }
94
ufs_qcom_host_clk_enable(struct device * dev,const char * name,struct clk * clk)95 static int ufs_qcom_host_clk_enable(struct device *dev,
96 const char *name, struct clk *clk)
97 {
98 int err = 0;
99
100 err = clk_prepare_enable(clk);
101 if (err)
102 dev_err(dev, "%s: %s enable failed %d\n", __func__, name, err);
103
104 return err;
105 }
106
ufs_qcom_disable_lane_clks(struct ufs_qcom_host * host)107 static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host)
108 {
109 if (!host->is_lane_clks_enabled)
110 return;
111
112 clk_disable_unprepare(host->tx_l1_sync_clk);
113 clk_disable_unprepare(host->tx_l0_sync_clk);
114 clk_disable_unprepare(host->rx_l1_sync_clk);
115 clk_disable_unprepare(host->rx_l0_sync_clk);
116
117 host->is_lane_clks_enabled = false;
118 }
119
ufs_qcom_enable_lane_clks(struct ufs_qcom_host * host)120 static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host)
121 {
122 int err = 0;
123 struct device *dev = host->hba->dev;
124
125 if (host->is_lane_clks_enabled)
126 return 0;
127
128 err = ufs_qcom_host_clk_enable(dev, "rx_lane0_sync_clk",
129 host->rx_l0_sync_clk);
130 if (err)
131 goto out;
132
133 err = ufs_qcom_host_clk_enable(dev, "tx_lane0_sync_clk",
134 host->tx_l0_sync_clk);
135 if (err)
136 goto disable_rx_l0;
137
138 err = ufs_qcom_host_clk_enable(dev, "rx_lane1_sync_clk",
139 host->rx_l1_sync_clk);
140 if (err)
141 goto disable_tx_l0;
142
143 err = ufs_qcom_host_clk_enable(dev, "tx_lane1_sync_clk",
144 host->tx_l1_sync_clk);
145 if (err)
146 goto disable_rx_l1;
147
148 host->is_lane_clks_enabled = true;
149 goto out;
150
151 disable_rx_l1:
152 clk_disable_unprepare(host->rx_l1_sync_clk);
153 disable_tx_l0:
154 clk_disable_unprepare(host->tx_l0_sync_clk);
155 disable_rx_l0:
156 clk_disable_unprepare(host->rx_l0_sync_clk);
157 out:
158 return err;
159 }
160
ufs_qcom_init_lane_clks(struct ufs_qcom_host * host)161 static int ufs_qcom_init_lane_clks(struct ufs_qcom_host *host)
162 {
163 int err = 0;
164 struct device *dev = host->hba->dev;
165
166 if (has_acpi_companion(dev))
167 return 0;
168
169 err = ufs_qcom_host_clk_get(dev, "rx_lane0_sync_clk",
170 &host->rx_l0_sync_clk, false);
171 if (err)
172 goto out;
173
174 err = ufs_qcom_host_clk_get(dev, "tx_lane0_sync_clk",
175 &host->tx_l0_sync_clk, false);
176 if (err)
177 goto out;
178
179 /* In case of single lane per direction, don't read lane1 clocks */
180 if (host->hba->lanes_per_direction > 1) {
181 err = ufs_qcom_host_clk_get(dev, "rx_lane1_sync_clk",
182 &host->rx_l1_sync_clk, false);
183 if (err)
184 goto out;
185
186 err = ufs_qcom_host_clk_get(dev, "tx_lane1_sync_clk",
187 &host->tx_l1_sync_clk, true);
188 }
189 out:
190 return err;
191 }
192
ufs_qcom_link_startup_post_change(struct ufs_hba * hba)193 static int ufs_qcom_link_startup_post_change(struct ufs_hba *hba)
194 {
195 u32 tx_lanes;
196
197 return ufs_qcom_get_connected_tx_lanes(hba, &tx_lanes);
198 }
199
ufs_qcom_check_hibern8(struct ufs_hba * hba)200 static int ufs_qcom_check_hibern8(struct ufs_hba *hba)
201 {
202 int err;
203 u32 tx_fsm_val = 0;
204 unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS);
205
206 do {
207 err = ufshcd_dme_get(hba,
208 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
209 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
210 &tx_fsm_val);
211 if (err || tx_fsm_val == TX_FSM_HIBERN8)
212 break;
213
214 /* sleep for max. 200us */
215 usleep_range(100, 200);
216 } while (time_before(jiffies, timeout));
217
218 /*
219 * we might have scheduled out for long during polling so
220 * check the state again.
221 */
222 if (time_after(jiffies, timeout))
223 err = ufshcd_dme_get(hba,
224 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
225 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
226 &tx_fsm_val);
227
228 if (err) {
229 dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n",
230 __func__, err);
231 } else if (tx_fsm_val != TX_FSM_HIBERN8) {
232 err = tx_fsm_val;
233 dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n",
234 __func__, err);
235 }
236
237 return err;
238 }
239
ufs_qcom_select_unipro_mode(struct ufs_qcom_host * host)240 static void ufs_qcom_select_unipro_mode(struct ufs_qcom_host *host)
241 {
242 ufshcd_rmwl(host->hba, QUNIPRO_SEL,
243 ufs_qcom_cap_qunipro(host) ? QUNIPRO_SEL : 0,
244 REG_UFS_CFG1);
245 /* make sure above configuration is applied before we return */
246 mb();
247 }
248
249 /*
250 * ufs_qcom_host_reset - reset host controller and PHY
251 */
ufs_qcom_host_reset(struct ufs_hba * hba)252 static int ufs_qcom_host_reset(struct ufs_hba *hba)
253 {
254 int ret = 0;
255 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
256 bool reenable_intr = false;
257
258 if (!host->core_reset) {
259 dev_warn(hba->dev, "%s: reset control not set\n", __func__);
260 goto out;
261 }
262
263 reenable_intr = hba->is_irq_enabled;
264 disable_irq(hba->irq);
265 hba->is_irq_enabled = false;
266
267 ret = reset_control_assert(host->core_reset);
268 if (ret) {
269 dev_err(hba->dev, "%s: core_reset assert failed, err = %d\n",
270 __func__, ret);
271 goto out;
272 }
273
274 /*
275 * The hardware requirement for delay between assert/deassert
276 * is at least 3-4 sleep clock (32.7KHz) cycles, which comes to
277 * ~125us (4/32768). To be on the safe side add 200us delay.
278 */
279 usleep_range(200, 210);
280
281 ret = reset_control_deassert(host->core_reset);
282 if (ret)
283 dev_err(hba->dev, "%s: core_reset deassert failed, err = %d\n",
284 __func__, ret);
285
286 usleep_range(1000, 1100);
287
288 if (reenable_intr) {
289 enable_irq(hba->irq);
290 hba->is_irq_enabled = true;
291 }
292
293 out:
294 return ret;
295 }
296
ufs_qcom_power_up_sequence(struct ufs_hba * hba)297 static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
298 {
299 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
300 struct phy *phy = host->generic_phy;
301 int ret = 0;
302 bool is_rate_B = (UFS_QCOM_LIMIT_HS_RATE == PA_HS_MODE_B)
303 ? true : false;
304
305 /* Reset UFS Host Controller and PHY */
306 ret = ufs_qcom_host_reset(hba);
307 if (ret)
308 dev_warn(hba->dev, "%s: host reset returned %d\n",
309 __func__, ret);
310
311 if (is_rate_B)
312 phy_set_mode(phy, PHY_MODE_UFS_HS_B);
313
314 /* phy initialization - calibrate the phy */
315 ret = phy_init(phy);
316 if (ret) {
317 dev_err(hba->dev, "%s: phy init failed, ret = %d\n",
318 __func__, ret);
319 goto out;
320 }
321
322 /* power on phy - start serdes and phy's power and clocks */
323 ret = phy_power_on(phy);
324 if (ret) {
325 dev_err(hba->dev, "%s: phy power on failed, ret = %d\n",
326 __func__, ret);
327 goto out_disable_phy;
328 }
329
330 ufs_qcom_select_unipro_mode(host);
331
332 return 0;
333
334 out_disable_phy:
335 phy_exit(phy);
336 out:
337 return ret;
338 }
339
340 /*
341 * The UTP controller has a number of internal clock gating cells (CGCs).
342 * Internal hardware sub-modules within the UTP controller control the CGCs.
343 * Hardware CGCs disable the clock to inactivate UTP sub-modules not involved
344 * in a specific operation, UTP controller CGCs are by default disabled and
345 * this function enables them (after every UFS link startup) to save some power
346 * leakage.
347 */
ufs_qcom_enable_hw_clk_gating(struct ufs_hba * hba)348 static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba)
349 {
350 ufshcd_writel(hba,
351 ufshcd_readl(hba, REG_UFS_CFG2) | REG_UFS_CFG2_CGC_EN_ALL,
352 REG_UFS_CFG2);
353
354 /* Ensure that HW clock gating is enabled before next operations */
355 mb();
356 }
357
ufs_qcom_hce_enable_notify(struct ufs_hba * hba,enum ufs_notify_change_status status)358 static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba,
359 enum ufs_notify_change_status status)
360 {
361 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
362 int err = 0;
363
364 switch (status) {
365 case PRE_CHANGE:
366 ufs_qcom_power_up_sequence(hba);
367 /*
368 * The PHY PLL output is the source of tx/rx lane symbol
369 * clocks, hence, enable the lane clocks only after PHY
370 * is initialized.
371 */
372 err = ufs_qcom_enable_lane_clks(host);
373 break;
374 case POST_CHANGE:
375 /* check if UFS PHY moved from DISABLED to HIBERN8 */
376 err = ufs_qcom_check_hibern8(hba);
377 ufs_qcom_enable_hw_clk_gating(hba);
378 ufs_qcom_ice_enable(host);
379 break;
380 default:
381 dev_err(hba->dev, "%s: invalid status %d\n", __func__, status);
382 err = -EINVAL;
383 break;
384 }
385 return err;
386 }
387
388 /*
389 * Returns zero for success and non-zero in case of a failure
390 */
ufs_qcom_cfg_timers(struct ufs_hba * hba,u32 gear,u32 hs,u32 rate,bool update_link_startup_timer)391 static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear,
392 u32 hs, u32 rate, bool update_link_startup_timer)
393 {
394 int ret = 0;
395 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
396 struct ufs_clk_info *clki;
397 u32 core_clk_period_in_ns;
398 u32 tx_clk_cycles_per_us = 0;
399 unsigned long core_clk_rate = 0;
400 u32 core_clk_cycles_per_us = 0;
401
402 static u32 pwm_fr_table[][2] = {
403 {UFS_PWM_G1, 0x1},
404 {UFS_PWM_G2, 0x1},
405 {UFS_PWM_G3, 0x1},
406 {UFS_PWM_G4, 0x1},
407 };
408
409 static u32 hs_fr_table_rA[][2] = {
410 {UFS_HS_G1, 0x1F},
411 {UFS_HS_G2, 0x3e},
412 {UFS_HS_G3, 0x7D},
413 };
414
415 static u32 hs_fr_table_rB[][2] = {
416 {UFS_HS_G1, 0x24},
417 {UFS_HS_G2, 0x49},
418 {UFS_HS_G3, 0x92},
419 };
420
421 /*
422 * The Qunipro controller does not use following registers:
423 * SYS1CLK_1US_REG, TX_SYMBOL_CLK_1US_REG, CLK_NS_REG &
424 * UFS_REG_PA_LINK_STARTUP_TIMER
425 * But UTP controller uses SYS1CLK_1US_REG register for Interrupt
426 * Aggregation logic.
427 */
428 if (ufs_qcom_cap_qunipro(host) && !ufshcd_is_intr_aggr_allowed(hba))
429 goto out;
430
431 if (gear == 0) {
432 dev_err(hba->dev, "%s: invalid gear = %d\n", __func__, gear);
433 goto out_error;
434 }
435
436 list_for_each_entry(clki, &hba->clk_list_head, list) {
437 if (!strcmp(clki->name, "core_clk"))
438 core_clk_rate = clk_get_rate(clki->clk);
439 }
440
441 /* If frequency is smaller than 1MHz, set to 1MHz */
442 if (core_clk_rate < DEFAULT_CLK_RATE_HZ)
443 core_clk_rate = DEFAULT_CLK_RATE_HZ;
444
445 core_clk_cycles_per_us = core_clk_rate / USEC_PER_SEC;
446 if (ufshcd_readl(hba, REG_UFS_SYS1CLK_1US) != core_clk_cycles_per_us) {
447 ufshcd_writel(hba, core_clk_cycles_per_us, REG_UFS_SYS1CLK_1US);
448 /*
449 * make sure above write gets applied before we return from
450 * this function.
451 */
452 mb();
453 }
454
455 if (ufs_qcom_cap_qunipro(host))
456 goto out;
457
458 core_clk_period_in_ns = NSEC_PER_SEC / core_clk_rate;
459 core_clk_period_in_ns <<= OFFSET_CLK_NS_REG;
460 core_clk_period_in_ns &= MASK_CLK_NS_REG;
461
462 switch (hs) {
463 case FASTAUTO_MODE:
464 case FAST_MODE:
465 if (rate == PA_HS_MODE_A) {
466 if (gear > ARRAY_SIZE(hs_fr_table_rA)) {
467 dev_err(hba->dev,
468 "%s: index %d exceeds table size %zu\n",
469 __func__, gear,
470 ARRAY_SIZE(hs_fr_table_rA));
471 goto out_error;
472 }
473 tx_clk_cycles_per_us = hs_fr_table_rA[gear-1][1];
474 } else if (rate == PA_HS_MODE_B) {
475 if (gear > ARRAY_SIZE(hs_fr_table_rB)) {
476 dev_err(hba->dev,
477 "%s: index %d exceeds table size %zu\n",
478 __func__, gear,
479 ARRAY_SIZE(hs_fr_table_rB));
480 goto out_error;
481 }
482 tx_clk_cycles_per_us = hs_fr_table_rB[gear-1][1];
483 } else {
484 dev_err(hba->dev, "%s: invalid rate = %d\n",
485 __func__, rate);
486 goto out_error;
487 }
488 break;
489 case SLOWAUTO_MODE:
490 case SLOW_MODE:
491 if (gear > ARRAY_SIZE(pwm_fr_table)) {
492 dev_err(hba->dev,
493 "%s: index %d exceeds table size %zu\n",
494 __func__, gear,
495 ARRAY_SIZE(pwm_fr_table));
496 goto out_error;
497 }
498 tx_clk_cycles_per_us = pwm_fr_table[gear-1][1];
499 break;
500 case UNCHANGED:
501 default:
502 dev_err(hba->dev, "%s: invalid mode = %d\n", __func__, hs);
503 goto out_error;
504 }
505
506 if (ufshcd_readl(hba, REG_UFS_TX_SYMBOL_CLK_NS_US) !=
507 (core_clk_period_in_ns | tx_clk_cycles_per_us)) {
508 /* this register 2 fields shall be written at once */
509 ufshcd_writel(hba, core_clk_period_in_ns | tx_clk_cycles_per_us,
510 REG_UFS_TX_SYMBOL_CLK_NS_US);
511 /*
512 * make sure above write gets applied before we return from
513 * this function.
514 */
515 mb();
516 }
517
518 if (update_link_startup_timer) {
519 ufshcd_writel(hba, ((core_clk_rate / MSEC_PER_SEC) * 100),
520 REG_UFS_PA_LINK_STARTUP_TIMER);
521 /*
522 * make sure that this configuration is applied before
523 * we return
524 */
525 mb();
526 }
527 goto out;
528
529 out_error:
530 ret = -EINVAL;
531 out:
532 return ret;
533 }
534
ufs_qcom_link_startup_notify(struct ufs_hba * hba,enum ufs_notify_change_status status)535 static int ufs_qcom_link_startup_notify(struct ufs_hba *hba,
536 enum ufs_notify_change_status status)
537 {
538 int err = 0;
539 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
540
541 switch (status) {
542 case PRE_CHANGE:
543 if (ufs_qcom_cfg_timers(hba, UFS_PWM_G1, SLOWAUTO_MODE,
544 0, true)) {
545 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
546 __func__);
547 err = -EINVAL;
548 goto out;
549 }
550
551 if (ufs_qcom_cap_qunipro(host))
552 /*
553 * set unipro core clock cycles to 150 & clear clock
554 * divider
555 */
556 err = ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba,
557 150);
558
559 /*
560 * Some UFS devices (and may be host) have issues if LCC is
561 * enabled. So we are setting PA_Local_TX_LCC_Enable to 0
562 * before link startup which will make sure that both host
563 * and device TX LCC are disabled once link startup is
564 * completed.
565 */
566 if (ufshcd_get_local_unipro_ver(hba) != UFS_UNIPRO_VER_1_41)
567 err = ufshcd_disable_host_tx_lcc(hba);
568
569 break;
570 case POST_CHANGE:
571 ufs_qcom_link_startup_post_change(hba);
572 break;
573 default:
574 break;
575 }
576
577 out:
578 return err;
579 }
580
ufs_qcom_suspend(struct ufs_hba * hba,enum ufs_pm_op pm_op)581 static int ufs_qcom_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
582 {
583 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
584 struct phy *phy = host->generic_phy;
585
586 if (ufs_qcom_is_link_off(hba)) {
587 /*
588 * Disable the tx/rx lane symbol clocks before PHY is
589 * powered down as the PLL source should be disabled
590 * after downstream clocks are disabled.
591 */
592 ufs_qcom_disable_lane_clks(host);
593 phy_power_off(phy);
594
595 } else if (!ufs_qcom_is_link_active(hba)) {
596 ufs_qcom_disable_lane_clks(host);
597 }
598
599 return 0;
600 }
601
ufs_qcom_resume(struct ufs_hba * hba,enum ufs_pm_op pm_op)602 static int ufs_qcom_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
603 {
604 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
605 struct phy *phy = host->generic_phy;
606 int err;
607
608 if (ufs_qcom_is_link_off(hba)) {
609 err = phy_power_on(phy);
610 if (err) {
611 dev_err(hba->dev, "%s: failed PHY power on: %d\n",
612 __func__, err);
613 return err;
614 }
615
616 err = ufs_qcom_enable_lane_clks(host);
617 if (err)
618 return err;
619
620 } else if (!ufs_qcom_is_link_active(hba)) {
621 err = ufs_qcom_enable_lane_clks(host);
622 if (err)
623 return err;
624 }
625
626 err = ufs_qcom_ice_resume(host);
627 if (err)
628 return err;
629
630 hba->is_sys_suspended = false;
631 return 0;
632 }
633
ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host * host,bool enable)634 static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host *host, bool enable)
635 {
636 if (host->dev_ref_clk_ctrl_mmio &&
637 (enable ^ host->is_dev_ref_clk_enabled)) {
638 u32 temp = readl_relaxed(host->dev_ref_clk_ctrl_mmio);
639
640 if (enable)
641 temp |= host->dev_ref_clk_en_mask;
642 else
643 temp &= ~host->dev_ref_clk_en_mask;
644
645 /*
646 * If we are here to disable this clock it might be immediately
647 * after entering into hibern8 in which case we need to make
648 * sure that device ref_clk is active for specific time after
649 * hibern8 enter.
650 */
651 if (!enable) {
652 unsigned long gating_wait;
653
654 gating_wait = host->hba->dev_info.clk_gating_wait_us;
655 if (!gating_wait) {
656 udelay(1);
657 } else {
658 /*
659 * bRefClkGatingWaitTime defines the minimum
660 * time for which the reference clock is
661 * required by device during transition from
662 * HS-MODE to LS-MODE or HIBERN8 state. Give it
663 * more delay to be on the safe side.
664 */
665 gating_wait += 10;
666 usleep_range(gating_wait, gating_wait + 10);
667 }
668 }
669
670 writel_relaxed(temp, host->dev_ref_clk_ctrl_mmio);
671
672 /* ensure that ref_clk is enabled/disabled before we return */
673 wmb();
674
675 /*
676 * If we call hibern8 exit after this, we need to make sure that
677 * device ref_clk is stable for at least 1us before the hibern8
678 * exit command.
679 */
680 if (enable)
681 udelay(1);
682
683 host->is_dev_ref_clk_enabled = enable;
684 }
685 }
686
ufs_qcom_pwr_change_notify(struct ufs_hba * hba,enum ufs_notify_change_status status,struct ufs_pa_layer_attr * dev_max_params,struct ufs_pa_layer_attr * dev_req_params)687 static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
688 enum ufs_notify_change_status status,
689 struct ufs_pa_layer_attr *dev_max_params,
690 struct ufs_pa_layer_attr *dev_req_params)
691 {
692 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
693 struct ufs_dev_params ufs_qcom_cap;
694 int ret = 0;
695
696 if (!dev_req_params) {
697 pr_err("%s: incoming dev_req_params is NULL\n", __func__);
698 ret = -EINVAL;
699 goto out;
700 }
701
702 switch (status) {
703 case PRE_CHANGE:
704 ufs_qcom_cap.tx_lanes = UFS_QCOM_LIMIT_NUM_LANES_TX;
705 ufs_qcom_cap.rx_lanes = UFS_QCOM_LIMIT_NUM_LANES_RX;
706 ufs_qcom_cap.hs_rx_gear = UFS_QCOM_LIMIT_HSGEAR_RX;
707 ufs_qcom_cap.hs_tx_gear = UFS_QCOM_LIMIT_HSGEAR_TX;
708 ufs_qcom_cap.pwm_rx_gear = UFS_QCOM_LIMIT_PWMGEAR_RX;
709 ufs_qcom_cap.pwm_tx_gear = UFS_QCOM_LIMIT_PWMGEAR_TX;
710 ufs_qcom_cap.rx_pwr_pwm = UFS_QCOM_LIMIT_RX_PWR_PWM;
711 ufs_qcom_cap.tx_pwr_pwm = UFS_QCOM_LIMIT_TX_PWR_PWM;
712 ufs_qcom_cap.rx_pwr_hs = UFS_QCOM_LIMIT_RX_PWR_HS;
713 ufs_qcom_cap.tx_pwr_hs = UFS_QCOM_LIMIT_TX_PWR_HS;
714 ufs_qcom_cap.hs_rate = UFS_QCOM_LIMIT_HS_RATE;
715 ufs_qcom_cap.desired_working_mode =
716 UFS_QCOM_LIMIT_DESIRED_MODE;
717
718 if (host->hw_ver.major == 0x1) {
719 /*
720 * HS-G3 operations may not reliably work on legacy QCOM
721 * UFS host controller hardware even though capability
722 * exchange during link startup phase may end up
723 * negotiating maximum supported gear as G3.
724 * Hence downgrade the maximum supported gear to HS-G2.
725 */
726 if (ufs_qcom_cap.hs_tx_gear > UFS_HS_G2)
727 ufs_qcom_cap.hs_tx_gear = UFS_HS_G2;
728 if (ufs_qcom_cap.hs_rx_gear > UFS_HS_G2)
729 ufs_qcom_cap.hs_rx_gear = UFS_HS_G2;
730 }
731
732 ret = ufshcd_get_pwr_dev_param(&ufs_qcom_cap,
733 dev_max_params,
734 dev_req_params);
735 if (ret) {
736 pr_err("%s: failed to determine capabilities\n",
737 __func__);
738 goto out;
739 }
740
741 /* enable the device ref clock before changing to HS mode */
742 if (!ufshcd_is_hs_mode(&hba->pwr_info) &&
743 ufshcd_is_hs_mode(dev_req_params))
744 ufs_qcom_dev_ref_clk_ctrl(host, true);
745
746 if (host->hw_ver.major >= 0x4) {
747 if (dev_req_params->gear_tx == UFS_HS_G4) {
748 /* INITIAL ADAPT */
749 ufshcd_dme_set(hba,
750 UIC_ARG_MIB(PA_TXHSADAPTTYPE),
751 PA_INITIAL_ADAPT);
752 } else {
753 /* NO ADAPT */
754 ufshcd_dme_set(hba,
755 UIC_ARG_MIB(PA_TXHSADAPTTYPE),
756 PA_NO_ADAPT);
757 }
758 }
759 break;
760 case POST_CHANGE:
761 if (ufs_qcom_cfg_timers(hba, dev_req_params->gear_rx,
762 dev_req_params->pwr_rx,
763 dev_req_params->hs_rate, false)) {
764 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
765 __func__);
766 /*
767 * we return error code at the end of the routine,
768 * but continue to configure UFS_PHY_TX_LANE_ENABLE
769 * and bus voting as usual
770 */
771 ret = -EINVAL;
772 }
773
774 /* cache the power mode parameters to use internally */
775 memcpy(&host->dev_req_params,
776 dev_req_params, sizeof(*dev_req_params));
777
778 /* disable the device ref clock if entered PWM mode */
779 if (ufshcd_is_hs_mode(&hba->pwr_info) &&
780 !ufshcd_is_hs_mode(dev_req_params))
781 ufs_qcom_dev_ref_clk_ctrl(host, false);
782 break;
783 default:
784 ret = -EINVAL;
785 break;
786 }
787 out:
788 return ret;
789 }
790
ufs_qcom_quirk_host_pa_saveconfigtime(struct ufs_hba * hba)791 static int ufs_qcom_quirk_host_pa_saveconfigtime(struct ufs_hba *hba)
792 {
793 int err;
794 u32 pa_vs_config_reg1;
795
796 err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
797 &pa_vs_config_reg1);
798 if (err)
799 goto out;
800
801 /* Allow extension of MSB bits of PA_SaveConfigTime attribute */
802 err = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
803 (pa_vs_config_reg1 | (1 << 12)));
804
805 out:
806 return err;
807 }
808
ufs_qcom_apply_dev_quirks(struct ufs_hba * hba)809 static int ufs_qcom_apply_dev_quirks(struct ufs_hba *hba)
810 {
811 int err = 0;
812
813 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME)
814 err = ufs_qcom_quirk_host_pa_saveconfigtime(hba);
815
816 if (hba->dev_info.wmanufacturerid == UFS_VENDOR_WDC)
817 hba->dev_quirks |= UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE;
818
819 return err;
820 }
821
ufs_qcom_get_ufs_hci_version(struct ufs_hba * hba)822 static u32 ufs_qcom_get_ufs_hci_version(struct ufs_hba *hba)
823 {
824 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
825
826 if (host->hw_ver.major == 0x1)
827 return UFSHCI_VERSION_11;
828 else
829 return UFSHCI_VERSION_20;
830 }
831
832 /**
833 * ufs_qcom_advertise_quirks - advertise the known QCOM UFS controller quirks
834 * @hba: host controller instance
835 *
836 * QCOM UFS host controller might have some non standard behaviours (quirks)
837 * than what is specified by UFSHCI specification. Advertise all such
838 * quirks to standard UFS host controller driver so standard takes them into
839 * account.
840 */
ufs_qcom_advertise_quirks(struct ufs_hba * hba)841 static void ufs_qcom_advertise_quirks(struct ufs_hba *hba)
842 {
843 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
844
845 if (host->hw_ver.major == 0x01) {
846 hba->quirks |= UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS
847 | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP
848 | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE;
849
850 if (host->hw_ver.minor == 0x0001 && host->hw_ver.step == 0x0001)
851 hba->quirks |= UFSHCD_QUIRK_BROKEN_INTR_AGGR;
852
853 hba->quirks |= UFSHCD_QUIRK_BROKEN_LCC;
854 }
855
856 if (host->hw_ver.major == 0x2) {
857 hba->quirks |= UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION;
858
859 if (!ufs_qcom_cap_qunipro(host))
860 /* Legacy UniPro mode still need following quirks */
861 hba->quirks |= (UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS
862 | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE
863 | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP);
864 }
865 }
866
ufs_qcom_set_caps(struct ufs_hba * hba)867 static void ufs_qcom_set_caps(struct ufs_hba *hba)
868 {
869 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
870
871 hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING;
872 hba->caps |= UFSHCD_CAP_CLK_SCALING;
873 hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND;
874 hba->caps |= UFSHCD_CAP_WB_EN;
875 hba->caps |= UFSHCD_CAP_CRYPTO;
876
877 if (host->hw_ver.major >= 0x2) {
878 host->caps = UFS_QCOM_CAP_QUNIPRO |
879 UFS_QCOM_CAP_RETAIN_SEC_CFG_AFTER_PWR_COLLAPSE;
880 }
881 }
882
883 /**
884 * ufs_qcom_setup_clocks - enables/disable clocks
885 * @hba: host controller instance
886 * @on: If true, enable clocks else disable them.
887 * @status: PRE_CHANGE or POST_CHANGE notify
888 *
889 * Returns 0 on success, non-zero on failure.
890 */
ufs_qcom_setup_clocks(struct ufs_hba * hba,bool on,enum ufs_notify_change_status status)891 static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on,
892 enum ufs_notify_change_status status)
893 {
894 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
895 int err = 0;
896
897 /*
898 * In case ufs_qcom_init() is not yet done, simply ignore.
899 * This ufs_qcom_setup_clocks() shall be called from
900 * ufs_qcom_init() after init is done.
901 */
902 if (!host)
903 return 0;
904
905 switch (status) {
906 case PRE_CHANGE:
907 if (!on) {
908 if (!ufs_qcom_is_link_active(hba)) {
909 /* disable device ref_clk */
910 ufs_qcom_dev_ref_clk_ctrl(host, false);
911 }
912 }
913 break;
914 case POST_CHANGE:
915 if (on) {
916 /* enable the device ref clock for HS mode*/
917 if (ufshcd_is_hs_mode(&hba->pwr_info))
918 ufs_qcom_dev_ref_clk_ctrl(host, true);
919 }
920 break;
921 }
922
923 return err;
924 }
925
926 static int
ufs_qcom_reset_assert(struct reset_controller_dev * rcdev,unsigned long id)927 ufs_qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
928 {
929 struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev);
930
931 /* Currently this code only knows about a single reset. */
932 WARN_ON(id);
933 ufs_qcom_assert_reset(host->hba);
934 /* provide 1ms delay to let the reset pulse propagate. */
935 usleep_range(1000, 1100);
936 return 0;
937 }
938
939 static int
ufs_qcom_reset_deassert(struct reset_controller_dev * rcdev,unsigned long id)940 ufs_qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
941 {
942 struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev);
943
944 /* Currently this code only knows about a single reset. */
945 WARN_ON(id);
946 ufs_qcom_deassert_reset(host->hba);
947
948 /*
949 * after reset deassertion, phy will need all ref clocks,
950 * voltage, current to settle down before starting serdes.
951 */
952 usleep_range(1000, 1100);
953 return 0;
954 }
955
956 static const struct reset_control_ops ufs_qcom_reset_ops = {
957 .assert = ufs_qcom_reset_assert,
958 .deassert = ufs_qcom_reset_deassert,
959 };
960
961 #define ANDROID_BOOT_DEV_MAX 30
962 static char android_boot_dev[ANDROID_BOOT_DEV_MAX];
963
964 #ifndef MODULE
get_android_boot_dev(char * str)965 static int __init get_android_boot_dev(char *str)
966 {
967 strlcpy(android_boot_dev, str, ANDROID_BOOT_DEV_MAX);
968 return 1;
969 }
970 __setup("androidboot.bootdevice=", get_android_boot_dev);
971 #endif
972
973 /**
974 * ufs_qcom_init - bind phy with controller
975 * @hba: host controller instance
976 *
977 * Binds PHY with controller and powers up PHY enabling clocks
978 * and regulators.
979 *
980 * Returns -EPROBE_DEFER if binding fails, returns negative error
981 * on phy power up failure and returns zero on success.
982 */
ufs_qcom_init(struct ufs_hba * hba)983 static int ufs_qcom_init(struct ufs_hba *hba)
984 {
985 int err;
986 struct device *dev = hba->dev;
987 struct platform_device *pdev = to_platform_device(dev);
988 struct ufs_qcom_host *host;
989 struct resource *res;
990
991 if (strlen(android_boot_dev) && strcmp(android_boot_dev, dev_name(dev)))
992 return -ENODEV;
993
994 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
995 if (!host) {
996 err = -ENOMEM;
997 dev_err(dev, "%s: no memory for qcom ufs host\n", __func__);
998 goto out;
999 }
1000
1001 /* Make a two way bind between the qcom host and the hba */
1002 host->hba = hba;
1003 ufshcd_set_variant(hba, host);
1004
1005 /* Setup the reset control of HCI */
1006 host->core_reset = devm_reset_control_get(hba->dev, "rst");
1007 if (IS_ERR(host->core_reset)) {
1008 err = PTR_ERR(host->core_reset);
1009 dev_warn(dev, "Failed to get reset control %d\n", err);
1010 host->core_reset = NULL;
1011 err = 0;
1012 }
1013
1014 /* Fire up the reset controller. Failure here is non-fatal. */
1015 host->rcdev.of_node = dev->of_node;
1016 host->rcdev.ops = &ufs_qcom_reset_ops;
1017 host->rcdev.owner = dev->driver->owner;
1018 host->rcdev.nr_resets = 1;
1019 err = devm_reset_controller_register(dev, &host->rcdev);
1020 if (err) {
1021 dev_warn(dev, "Failed to register reset controller\n");
1022 err = 0;
1023 }
1024
1025 /*
1026 * voting/devoting device ref_clk source is time consuming hence
1027 * skip devoting it during aggressive clock gating. This clock
1028 * will still be gated off during runtime suspend.
1029 */
1030 host->generic_phy = devm_phy_get(dev, "ufsphy");
1031
1032 if (host->generic_phy == ERR_PTR(-EPROBE_DEFER)) {
1033 /*
1034 * UFS driver might be probed before the phy driver does.
1035 * In that case we would like to return EPROBE_DEFER code.
1036 */
1037 err = -EPROBE_DEFER;
1038 dev_warn(dev, "%s: required phy device. hasn't probed yet. err = %d\n",
1039 __func__, err);
1040 goto out_variant_clear;
1041 } else if (IS_ERR(host->generic_phy)) {
1042 if (has_acpi_companion(dev)) {
1043 host->generic_phy = NULL;
1044 } else {
1045 err = PTR_ERR(host->generic_phy);
1046 dev_err(dev, "%s: PHY get failed %d\n", __func__, err);
1047 goto out_variant_clear;
1048 }
1049 }
1050
1051 host->device_reset = devm_gpiod_get_optional(dev, "reset",
1052 GPIOD_OUT_HIGH);
1053 if (IS_ERR(host->device_reset)) {
1054 err = PTR_ERR(host->device_reset);
1055 if (err != -EPROBE_DEFER)
1056 dev_err(dev, "failed to acquire reset gpio: %d\n", err);
1057 goto out_variant_clear;
1058 }
1059
1060 ufs_qcom_get_controller_revision(hba, &host->hw_ver.major,
1061 &host->hw_ver.minor, &host->hw_ver.step);
1062
1063 /*
1064 * for newer controllers, device reference clock control bit has
1065 * moved inside UFS controller register address space itself.
1066 */
1067 if (host->hw_ver.major >= 0x02) {
1068 host->dev_ref_clk_ctrl_mmio = hba->mmio_base + REG_UFS_CFG1;
1069 host->dev_ref_clk_en_mask = BIT(26);
1070 } else {
1071 /* "dev_ref_clk_ctrl_mem" is optional resource */
1072 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1073 "dev_ref_clk_ctrl_mem");
1074 if (res) {
1075 host->dev_ref_clk_ctrl_mmio =
1076 devm_ioremap_resource(dev, res);
1077 if (IS_ERR(host->dev_ref_clk_ctrl_mmio)) {
1078 dev_warn(dev,
1079 "%s: could not map dev_ref_clk_ctrl_mmio, err %ld\n",
1080 __func__,
1081 PTR_ERR(host->dev_ref_clk_ctrl_mmio));
1082 host->dev_ref_clk_ctrl_mmio = NULL;
1083 }
1084 host->dev_ref_clk_en_mask = BIT(5);
1085 }
1086 }
1087
1088 err = ufs_qcom_init_lane_clks(host);
1089 if (err)
1090 goto out_variant_clear;
1091
1092 ufs_qcom_set_caps(hba);
1093 ufs_qcom_advertise_quirks(hba);
1094
1095 err = ufs_qcom_ice_init(host);
1096 if (err)
1097 goto out_variant_clear;
1098
1099 ufs_qcom_setup_clocks(hba, true, POST_CHANGE);
1100
1101 if (hba->dev->id < MAX_UFS_QCOM_HOSTS)
1102 ufs_qcom_hosts[hba->dev->id] = host;
1103
1104 host->dbg_print_en |= UFS_QCOM_DEFAULT_DBG_PRINT_EN;
1105 ufs_qcom_get_default_testbus_cfg(host);
1106 err = ufs_qcom_testbus_config(host);
1107 if (err) {
1108 dev_warn(dev, "%s: failed to configure the testbus %d\n",
1109 __func__, err);
1110 err = 0;
1111 }
1112
1113 goto out;
1114
1115 out_variant_clear:
1116 ufshcd_set_variant(hba, NULL);
1117 out:
1118 return err;
1119 }
1120
ufs_qcom_exit(struct ufs_hba * hba)1121 static void ufs_qcom_exit(struct ufs_hba *hba)
1122 {
1123 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1124
1125 ufs_qcom_disable_lane_clks(host);
1126 phy_power_off(host->generic_phy);
1127 phy_exit(host->generic_phy);
1128 }
1129
ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba * hba,u32 clk_cycles)1130 static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba,
1131 u32 clk_cycles)
1132 {
1133 int err;
1134 u32 core_clk_ctrl_reg;
1135
1136 if (clk_cycles > DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK)
1137 return -EINVAL;
1138
1139 err = ufshcd_dme_get(hba,
1140 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1141 &core_clk_ctrl_reg);
1142 if (err)
1143 goto out;
1144
1145 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK;
1146 core_clk_ctrl_reg |= clk_cycles;
1147
1148 /* Clear CORE_CLK_DIV_EN */
1149 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
1150
1151 err = ufshcd_dme_set(hba,
1152 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1153 core_clk_ctrl_reg);
1154 out:
1155 return err;
1156 }
1157
ufs_qcom_clk_scale_up_pre_change(struct ufs_hba * hba)1158 static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba)
1159 {
1160 /* nothing to do as of now */
1161 return 0;
1162 }
1163
ufs_qcom_clk_scale_up_post_change(struct ufs_hba * hba)1164 static int ufs_qcom_clk_scale_up_post_change(struct ufs_hba *hba)
1165 {
1166 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1167
1168 if (!ufs_qcom_cap_qunipro(host))
1169 return 0;
1170
1171 /* set unipro core clock cycles to 150 and clear clock divider */
1172 return ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 150);
1173 }
1174
ufs_qcom_clk_scale_down_pre_change(struct ufs_hba * hba)1175 static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba)
1176 {
1177 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1178 int err;
1179 u32 core_clk_ctrl_reg;
1180
1181 if (!ufs_qcom_cap_qunipro(host))
1182 return 0;
1183
1184 err = ufshcd_dme_get(hba,
1185 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1186 &core_clk_ctrl_reg);
1187
1188 /* make sure CORE_CLK_DIV_EN is cleared */
1189 if (!err &&
1190 (core_clk_ctrl_reg & DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT)) {
1191 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
1192 err = ufshcd_dme_set(hba,
1193 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1194 core_clk_ctrl_reg);
1195 }
1196
1197 return err;
1198 }
1199
ufs_qcom_clk_scale_down_post_change(struct ufs_hba * hba)1200 static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba)
1201 {
1202 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1203
1204 if (!ufs_qcom_cap_qunipro(host))
1205 return 0;
1206
1207 /* set unipro core clock cycles to 75 and clear clock divider */
1208 return ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 75);
1209 }
1210
ufs_qcom_clk_scale_notify(struct ufs_hba * hba,bool scale_up,enum ufs_notify_change_status status)1211 static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba,
1212 bool scale_up, enum ufs_notify_change_status status)
1213 {
1214 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1215 struct ufs_pa_layer_attr *dev_req_params = &host->dev_req_params;
1216 int err = 0;
1217
1218 if (status == PRE_CHANGE) {
1219 if (scale_up)
1220 err = ufs_qcom_clk_scale_up_pre_change(hba);
1221 else
1222 err = ufs_qcom_clk_scale_down_pre_change(hba);
1223 } else {
1224 if (scale_up)
1225 err = ufs_qcom_clk_scale_up_post_change(hba);
1226 else
1227 err = ufs_qcom_clk_scale_down_post_change(hba);
1228
1229 if (err || !dev_req_params)
1230 goto out;
1231
1232 ufs_qcom_cfg_timers(hba,
1233 dev_req_params->gear_rx,
1234 dev_req_params->pwr_rx,
1235 dev_req_params->hs_rate,
1236 false);
1237 }
1238
1239 out:
1240 return err;
1241 }
1242
ufs_qcom_print_hw_debug_reg_all(struct ufs_hba * hba,void * priv,void (* print_fn)(struct ufs_hba * hba,int offset,int num_regs,const char * str,void * priv))1243 static void ufs_qcom_print_hw_debug_reg_all(struct ufs_hba *hba,
1244 void *priv, void (*print_fn)(struct ufs_hba *hba,
1245 int offset, int num_regs, const char *str, void *priv))
1246 {
1247 u32 reg;
1248 struct ufs_qcom_host *host;
1249
1250 if (unlikely(!hba)) {
1251 pr_err("%s: hba is NULL\n", __func__);
1252 return;
1253 }
1254 if (unlikely(!print_fn)) {
1255 dev_err(hba->dev, "%s: print_fn is NULL\n", __func__);
1256 return;
1257 }
1258
1259 host = ufshcd_get_variant(hba);
1260 if (!(host->dbg_print_en & UFS_QCOM_DBG_PRINT_REGS_EN))
1261 return;
1262
1263 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_REG_OCSC);
1264 print_fn(hba, reg, 44, "UFS_UFS_DBG_RD_REG_OCSC ", priv);
1265
1266 reg = ufshcd_readl(hba, REG_UFS_CFG1);
1267 reg |= UTP_DBG_RAMS_EN;
1268 ufshcd_writel(hba, reg, REG_UFS_CFG1);
1269
1270 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_EDTL_RAM);
1271 print_fn(hba, reg, 32, "UFS_UFS_DBG_RD_EDTL_RAM ", priv);
1272
1273 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_DESC_RAM);
1274 print_fn(hba, reg, 128, "UFS_UFS_DBG_RD_DESC_RAM ", priv);
1275
1276 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_PRDT_RAM);
1277 print_fn(hba, reg, 64, "UFS_UFS_DBG_RD_PRDT_RAM ", priv);
1278
1279 /* clear bit 17 - UTP_DBG_RAMS_EN */
1280 ufshcd_rmwl(hba, UTP_DBG_RAMS_EN, 0, REG_UFS_CFG1);
1281
1282 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UAWM);
1283 print_fn(hba, reg, 4, "UFS_DBG_RD_REG_UAWM ", priv);
1284
1285 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UARM);
1286 print_fn(hba, reg, 4, "UFS_DBG_RD_REG_UARM ", priv);
1287
1288 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TXUC);
1289 print_fn(hba, reg, 48, "UFS_DBG_RD_REG_TXUC ", priv);
1290
1291 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_RXUC);
1292 print_fn(hba, reg, 27, "UFS_DBG_RD_REG_RXUC ", priv);
1293
1294 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_DFC);
1295 print_fn(hba, reg, 19, "UFS_DBG_RD_REG_DFC ", priv);
1296
1297 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TRLUT);
1298 print_fn(hba, reg, 34, "UFS_DBG_RD_REG_TRLUT ", priv);
1299
1300 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TMRLUT);
1301 print_fn(hba, reg, 9, "UFS_DBG_RD_REG_TMRLUT ", priv);
1302 }
1303
ufs_qcom_enable_test_bus(struct ufs_qcom_host * host)1304 static void ufs_qcom_enable_test_bus(struct ufs_qcom_host *host)
1305 {
1306 if (host->dbg_print_en & UFS_QCOM_DBG_PRINT_TEST_BUS_EN) {
1307 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN,
1308 UFS_REG_TEST_BUS_EN, REG_UFS_CFG1);
1309 ufshcd_rmwl(host->hba, TEST_BUS_EN, TEST_BUS_EN, REG_UFS_CFG1);
1310 } else {
1311 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN, 0, REG_UFS_CFG1);
1312 ufshcd_rmwl(host->hba, TEST_BUS_EN, 0, REG_UFS_CFG1);
1313 }
1314 }
1315
ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host * host)1316 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host)
1317 {
1318 /* provide a legal default configuration */
1319 host->testbus.select_major = TSTBUS_UNIPRO;
1320 host->testbus.select_minor = 37;
1321 }
1322
ufs_qcom_testbus_cfg_is_ok(struct ufs_qcom_host * host)1323 static bool ufs_qcom_testbus_cfg_is_ok(struct ufs_qcom_host *host)
1324 {
1325 if (host->testbus.select_major >= TSTBUS_MAX) {
1326 dev_err(host->hba->dev,
1327 "%s: UFS_CFG1[TEST_BUS_SEL} may not equal 0x%05X\n",
1328 __func__, host->testbus.select_major);
1329 return false;
1330 }
1331
1332 return true;
1333 }
1334
ufs_qcom_testbus_config(struct ufs_qcom_host * host)1335 int ufs_qcom_testbus_config(struct ufs_qcom_host *host)
1336 {
1337 int reg;
1338 int offset;
1339 u32 mask = TEST_BUS_SUB_SEL_MASK;
1340
1341 if (!host)
1342 return -EINVAL;
1343
1344 if (!ufs_qcom_testbus_cfg_is_ok(host))
1345 return -EPERM;
1346
1347 switch (host->testbus.select_major) {
1348 case TSTBUS_UAWM:
1349 reg = UFS_TEST_BUS_CTRL_0;
1350 offset = 24;
1351 break;
1352 case TSTBUS_UARM:
1353 reg = UFS_TEST_BUS_CTRL_0;
1354 offset = 16;
1355 break;
1356 case TSTBUS_TXUC:
1357 reg = UFS_TEST_BUS_CTRL_0;
1358 offset = 8;
1359 break;
1360 case TSTBUS_RXUC:
1361 reg = UFS_TEST_BUS_CTRL_0;
1362 offset = 0;
1363 break;
1364 case TSTBUS_DFC:
1365 reg = UFS_TEST_BUS_CTRL_1;
1366 offset = 24;
1367 break;
1368 case TSTBUS_TRLUT:
1369 reg = UFS_TEST_BUS_CTRL_1;
1370 offset = 16;
1371 break;
1372 case TSTBUS_TMRLUT:
1373 reg = UFS_TEST_BUS_CTRL_1;
1374 offset = 8;
1375 break;
1376 case TSTBUS_OCSC:
1377 reg = UFS_TEST_BUS_CTRL_1;
1378 offset = 0;
1379 break;
1380 case TSTBUS_WRAPPER:
1381 reg = UFS_TEST_BUS_CTRL_2;
1382 offset = 16;
1383 break;
1384 case TSTBUS_COMBINED:
1385 reg = UFS_TEST_BUS_CTRL_2;
1386 offset = 8;
1387 break;
1388 case TSTBUS_UTP_HCI:
1389 reg = UFS_TEST_BUS_CTRL_2;
1390 offset = 0;
1391 break;
1392 case TSTBUS_UNIPRO:
1393 reg = UFS_UNIPRO_CFG;
1394 offset = 20;
1395 mask = 0xFFF;
1396 break;
1397 /*
1398 * No need for a default case, since
1399 * ufs_qcom_testbus_cfg_is_ok() checks that the configuration
1400 * is legal
1401 */
1402 }
1403 mask <<= offset;
1404 ufshcd_rmwl(host->hba, TEST_BUS_SEL,
1405 (u32)host->testbus.select_major << 19,
1406 REG_UFS_CFG1);
1407 ufshcd_rmwl(host->hba, mask,
1408 (u32)host->testbus.select_minor << offset,
1409 reg);
1410 ufs_qcom_enable_test_bus(host);
1411 /*
1412 * Make sure the test bus configuration is
1413 * committed before returning.
1414 */
1415 mb();
1416
1417 return 0;
1418 }
1419
ufs_qcom_dump_dbg_regs(struct ufs_hba * hba)1420 static void ufs_qcom_dump_dbg_regs(struct ufs_hba *hba)
1421 {
1422 ufshcd_dump_regs(hba, REG_UFS_SYS1CLK_1US, 16 * 4,
1423 "HCI Vendor Specific Registers ");
1424
1425 ufs_qcom_print_hw_debug_reg_all(hba, NULL, ufs_qcom_dump_regs_wrapper);
1426 }
1427
1428 /**
1429 * ufs_qcom_device_reset() - toggle the (optional) device reset line
1430 * @hba: per-adapter instance
1431 *
1432 * Toggles the (optional) reset line to reset the attached device.
1433 */
ufs_qcom_device_reset(struct ufs_hba * hba)1434 static int ufs_qcom_device_reset(struct ufs_hba *hba)
1435 {
1436 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1437
1438 /* reset gpio is optional */
1439 if (!host->device_reset)
1440 return -EOPNOTSUPP;
1441
1442 /*
1443 * The UFS device shall detect reset pulses of 1us, sleep for 10us to
1444 * be on the safe side.
1445 */
1446 gpiod_set_value_cansleep(host->device_reset, 1);
1447 usleep_range(10, 15);
1448
1449 gpiod_set_value_cansleep(host->device_reset, 0);
1450 usleep_range(10, 15);
1451
1452 return 0;
1453 }
1454
1455 #if IS_ENABLED(CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND)
ufs_qcom_config_scaling_param(struct ufs_hba * hba,struct devfreq_dev_profile * p,void * data)1456 static void ufs_qcom_config_scaling_param(struct ufs_hba *hba,
1457 struct devfreq_dev_profile *p,
1458 void *data)
1459 {
1460 static struct devfreq_simple_ondemand_data *d;
1461
1462 if (!data)
1463 return;
1464
1465 d = (struct devfreq_simple_ondemand_data *)data;
1466 p->polling_ms = 60;
1467 d->upthreshold = 70;
1468 d->downdifferential = 5;
1469 }
1470 #else
ufs_qcom_config_scaling_param(struct ufs_hba * hba,struct devfreq_dev_profile * p,void * data)1471 static void ufs_qcom_config_scaling_param(struct ufs_hba *hba,
1472 struct devfreq_dev_profile *p,
1473 void *data)
1474 {
1475 }
1476 #endif
1477
1478 /*
1479 * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations
1480 *
1481 * The variant operations configure the necessary controller and PHY
1482 * handshake during initialization.
1483 */
1484 static const struct ufs_hba_variant_ops ufs_hba_qcom_vops = {
1485 .name = "qcom",
1486 .init = ufs_qcom_init,
1487 .exit = ufs_qcom_exit,
1488 .get_ufs_hci_version = ufs_qcom_get_ufs_hci_version,
1489 .clk_scale_notify = ufs_qcom_clk_scale_notify,
1490 .setup_clocks = ufs_qcom_setup_clocks,
1491 .hce_enable_notify = ufs_qcom_hce_enable_notify,
1492 .link_startup_notify = ufs_qcom_link_startup_notify,
1493 .pwr_change_notify = ufs_qcom_pwr_change_notify,
1494 .apply_dev_quirks = ufs_qcom_apply_dev_quirks,
1495 .suspend = ufs_qcom_suspend,
1496 .resume = ufs_qcom_resume,
1497 .dbg_register_dump = ufs_qcom_dump_dbg_regs,
1498 .device_reset = ufs_qcom_device_reset,
1499 .config_scaling_param = ufs_qcom_config_scaling_param,
1500 .program_key = ufs_qcom_ice_program_key,
1501 };
1502
1503 /**
1504 * ufs_qcom_probe - probe routine of the driver
1505 * @pdev: pointer to Platform device handle
1506 *
1507 * Return zero for success and non-zero for failure
1508 */
ufs_qcom_probe(struct platform_device * pdev)1509 static int ufs_qcom_probe(struct platform_device *pdev)
1510 {
1511 int err;
1512 struct device *dev = &pdev->dev;
1513
1514 /* Perform generic probe */
1515 err = ufshcd_pltfrm_init(pdev, &ufs_hba_qcom_vops);
1516 if (err)
1517 dev_err(dev, "ufshcd_pltfrm_init() failed %d\n", err);
1518
1519 return err;
1520 }
1521
1522 /**
1523 * ufs_qcom_remove - set driver_data of the device to NULL
1524 * @pdev: pointer to platform device handle
1525 *
1526 * Always returns 0
1527 */
ufs_qcom_remove(struct platform_device * pdev)1528 static int ufs_qcom_remove(struct platform_device *pdev)
1529 {
1530 struct ufs_hba *hba = platform_get_drvdata(pdev);
1531
1532 pm_runtime_get_sync(&(pdev)->dev);
1533 ufshcd_remove(hba);
1534 return 0;
1535 }
1536
1537 static const struct of_device_id ufs_qcom_of_match[] = {
1538 { .compatible = "qcom,ufshc"},
1539 {},
1540 };
1541 MODULE_DEVICE_TABLE(of, ufs_qcom_of_match);
1542
1543 #ifdef CONFIG_ACPI
1544 static const struct acpi_device_id ufs_qcom_acpi_match[] = {
1545 { "QCOM24A5" },
1546 { },
1547 };
1548 MODULE_DEVICE_TABLE(acpi, ufs_qcom_acpi_match);
1549 #endif
1550
1551 static const struct dev_pm_ops ufs_qcom_pm_ops = {
1552 .suspend = ufshcd_pltfrm_suspend,
1553 .resume = ufshcd_pltfrm_resume,
1554 .runtime_suspend = ufshcd_pltfrm_runtime_suspend,
1555 .runtime_resume = ufshcd_pltfrm_runtime_resume,
1556 .runtime_idle = ufshcd_pltfrm_runtime_idle,
1557 };
1558
1559 static struct platform_driver ufs_qcom_pltform = {
1560 .probe = ufs_qcom_probe,
1561 .remove = ufs_qcom_remove,
1562 .shutdown = ufshcd_pltfrm_shutdown,
1563 .driver = {
1564 .name = "ufshcd-qcom",
1565 .pm = &ufs_qcom_pm_ops,
1566 .of_match_table = of_match_ptr(ufs_qcom_of_match),
1567 .acpi_match_table = ACPI_PTR(ufs_qcom_acpi_match),
1568 },
1569 };
1570 module_platform_driver(ufs_qcom_pltform);
1571
1572 MODULE_LICENSE("GPL v2");
1573