1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Probe module for 8250/16550-type PCI serial ports.
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Copyright (C) 2001 Russell King, All Rights Reserved.
8 */
9 #undef DEBUG
10 #include <linux/module.h>
11 #include <linux/pci.h>
12 #include <linux/string.h>
13 #include <linux/kernel.h>
14 #include <linux/slab.h>
15 #include <linux/delay.h>
16 #include <linux/tty.h>
17 #include <linux/serial_reg.h>
18 #include <linux/serial_core.h>
19 #include <linux/8250_pci.h>
20 #include <linux/bitops.h>
21
22 #include <asm/byteorder.h>
23 #include <asm/io.h>
24
25 #include "8250.h"
26
27 /*
28 * init function returns:
29 * > 0 - number of ports
30 * = 0 - use board->num_ports
31 * < 0 - error
32 */
33 struct pci_serial_quirk {
34 u32 vendor;
35 u32 device;
36 u32 subvendor;
37 u32 subdevice;
38 int (*probe)(struct pci_dev *dev);
39 int (*init)(struct pci_dev *dev);
40 int (*setup)(struct serial_private *,
41 const struct pciserial_board *,
42 struct uart_8250_port *, int);
43 void (*exit)(struct pci_dev *dev);
44 };
45
46 struct f815xxa_data {
47 spinlock_t lock;
48 int idx;
49 };
50
51 struct serial_private {
52 struct pci_dev *dev;
53 unsigned int nr;
54 struct pci_serial_quirk *quirk;
55 const struct pciserial_board *board;
56 int line[];
57 };
58
59 #define PCI_DEVICE_ID_HPE_PCI_SERIAL 0x37e
60
61 static const struct pci_device_id pci_use_msi[] = {
62 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
63 0xA000, 0x1000) },
64 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
65 0xA000, 0x1000) },
66 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
67 0xA000, 0x1000) },
68 { PCI_DEVICE_SUB(PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL,
69 PCI_ANY_ID, PCI_ANY_ID) },
70 { }
71 };
72
73 static int pci_default_setup(struct serial_private*,
74 const struct pciserial_board*, struct uart_8250_port *, int);
75
moan_device(const char * str,struct pci_dev * dev)76 static void moan_device(const char *str, struct pci_dev *dev)
77 {
78 dev_err(&dev->dev,
79 "%s: %s\n"
80 "Please send the output of lspci -vv, this\n"
81 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
82 "manufacturer and name of serial board or\n"
83 "modem board to <linux-serial@vger.kernel.org>.\n",
84 pci_name(dev), str, dev->vendor, dev->device,
85 dev->subsystem_vendor, dev->subsystem_device);
86 }
87
88 static int
setup_port(struct serial_private * priv,struct uart_8250_port * port,u8 bar,unsigned int offset,int regshift)89 setup_port(struct serial_private *priv, struct uart_8250_port *port,
90 u8 bar, unsigned int offset, int regshift)
91 {
92 struct pci_dev *dev = priv->dev;
93
94 if (bar >= PCI_STD_NUM_BARS)
95 return -EINVAL;
96
97 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
98 if (!pcim_iomap(dev, bar, 0) && !pcim_iomap_table(dev))
99 return -ENOMEM;
100
101 port->port.iotype = UPIO_MEM;
102 port->port.iobase = 0;
103 port->port.mapbase = pci_resource_start(dev, bar) + offset;
104 port->port.membase = pcim_iomap_table(dev)[bar] + offset;
105 port->port.regshift = regshift;
106 } else {
107 port->port.iotype = UPIO_PORT;
108 port->port.iobase = pci_resource_start(dev, bar) + offset;
109 port->port.mapbase = 0;
110 port->port.membase = NULL;
111 port->port.regshift = 0;
112 }
113 return 0;
114 }
115
116 /*
117 * ADDI-DATA GmbH communication cards <info@addi-data.com>
118 */
addidata_apci7800_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)119 static int addidata_apci7800_setup(struct serial_private *priv,
120 const struct pciserial_board *board,
121 struct uart_8250_port *port, int idx)
122 {
123 unsigned int bar = 0, offset = board->first_offset;
124 bar = FL_GET_BASE(board->flags);
125
126 if (idx < 2) {
127 offset += idx * board->uart_offset;
128 } else if ((idx >= 2) && (idx < 4)) {
129 bar += 1;
130 offset += ((idx - 2) * board->uart_offset);
131 } else if ((idx >= 4) && (idx < 6)) {
132 bar += 2;
133 offset += ((idx - 4) * board->uart_offset);
134 } else if (idx >= 6) {
135 bar += 3;
136 offset += ((idx - 6) * board->uart_offset);
137 }
138
139 return setup_port(priv, port, bar, offset, board->reg_shift);
140 }
141
142 /*
143 * AFAVLAB uses a different mixture of BARs and offsets
144 * Not that ugly ;) -- HW
145 */
146 static int
afavlab_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)147 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
148 struct uart_8250_port *port, int idx)
149 {
150 unsigned int bar, offset = board->first_offset;
151
152 bar = FL_GET_BASE(board->flags);
153 if (idx < 4)
154 bar += idx;
155 else {
156 bar = 4;
157 offset += (idx - 4) * board->uart_offset;
158 }
159
160 return setup_port(priv, port, bar, offset, board->reg_shift);
161 }
162
163 /*
164 * HP's Remote Management Console. The Diva chip came in several
165 * different versions. N-class, L2000 and A500 have two Diva chips, each
166 * with 3 UARTs (the third UART on the second chip is unused). Superdome
167 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
168 * one Diva chip, but it has been expanded to 5 UARTs.
169 */
pci_hp_diva_init(struct pci_dev * dev)170 static int pci_hp_diva_init(struct pci_dev *dev)
171 {
172 int rc = 0;
173
174 switch (dev->subsystem_device) {
175 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
176 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
177 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
178 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
179 rc = 3;
180 break;
181 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
182 rc = 2;
183 break;
184 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
185 rc = 4;
186 break;
187 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
188 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
189 rc = 1;
190 break;
191 }
192
193 return rc;
194 }
195
196 /*
197 * HP's Diva chip puts the 4th/5th serial port further out, and
198 * some serial ports are supposed to be hidden on certain models.
199 */
200 static int
pci_hp_diva_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)201 pci_hp_diva_setup(struct serial_private *priv,
202 const struct pciserial_board *board,
203 struct uart_8250_port *port, int idx)
204 {
205 unsigned int offset = board->first_offset;
206 unsigned int bar = FL_GET_BASE(board->flags);
207
208 switch (priv->dev->subsystem_device) {
209 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
210 if (idx == 3)
211 idx++;
212 break;
213 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
214 if (idx > 0)
215 idx++;
216 if (idx > 2)
217 idx++;
218 break;
219 }
220 if (idx > 2)
221 offset = 0x18;
222
223 offset += idx * board->uart_offset;
224
225 return setup_port(priv, port, bar, offset, board->reg_shift);
226 }
227
228 /*
229 * Added for EKF Intel i960 serial boards
230 */
pci_inteli960ni_init(struct pci_dev * dev)231 static int pci_inteli960ni_init(struct pci_dev *dev)
232 {
233 u32 oldval;
234
235 if (!(dev->subsystem_device & 0x1000))
236 return -ENODEV;
237
238 /* is firmware started? */
239 pci_read_config_dword(dev, 0x44, &oldval);
240 if (oldval == 0x00001000L) { /* RESET value */
241 dev_dbg(&dev->dev, "Local i960 firmware missing\n");
242 return -ENODEV;
243 }
244 return 0;
245 }
246
247 /*
248 * Some PCI serial cards using the PLX 9050 PCI interface chip require
249 * that the card interrupt be explicitly enabled or disabled. This
250 * seems to be mainly needed on card using the PLX which also use I/O
251 * mapped memory.
252 */
pci_plx9050_init(struct pci_dev * dev)253 static int pci_plx9050_init(struct pci_dev *dev)
254 {
255 u8 irq_config;
256 void __iomem *p;
257
258 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
259 moan_device("no memory in bar 0", dev);
260 return 0;
261 }
262
263 irq_config = 0x41;
264 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
265 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
266 irq_config = 0x43;
267
268 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
269 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
270 /*
271 * As the megawolf cards have the int pins active
272 * high, and have 2 UART chips, both ints must be
273 * enabled on the 9050. Also, the UARTS are set in
274 * 16450 mode by default, so we have to enable the
275 * 16C950 'enhanced' mode so that we can use the
276 * deep FIFOs
277 */
278 irq_config = 0x5b;
279 /*
280 * enable/disable interrupts
281 */
282 p = ioremap(pci_resource_start(dev, 0), 0x80);
283 if (p == NULL)
284 return -ENOMEM;
285 writel(irq_config, p + 0x4c);
286
287 /*
288 * Read the register back to ensure that it took effect.
289 */
290 readl(p + 0x4c);
291 iounmap(p);
292
293 return 0;
294 }
295
pci_plx9050_exit(struct pci_dev * dev)296 static void pci_plx9050_exit(struct pci_dev *dev)
297 {
298 u8 __iomem *p;
299
300 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
301 return;
302
303 /*
304 * disable interrupts
305 */
306 p = ioremap(pci_resource_start(dev, 0), 0x80);
307 if (p != NULL) {
308 writel(0, p + 0x4c);
309
310 /*
311 * Read the register back to ensure that it took effect.
312 */
313 readl(p + 0x4c);
314 iounmap(p);
315 }
316 }
317
318 #define NI8420_INT_ENABLE_REG 0x38
319 #define NI8420_INT_ENABLE_BIT 0x2000
320
pci_ni8420_exit(struct pci_dev * dev)321 static void pci_ni8420_exit(struct pci_dev *dev)
322 {
323 void __iomem *p;
324 unsigned int bar = 0;
325
326 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
327 moan_device("no memory in bar", dev);
328 return;
329 }
330
331 p = pci_ioremap_bar(dev, bar);
332 if (p == NULL)
333 return;
334
335 /* Disable the CPU Interrupt */
336 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
337 p + NI8420_INT_ENABLE_REG);
338 iounmap(p);
339 }
340
341
342 /* MITE registers */
343 #define MITE_IOWBSR1 0xc4
344 #define MITE_IOWCR1 0xf4
345 #define MITE_LCIMR1 0x08
346 #define MITE_LCIMR2 0x10
347
348 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
349
pci_ni8430_exit(struct pci_dev * dev)350 static void pci_ni8430_exit(struct pci_dev *dev)
351 {
352 void __iomem *p;
353 unsigned int bar = 0;
354
355 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
356 moan_device("no memory in bar", dev);
357 return;
358 }
359
360 p = pci_ioremap_bar(dev, bar);
361 if (p == NULL)
362 return;
363
364 /* Disable the CPU Interrupt */
365 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
366 iounmap(p);
367 }
368
369 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
370 static int
sbs_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)371 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
372 struct uart_8250_port *port, int idx)
373 {
374 unsigned int bar, offset = board->first_offset;
375
376 bar = 0;
377
378 if (idx < 4) {
379 /* first four channels map to 0, 0x100, 0x200, 0x300 */
380 offset += idx * board->uart_offset;
381 } else if (idx < 8) {
382 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
383 offset += idx * board->uart_offset + 0xC00;
384 } else /* we have only 8 ports on PMC-OCTALPRO */
385 return 1;
386
387 return setup_port(priv, port, bar, offset, board->reg_shift);
388 }
389
390 /*
391 * This does initialization for PMC OCTALPRO cards:
392 * maps the device memory, resets the UARTs (needed, bc
393 * if the module is removed and inserted again, the card
394 * is in the sleep mode) and enables global interrupt.
395 */
396
397 /* global control register offset for SBS PMC-OctalPro */
398 #define OCT_REG_CR_OFF 0x500
399
sbs_init(struct pci_dev * dev)400 static int sbs_init(struct pci_dev *dev)
401 {
402 u8 __iomem *p;
403
404 p = pci_ioremap_bar(dev, 0);
405
406 if (p == NULL)
407 return -ENOMEM;
408 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
409 writeb(0x10, p + OCT_REG_CR_OFF);
410 udelay(50);
411 writeb(0x0, p + OCT_REG_CR_OFF);
412
413 /* Set bit-2 (INTENABLE) of Control Register */
414 writeb(0x4, p + OCT_REG_CR_OFF);
415 iounmap(p);
416
417 return 0;
418 }
419
420 /*
421 * Disables the global interrupt of PMC-OctalPro
422 */
423
sbs_exit(struct pci_dev * dev)424 static void sbs_exit(struct pci_dev *dev)
425 {
426 u8 __iomem *p;
427
428 p = pci_ioremap_bar(dev, 0);
429 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
430 if (p != NULL)
431 writeb(0, p + OCT_REG_CR_OFF);
432 iounmap(p);
433 }
434
435 /*
436 * SIIG serial cards have an PCI interface chip which also controls
437 * the UART clocking frequency. Each UART can be clocked independently
438 * (except cards equipped with 4 UARTs) and initial clocking settings
439 * are stored in the EEPROM chip. It can cause problems because this
440 * version of serial driver doesn't support differently clocked UART's
441 * on single PCI card. To prevent this, initialization functions set
442 * high frequency clocking for all UART's on given card. It is safe (I
443 * hope) because it doesn't touch EEPROM settings to prevent conflicts
444 * with other OSes (like M$ DOS).
445 *
446 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
447 *
448 * There is two family of SIIG serial cards with different PCI
449 * interface chip and different configuration methods:
450 * - 10x cards have control registers in IO and/or memory space;
451 * - 20x cards have control registers in standard PCI configuration space.
452 *
453 * Note: all 10x cards have PCI device ids 0x10..
454 * all 20x cards have PCI device ids 0x20..
455 *
456 * There are also Quartet Serial cards which use Oxford Semiconductor
457 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
458 *
459 * Note: some SIIG cards are probed by the parport_serial object.
460 */
461
462 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
463 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
464
pci_siig10x_init(struct pci_dev * dev)465 static int pci_siig10x_init(struct pci_dev *dev)
466 {
467 u16 data;
468 void __iomem *p;
469
470 switch (dev->device & 0xfff8) {
471 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
472 data = 0xffdf;
473 break;
474 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
475 data = 0xf7ff;
476 break;
477 default: /* 1S1P, 4S */
478 data = 0xfffb;
479 break;
480 }
481
482 p = ioremap(pci_resource_start(dev, 0), 0x80);
483 if (p == NULL)
484 return -ENOMEM;
485
486 writew(readw(p + 0x28) & data, p + 0x28);
487 readw(p + 0x28);
488 iounmap(p);
489 return 0;
490 }
491
492 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
493 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
494
pci_siig20x_init(struct pci_dev * dev)495 static int pci_siig20x_init(struct pci_dev *dev)
496 {
497 u8 data;
498
499 /* Change clock frequency for the first UART. */
500 pci_read_config_byte(dev, 0x6f, &data);
501 pci_write_config_byte(dev, 0x6f, data & 0xef);
502
503 /* If this card has 2 UART, we have to do the same with second UART. */
504 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
505 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
506 pci_read_config_byte(dev, 0x73, &data);
507 pci_write_config_byte(dev, 0x73, data & 0xef);
508 }
509 return 0;
510 }
511
pci_siig_init(struct pci_dev * dev)512 static int pci_siig_init(struct pci_dev *dev)
513 {
514 unsigned int type = dev->device & 0xff00;
515
516 if (type == 0x1000)
517 return pci_siig10x_init(dev);
518 else if (type == 0x2000)
519 return pci_siig20x_init(dev);
520
521 moan_device("Unknown SIIG card", dev);
522 return -ENODEV;
523 }
524
pci_siig_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)525 static int pci_siig_setup(struct serial_private *priv,
526 const struct pciserial_board *board,
527 struct uart_8250_port *port, int idx)
528 {
529 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
530
531 if (idx > 3) {
532 bar = 4;
533 offset = (idx - 4) * 8;
534 }
535
536 return setup_port(priv, port, bar, offset, 0);
537 }
538
539 /*
540 * Timedia has an explosion of boards, and to avoid the PCI table from
541 * growing *huge*, we use this function to collapse some 70 entries
542 * in the PCI table into one, for sanity's and compactness's sake.
543 */
544 static const unsigned short timedia_single_port[] = {
545 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
546 };
547
548 static const unsigned short timedia_dual_port[] = {
549 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
550 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
551 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
552 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
553 0xD079, 0
554 };
555
556 static const unsigned short timedia_quad_port[] = {
557 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
558 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
559 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
560 0xB157, 0
561 };
562
563 static const unsigned short timedia_eight_port[] = {
564 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
565 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
566 };
567
568 static const struct timedia_struct {
569 int num;
570 const unsigned short *ids;
571 } timedia_data[] = {
572 { 1, timedia_single_port },
573 { 2, timedia_dual_port },
574 { 4, timedia_quad_port },
575 { 8, timedia_eight_port }
576 };
577
578 /*
579 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
580 * listing them individually, this driver merely grabs them all with
581 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
582 * and should be left free to be claimed by parport_serial instead.
583 */
pci_timedia_probe(struct pci_dev * dev)584 static int pci_timedia_probe(struct pci_dev *dev)
585 {
586 /*
587 * Check the third digit of the subdevice ID
588 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
589 */
590 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
591 dev_info(&dev->dev,
592 "ignoring Timedia subdevice %04x for parport_serial\n",
593 dev->subsystem_device);
594 return -ENODEV;
595 }
596
597 return 0;
598 }
599
pci_timedia_init(struct pci_dev * dev)600 static int pci_timedia_init(struct pci_dev *dev)
601 {
602 const unsigned short *ids;
603 int i, j;
604
605 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
606 ids = timedia_data[i].ids;
607 for (j = 0; ids[j]; j++)
608 if (dev->subsystem_device == ids[j])
609 return timedia_data[i].num;
610 }
611 return 0;
612 }
613
614 /*
615 * Timedia/SUNIX uses a mixture of BARs and offsets
616 * Ugh, this is ugly as all hell --- TYT
617 */
618 static int
pci_timedia_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)619 pci_timedia_setup(struct serial_private *priv,
620 const struct pciserial_board *board,
621 struct uart_8250_port *port, int idx)
622 {
623 unsigned int bar = 0, offset = board->first_offset;
624
625 switch (idx) {
626 case 0:
627 bar = 0;
628 break;
629 case 1:
630 offset = board->uart_offset;
631 bar = 0;
632 break;
633 case 2:
634 bar = 1;
635 break;
636 case 3:
637 offset = board->uart_offset;
638 fallthrough;
639 case 4: /* BAR 2 */
640 case 5: /* BAR 3 */
641 case 6: /* BAR 4 */
642 case 7: /* BAR 5 */
643 bar = idx - 2;
644 }
645
646 return setup_port(priv, port, bar, offset, board->reg_shift);
647 }
648
649 /*
650 * Some Titan cards are also a little weird
651 */
652 static int
titan_400l_800l_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)653 titan_400l_800l_setup(struct serial_private *priv,
654 const struct pciserial_board *board,
655 struct uart_8250_port *port, int idx)
656 {
657 unsigned int bar, offset = board->first_offset;
658
659 switch (idx) {
660 case 0:
661 bar = 1;
662 break;
663 case 1:
664 bar = 2;
665 break;
666 default:
667 bar = 4;
668 offset = (idx - 2) * board->uart_offset;
669 }
670
671 return setup_port(priv, port, bar, offset, board->reg_shift);
672 }
673
pci_xircom_init(struct pci_dev * dev)674 static int pci_xircom_init(struct pci_dev *dev)
675 {
676 msleep(100);
677 return 0;
678 }
679
pci_ni8420_init(struct pci_dev * dev)680 static int pci_ni8420_init(struct pci_dev *dev)
681 {
682 void __iomem *p;
683 unsigned int bar = 0;
684
685 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
686 moan_device("no memory in bar", dev);
687 return 0;
688 }
689
690 p = pci_ioremap_bar(dev, bar);
691 if (p == NULL)
692 return -ENOMEM;
693
694 /* Enable CPU Interrupt */
695 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
696 p + NI8420_INT_ENABLE_REG);
697
698 iounmap(p);
699 return 0;
700 }
701
702 #define MITE_IOWBSR1_WSIZE 0xa
703 #define MITE_IOWBSR1_WIN_OFFSET 0x800
704 #define MITE_IOWBSR1_WENAB (1 << 7)
705 #define MITE_LCIMR1_IO_IE_0 (1 << 24)
706 #define MITE_LCIMR2_SET_CPU_IE (1 << 31)
707 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
708
pci_ni8430_init(struct pci_dev * dev)709 static int pci_ni8430_init(struct pci_dev *dev)
710 {
711 void __iomem *p;
712 struct pci_bus_region region;
713 u32 device_window;
714 unsigned int bar = 0;
715
716 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
717 moan_device("no memory in bar", dev);
718 return 0;
719 }
720
721 p = pci_ioremap_bar(dev, bar);
722 if (p == NULL)
723 return -ENOMEM;
724
725 /*
726 * Set device window address and size in BAR0, while acknowledging that
727 * the resource structure may contain a translated address that differs
728 * from the address the device responds to.
729 */
730 pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]);
731 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
732 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
733 writel(device_window, p + MITE_IOWBSR1);
734
735 /* Set window access to go to RAMSEL IO address space */
736 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
737 p + MITE_IOWCR1);
738
739 /* Enable IO Bus Interrupt 0 */
740 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
741
742 /* Enable CPU Interrupt */
743 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
744
745 iounmap(p);
746 return 0;
747 }
748
749 /* UART Port Control Register */
750 #define NI8430_PORTCON 0x0f
751 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
752
753 static int
pci_ni8430_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)754 pci_ni8430_setup(struct serial_private *priv,
755 const struct pciserial_board *board,
756 struct uart_8250_port *port, int idx)
757 {
758 struct pci_dev *dev = priv->dev;
759 void __iomem *p;
760 unsigned int bar, offset = board->first_offset;
761
762 if (idx >= board->num_ports)
763 return 1;
764
765 bar = FL_GET_BASE(board->flags);
766 offset += idx * board->uart_offset;
767
768 p = pci_ioremap_bar(dev, bar);
769 if (!p)
770 return -ENOMEM;
771
772 /* enable the transceiver */
773 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
774 p + offset + NI8430_PORTCON);
775
776 iounmap(p);
777
778 return setup_port(priv, port, bar, offset, board->reg_shift);
779 }
780
pci_netmos_9900_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)781 static int pci_netmos_9900_setup(struct serial_private *priv,
782 const struct pciserial_board *board,
783 struct uart_8250_port *port, int idx)
784 {
785 unsigned int bar;
786
787 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
788 (priv->dev->subsystem_device & 0xff00) == 0x3000) {
789 /* netmos apparently orders BARs by datasheet layout, so serial
790 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
791 */
792 bar = 3 * idx;
793
794 return setup_port(priv, port, bar, 0, board->reg_shift);
795 } else {
796 return pci_default_setup(priv, board, port, idx);
797 }
798 }
799
800 /* the 99xx series comes with a range of device IDs and a variety
801 * of capabilities:
802 *
803 * 9900 has varying capabilities and can cascade to sub-controllers
804 * (cascading should be purely internal)
805 * 9904 is hardwired with 4 serial ports
806 * 9912 and 9922 are hardwired with 2 serial ports
807 */
pci_netmos_9900_numports(struct pci_dev * dev)808 static int pci_netmos_9900_numports(struct pci_dev *dev)
809 {
810 unsigned int c = dev->class;
811 unsigned int pi;
812 unsigned short sub_serports;
813
814 pi = c & 0xff;
815
816 if (pi == 2)
817 return 1;
818
819 if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
820 /* two possibilities: 0x30ps encodes number of parallel and
821 * serial ports, or 0x1000 indicates *something*. This is not
822 * immediately obvious, since the 2s1p+4s configuration seems
823 * to offer all functionality on functions 0..2, while still
824 * advertising the same function 3 as the 4s+2s1p config.
825 */
826 sub_serports = dev->subsystem_device & 0xf;
827 if (sub_serports > 0)
828 return sub_serports;
829
830 dev_err(&dev->dev,
831 "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
832 return 0;
833 }
834
835 moan_device("unknown NetMos/Mostech program interface", dev);
836 return 0;
837 }
838
pci_netmos_init(struct pci_dev * dev)839 static int pci_netmos_init(struct pci_dev *dev)
840 {
841 /* subdevice 0x00PS means <P> parallel, <S> serial */
842 unsigned int num_serial = dev->subsystem_device & 0xf;
843
844 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
845 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
846 return 0;
847
848 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
849 dev->subsystem_device == 0x0299)
850 return 0;
851
852 switch (dev->device) { /* FALLTHROUGH on all */
853 case PCI_DEVICE_ID_NETMOS_9904:
854 case PCI_DEVICE_ID_NETMOS_9912:
855 case PCI_DEVICE_ID_NETMOS_9922:
856 case PCI_DEVICE_ID_NETMOS_9900:
857 num_serial = pci_netmos_9900_numports(dev);
858 break;
859
860 default:
861 break;
862 }
863
864 if (num_serial == 0) {
865 moan_device("unknown NetMos/Mostech device", dev);
866 return -ENODEV;
867 }
868
869 return num_serial;
870 }
871
872 /*
873 * These chips are available with optionally one parallel port and up to
874 * two serial ports. Unfortunately they all have the same product id.
875 *
876 * Basic configuration is done over a region of 32 I/O ports. The base
877 * ioport is called INTA or INTC, depending on docs/other drivers.
878 *
879 * The region of the 32 I/O ports is configured in POSIO0R...
880 */
881
882 /* registers */
883 #define ITE_887x_MISCR 0x9c
884 #define ITE_887x_INTCBAR 0x78
885 #define ITE_887x_UARTBAR 0x7c
886 #define ITE_887x_PS0BAR 0x10
887 #define ITE_887x_POSIO0 0x60
888
889 /* I/O space size */
890 #define ITE_887x_IOSIZE 32
891 /* I/O space size (bits 26-24; 8 bytes = 011b) */
892 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
893 /* I/O space size (bits 26-24; 32 bytes = 101b) */
894 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
895 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
896 #define ITE_887x_POSIO_SPEED (3 << 29)
897 /* enable IO_Space bit */
898 #define ITE_887x_POSIO_ENABLE (1 << 31)
899
pci_ite887x_init(struct pci_dev * dev)900 static int pci_ite887x_init(struct pci_dev *dev)
901 {
902 /* inta_addr are the configuration addresses of the ITE */
903 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
904 0x200, 0x280, 0 };
905 int ret, i, type;
906 struct resource *iobase = NULL;
907 u32 miscr, uartbar, ioport;
908
909 /* search for the base-ioport */
910 i = 0;
911 while (inta_addr[i] && iobase == NULL) {
912 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
913 "ite887x");
914 if (iobase != NULL) {
915 /* write POSIO0R - speed | size | ioport */
916 pci_write_config_dword(dev, ITE_887x_POSIO0,
917 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
918 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
919 /* write INTCBAR - ioport */
920 pci_write_config_dword(dev, ITE_887x_INTCBAR,
921 inta_addr[i]);
922 ret = inb(inta_addr[i]);
923 if (ret != 0xff) {
924 /* ioport connected */
925 break;
926 }
927 release_region(iobase->start, ITE_887x_IOSIZE);
928 iobase = NULL;
929 }
930 i++;
931 }
932
933 if (!inta_addr[i]) {
934 dev_err(&dev->dev, "ite887x: could not find iobase\n");
935 return -ENODEV;
936 }
937
938 /* start of undocumented type checking (see parport_pc.c) */
939 type = inb(iobase->start + 0x18) & 0x0f;
940
941 switch (type) {
942 case 0x2: /* ITE8871 (1P) */
943 case 0xa: /* ITE8875 (1P) */
944 ret = 0;
945 break;
946 case 0xe: /* ITE8872 (2S1P) */
947 ret = 2;
948 break;
949 case 0x6: /* ITE8873 (1S) */
950 ret = 1;
951 break;
952 case 0x8: /* ITE8874 (2S) */
953 ret = 2;
954 break;
955 default:
956 moan_device("Unknown ITE887x", dev);
957 ret = -ENODEV;
958 }
959
960 /* configure all serial ports */
961 for (i = 0; i < ret; i++) {
962 /* read the I/O port from the device */
963 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
964 &ioport);
965 ioport &= 0x0000FF00; /* the actual base address */
966 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
967 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
968 ITE_887x_POSIO_IOSIZE_8 | ioport);
969
970 /* write the ioport to the UARTBAR */
971 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
972 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
973 uartbar |= (ioport << (16 * i)); /* set the ioport */
974 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
975
976 /* get current config */
977 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
978 /* disable interrupts (UARTx_Routing[3:0]) */
979 miscr &= ~(0xf << (12 - 4 * i));
980 /* activate the UART (UARTx_En) */
981 miscr |= 1 << (23 - i);
982 /* write new config with activated UART */
983 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
984 }
985
986 if (ret <= 0) {
987 /* the device has no UARTs if we get here */
988 release_region(iobase->start, ITE_887x_IOSIZE);
989 }
990
991 return ret;
992 }
993
pci_ite887x_exit(struct pci_dev * dev)994 static void pci_ite887x_exit(struct pci_dev *dev)
995 {
996 u32 ioport;
997 /* the ioport is bit 0-15 in POSIO0R */
998 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
999 ioport &= 0xffff;
1000 release_region(ioport, ITE_887x_IOSIZE);
1001 }
1002
1003 /*
1004 * EndRun Technologies.
1005 * Determine the number of ports available on the device.
1006 */
1007 #define PCI_VENDOR_ID_ENDRUN 0x7401
1008 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100
1009
pci_endrun_init(struct pci_dev * dev)1010 static int pci_endrun_init(struct pci_dev *dev)
1011 {
1012 u8 __iomem *p;
1013 unsigned long deviceID;
1014 unsigned int number_uarts = 0;
1015
1016 /* EndRun device is all 0xexxx */
1017 if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
1018 (dev->device & 0xf000) != 0xe000)
1019 return 0;
1020
1021 p = pci_iomap(dev, 0, 5);
1022 if (p == NULL)
1023 return -ENOMEM;
1024
1025 deviceID = ioread32(p);
1026 /* EndRun device */
1027 if (deviceID == 0x07000200) {
1028 number_uarts = ioread8(p + 4);
1029 dev_dbg(&dev->dev,
1030 "%d ports detected on EndRun PCI Express device\n",
1031 number_uarts);
1032 }
1033 pci_iounmap(dev, p);
1034 return number_uarts;
1035 }
1036
1037 /*
1038 * Oxford Semiconductor Inc.
1039 * Check that device is part of the Tornado range of devices, then determine
1040 * the number of ports available on the device.
1041 */
pci_oxsemi_tornado_init(struct pci_dev * dev)1042 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1043 {
1044 u8 __iomem *p;
1045 unsigned long deviceID;
1046 unsigned int number_uarts = 0;
1047
1048 /* OxSemi Tornado devices are all 0xCxxx */
1049 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1050 (dev->device & 0xF000) != 0xC000)
1051 return 0;
1052
1053 p = pci_iomap(dev, 0, 5);
1054 if (p == NULL)
1055 return -ENOMEM;
1056
1057 deviceID = ioread32(p);
1058 /* Tornado device */
1059 if (deviceID == 0x07000200) {
1060 number_uarts = ioread8(p + 4);
1061 dev_dbg(&dev->dev,
1062 "%d ports detected on Oxford PCI Express device\n",
1063 number_uarts);
1064 }
1065 pci_iounmap(dev, p);
1066 return number_uarts;
1067 }
1068
pci_asix_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1069 static int pci_asix_setup(struct serial_private *priv,
1070 const struct pciserial_board *board,
1071 struct uart_8250_port *port, int idx)
1072 {
1073 port->bugs |= UART_BUG_PARITY;
1074 return pci_default_setup(priv, board, port, idx);
1075 }
1076
1077 /* Quatech devices have their own extra interface features */
1078
1079 struct quatech_feature {
1080 u16 devid;
1081 bool amcc;
1082 };
1083
1084 #define QPCR_TEST_FOR1 0x3F
1085 #define QPCR_TEST_GET1 0x00
1086 #define QPCR_TEST_FOR2 0x40
1087 #define QPCR_TEST_GET2 0x40
1088 #define QPCR_TEST_FOR3 0x80
1089 #define QPCR_TEST_GET3 0x40
1090 #define QPCR_TEST_FOR4 0xC0
1091 #define QPCR_TEST_GET4 0x80
1092
1093 #define QOPR_CLOCK_X1 0x0000
1094 #define QOPR_CLOCK_X2 0x0001
1095 #define QOPR_CLOCK_X4 0x0002
1096 #define QOPR_CLOCK_X8 0x0003
1097 #define QOPR_CLOCK_RATE_MASK 0x0003
1098
1099
1100 static struct quatech_feature quatech_cards[] = {
1101 { PCI_DEVICE_ID_QUATECH_QSC100, 1 },
1102 { PCI_DEVICE_ID_QUATECH_DSC100, 1 },
1103 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 },
1104 { PCI_DEVICE_ID_QUATECH_DSC200, 1 },
1105 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 },
1106 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 },
1107 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 },
1108 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 },
1109 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 },
1110 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 },
1111 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 },
1112 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1113 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1114 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1115 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1116 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1117 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1118 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1119 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1120 { 0, }
1121 };
1122
pci_quatech_amcc(u16 devid)1123 static int pci_quatech_amcc(u16 devid)
1124 {
1125 struct quatech_feature *qf = &quatech_cards[0];
1126 while (qf->devid) {
1127 if (qf->devid == devid)
1128 return qf->amcc;
1129 qf++;
1130 }
1131 pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1132 return 0;
1133 };
1134
pci_quatech_rqopr(struct uart_8250_port * port)1135 static int pci_quatech_rqopr(struct uart_8250_port *port)
1136 {
1137 unsigned long base = port->port.iobase;
1138 u8 LCR, val;
1139
1140 LCR = inb(base + UART_LCR);
1141 outb(0xBF, base + UART_LCR);
1142 val = inb(base + UART_SCR);
1143 outb(LCR, base + UART_LCR);
1144 return val;
1145 }
1146
pci_quatech_wqopr(struct uart_8250_port * port,u8 qopr)1147 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1148 {
1149 unsigned long base = port->port.iobase;
1150 u8 LCR;
1151
1152 LCR = inb(base + UART_LCR);
1153 outb(0xBF, base + UART_LCR);
1154 inb(base + UART_SCR);
1155 outb(qopr, base + UART_SCR);
1156 outb(LCR, base + UART_LCR);
1157 }
1158
pci_quatech_rqmcr(struct uart_8250_port * port)1159 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1160 {
1161 unsigned long base = port->port.iobase;
1162 u8 LCR, val, qmcr;
1163
1164 LCR = inb(base + UART_LCR);
1165 outb(0xBF, base + UART_LCR);
1166 val = inb(base + UART_SCR);
1167 outb(val | 0x10, base + UART_SCR);
1168 qmcr = inb(base + UART_MCR);
1169 outb(val, base + UART_SCR);
1170 outb(LCR, base + UART_LCR);
1171
1172 return qmcr;
1173 }
1174
pci_quatech_wqmcr(struct uart_8250_port * port,u8 qmcr)1175 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1176 {
1177 unsigned long base = port->port.iobase;
1178 u8 LCR, val;
1179
1180 LCR = inb(base + UART_LCR);
1181 outb(0xBF, base + UART_LCR);
1182 val = inb(base + UART_SCR);
1183 outb(val | 0x10, base + UART_SCR);
1184 outb(qmcr, base + UART_MCR);
1185 outb(val, base + UART_SCR);
1186 outb(LCR, base + UART_LCR);
1187 }
1188
pci_quatech_has_qmcr(struct uart_8250_port * port)1189 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1190 {
1191 unsigned long base = port->port.iobase;
1192 u8 LCR, val;
1193
1194 LCR = inb(base + UART_LCR);
1195 outb(0xBF, base + UART_LCR);
1196 val = inb(base + UART_SCR);
1197 if (val & 0x20) {
1198 outb(0x80, UART_LCR);
1199 if (!(inb(UART_SCR) & 0x20)) {
1200 outb(LCR, base + UART_LCR);
1201 return 1;
1202 }
1203 }
1204 return 0;
1205 }
1206
pci_quatech_test(struct uart_8250_port * port)1207 static int pci_quatech_test(struct uart_8250_port *port)
1208 {
1209 u8 reg, qopr;
1210
1211 qopr = pci_quatech_rqopr(port);
1212 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1213 reg = pci_quatech_rqopr(port) & 0xC0;
1214 if (reg != QPCR_TEST_GET1)
1215 return -EINVAL;
1216 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1217 reg = pci_quatech_rqopr(port) & 0xC0;
1218 if (reg != QPCR_TEST_GET2)
1219 return -EINVAL;
1220 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1221 reg = pci_quatech_rqopr(port) & 0xC0;
1222 if (reg != QPCR_TEST_GET3)
1223 return -EINVAL;
1224 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1225 reg = pci_quatech_rqopr(port) & 0xC0;
1226 if (reg != QPCR_TEST_GET4)
1227 return -EINVAL;
1228
1229 pci_quatech_wqopr(port, qopr);
1230 return 0;
1231 }
1232
pci_quatech_clock(struct uart_8250_port * port)1233 static int pci_quatech_clock(struct uart_8250_port *port)
1234 {
1235 u8 qopr, reg, set;
1236 unsigned long clock;
1237
1238 if (pci_quatech_test(port) < 0)
1239 return 1843200;
1240
1241 qopr = pci_quatech_rqopr(port);
1242
1243 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1244 reg = pci_quatech_rqopr(port);
1245 if (reg & QOPR_CLOCK_X8) {
1246 clock = 1843200;
1247 goto out;
1248 }
1249 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1250 reg = pci_quatech_rqopr(port);
1251 if (!(reg & QOPR_CLOCK_X8)) {
1252 clock = 1843200;
1253 goto out;
1254 }
1255 reg &= QOPR_CLOCK_X8;
1256 if (reg == QOPR_CLOCK_X2) {
1257 clock = 3685400;
1258 set = QOPR_CLOCK_X2;
1259 } else if (reg == QOPR_CLOCK_X4) {
1260 clock = 7372800;
1261 set = QOPR_CLOCK_X4;
1262 } else if (reg == QOPR_CLOCK_X8) {
1263 clock = 14745600;
1264 set = QOPR_CLOCK_X8;
1265 } else {
1266 clock = 1843200;
1267 set = QOPR_CLOCK_X1;
1268 }
1269 qopr &= ~QOPR_CLOCK_RATE_MASK;
1270 qopr |= set;
1271
1272 out:
1273 pci_quatech_wqopr(port, qopr);
1274 return clock;
1275 }
1276
pci_quatech_rs422(struct uart_8250_port * port)1277 static int pci_quatech_rs422(struct uart_8250_port *port)
1278 {
1279 u8 qmcr;
1280 int rs422 = 0;
1281
1282 if (!pci_quatech_has_qmcr(port))
1283 return 0;
1284 qmcr = pci_quatech_rqmcr(port);
1285 pci_quatech_wqmcr(port, 0xFF);
1286 if (pci_quatech_rqmcr(port))
1287 rs422 = 1;
1288 pci_quatech_wqmcr(port, qmcr);
1289 return rs422;
1290 }
1291
pci_quatech_init(struct pci_dev * dev)1292 static int pci_quatech_init(struct pci_dev *dev)
1293 {
1294 if (pci_quatech_amcc(dev->device)) {
1295 unsigned long base = pci_resource_start(dev, 0);
1296 if (base) {
1297 u32 tmp;
1298
1299 outl(inl(base + 0x38) | 0x00002000, base + 0x38);
1300 tmp = inl(base + 0x3c);
1301 outl(tmp | 0x01000000, base + 0x3c);
1302 outl(tmp &= ~0x01000000, base + 0x3c);
1303 }
1304 }
1305 return 0;
1306 }
1307
pci_quatech_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1308 static int pci_quatech_setup(struct serial_private *priv,
1309 const struct pciserial_board *board,
1310 struct uart_8250_port *port, int idx)
1311 {
1312 /* Needed by pci_quatech calls below */
1313 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1314 /* Set up the clocking */
1315 port->port.uartclk = pci_quatech_clock(port);
1316 /* For now just warn about RS422 */
1317 if (pci_quatech_rs422(port))
1318 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1319 return pci_default_setup(priv, board, port, idx);
1320 }
1321
pci_quatech_exit(struct pci_dev * dev)1322 static void pci_quatech_exit(struct pci_dev *dev)
1323 {
1324 }
1325
pci_default_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1326 static int pci_default_setup(struct serial_private *priv,
1327 const struct pciserial_board *board,
1328 struct uart_8250_port *port, int idx)
1329 {
1330 unsigned int bar, offset = board->first_offset, maxnr;
1331
1332 bar = FL_GET_BASE(board->flags);
1333 if (board->flags & FL_BASE_BARS)
1334 bar += idx;
1335 else
1336 offset += idx * board->uart_offset;
1337
1338 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1339 (board->reg_shift + 3);
1340
1341 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1342 return 1;
1343
1344 return setup_port(priv, port, bar, offset, board->reg_shift);
1345 }
1346 static void
pericom_do_set_divisor(struct uart_port * port,unsigned int baud,unsigned int quot,unsigned int quot_frac)1347 pericom_do_set_divisor(struct uart_port *port, unsigned int baud,
1348 unsigned int quot, unsigned int quot_frac)
1349 {
1350 int scr;
1351 int lcr;
1352
1353 for (scr = 16; scr > 4; scr--) {
1354 unsigned int maxrate = port->uartclk / scr;
1355 unsigned int divisor = max(maxrate / baud, 1U);
1356 int delta = maxrate / divisor - baud;
1357
1358 if (baud > maxrate + baud / 50)
1359 continue;
1360
1361 if (delta > baud / 50)
1362 divisor++;
1363
1364 if (divisor > 0xffff)
1365 continue;
1366
1367 /* Update delta due to possible divisor change */
1368 delta = maxrate / divisor - baud;
1369 if (abs(delta) < baud / 50) {
1370 lcr = serial_port_in(port, UART_LCR);
1371 serial_port_out(port, UART_LCR, lcr | 0x80);
1372 serial_port_out(port, UART_DLL, divisor & 0xff);
1373 serial_port_out(port, UART_DLM, divisor >> 8 & 0xff);
1374 serial_port_out(port, 2, 16 - scr);
1375 serial_port_out(port, UART_LCR, lcr);
1376 return;
1377 }
1378 }
1379 }
pci_pericom_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1380 static int pci_pericom_setup(struct serial_private *priv,
1381 const struct pciserial_board *board,
1382 struct uart_8250_port *port, int idx)
1383 {
1384 unsigned int bar, offset = board->first_offset, maxnr;
1385
1386 bar = FL_GET_BASE(board->flags);
1387 if (board->flags & FL_BASE_BARS)
1388 bar += idx;
1389 else
1390 offset += idx * board->uart_offset;
1391
1392
1393 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1394 (board->reg_shift + 3);
1395
1396 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1397 return 1;
1398
1399 port->port.set_divisor = pericom_do_set_divisor;
1400
1401 return setup_port(priv, port, bar, offset, board->reg_shift);
1402 }
1403
pci_pericom_setup_four_at_eight(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1404 static int pci_pericom_setup_four_at_eight(struct serial_private *priv,
1405 const struct pciserial_board *board,
1406 struct uart_8250_port *port, int idx)
1407 {
1408 unsigned int bar, offset = board->first_offset, maxnr;
1409
1410 bar = FL_GET_BASE(board->flags);
1411 if (board->flags & FL_BASE_BARS)
1412 bar += idx;
1413 else
1414 offset += idx * board->uart_offset;
1415
1416 if (idx==3)
1417 offset = 0x38;
1418
1419 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1420 (board->reg_shift + 3);
1421
1422 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1423 return 1;
1424
1425 port->port.set_divisor = pericom_do_set_divisor;
1426
1427 return setup_port(priv, port, bar, offset, board->reg_shift);
1428 }
1429
1430 static int
ce4100_serial_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1431 ce4100_serial_setup(struct serial_private *priv,
1432 const struct pciserial_board *board,
1433 struct uart_8250_port *port, int idx)
1434 {
1435 int ret;
1436
1437 ret = setup_port(priv, port, idx, 0, board->reg_shift);
1438 port->port.iotype = UPIO_MEM32;
1439 port->port.type = PORT_XSCALE;
1440 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1441 port->port.regshift = 2;
1442
1443 return ret;
1444 }
1445
1446 static int
pci_omegapci_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1447 pci_omegapci_setup(struct serial_private *priv,
1448 const struct pciserial_board *board,
1449 struct uart_8250_port *port, int idx)
1450 {
1451 return setup_port(priv, port, 2, idx * 8, 0);
1452 }
1453
1454 static int
pci_brcm_trumanage_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1455 pci_brcm_trumanage_setup(struct serial_private *priv,
1456 const struct pciserial_board *board,
1457 struct uart_8250_port *port, int idx)
1458 {
1459 int ret = pci_default_setup(priv, board, port, idx);
1460
1461 port->port.type = PORT_BRCM_TRUMANAGE;
1462 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1463 return ret;
1464 }
1465
1466 /* RTS will control by MCR if this bit is 0 */
1467 #define FINTEK_RTS_CONTROL_BY_HW BIT(4)
1468 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */
1469 #define FINTEK_RTS_INVERT BIT(5)
1470
1471 /* We should do proper H/W transceiver setting before change to RS485 mode */
pci_fintek_rs485_config(struct uart_port * port,struct serial_rs485 * rs485)1472 static int pci_fintek_rs485_config(struct uart_port *port,
1473 struct serial_rs485 *rs485)
1474 {
1475 struct pci_dev *pci_dev = to_pci_dev(port->dev);
1476 u8 setting;
1477 u8 *index = (u8 *) port->private_data;
1478
1479 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting);
1480
1481 if (!rs485)
1482 rs485 = &port->rs485;
1483 else if (rs485->flags & SER_RS485_ENABLED)
1484 memset(rs485->padding, 0, sizeof(rs485->padding));
1485 else
1486 memset(rs485, 0, sizeof(*rs485));
1487
1488 /* F81504/508/512 not support RTS delay before or after send */
1489 rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND;
1490
1491 if (rs485->flags & SER_RS485_ENABLED) {
1492 /* Enable RTS H/W control mode */
1493 setting |= FINTEK_RTS_CONTROL_BY_HW;
1494
1495 if (rs485->flags & SER_RS485_RTS_ON_SEND) {
1496 /* RTS driving high on TX */
1497 setting &= ~FINTEK_RTS_INVERT;
1498 } else {
1499 /* RTS driving low on TX */
1500 setting |= FINTEK_RTS_INVERT;
1501 }
1502
1503 rs485->delay_rts_after_send = 0;
1504 rs485->delay_rts_before_send = 0;
1505 } else {
1506 /* Disable RTS H/W control mode */
1507 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT);
1508 }
1509
1510 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting);
1511
1512 if (rs485 != &port->rs485)
1513 port->rs485 = *rs485;
1514
1515 return 0;
1516 }
1517
pci_fintek_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1518 static int pci_fintek_setup(struct serial_private *priv,
1519 const struct pciserial_board *board,
1520 struct uart_8250_port *port, int idx)
1521 {
1522 struct pci_dev *pdev = priv->dev;
1523 u8 *data;
1524 u8 config_base;
1525 u16 iobase;
1526
1527 config_base = 0x40 + 0x08 * idx;
1528
1529 /* Get the io address from configuration space */
1530 pci_read_config_word(pdev, config_base + 4, &iobase);
1531
1532 dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%x", __func__, idx, iobase);
1533
1534 port->port.iotype = UPIO_PORT;
1535 port->port.iobase = iobase;
1536 port->port.rs485_config = pci_fintek_rs485_config;
1537
1538 data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL);
1539 if (!data)
1540 return -ENOMEM;
1541
1542 /* preserve index in PCI configuration space */
1543 *data = idx;
1544 port->port.private_data = data;
1545
1546 return 0;
1547 }
1548
pci_fintek_init(struct pci_dev * dev)1549 static int pci_fintek_init(struct pci_dev *dev)
1550 {
1551 unsigned long iobase;
1552 u32 max_port, i;
1553 resource_size_t bar_data[3];
1554 u8 config_base;
1555 struct serial_private *priv = pci_get_drvdata(dev);
1556 struct uart_8250_port *port;
1557
1558 if (!(pci_resource_flags(dev, 5) & IORESOURCE_IO) ||
1559 !(pci_resource_flags(dev, 4) & IORESOURCE_IO) ||
1560 !(pci_resource_flags(dev, 3) & IORESOURCE_IO))
1561 return -ENODEV;
1562
1563 switch (dev->device) {
1564 case 0x1104: /* 4 ports */
1565 case 0x1108: /* 8 ports */
1566 max_port = dev->device & 0xff;
1567 break;
1568 case 0x1112: /* 12 ports */
1569 max_port = 12;
1570 break;
1571 default:
1572 return -EINVAL;
1573 }
1574
1575 /* Get the io address dispatch from the BIOS */
1576 bar_data[0] = pci_resource_start(dev, 5);
1577 bar_data[1] = pci_resource_start(dev, 4);
1578 bar_data[2] = pci_resource_start(dev, 3);
1579
1580 for (i = 0; i < max_port; ++i) {
1581 /* UART0 configuration offset start from 0x40 */
1582 config_base = 0x40 + 0x08 * i;
1583
1584 /* Calculate Real IO Port */
1585 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8;
1586
1587 /* Enable UART I/O port */
1588 pci_write_config_byte(dev, config_base + 0x00, 0x01);
1589
1590 /* Select 128-byte FIFO and 8x FIFO threshold */
1591 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1592
1593 /* LSB UART */
1594 pci_write_config_byte(dev, config_base + 0x04,
1595 (u8)(iobase & 0xff));
1596
1597 /* MSB UART */
1598 pci_write_config_byte(dev, config_base + 0x05,
1599 (u8)((iobase & 0xff00) >> 8));
1600
1601 pci_write_config_byte(dev, config_base + 0x06, dev->irq);
1602
1603 if (priv) {
1604 /* re-apply RS232/485 mode when
1605 * pciserial_resume_ports()
1606 */
1607 port = serial8250_get_port(priv->line[i]);
1608 pci_fintek_rs485_config(&port->port, NULL);
1609 } else {
1610 /* First init without port data
1611 * force init to RS232 Mode
1612 */
1613 pci_write_config_byte(dev, config_base + 0x07, 0x01);
1614 }
1615 }
1616
1617 return max_port;
1618 }
1619
f815xxa_mem_serial_out(struct uart_port * p,int offset,int value)1620 static void f815xxa_mem_serial_out(struct uart_port *p, int offset, int value)
1621 {
1622 struct f815xxa_data *data = p->private_data;
1623 unsigned long flags;
1624
1625 spin_lock_irqsave(&data->lock, flags);
1626 writeb(value, p->membase + offset);
1627 readb(p->membase + UART_SCR); /* Dummy read for flush pcie tx queue */
1628 spin_unlock_irqrestore(&data->lock, flags);
1629 }
1630
pci_fintek_f815xxa_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1631 static int pci_fintek_f815xxa_setup(struct serial_private *priv,
1632 const struct pciserial_board *board,
1633 struct uart_8250_port *port, int idx)
1634 {
1635 struct pci_dev *pdev = priv->dev;
1636 struct f815xxa_data *data;
1637
1638 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
1639 if (!data)
1640 return -ENOMEM;
1641
1642 data->idx = idx;
1643 spin_lock_init(&data->lock);
1644
1645 port->port.private_data = data;
1646 port->port.iotype = UPIO_MEM;
1647 port->port.flags |= UPF_IOREMAP;
1648 port->port.mapbase = pci_resource_start(pdev, 0) + 8 * idx;
1649 port->port.serial_out = f815xxa_mem_serial_out;
1650
1651 return 0;
1652 }
1653
pci_fintek_f815xxa_init(struct pci_dev * dev)1654 static int pci_fintek_f815xxa_init(struct pci_dev *dev)
1655 {
1656 u32 max_port, i;
1657 int config_base;
1658
1659 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM))
1660 return -ENODEV;
1661
1662 switch (dev->device) {
1663 case 0x1204: /* 4 ports */
1664 case 0x1208: /* 8 ports */
1665 max_port = dev->device & 0xff;
1666 break;
1667 case 0x1212: /* 12 ports */
1668 max_port = 12;
1669 break;
1670 default:
1671 return -EINVAL;
1672 }
1673
1674 /* Set to mmio decode */
1675 pci_write_config_byte(dev, 0x209, 0x40);
1676
1677 for (i = 0; i < max_port; ++i) {
1678 /* UART0 configuration offset start from 0x2A0 */
1679 config_base = 0x2A0 + 0x08 * i;
1680
1681 /* Select 128-byte FIFO and 8x FIFO threshold */
1682 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1683
1684 /* Enable UART I/O port */
1685 pci_write_config_byte(dev, config_base + 0, 0x01);
1686 }
1687
1688 return max_port;
1689 }
1690
skip_tx_en_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1691 static int skip_tx_en_setup(struct serial_private *priv,
1692 const struct pciserial_board *board,
1693 struct uart_8250_port *port, int idx)
1694 {
1695 port->port.quirks |= UPQ_NO_TXEN_TEST;
1696 dev_dbg(&priv->dev->dev,
1697 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1698 priv->dev->vendor, priv->dev->device,
1699 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
1700
1701 return pci_default_setup(priv, board, port, idx);
1702 }
1703
kt_handle_break(struct uart_port * p)1704 static void kt_handle_break(struct uart_port *p)
1705 {
1706 struct uart_8250_port *up = up_to_u8250p(p);
1707 /*
1708 * On receipt of a BI, serial device in Intel ME (Intel
1709 * management engine) needs to have its fifos cleared for sane
1710 * SOL (Serial Over Lan) output.
1711 */
1712 serial8250_clear_and_reinit_fifos(up);
1713 }
1714
kt_serial_in(struct uart_port * p,int offset)1715 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1716 {
1717 struct uart_8250_port *up = up_to_u8250p(p);
1718 unsigned int val;
1719
1720 /*
1721 * When the Intel ME (management engine) gets reset its serial
1722 * port registers could return 0 momentarily. Functions like
1723 * serial8250_console_write, read and save the IER, perform
1724 * some operation and then restore it. In order to avoid
1725 * setting IER register inadvertently to 0, if the value read
1726 * is 0, double check with ier value in uart_8250_port and use
1727 * that instead. up->ier should be the same value as what is
1728 * currently configured.
1729 */
1730 val = inb(p->iobase + offset);
1731 if (offset == UART_IER) {
1732 if (val == 0)
1733 val = up->ier;
1734 }
1735 return val;
1736 }
1737
kt_serial_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1738 static int kt_serial_setup(struct serial_private *priv,
1739 const struct pciserial_board *board,
1740 struct uart_8250_port *port, int idx)
1741 {
1742 port->port.flags |= UPF_BUG_THRE;
1743 port->port.serial_in = kt_serial_in;
1744 port->port.handle_break = kt_handle_break;
1745 return skip_tx_en_setup(priv, board, port, idx);
1746 }
1747
pci_eg20t_init(struct pci_dev * dev)1748 static int pci_eg20t_init(struct pci_dev *dev)
1749 {
1750 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1751 return -ENODEV;
1752 #else
1753 return 0;
1754 #endif
1755 }
1756
1757 static int
pci_wch_ch353_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1758 pci_wch_ch353_setup(struct serial_private *priv,
1759 const struct pciserial_board *board,
1760 struct uart_8250_port *port, int idx)
1761 {
1762 port->port.flags |= UPF_FIXED_TYPE;
1763 port->port.type = PORT_16550A;
1764 return pci_default_setup(priv, board, port, idx);
1765 }
1766
1767 static int
pci_wch_ch355_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1768 pci_wch_ch355_setup(struct serial_private *priv,
1769 const struct pciserial_board *board,
1770 struct uart_8250_port *port, int idx)
1771 {
1772 port->port.flags |= UPF_FIXED_TYPE;
1773 port->port.type = PORT_16550A;
1774 return pci_default_setup(priv, board, port, idx);
1775 }
1776
1777 static int
pci_wch_ch38x_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1778 pci_wch_ch38x_setup(struct serial_private *priv,
1779 const struct pciserial_board *board,
1780 struct uart_8250_port *port, int idx)
1781 {
1782 port->port.flags |= UPF_FIXED_TYPE;
1783 port->port.type = PORT_16850;
1784 return pci_default_setup(priv, board, port, idx);
1785 }
1786
1787
1788 #define CH384_XINT_ENABLE_REG 0xEB
1789 #define CH384_XINT_ENABLE_BIT 0x02
1790
pci_wch_ch38x_init(struct pci_dev * dev)1791 static int pci_wch_ch38x_init(struct pci_dev *dev)
1792 {
1793 int max_port;
1794 unsigned long iobase;
1795
1796
1797 switch (dev->device) {
1798 case 0x3853: /* 8 ports */
1799 max_port = 8;
1800 break;
1801 default:
1802 return -EINVAL;
1803 }
1804
1805 iobase = pci_resource_start(dev, 0);
1806 outb(CH384_XINT_ENABLE_BIT, iobase + CH384_XINT_ENABLE_REG);
1807
1808 return max_port;
1809 }
1810
pci_wch_ch38x_exit(struct pci_dev * dev)1811 static void pci_wch_ch38x_exit(struct pci_dev *dev)
1812 {
1813 unsigned long iobase;
1814
1815 iobase = pci_resource_start(dev, 0);
1816 outb(0x0, iobase + CH384_XINT_ENABLE_REG);
1817 }
1818
1819
1820 static int
pci_sunix_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1821 pci_sunix_setup(struct serial_private *priv,
1822 const struct pciserial_board *board,
1823 struct uart_8250_port *port, int idx)
1824 {
1825 int bar;
1826 int offset;
1827
1828 port->port.flags |= UPF_FIXED_TYPE;
1829 port->port.type = PORT_SUNIX;
1830
1831 if (idx < 4) {
1832 bar = 0;
1833 offset = idx * board->uart_offset;
1834 } else {
1835 bar = 1;
1836 idx -= 4;
1837 idx = div_s64_rem(idx, 4, &offset);
1838 offset = idx * 64 + offset * board->uart_offset;
1839 }
1840
1841 return setup_port(priv, port, bar, offset, 0);
1842 }
1843
1844 static int
pci_moxa_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1845 pci_moxa_setup(struct serial_private *priv,
1846 const struct pciserial_board *board,
1847 struct uart_8250_port *port, int idx)
1848 {
1849 unsigned int bar = FL_GET_BASE(board->flags);
1850 int offset;
1851
1852 if (board->num_ports == 4 && idx == 3)
1853 offset = 7 * board->uart_offset;
1854 else
1855 offset = idx * board->uart_offset;
1856
1857 return setup_port(priv, port, bar, offset, 0);
1858 }
1859
1860 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1861 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1862 #define PCI_DEVICE_ID_OCTPRO 0x0001
1863 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1864 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1865 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1866 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
1867 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
1868 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
1869 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
1870 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1871 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1872 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
1873 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
1874 #define PCI_DEVICE_ID_TITAN_200I 0x8028
1875 #define PCI_DEVICE_ID_TITAN_400I 0x8048
1876 #define PCI_DEVICE_ID_TITAN_800I 0x8088
1877 #define PCI_DEVICE_ID_TITAN_800EH 0xA007
1878 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1879 #define PCI_DEVICE_ID_TITAN_400EH 0xA009
1880 #define PCI_DEVICE_ID_TITAN_100E 0xA010
1881 #define PCI_DEVICE_ID_TITAN_200E 0xA012
1882 #define PCI_DEVICE_ID_TITAN_400E 0xA013
1883 #define PCI_DEVICE_ID_TITAN_800E 0xA014
1884 #define PCI_DEVICE_ID_TITAN_200EI 0xA016
1885 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017
1886 #define PCI_DEVICE_ID_TITAN_200V3 0xA306
1887 #define PCI_DEVICE_ID_TITAN_400V3 0xA310
1888 #define PCI_DEVICE_ID_TITAN_410V3 0xA312
1889 #define PCI_DEVICE_ID_TITAN_800V3 0xA314
1890 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315
1891 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
1892 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
1893 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
1894 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1895 #define PCI_VENDOR_ID_WCH 0x4348
1896 #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253
1897 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453
1898 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046
1899 #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053
1900 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053
1901 #define PCI_DEVICE_ID_WCH_CH355_4S 0x7173
1902 #define PCI_VENDOR_ID_AGESTAR 0x5372
1903 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872
1904 #define PCI_VENDOR_ID_ASIX 0x9710
1905 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1906 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
1907
1908 #define PCIE_VENDOR_ID_WCH 0x1c00
1909 #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250
1910 #define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470
1911 #define PCIE_DEVICE_ID_WCH_CH384_8S 0x3853
1912 #define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253
1913
1914 #define PCI_VENDOR_ID_ACCESIO 0x494f
1915 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB 0x1051
1916 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S 0x1053
1917 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB 0x105C
1918 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S 0x105E
1919 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB 0x1091
1920 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2 0x1093
1921 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB 0x1099
1922 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4 0x109B
1923 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB 0x10D1
1924 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM 0x10D3
1925 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB 0x10DA
1926 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM 0x10DC
1927 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1 0x1108
1928 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2 0x1110
1929 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2 0x1111
1930 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4 0x1118
1931 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4 0x1119
1932 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S 0x1152
1933 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S 0x115A
1934 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2 0x1190
1935 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2 0x1191
1936 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4 0x1198
1937 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4 0x1199
1938 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM 0x11D0
1939 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4 0x105A
1940 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4 0x105B
1941 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8 0x106A
1942 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8 0x106B
1943 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4 0x1098
1944 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8 0x10A9
1945 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM 0x10D9
1946 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM 0x10E9
1947 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM 0x11D8
1948
1949
1950 #define PCI_DEVICE_ID_MOXA_CP102E 0x1024
1951 #define PCI_DEVICE_ID_MOXA_CP102EL 0x1025
1952 #define PCI_DEVICE_ID_MOXA_CP104EL_A 0x1045
1953 #define PCI_DEVICE_ID_MOXA_CP114EL 0x1144
1954 #define PCI_DEVICE_ID_MOXA_CP116E_A_A 0x1160
1955 #define PCI_DEVICE_ID_MOXA_CP116E_A_B 0x1161
1956 #define PCI_DEVICE_ID_MOXA_CP118EL_A 0x1182
1957 #define PCI_DEVICE_ID_MOXA_CP118E_A_I 0x1183
1958 #define PCI_DEVICE_ID_MOXA_CP132EL 0x1322
1959 #define PCI_DEVICE_ID_MOXA_CP134EL_A 0x1342
1960 #define PCI_DEVICE_ID_MOXA_CP138E_A 0x1381
1961 #define PCI_DEVICE_ID_MOXA_CP168EL_A 0x1683
1962
1963 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1964 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1965 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
1966
1967 /*
1968 * Master list of serial port init/setup/exit quirks.
1969 * This does not describe the general nature of the port.
1970 * (ie, baud base, number and location of ports, etc)
1971 *
1972 * This list is ordered alphabetically by vendor then device.
1973 * Specific entries must come before more generic entries.
1974 */
1975 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1976 /*
1977 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1978 */
1979 {
1980 .vendor = PCI_VENDOR_ID_AMCC,
1981 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
1982 .subvendor = PCI_ANY_ID,
1983 .subdevice = PCI_ANY_ID,
1984 .setup = addidata_apci7800_setup,
1985 },
1986 /*
1987 * AFAVLAB cards - these may be called via parport_serial
1988 * It is not clear whether this applies to all products.
1989 */
1990 {
1991 .vendor = PCI_VENDOR_ID_AFAVLAB,
1992 .device = PCI_ANY_ID,
1993 .subvendor = PCI_ANY_ID,
1994 .subdevice = PCI_ANY_ID,
1995 .setup = afavlab_setup,
1996 },
1997 /*
1998 * HP Diva
1999 */
2000 {
2001 .vendor = PCI_VENDOR_ID_HP,
2002 .device = PCI_DEVICE_ID_HP_DIVA,
2003 .subvendor = PCI_ANY_ID,
2004 .subdevice = PCI_ANY_ID,
2005 .init = pci_hp_diva_init,
2006 .setup = pci_hp_diva_setup,
2007 },
2008 /*
2009 * HPE PCI serial device
2010 */
2011 {
2012 .vendor = PCI_VENDOR_ID_HP_3PAR,
2013 .device = PCI_DEVICE_ID_HPE_PCI_SERIAL,
2014 .subvendor = PCI_ANY_ID,
2015 .subdevice = PCI_ANY_ID,
2016 .setup = pci_hp_diva_setup,
2017 },
2018 /*
2019 * Intel
2020 */
2021 {
2022 .vendor = PCI_VENDOR_ID_INTEL,
2023 .device = PCI_DEVICE_ID_INTEL_80960_RP,
2024 .subvendor = 0xe4bf,
2025 .subdevice = PCI_ANY_ID,
2026 .init = pci_inteli960ni_init,
2027 .setup = pci_default_setup,
2028 },
2029 {
2030 .vendor = PCI_VENDOR_ID_INTEL,
2031 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
2032 .subvendor = PCI_ANY_ID,
2033 .subdevice = PCI_ANY_ID,
2034 .setup = skip_tx_en_setup,
2035 },
2036 {
2037 .vendor = PCI_VENDOR_ID_INTEL,
2038 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
2039 .subvendor = PCI_ANY_ID,
2040 .subdevice = PCI_ANY_ID,
2041 .setup = skip_tx_en_setup,
2042 },
2043 {
2044 .vendor = PCI_VENDOR_ID_INTEL,
2045 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
2046 .subvendor = PCI_ANY_ID,
2047 .subdevice = PCI_ANY_ID,
2048 .setup = skip_tx_en_setup,
2049 },
2050 {
2051 .vendor = PCI_VENDOR_ID_INTEL,
2052 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
2053 .subvendor = PCI_ANY_ID,
2054 .subdevice = PCI_ANY_ID,
2055 .setup = ce4100_serial_setup,
2056 },
2057 {
2058 .vendor = PCI_VENDOR_ID_INTEL,
2059 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
2060 .subvendor = PCI_ANY_ID,
2061 .subdevice = PCI_ANY_ID,
2062 .setup = kt_serial_setup,
2063 },
2064 /*
2065 * ITE
2066 */
2067 {
2068 .vendor = PCI_VENDOR_ID_ITE,
2069 .device = PCI_DEVICE_ID_ITE_8872,
2070 .subvendor = PCI_ANY_ID,
2071 .subdevice = PCI_ANY_ID,
2072 .init = pci_ite887x_init,
2073 .setup = pci_default_setup,
2074 .exit = pci_ite887x_exit,
2075 },
2076 /*
2077 * National Instruments
2078 */
2079 {
2080 .vendor = PCI_VENDOR_ID_NI,
2081 .device = PCI_DEVICE_ID_NI_PCI23216,
2082 .subvendor = PCI_ANY_ID,
2083 .subdevice = PCI_ANY_ID,
2084 .init = pci_ni8420_init,
2085 .setup = pci_default_setup,
2086 .exit = pci_ni8420_exit,
2087 },
2088 {
2089 .vendor = PCI_VENDOR_ID_NI,
2090 .device = PCI_DEVICE_ID_NI_PCI2328,
2091 .subvendor = PCI_ANY_ID,
2092 .subdevice = PCI_ANY_ID,
2093 .init = pci_ni8420_init,
2094 .setup = pci_default_setup,
2095 .exit = pci_ni8420_exit,
2096 },
2097 {
2098 .vendor = PCI_VENDOR_ID_NI,
2099 .device = PCI_DEVICE_ID_NI_PCI2324,
2100 .subvendor = PCI_ANY_ID,
2101 .subdevice = PCI_ANY_ID,
2102 .init = pci_ni8420_init,
2103 .setup = pci_default_setup,
2104 .exit = pci_ni8420_exit,
2105 },
2106 {
2107 .vendor = PCI_VENDOR_ID_NI,
2108 .device = PCI_DEVICE_ID_NI_PCI2322,
2109 .subvendor = PCI_ANY_ID,
2110 .subdevice = PCI_ANY_ID,
2111 .init = pci_ni8420_init,
2112 .setup = pci_default_setup,
2113 .exit = pci_ni8420_exit,
2114 },
2115 {
2116 .vendor = PCI_VENDOR_ID_NI,
2117 .device = PCI_DEVICE_ID_NI_PCI2324I,
2118 .subvendor = PCI_ANY_ID,
2119 .subdevice = PCI_ANY_ID,
2120 .init = pci_ni8420_init,
2121 .setup = pci_default_setup,
2122 .exit = pci_ni8420_exit,
2123 },
2124 {
2125 .vendor = PCI_VENDOR_ID_NI,
2126 .device = PCI_DEVICE_ID_NI_PCI2322I,
2127 .subvendor = PCI_ANY_ID,
2128 .subdevice = PCI_ANY_ID,
2129 .init = pci_ni8420_init,
2130 .setup = pci_default_setup,
2131 .exit = pci_ni8420_exit,
2132 },
2133 {
2134 .vendor = PCI_VENDOR_ID_NI,
2135 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
2136 .subvendor = PCI_ANY_ID,
2137 .subdevice = PCI_ANY_ID,
2138 .init = pci_ni8420_init,
2139 .setup = pci_default_setup,
2140 .exit = pci_ni8420_exit,
2141 },
2142 {
2143 .vendor = PCI_VENDOR_ID_NI,
2144 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
2145 .subvendor = PCI_ANY_ID,
2146 .subdevice = PCI_ANY_ID,
2147 .init = pci_ni8420_init,
2148 .setup = pci_default_setup,
2149 .exit = pci_ni8420_exit,
2150 },
2151 {
2152 .vendor = PCI_VENDOR_ID_NI,
2153 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
2154 .subvendor = PCI_ANY_ID,
2155 .subdevice = PCI_ANY_ID,
2156 .init = pci_ni8420_init,
2157 .setup = pci_default_setup,
2158 .exit = pci_ni8420_exit,
2159 },
2160 {
2161 .vendor = PCI_VENDOR_ID_NI,
2162 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
2163 .subvendor = PCI_ANY_ID,
2164 .subdevice = PCI_ANY_ID,
2165 .init = pci_ni8420_init,
2166 .setup = pci_default_setup,
2167 .exit = pci_ni8420_exit,
2168 },
2169 {
2170 .vendor = PCI_VENDOR_ID_NI,
2171 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
2172 .subvendor = PCI_ANY_ID,
2173 .subdevice = PCI_ANY_ID,
2174 .init = pci_ni8420_init,
2175 .setup = pci_default_setup,
2176 .exit = pci_ni8420_exit,
2177 },
2178 {
2179 .vendor = PCI_VENDOR_ID_NI,
2180 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
2181 .subvendor = PCI_ANY_ID,
2182 .subdevice = PCI_ANY_ID,
2183 .init = pci_ni8420_init,
2184 .setup = pci_default_setup,
2185 .exit = pci_ni8420_exit,
2186 },
2187 {
2188 .vendor = PCI_VENDOR_ID_NI,
2189 .device = PCI_ANY_ID,
2190 .subvendor = PCI_ANY_ID,
2191 .subdevice = PCI_ANY_ID,
2192 .init = pci_ni8430_init,
2193 .setup = pci_ni8430_setup,
2194 .exit = pci_ni8430_exit,
2195 },
2196 /* Quatech */
2197 {
2198 .vendor = PCI_VENDOR_ID_QUATECH,
2199 .device = PCI_ANY_ID,
2200 .subvendor = PCI_ANY_ID,
2201 .subdevice = PCI_ANY_ID,
2202 .init = pci_quatech_init,
2203 .setup = pci_quatech_setup,
2204 .exit = pci_quatech_exit,
2205 },
2206 /*
2207 * Panacom
2208 */
2209 {
2210 .vendor = PCI_VENDOR_ID_PANACOM,
2211 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2212 .subvendor = PCI_ANY_ID,
2213 .subdevice = PCI_ANY_ID,
2214 .init = pci_plx9050_init,
2215 .setup = pci_default_setup,
2216 .exit = pci_plx9050_exit,
2217 },
2218 {
2219 .vendor = PCI_VENDOR_ID_PANACOM,
2220 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2221 .subvendor = PCI_ANY_ID,
2222 .subdevice = PCI_ANY_ID,
2223 .init = pci_plx9050_init,
2224 .setup = pci_default_setup,
2225 .exit = pci_plx9050_exit,
2226 },
2227 /*
2228 * Pericom (Only 7954 - It have a offset jump for port 4)
2229 */
2230 {
2231 .vendor = PCI_VENDOR_ID_PERICOM,
2232 .device = PCI_DEVICE_ID_PERICOM_PI7C9X7954,
2233 .subvendor = PCI_ANY_ID,
2234 .subdevice = PCI_ANY_ID,
2235 .setup = pci_pericom_setup_four_at_eight,
2236 },
2237 /*
2238 * PLX
2239 */
2240 {
2241 .vendor = PCI_VENDOR_ID_PLX,
2242 .device = PCI_DEVICE_ID_PLX_9050,
2243 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
2244 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
2245 .init = pci_plx9050_init,
2246 .setup = pci_default_setup,
2247 .exit = pci_plx9050_exit,
2248 },
2249 {
2250 .vendor = PCI_VENDOR_ID_PLX,
2251 .device = PCI_DEVICE_ID_PLX_9050,
2252 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
2253 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2254 .init = pci_plx9050_init,
2255 .setup = pci_default_setup,
2256 .exit = pci_plx9050_exit,
2257 },
2258 {
2259 .vendor = PCI_VENDOR_ID_PLX,
2260 .device = PCI_DEVICE_ID_PLX_ROMULUS,
2261 .subvendor = PCI_VENDOR_ID_PLX,
2262 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
2263 .init = pci_plx9050_init,
2264 .setup = pci_default_setup,
2265 .exit = pci_plx9050_exit,
2266 },
2267 {
2268 .vendor = PCI_VENDOR_ID_ACCESIO,
2269 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB,
2270 .subvendor = PCI_ANY_ID,
2271 .subdevice = PCI_ANY_ID,
2272 .setup = pci_pericom_setup_four_at_eight,
2273 },
2274 {
2275 .vendor = PCI_VENDOR_ID_ACCESIO,
2276 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S,
2277 .subvendor = PCI_ANY_ID,
2278 .subdevice = PCI_ANY_ID,
2279 .setup = pci_pericom_setup_four_at_eight,
2280 },
2281 {
2282 .vendor = PCI_VENDOR_ID_ACCESIO,
2283 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB,
2284 .subvendor = PCI_ANY_ID,
2285 .subdevice = PCI_ANY_ID,
2286 .setup = pci_pericom_setup_four_at_eight,
2287 },
2288 {
2289 .vendor = PCI_VENDOR_ID_ACCESIO,
2290 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4,
2291 .subvendor = PCI_ANY_ID,
2292 .subdevice = PCI_ANY_ID,
2293 .setup = pci_pericom_setup_four_at_eight,
2294 },
2295 {
2296 .vendor = PCI_VENDOR_ID_ACCESIO,
2297 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB,
2298 .subvendor = PCI_ANY_ID,
2299 .subdevice = PCI_ANY_ID,
2300 .setup = pci_pericom_setup_four_at_eight,
2301 },
2302 {
2303 .vendor = PCI_VENDOR_ID_ACCESIO,
2304 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM,
2305 .subvendor = PCI_ANY_ID,
2306 .subdevice = PCI_ANY_ID,
2307 .setup = pci_pericom_setup_four_at_eight,
2308 },
2309 {
2310 .vendor = PCI_VENDOR_ID_ACCESIO,
2311 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4,
2312 .subvendor = PCI_ANY_ID,
2313 .subdevice = PCI_ANY_ID,
2314 .setup = pci_pericom_setup_four_at_eight,
2315 },
2316 {
2317 .vendor = PCI_VENDOR_ID_ACCESIO,
2318 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4,
2319 .subvendor = PCI_ANY_ID,
2320 .subdevice = PCI_ANY_ID,
2321 .setup = pci_pericom_setup_four_at_eight,
2322 },
2323 {
2324 .vendor = PCI_VENDOR_ID_ACCESIO,
2325 .device = PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4,
2326 .subvendor = PCI_ANY_ID,
2327 .subdevice = PCI_ANY_ID,
2328 .setup = pci_pericom_setup_four_at_eight,
2329 },
2330 {
2331 .vendor = PCI_VENDOR_ID_ACCESIO,
2332 .device = PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S,
2333 .subvendor = PCI_ANY_ID,
2334 .subdevice = PCI_ANY_ID,
2335 .setup = pci_pericom_setup_four_at_eight,
2336 },
2337 {
2338 .vendor = PCI_VENDOR_ID_ACCESIO,
2339 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4,
2340 .subvendor = PCI_ANY_ID,
2341 .subdevice = PCI_ANY_ID,
2342 .setup = pci_pericom_setup_four_at_eight,
2343 },
2344 {
2345 .vendor = PCI_VENDOR_ID_ACCESIO,
2346 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4,
2347 .subvendor = PCI_ANY_ID,
2348 .subdevice = PCI_ANY_ID,
2349 .setup = pci_pericom_setup_four_at_eight,
2350 },
2351 {
2352 .vendor = PCI_VENDOR_ID_ACCESIO,
2353 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4,
2354 .subvendor = PCI_ANY_ID,
2355 .subdevice = PCI_ANY_ID,
2356 .setup = pci_pericom_setup_four_at_eight,
2357 },
2358 {
2359 .vendor = PCI_VENDOR_ID_ACCESIO,
2360 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4,
2361 .subvendor = PCI_ANY_ID,
2362 .subdevice = PCI_ANY_ID,
2363 .setup = pci_pericom_setup_four_at_eight,
2364 },
2365 {
2366 .vendor = PCI_VENDOR_ID_ACCESIO,
2367 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM,
2368 .subvendor = PCI_ANY_ID,
2369 .subdevice = PCI_ANY_ID,
2370 .setup = pci_pericom_setup_four_at_eight,
2371 },
2372 {
2373 .vendor = PCI_VENDOR_ID_ACCESIO,
2374 .device = PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM,
2375 .subvendor = PCI_ANY_ID,
2376 .subdevice = PCI_ANY_ID,
2377 .setup = pci_pericom_setup_four_at_eight,
2378 },
2379 {
2380 .vendor = PCI_VENDOR_ID_ACCESIO,
2381 .device = PCI_ANY_ID,
2382 .subvendor = PCI_ANY_ID,
2383 .subdevice = PCI_ANY_ID,
2384 .setup = pci_pericom_setup,
2385 }, /*
2386 * SBS Technologies, Inc., PMC-OCTALPRO 232
2387 */
2388 {
2389 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2390 .device = PCI_DEVICE_ID_OCTPRO,
2391 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2392 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
2393 .init = sbs_init,
2394 .setup = sbs_setup,
2395 .exit = sbs_exit,
2396 },
2397 /*
2398 * SBS Technologies, Inc., PMC-OCTALPRO 422
2399 */
2400 {
2401 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2402 .device = PCI_DEVICE_ID_OCTPRO,
2403 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2404 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
2405 .init = sbs_init,
2406 .setup = sbs_setup,
2407 .exit = sbs_exit,
2408 },
2409 /*
2410 * SBS Technologies, Inc., P-Octal 232
2411 */
2412 {
2413 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2414 .device = PCI_DEVICE_ID_OCTPRO,
2415 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2416 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
2417 .init = sbs_init,
2418 .setup = sbs_setup,
2419 .exit = sbs_exit,
2420 },
2421 /*
2422 * SBS Technologies, Inc., P-Octal 422
2423 */
2424 {
2425 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2426 .device = PCI_DEVICE_ID_OCTPRO,
2427 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2428 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
2429 .init = sbs_init,
2430 .setup = sbs_setup,
2431 .exit = sbs_exit,
2432 },
2433 /*
2434 * SIIG cards - these may be called via parport_serial
2435 */
2436 {
2437 .vendor = PCI_VENDOR_ID_SIIG,
2438 .device = PCI_ANY_ID,
2439 .subvendor = PCI_ANY_ID,
2440 .subdevice = PCI_ANY_ID,
2441 .init = pci_siig_init,
2442 .setup = pci_siig_setup,
2443 },
2444 /*
2445 * Titan cards
2446 */
2447 {
2448 .vendor = PCI_VENDOR_ID_TITAN,
2449 .device = PCI_DEVICE_ID_TITAN_400L,
2450 .subvendor = PCI_ANY_ID,
2451 .subdevice = PCI_ANY_ID,
2452 .setup = titan_400l_800l_setup,
2453 },
2454 {
2455 .vendor = PCI_VENDOR_ID_TITAN,
2456 .device = PCI_DEVICE_ID_TITAN_800L,
2457 .subvendor = PCI_ANY_ID,
2458 .subdevice = PCI_ANY_ID,
2459 .setup = titan_400l_800l_setup,
2460 },
2461 /*
2462 * Timedia cards
2463 */
2464 {
2465 .vendor = PCI_VENDOR_ID_TIMEDIA,
2466 .device = PCI_DEVICE_ID_TIMEDIA_1889,
2467 .subvendor = PCI_VENDOR_ID_TIMEDIA,
2468 .subdevice = PCI_ANY_ID,
2469 .probe = pci_timedia_probe,
2470 .init = pci_timedia_init,
2471 .setup = pci_timedia_setup,
2472 },
2473 {
2474 .vendor = PCI_VENDOR_ID_TIMEDIA,
2475 .device = PCI_ANY_ID,
2476 .subvendor = PCI_ANY_ID,
2477 .subdevice = PCI_ANY_ID,
2478 .setup = pci_timedia_setup,
2479 },
2480 /*
2481 * Sunix PCI serial boards
2482 */
2483 {
2484 .vendor = PCI_VENDOR_ID_SUNIX,
2485 .device = PCI_DEVICE_ID_SUNIX_1999,
2486 .subvendor = PCI_VENDOR_ID_SUNIX,
2487 .subdevice = PCI_ANY_ID,
2488 .setup = pci_sunix_setup,
2489 },
2490 /*
2491 * Xircom cards
2492 */
2493 {
2494 .vendor = PCI_VENDOR_ID_XIRCOM,
2495 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2496 .subvendor = PCI_ANY_ID,
2497 .subdevice = PCI_ANY_ID,
2498 .init = pci_xircom_init,
2499 .setup = pci_default_setup,
2500 },
2501 /*
2502 * Netmos cards - these may be called via parport_serial
2503 */
2504 {
2505 .vendor = PCI_VENDOR_ID_NETMOS,
2506 .device = PCI_ANY_ID,
2507 .subvendor = PCI_ANY_ID,
2508 .subdevice = PCI_ANY_ID,
2509 .init = pci_netmos_init,
2510 .setup = pci_netmos_9900_setup,
2511 },
2512 /*
2513 * EndRun Technologies
2514 */
2515 {
2516 .vendor = PCI_VENDOR_ID_ENDRUN,
2517 .device = PCI_ANY_ID,
2518 .subvendor = PCI_ANY_ID,
2519 .subdevice = PCI_ANY_ID,
2520 .init = pci_endrun_init,
2521 .setup = pci_default_setup,
2522 },
2523 /*
2524 * For Oxford Semiconductor Tornado based devices
2525 */
2526 {
2527 .vendor = PCI_VENDOR_ID_OXSEMI,
2528 .device = PCI_ANY_ID,
2529 .subvendor = PCI_ANY_ID,
2530 .subdevice = PCI_ANY_ID,
2531 .init = pci_oxsemi_tornado_init,
2532 .setup = pci_default_setup,
2533 },
2534 {
2535 .vendor = PCI_VENDOR_ID_MAINPINE,
2536 .device = PCI_ANY_ID,
2537 .subvendor = PCI_ANY_ID,
2538 .subdevice = PCI_ANY_ID,
2539 .init = pci_oxsemi_tornado_init,
2540 .setup = pci_default_setup,
2541 },
2542 {
2543 .vendor = PCI_VENDOR_ID_DIGI,
2544 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2545 .subvendor = PCI_SUBVENDOR_ID_IBM,
2546 .subdevice = PCI_ANY_ID,
2547 .init = pci_oxsemi_tornado_init,
2548 .setup = pci_default_setup,
2549 },
2550 {
2551 .vendor = PCI_VENDOR_ID_INTEL,
2552 .device = 0x8811,
2553 .subvendor = PCI_ANY_ID,
2554 .subdevice = PCI_ANY_ID,
2555 .init = pci_eg20t_init,
2556 .setup = pci_default_setup,
2557 },
2558 {
2559 .vendor = PCI_VENDOR_ID_INTEL,
2560 .device = 0x8812,
2561 .subvendor = PCI_ANY_ID,
2562 .subdevice = PCI_ANY_ID,
2563 .init = pci_eg20t_init,
2564 .setup = pci_default_setup,
2565 },
2566 {
2567 .vendor = PCI_VENDOR_ID_INTEL,
2568 .device = 0x8813,
2569 .subvendor = PCI_ANY_ID,
2570 .subdevice = PCI_ANY_ID,
2571 .init = pci_eg20t_init,
2572 .setup = pci_default_setup,
2573 },
2574 {
2575 .vendor = PCI_VENDOR_ID_INTEL,
2576 .device = 0x8814,
2577 .subvendor = PCI_ANY_ID,
2578 .subdevice = PCI_ANY_ID,
2579 .init = pci_eg20t_init,
2580 .setup = pci_default_setup,
2581 },
2582 {
2583 .vendor = 0x10DB,
2584 .device = 0x8027,
2585 .subvendor = PCI_ANY_ID,
2586 .subdevice = PCI_ANY_ID,
2587 .init = pci_eg20t_init,
2588 .setup = pci_default_setup,
2589 },
2590 {
2591 .vendor = 0x10DB,
2592 .device = 0x8028,
2593 .subvendor = PCI_ANY_ID,
2594 .subdevice = PCI_ANY_ID,
2595 .init = pci_eg20t_init,
2596 .setup = pci_default_setup,
2597 },
2598 {
2599 .vendor = 0x10DB,
2600 .device = 0x8029,
2601 .subvendor = PCI_ANY_ID,
2602 .subdevice = PCI_ANY_ID,
2603 .init = pci_eg20t_init,
2604 .setup = pci_default_setup,
2605 },
2606 {
2607 .vendor = 0x10DB,
2608 .device = 0x800C,
2609 .subvendor = PCI_ANY_ID,
2610 .subdevice = PCI_ANY_ID,
2611 .init = pci_eg20t_init,
2612 .setup = pci_default_setup,
2613 },
2614 {
2615 .vendor = 0x10DB,
2616 .device = 0x800D,
2617 .subvendor = PCI_ANY_ID,
2618 .subdevice = PCI_ANY_ID,
2619 .init = pci_eg20t_init,
2620 .setup = pci_default_setup,
2621 },
2622 /*
2623 * Cronyx Omega PCI (PLX-chip based)
2624 */
2625 {
2626 .vendor = PCI_VENDOR_ID_PLX,
2627 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2628 .subvendor = PCI_ANY_ID,
2629 .subdevice = PCI_ANY_ID,
2630 .setup = pci_omegapci_setup,
2631 },
2632 /* WCH CH353 1S1P card (16550 clone) */
2633 {
2634 .vendor = PCI_VENDOR_ID_WCH,
2635 .device = PCI_DEVICE_ID_WCH_CH353_1S1P,
2636 .subvendor = PCI_ANY_ID,
2637 .subdevice = PCI_ANY_ID,
2638 .setup = pci_wch_ch353_setup,
2639 },
2640 /* WCH CH353 2S1P card (16550 clone) */
2641 {
2642 .vendor = PCI_VENDOR_ID_WCH,
2643 .device = PCI_DEVICE_ID_WCH_CH353_2S1P,
2644 .subvendor = PCI_ANY_ID,
2645 .subdevice = PCI_ANY_ID,
2646 .setup = pci_wch_ch353_setup,
2647 },
2648 /* WCH CH353 4S card (16550 clone) */
2649 {
2650 .vendor = PCI_VENDOR_ID_WCH,
2651 .device = PCI_DEVICE_ID_WCH_CH353_4S,
2652 .subvendor = PCI_ANY_ID,
2653 .subdevice = PCI_ANY_ID,
2654 .setup = pci_wch_ch353_setup,
2655 },
2656 /* WCH CH353 2S1PF card (16550 clone) */
2657 {
2658 .vendor = PCI_VENDOR_ID_WCH,
2659 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2660 .subvendor = PCI_ANY_ID,
2661 .subdevice = PCI_ANY_ID,
2662 .setup = pci_wch_ch353_setup,
2663 },
2664 /* WCH CH352 2S card (16550 clone) */
2665 {
2666 .vendor = PCI_VENDOR_ID_WCH,
2667 .device = PCI_DEVICE_ID_WCH_CH352_2S,
2668 .subvendor = PCI_ANY_ID,
2669 .subdevice = PCI_ANY_ID,
2670 .setup = pci_wch_ch353_setup,
2671 },
2672 /* WCH CH355 4S card (16550 clone) */
2673 {
2674 .vendor = PCI_VENDOR_ID_WCH,
2675 .device = PCI_DEVICE_ID_WCH_CH355_4S,
2676 .subvendor = PCI_ANY_ID,
2677 .subdevice = PCI_ANY_ID,
2678 .setup = pci_wch_ch355_setup,
2679 },
2680 /* WCH CH382 2S card (16850 clone) */
2681 {
2682 .vendor = PCIE_VENDOR_ID_WCH,
2683 .device = PCIE_DEVICE_ID_WCH_CH382_2S,
2684 .subvendor = PCI_ANY_ID,
2685 .subdevice = PCI_ANY_ID,
2686 .setup = pci_wch_ch38x_setup,
2687 },
2688 /* WCH CH382 2S1P card (16850 clone) */
2689 {
2690 .vendor = PCIE_VENDOR_ID_WCH,
2691 .device = PCIE_DEVICE_ID_WCH_CH382_2S1P,
2692 .subvendor = PCI_ANY_ID,
2693 .subdevice = PCI_ANY_ID,
2694 .setup = pci_wch_ch38x_setup,
2695 },
2696 /* WCH CH384 4S card (16850 clone) */
2697 {
2698 .vendor = PCIE_VENDOR_ID_WCH,
2699 .device = PCIE_DEVICE_ID_WCH_CH384_4S,
2700 .subvendor = PCI_ANY_ID,
2701 .subdevice = PCI_ANY_ID,
2702 .setup = pci_wch_ch38x_setup,
2703 },
2704 /* WCH CH384 8S card (16850 clone) */
2705 {
2706 .vendor = PCIE_VENDOR_ID_WCH,
2707 .device = PCIE_DEVICE_ID_WCH_CH384_8S,
2708 .subvendor = PCI_ANY_ID,
2709 .subdevice = PCI_ANY_ID,
2710 .init = pci_wch_ch38x_init,
2711 .exit = pci_wch_ch38x_exit,
2712 .setup = pci_wch_ch38x_setup,
2713 },
2714 /*
2715 * ASIX devices with FIFO bug
2716 */
2717 {
2718 .vendor = PCI_VENDOR_ID_ASIX,
2719 .device = PCI_ANY_ID,
2720 .subvendor = PCI_ANY_ID,
2721 .subdevice = PCI_ANY_ID,
2722 .setup = pci_asix_setup,
2723 },
2724 /*
2725 * Broadcom TruManage (NetXtreme)
2726 */
2727 {
2728 .vendor = PCI_VENDOR_ID_BROADCOM,
2729 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2730 .subvendor = PCI_ANY_ID,
2731 .subdevice = PCI_ANY_ID,
2732 .setup = pci_brcm_trumanage_setup,
2733 },
2734 {
2735 .vendor = 0x1c29,
2736 .device = 0x1104,
2737 .subvendor = PCI_ANY_ID,
2738 .subdevice = PCI_ANY_ID,
2739 .setup = pci_fintek_setup,
2740 .init = pci_fintek_init,
2741 },
2742 {
2743 .vendor = 0x1c29,
2744 .device = 0x1108,
2745 .subvendor = PCI_ANY_ID,
2746 .subdevice = PCI_ANY_ID,
2747 .setup = pci_fintek_setup,
2748 .init = pci_fintek_init,
2749 },
2750 {
2751 .vendor = 0x1c29,
2752 .device = 0x1112,
2753 .subvendor = PCI_ANY_ID,
2754 .subdevice = PCI_ANY_ID,
2755 .setup = pci_fintek_setup,
2756 .init = pci_fintek_init,
2757 },
2758 /*
2759 * MOXA
2760 */
2761 {
2762 .vendor = PCI_VENDOR_ID_MOXA,
2763 .device = PCI_ANY_ID,
2764 .subvendor = PCI_ANY_ID,
2765 .subdevice = PCI_ANY_ID,
2766 .setup = pci_moxa_setup,
2767 },
2768 {
2769 .vendor = 0x1c29,
2770 .device = 0x1204,
2771 .subvendor = PCI_ANY_ID,
2772 .subdevice = PCI_ANY_ID,
2773 .setup = pci_fintek_f815xxa_setup,
2774 .init = pci_fintek_f815xxa_init,
2775 },
2776 {
2777 .vendor = 0x1c29,
2778 .device = 0x1208,
2779 .subvendor = PCI_ANY_ID,
2780 .subdevice = PCI_ANY_ID,
2781 .setup = pci_fintek_f815xxa_setup,
2782 .init = pci_fintek_f815xxa_init,
2783 },
2784 {
2785 .vendor = 0x1c29,
2786 .device = 0x1212,
2787 .subvendor = PCI_ANY_ID,
2788 .subdevice = PCI_ANY_ID,
2789 .setup = pci_fintek_f815xxa_setup,
2790 .init = pci_fintek_f815xxa_init,
2791 },
2792
2793 /*
2794 * Default "match everything" terminator entry
2795 */
2796 {
2797 .vendor = PCI_ANY_ID,
2798 .device = PCI_ANY_ID,
2799 .subvendor = PCI_ANY_ID,
2800 .subdevice = PCI_ANY_ID,
2801 .setup = pci_default_setup,
2802 }
2803 };
2804
quirk_id_matches(u32 quirk_id,u32 dev_id)2805 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2806 {
2807 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2808 }
2809
find_quirk(struct pci_dev * dev)2810 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2811 {
2812 struct pci_serial_quirk *quirk;
2813
2814 for (quirk = pci_serial_quirks; ; quirk++)
2815 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2816 quirk_id_matches(quirk->device, dev->device) &&
2817 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2818 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2819 break;
2820 return quirk;
2821 }
2822
2823 /*
2824 * This is the configuration table for all of the PCI serial boards
2825 * which we support. It is directly indexed by the pci_board_num_t enum
2826 * value, which is encoded in the pci_device_id PCI probe table's
2827 * driver_data member.
2828 *
2829 * The makeup of these names are:
2830 * pbn_bn{_bt}_n_baud{_offsetinhex}
2831 *
2832 * bn = PCI BAR number
2833 * bt = Index using PCI BARs
2834 * n = number of serial ports
2835 * baud = baud rate
2836 * offsetinhex = offset for each sequential port (in hex)
2837 *
2838 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
2839 *
2840 * Please note: in theory if n = 1, _bt infix should make no difference.
2841 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2842 */
2843 enum pci_board_num_t {
2844 pbn_default = 0,
2845
2846 pbn_b0_1_115200,
2847 pbn_b0_2_115200,
2848 pbn_b0_4_115200,
2849 pbn_b0_5_115200,
2850 pbn_b0_8_115200,
2851
2852 pbn_b0_1_921600,
2853 pbn_b0_2_921600,
2854 pbn_b0_4_921600,
2855
2856 pbn_b0_2_1130000,
2857
2858 pbn_b0_4_1152000,
2859
2860 pbn_b0_4_1250000,
2861
2862 pbn_b0_2_1843200,
2863 pbn_b0_4_1843200,
2864
2865 pbn_b0_1_4000000,
2866
2867 pbn_b0_bt_1_115200,
2868 pbn_b0_bt_2_115200,
2869 pbn_b0_bt_4_115200,
2870 pbn_b0_bt_8_115200,
2871
2872 pbn_b0_bt_1_460800,
2873 pbn_b0_bt_2_460800,
2874 pbn_b0_bt_4_460800,
2875
2876 pbn_b0_bt_1_921600,
2877 pbn_b0_bt_2_921600,
2878 pbn_b0_bt_4_921600,
2879 pbn_b0_bt_8_921600,
2880
2881 pbn_b1_1_115200,
2882 pbn_b1_2_115200,
2883 pbn_b1_4_115200,
2884 pbn_b1_8_115200,
2885 pbn_b1_16_115200,
2886
2887 pbn_b1_1_921600,
2888 pbn_b1_2_921600,
2889 pbn_b1_4_921600,
2890 pbn_b1_8_921600,
2891
2892 pbn_b1_2_1250000,
2893
2894 pbn_b1_bt_1_115200,
2895 pbn_b1_bt_2_115200,
2896 pbn_b1_bt_4_115200,
2897
2898 pbn_b1_bt_2_921600,
2899
2900 pbn_b1_1_1382400,
2901 pbn_b1_2_1382400,
2902 pbn_b1_4_1382400,
2903 pbn_b1_8_1382400,
2904
2905 pbn_b2_1_115200,
2906 pbn_b2_2_115200,
2907 pbn_b2_4_115200,
2908 pbn_b2_8_115200,
2909
2910 pbn_b2_1_460800,
2911 pbn_b2_4_460800,
2912 pbn_b2_8_460800,
2913 pbn_b2_16_460800,
2914
2915 pbn_b2_1_921600,
2916 pbn_b2_4_921600,
2917 pbn_b2_8_921600,
2918
2919 pbn_b2_8_1152000,
2920
2921 pbn_b2_bt_1_115200,
2922 pbn_b2_bt_2_115200,
2923 pbn_b2_bt_4_115200,
2924
2925 pbn_b2_bt_2_921600,
2926 pbn_b2_bt_4_921600,
2927
2928 pbn_b3_2_115200,
2929 pbn_b3_4_115200,
2930 pbn_b3_8_115200,
2931
2932 pbn_b4_bt_2_921600,
2933 pbn_b4_bt_4_921600,
2934 pbn_b4_bt_8_921600,
2935
2936 /*
2937 * Board-specific versions.
2938 */
2939 pbn_panacom,
2940 pbn_panacom2,
2941 pbn_panacom4,
2942 pbn_plx_romulus,
2943 pbn_endrun_2_4000000,
2944 pbn_oxsemi,
2945 pbn_oxsemi_1_4000000,
2946 pbn_oxsemi_2_4000000,
2947 pbn_oxsemi_4_4000000,
2948 pbn_oxsemi_8_4000000,
2949 pbn_intel_i960,
2950 pbn_sgi_ioc3,
2951 pbn_computone_4,
2952 pbn_computone_6,
2953 pbn_computone_8,
2954 pbn_sbsxrsio,
2955 pbn_pasemi_1682M,
2956 pbn_ni8430_2,
2957 pbn_ni8430_4,
2958 pbn_ni8430_8,
2959 pbn_ni8430_16,
2960 pbn_ADDIDATA_PCIe_1_3906250,
2961 pbn_ADDIDATA_PCIe_2_3906250,
2962 pbn_ADDIDATA_PCIe_4_3906250,
2963 pbn_ADDIDATA_PCIe_8_3906250,
2964 pbn_ce4100_1_115200,
2965 pbn_omegapci,
2966 pbn_NETMOS9900_2s_115200,
2967 pbn_brcm_trumanage,
2968 pbn_fintek_4,
2969 pbn_fintek_8,
2970 pbn_fintek_12,
2971 pbn_fintek_F81504A,
2972 pbn_fintek_F81508A,
2973 pbn_fintek_F81512A,
2974 pbn_wch382_2,
2975 pbn_wch384_4,
2976 pbn_wch384_8,
2977 pbn_pericom_PI7C9X7951,
2978 pbn_pericom_PI7C9X7952,
2979 pbn_pericom_PI7C9X7954,
2980 pbn_pericom_PI7C9X7958,
2981 pbn_sunix_pci_1s,
2982 pbn_sunix_pci_2s,
2983 pbn_sunix_pci_4s,
2984 pbn_sunix_pci_8s,
2985 pbn_sunix_pci_16s,
2986 pbn_moxa8250_2p,
2987 pbn_moxa8250_4p,
2988 pbn_moxa8250_8p,
2989 };
2990
2991 /*
2992 * uart_offset - the space between channels
2993 * reg_shift - describes how the UART registers are mapped
2994 * to PCI memory by the card.
2995 * For example IER register on SBS, Inc. PMC-OctPro is located at
2996 * offset 0x10 from the UART base, while UART_IER is defined as 1
2997 * in include/linux/serial_reg.h,
2998 * see first lines of serial_in() and serial_out() in 8250.c
2999 */
3000
3001 static struct pciserial_board pci_boards[] = {
3002 [pbn_default] = {
3003 .flags = FL_BASE0,
3004 .num_ports = 1,
3005 .base_baud = 115200,
3006 .uart_offset = 8,
3007 },
3008 [pbn_b0_1_115200] = {
3009 .flags = FL_BASE0,
3010 .num_ports = 1,
3011 .base_baud = 115200,
3012 .uart_offset = 8,
3013 },
3014 [pbn_b0_2_115200] = {
3015 .flags = FL_BASE0,
3016 .num_ports = 2,
3017 .base_baud = 115200,
3018 .uart_offset = 8,
3019 },
3020 [pbn_b0_4_115200] = {
3021 .flags = FL_BASE0,
3022 .num_ports = 4,
3023 .base_baud = 115200,
3024 .uart_offset = 8,
3025 },
3026 [pbn_b0_5_115200] = {
3027 .flags = FL_BASE0,
3028 .num_ports = 5,
3029 .base_baud = 115200,
3030 .uart_offset = 8,
3031 },
3032 [pbn_b0_8_115200] = {
3033 .flags = FL_BASE0,
3034 .num_ports = 8,
3035 .base_baud = 115200,
3036 .uart_offset = 8,
3037 },
3038 [pbn_b0_1_921600] = {
3039 .flags = FL_BASE0,
3040 .num_ports = 1,
3041 .base_baud = 921600,
3042 .uart_offset = 8,
3043 },
3044 [pbn_b0_2_921600] = {
3045 .flags = FL_BASE0,
3046 .num_ports = 2,
3047 .base_baud = 921600,
3048 .uart_offset = 8,
3049 },
3050 [pbn_b0_4_921600] = {
3051 .flags = FL_BASE0,
3052 .num_ports = 4,
3053 .base_baud = 921600,
3054 .uart_offset = 8,
3055 },
3056
3057 [pbn_b0_2_1130000] = {
3058 .flags = FL_BASE0,
3059 .num_ports = 2,
3060 .base_baud = 1130000,
3061 .uart_offset = 8,
3062 },
3063
3064 [pbn_b0_4_1152000] = {
3065 .flags = FL_BASE0,
3066 .num_ports = 4,
3067 .base_baud = 1152000,
3068 .uart_offset = 8,
3069 },
3070
3071 [pbn_b0_4_1250000] = {
3072 .flags = FL_BASE0,
3073 .num_ports = 4,
3074 .base_baud = 1250000,
3075 .uart_offset = 8,
3076 },
3077
3078 [pbn_b0_2_1843200] = {
3079 .flags = FL_BASE0,
3080 .num_ports = 2,
3081 .base_baud = 1843200,
3082 .uart_offset = 8,
3083 },
3084 [pbn_b0_4_1843200] = {
3085 .flags = FL_BASE0,
3086 .num_ports = 4,
3087 .base_baud = 1843200,
3088 .uart_offset = 8,
3089 },
3090
3091 [pbn_b0_1_4000000] = {
3092 .flags = FL_BASE0,
3093 .num_ports = 1,
3094 .base_baud = 4000000,
3095 .uart_offset = 8,
3096 },
3097
3098 [pbn_b0_bt_1_115200] = {
3099 .flags = FL_BASE0|FL_BASE_BARS,
3100 .num_ports = 1,
3101 .base_baud = 115200,
3102 .uart_offset = 8,
3103 },
3104 [pbn_b0_bt_2_115200] = {
3105 .flags = FL_BASE0|FL_BASE_BARS,
3106 .num_ports = 2,
3107 .base_baud = 115200,
3108 .uart_offset = 8,
3109 },
3110 [pbn_b0_bt_4_115200] = {
3111 .flags = FL_BASE0|FL_BASE_BARS,
3112 .num_ports = 4,
3113 .base_baud = 115200,
3114 .uart_offset = 8,
3115 },
3116 [pbn_b0_bt_8_115200] = {
3117 .flags = FL_BASE0|FL_BASE_BARS,
3118 .num_ports = 8,
3119 .base_baud = 115200,
3120 .uart_offset = 8,
3121 },
3122
3123 [pbn_b0_bt_1_460800] = {
3124 .flags = FL_BASE0|FL_BASE_BARS,
3125 .num_ports = 1,
3126 .base_baud = 460800,
3127 .uart_offset = 8,
3128 },
3129 [pbn_b0_bt_2_460800] = {
3130 .flags = FL_BASE0|FL_BASE_BARS,
3131 .num_ports = 2,
3132 .base_baud = 460800,
3133 .uart_offset = 8,
3134 },
3135 [pbn_b0_bt_4_460800] = {
3136 .flags = FL_BASE0|FL_BASE_BARS,
3137 .num_ports = 4,
3138 .base_baud = 460800,
3139 .uart_offset = 8,
3140 },
3141
3142 [pbn_b0_bt_1_921600] = {
3143 .flags = FL_BASE0|FL_BASE_BARS,
3144 .num_ports = 1,
3145 .base_baud = 921600,
3146 .uart_offset = 8,
3147 },
3148 [pbn_b0_bt_2_921600] = {
3149 .flags = FL_BASE0|FL_BASE_BARS,
3150 .num_ports = 2,
3151 .base_baud = 921600,
3152 .uart_offset = 8,
3153 },
3154 [pbn_b0_bt_4_921600] = {
3155 .flags = FL_BASE0|FL_BASE_BARS,
3156 .num_ports = 4,
3157 .base_baud = 921600,
3158 .uart_offset = 8,
3159 },
3160 [pbn_b0_bt_8_921600] = {
3161 .flags = FL_BASE0|FL_BASE_BARS,
3162 .num_ports = 8,
3163 .base_baud = 921600,
3164 .uart_offset = 8,
3165 },
3166
3167 [pbn_b1_1_115200] = {
3168 .flags = FL_BASE1,
3169 .num_ports = 1,
3170 .base_baud = 115200,
3171 .uart_offset = 8,
3172 },
3173 [pbn_b1_2_115200] = {
3174 .flags = FL_BASE1,
3175 .num_ports = 2,
3176 .base_baud = 115200,
3177 .uart_offset = 8,
3178 },
3179 [pbn_b1_4_115200] = {
3180 .flags = FL_BASE1,
3181 .num_ports = 4,
3182 .base_baud = 115200,
3183 .uart_offset = 8,
3184 },
3185 [pbn_b1_8_115200] = {
3186 .flags = FL_BASE1,
3187 .num_ports = 8,
3188 .base_baud = 115200,
3189 .uart_offset = 8,
3190 },
3191 [pbn_b1_16_115200] = {
3192 .flags = FL_BASE1,
3193 .num_ports = 16,
3194 .base_baud = 115200,
3195 .uart_offset = 8,
3196 },
3197
3198 [pbn_b1_1_921600] = {
3199 .flags = FL_BASE1,
3200 .num_ports = 1,
3201 .base_baud = 921600,
3202 .uart_offset = 8,
3203 },
3204 [pbn_b1_2_921600] = {
3205 .flags = FL_BASE1,
3206 .num_ports = 2,
3207 .base_baud = 921600,
3208 .uart_offset = 8,
3209 },
3210 [pbn_b1_4_921600] = {
3211 .flags = FL_BASE1,
3212 .num_ports = 4,
3213 .base_baud = 921600,
3214 .uart_offset = 8,
3215 },
3216 [pbn_b1_8_921600] = {
3217 .flags = FL_BASE1,
3218 .num_ports = 8,
3219 .base_baud = 921600,
3220 .uart_offset = 8,
3221 },
3222 [pbn_b1_2_1250000] = {
3223 .flags = FL_BASE1,
3224 .num_ports = 2,
3225 .base_baud = 1250000,
3226 .uart_offset = 8,
3227 },
3228
3229 [pbn_b1_bt_1_115200] = {
3230 .flags = FL_BASE1|FL_BASE_BARS,
3231 .num_ports = 1,
3232 .base_baud = 115200,
3233 .uart_offset = 8,
3234 },
3235 [pbn_b1_bt_2_115200] = {
3236 .flags = FL_BASE1|FL_BASE_BARS,
3237 .num_ports = 2,
3238 .base_baud = 115200,
3239 .uart_offset = 8,
3240 },
3241 [pbn_b1_bt_4_115200] = {
3242 .flags = FL_BASE1|FL_BASE_BARS,
3243 .num_ports = 4,
3244 .base_baud = 115200,
3245 .uart_offset = 8,
3246 },
3247
3248 [pbn_b1_bt_2_921600] = {
3249 .flags = FL_BASE1|FL_BASE_BARS,
3250 .num_ports = 2,
3251 .base_baud = 921600,
3252 .uart_offset = 8,
3253 },
3254
3255 [pbn_b1_1_1382400] = {
3256 .flags = FL_BASE1,
3257 .num_ports = 1,
3258 .base_baud = 1382400,
3259 .uart_offset = 8,
3260 },
3261 [pbn_b1_2_1382400] = {
3262 .flags = FL_BASE1,
3263 .num_ports = 2,
3264 .base_baud = 1382400,
3265 .uart_offset = 8,
3266 },
3267 [pbn_b1_4_1382400] = {
3268 .flags = FL_BASE1,
3269 .num_ports = 4,
3270 .base_baud = 1382400,
3271 .uart_offset = 8,
3272 },
3273 [pbn_b1_8_1382400] = {
3274 .flags = FL_BASE1,
3275 .num_ports = 8,
3276 .base_baud = 1382400,
3277 .uart_offset = 8,
3278 },
3279
3280 [pbn_b2_1_115200] = {
3281 .flags = FL_BASE2,
3282 .num_ports = 1,
3283 .base_baud = 115200,
3284 .uart_offset = 8,
3285 },
3286 [pbn_b2_2_115200] = {
3287 .flags = FL_BASE2,
3288 .num_ports = 2,
3289 .base_baud = 115200,
3290 .uart_offset = 8,
3291 },
3292 [pbn_b2_4_115200] = {
3293 .flags = FL_BASE2,
3294 .num_ports = 4,
3295 .base_baud = 115200,
3296 .uart_offset = 8,
3297 },
3298 [pbn_b2_8_115200] = {
3299 .flags = FL_BASE2,
3300 .num_ports = 8,
3301 .base_baud = 115200,
3302 .uart_offset = 8,
3303 },
3304
3305 [pbn_b2_1_460800] = {
3306 .flags = FL_BASE2,
3307 .num_ports = 1,
3308 .base_baud = 460800,
3309 .uart_offset = 8,
3310 },
3311 [pbn_b2_4_460800] = {
3312 .flags = FL_BASE2,
3313 .num_ports = 4,
3314 .base_baud = 460800,
3315 .uart_offset = 8,
3316 },
3317 [pbn_b2_8_460800] = {
3318 .flags = FL_BASE2,
3319 .num_ports = 8,
3320 .base_baud = 460800,
3321 .uart_offset = 8,
3322 },
3323 [pbn_b2_16_460800] = {
3324 .flags = FL_BASE2,
3325 .num_ports = 16,
3326 .base_baud = 460800,
3327 .uart_offset = 8,
3328 },
3329
3330 [pbn_b2_1_921600] = {
3331 .flags = FL_BASE2,
3332 .num_ports = 1,
3333 .base_baud = 921600,
3334 .uart_offset = 8,
3335 },
3336 [pbn_b2_4_921600] = {
3337 .flags = FL_BASE2,
3338 .num_ports = 4,
3339 .base_baud = 921600,
3340 .uart_offset = 8,
3341 },
3342 [pbn_b2_8_921600] = {
3343 .flags = FL_BASE2,
3344 .num_ports = 8,
3345 .base_baud = 921600,
3346 .uart_offset = 8,
3347 },
3348
3349 [pbn_b2_8_1152000] = {
3350 .flags = FL_BASE2,
3351 .num_ports = 8,
3352 .base_baud = 1152000,
3353 .uart_offset = 8,
3354 },
3355
3356 [pbn_b2_bt_1_115200] = {
3357 .flags = FL_BASE2|FL_BASE_BARS,
3358 .num_ports = 1,
3359 .base_baud = 115200,
3360 .uart_offset = 8,
3361 },
3362 [pbn_b2_bt_2_115200] = {
3363 .flags = FL_BASE2|FL_BASE_BARS,
3364 .num_ports = 2,
3365 .base_baud = 115200,
3366 .uart_offset = 8,
3367 },
3368 [pbn_b2_bt_4_115200] = {
3369 .flags = FL_BASE2|FL_BASE_BARS,
3370 .num_ports = 4,
3371 .base_baud = 115200,
3372 .uart_offset = 8,
3373 },
3374
3375 [pbn_b2_bt_2_921600] = {
3376 .flags = FL_BASE2|FL_BASE_BARS,
3377 .num_ports = 2,
3378 .base_baud = 921600,
3379 .uart_offset = 8,
3380 },
3381 [pbn_b2_bt_4_921600] = {
3382 .flags = FL_BASE2|FL_BASE_BARS,
3383 .num_ports = 4,
3384 .base_baud = 921600,
3385 .uart_offset = 8,
3386 },
3387
3388 [pbn_b3_2_115200] = {
3389 .flags = FL_BASE3,
3390 .num_ports = 2,
3391 .base_baud = 115200,
3392 .uart_offset = 8,
3393 },
3394 [pbn_b3_4_115200] = {
3395 .flags = FL_BASE3,
3396 .num_ports = 4,
3397 .base_baud = 115200,
3398 .uart_offset = 8,
3399 },
3400 [pbn_b3_8_115200] = {
3401 .flags = FL_BASE3,
3402 .num_ports = 8,
3403 .base_baud = 115200,
3404 .uart_offset = 8,
3405 },
3406
3407 [pbn_b4_bt_2_921600] = {
3408 .flags = FL_BASE4,
3409 .num_ports = 2,
3410 .base_baud = 921600,
3411 .uart_offset = 8,
3412 },
3413 [pbn_b4_bt_4_921600] = {
3414 .flags = FL_BASE4,
3415 .num_ports = 4,
3416 .base_baud = 921600,
3417 .uart_offset = 8,
3418 },
3419 [pbn_b4_bt_8_921600] = {
3420 .flags = FL_BASE4,
3421 .num_ports = 8,
3422 .base_baud = 921600,
3423 .uart_offset = 8,
3424 },
3425
3426 /*
3427 * Entries following this are board-specific.
3428 */
3429
3430 /*
3431 * Panacom - IOMEM
3432 */
3433 [pbn_panacom] = {
3434 .flags = FL_BASE2,
3435 .num_ports = 2,
3436 .base_baud = 921600,
3437 .uart_offset = 0x400,
3438 .reg_shift = 7,
3439 },
3440 [pbn_panacom2] = {
3441 .flags = FL_BASE2|FL_BASE_BARS,
3442 .num_ports = 2,
3443 .base_baud = 921600,
3444 .uart_offset = 0x400,
3445 .reg_shift = 7,
3446 },
3447 [pbn_panacom4] = {
3448 .flags = FL_BASE2|FL_BASE_BARS,
3449 .num_ports = 4,
3450 .base_baud = 921600,
3451 .uart_offset = 0x400,
3452 .reg_shift = 7,
3453 },
3454
3455 /* I think this entry is broken - the first_offset looks wrong --rmk */
3456 [pbn_plx_romulus] = {
3457 .flags = FL_BASE2,
3458 .num_ports = 4,
3459 .base_baud = 921600,
3460 .uart_offset = 8 << 2,
3461 .reg_shift = 2,
3462 .first_offset = 0x03,
3463 },
3464
3465 /*
3466 * EndRun Technologies
3467 * Uses the size of PCI Base region 0 to
3468 * signal now many ports are available
3469 * 2 port 952 Uart support
3470 */
3471 [pbn_endrun_2_4000000] = {
3472 .flags = FL_BASE0,
3473 .num_ports = 2,
3474 .base_baud = 4000000,
3475 .uart_offset = 0x200,
3476 .first_offset = 0x1000,
3477 },
3478
3479 /*
3480 * This board uses the size of PCI Base region 0 to
3481 * signal now many ports are available
3482 */
3483 [pbn_oxsemi] = {
3484 .flags = FL_BASE0|FL_REGION_SZ_CAP,
3485 .num_ports = 32,
3486 .base_baud = 115200,
3487 .uart_offset = 8,
3488 },
3489 [pbn_oxsemi_1_4000000] = {
3490 .flags = FL_BASE0,
3491 .num_ports = 1,
3492 .base_baud = 4000000,
3493 .uart_offset = 0x200,
3494 .first_offset = 0x1000,
3495 },
3496 [pbn_oxsemi_2_4000000] = {
3497 .flags = FL_BASE0,
3498 .num_ports = 2,
3499 .base_baud = 4000000,
3500 .uart_offset = 0x200,
3501 .first_offset = 0x1000,
3502 },
3503 [pbn_oxsemi_4_4000000] = {
3504 .flags = FL_BASE0,
3505 .num_ports = 4,
3506 .base_baud = 4000000,
3507 .uart_offset = 0x200,
3508 .first_offset = 0x1000,
3509 },
3510 [pbn_oxsemi_8_4000000] = {
3511 .flags = FL_BASE0,
3512 .num_ports = 8,
3513 .base_baud = 4000000,
3514 .uart_offset = 0x200,
3515 .first_offset = 0x1000,
3516 },
3517
3518
3519 /*
3520 * EKF addition for i960 Boards form EKF with serial port.
3521 * Max 256 ports.
3522 */
3523 [pbn_intel_i960] = {
3524 .flags = FL_BASE0,
3525 .num_ports = 32,
3526 .base_baud = 921600,
3527 .uart_offset = 8 << 2,
3528 .reg_shift = 2,
3529 .first_offset = 0x10000,
3530 },
3531 [pbn_sgi_ioc3] = {
3532 .flags = FL_BASE0|FL_NOIRQ,
3533 .num_ports = 1,
3534 .base_baud = 458333,
3535 .uart_offset = 8,
3536 .reg_shift = 0,
3537 .first_offset = 0x20178,
3538 },
3539
3540 /*
3541 * Computone - uses IOMEM.
3542 */
3543 [pbn_computone_4] = {
3544 .flags = FL_BASE0,
3545 .num_ports = 4,
3546 .base_baud = 921600,
3547 .uart_offset = 0x40,
3548 .reg_shift = 2,
3549 .first_offset = 0x200,
3550 },
3551 [pbn_computone_6] = {
3552 .flags = FL_BASE0,
3553 .num_ports = 6,
3554 .base_baud = 921600,
3555 .uart_offset = 0x40,
3556 .reg_shift = 2,
3557 .first_offset = 0x200,
3558 },
3559 [pbn_computone_8] = {
3560 .flags = FL_BASE0,
3561 .num_ports = 8,
3562 .base_baud = 921600,
3563 .uart_offset = 0x40,
3564 .reg_shift = 2,
3565 .first_offset = 0x200,
3566 },
3567 [pbn_sbsxrsio] = {
3568 .flags = FL_BASE0,
3569 .num_ports = 8,
3570 .base_baud = 460800,
3571 .uart_offset = 256,
3572 .reg_shift = 4,
3573 },
3574 /*
3575 * PA Semi PWRficient PA6T-1682M on-chip UART
3576 */
3577 [pbn_pasemi_1682M] = {
3578 .flags = FL_BASE0,
3579 .num_ports = 1,
3580 .base_baud = 8333333,
3581 },
3582 /*
3583 * National Instruments 843x
3584 */
3585 [pbn_ni8430_16] = {
3586 .flags = FL_BASE0,
3587 .num_ports = 16,
3588 .base_baud = 3686400,
3589 .uart_offset = 0x10,
3590 .first_offset = 0x800,
3591 },
3592 [pbn_ni8430_8] = {
3593 .flags = FL_BASE0,
3594 .num_ports = 8,
3595 .base_baud = 3686400,
3596 .uart_offset = 0x10,
3597 .first_offset = 0x800,
3598 },
3599 [pbn_ni8430_4] = {
3600 .flags = FL_BASE0,
3601 .num_ports = 4,
3602 .base_baud = 3686400,
3603 .uart_offset = 0x10,
3604 .first_offset = 0x800,
3605 },
3606 [pbn_ni8430_2] = {
3607 .flags = FL_BASE0,
3608 .num_ports = 2,
3609 .base_baud = 3686400,
3610 .uart_offset = 0x10,
3611 .first_offset = 0x800,
3612 },
3613 /*
3614 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3615 */
3616 [pbn_ADDIDATA_PCIe_1_3906250] = {
3617 .flags = FL_BASE0,
3618 .num_ports = 1,
3619 .base_baud = 3906250,
3620 .uart_offset = 0x200,
3621 .first_offset = 0x1000,
3622 },
3623 [pbn_ADDIDATA_PCIe_2_3906250] = {
3624 .flags = FL_BASE0,
3625 .num_ports = 2,
3626 .base_baud = 3906250,
3627 .uart_offset = 0x200,
3628 .first_offset = 0x1000,
3629 },
3630 [pbn_ADDIDATA_PCIe_4_3906250] = {
3631 .flags = FL_BASE0,
3632 .num_ports = 4,
3633 .base_baud = 3906250,
3634 .uart_offset = 0x200,
3635 .first_offset = 0x1000,
3636 },
3637 [pbn_ADDIDATA_PCIe_8_3906250] = {
3638 .flags = FL_BASE0,
3639 .num_ports = 8,
3640 .base_baud = 3906250,
3641 .uart_offset = 0x200,
3642 .first_offset = 0x1000,
3643 },
3644 [pbn_ce4100_1_115200] = {
3645 .flags = FL_BASE_BARS,
3646 .num_ports = 2,
3647 .base_baud = 921600,
3648 .reg_shift = 2,
3649 },
3650 [pbn_omegapci] = {
3651 .flags = FL_BASE0,
3652 .num_ports = 8,
3653 .base_baud = 115200,
3654 .uart_offset = 0x200,
3655 },
3656 [pbn_NETMOS9900_2s_115200] = {
3657 .flags = FL_BASE0,
3658 .num_ports = 2,
3659 .base_baud = 115200,
3660 },
3661 [pbn_brcm_trumanage] = {
3662 .flags = FL_BASE0,
3663 .num_ports = 1,
3664 .reg_shift = 2,
3665 .base_baud = 115200,
3666 },
3667 [pbn_fintek_4] = {
3668 .num_ports = 4,
3669 .uart_offset = 8,
3670 .base_baud = 115200,
3671 .first_offset = 0x40,
3672 },
3673 [pbn_fintek_8] = {
3674 .num_ports = 8,
3675 .uart_offset = 8,
3676 .base_baud = 115200,
3677 .first_offset = 0x40,
3678 },
3679 [pbn_fintek_12] = {
3680 .num_ports = 12,
3681 .uart_offset = 8,
3682 .base_baud = 115200,
3683 .first_offset = 0x40,
3684 },
3685 [pbn_fintek_F81504A] = {
3686 .num_ports = 4,
3687 .uart_offset = 8,
3688 .base_baud = 115200,
3689 },
3690 [pbn_fintek_F81508A] = {
3691 .num_ports = 8,
3692 .uart_offset = 8,
3693 .base_baud = 115200,
3694 },
3695 [pbn_fintek_F81512A] = {
3696 .num_ports = 12,
3697 .uart_offset = 8,
3698 .base_baud = 115200,
3699 },
3700 [pbn_wch382_2] = {
3701 .flags = FL_BASE0,
3702 .num_ports = 2,
3703 .base_baud = 115200,
3704 .uart_offset = 8,
3705 .first_offset = 0xC0,
3706 },
3707 [pbn_wch384_4] = {
3708 .flags = FL_BASE0,
3709 .num_ports = 4,
3710 .base_baud = 115200,
3711 .uart_offset = 8,
3712 .first_offset = 0xC0,
3713 },
3714 [pbn_wch384_8] = {
3715 .flags = FL_BASE0,
3716 .num_ports = 8,
3717 .base_baud = 115200,
3718 .uart_offset = 8,
3719 .first_offset = 0x00,
3720 },
3721 /*
3722 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
3723 */
3724 [pbn_pericom_PI7C9X7951] = {
3725 .flags = FL_BASE0,
3726 .num_ports = 1,
3727 .base_baud = 921600,
3728 .uart_offset = 0x8,
3729 },
3730 [pbn_pericom_PI7C9X7952] = {
3731 .flags = FL_BASE0,
3732 .num_ports = 2,
3733 .base_baud = 921600,
3734 .uart_offset = 0x8,
3735 },
3736 [pbn_pericom_PI7C9X7954] = {
3737 .flags = FL_BASE0,
3738 .num_ports = 4,
3739 .base_baud = 921600,
3740 .uart_offset = 0x8,
3741 },
3742 [pbn_pericom_PI7C9X7958] = {
3743 .flags = FL_BASE0,
3744 .num_ports = 8,
3745 .base_baud = 921600,
3746 .uart_offset = 0x8,
3747 },
3748 [pbn_sunix_pci_1s] = {
3749 .num_ports = 1,
3750 .base_baud = 921600,
3751 .uart_offset = 0x8,
3752 },
3753 [pbn_sunix_pci_2s] = {
3754 .num_ports = 2,
3755 .base_baud = 921600,
3756 .uart_offset = 0x8,
3757 },
3758 [pbn_sunix_pci_4s] = {
3759 .num_ports = 4,
3760 .base_baud = 921600,
3761 .uart_offset = 0x8,
3762 },
3763 [pbn_sunix_pci_8s] = {
3764 .num_ports = 8,
3765 .base_baud = 921600,
3766 .uart_offset = 0x8,
3767 },
3768 [pbn_sunix_pci_16s] = {
3769 .num_ports = 16,
3770 .base_baud = 921600,
3771 .uart_offset = 0x8,
3772 },
3773 [pbn_moxa8250_2p] = {
3774 .flags = FL_BASE1,
3775 .num_ports = 2,
3776 .base_baud = 921600,
3777 .uart_offset = 0x200,
3778 },
3779 [pbn_moxa8250_4p] = {
3780 .flags = FL_BASE1,
3781 .num_ports = 4,
3782 .base_baud = 921600,
3783 .uart_offset = 0x200,
3784 },
3785 [pbn_moxa8250_8p] = {
3786 .flags = FL_BASE1,
3787 .num_ports = 8,
3788 .base_baud = 921600,
3789 .uart_offset = 0x200,
3790 },
3791 };
3792
3793 static const struct pci_device_id blacklist[] = {
3794 /* softmodems */
3795 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3796 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3797 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3798
3799 /* multi-io cards handled by parport_serial */
3800 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
3801 { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
3802 { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */
3803
3804 /* Intel platforms with MID UART */
3805 { PCI_VDEVICE(INTEL, 0x081b), },
3806 { PCI_VDEVICE(INTEL, 0x081c), },
3807 { PCI_VDEVICE(INTEL, 0x081d), },
3808 { PCI_VDEVICE(INTEL, 0x1191), },
3809 { PCI_VDEVICE(INTEL, 0x18d8), },
3810 { PCI_VDEVICE(INTEL, 0x19d8), },
3811
3812 /* Intel platforms with DesignWare UART */
3813 { PCI_VDEVICE(INTEL, 0x0936), },
3814 { PCI_VDEVICE(INTEL, 0x0f0a), },
3815 { PCI_VDEVICE(INTEL, 0x0f0c), },
3816 { PCI_VDEVICE(INTEL, 0x228a), },
3817 { PCI_VDEVICE(INTEL, 0x228c), },
3818 { PCI_VDEVICE(INTEL, 0x4b96), },
3819 { PCI_VDEVICE(INTEL, 0x4b97), },
3820 { PCI_VDEVICE(INTEL, 0x4b98), },
3821 { PCI_VDEVICE(INTEL, 0x4b99), },
3822 { PCI_VDEVICE(INTEL, 0x4b9a), },
3823 { PCI_VDEVICE(INTEL, 0x4b9b), },
3824 { PCI_VDEVICE(INTEL, 0x9ce3), },
3825 { PCI_VDEVICE(INTEL, 0x9ce4), },
3826
3827 /* Exar devices */
3828 { PCI_VDEVICE(EXAR, PCI_ANY_ID), },
3829 { PCI_VDEVICE(COMMTECH, PCI_ANY_ID), },
3830
3831 /* End of the black list */
3832 { }
3833 };
3834
serial_pci_is_class_communication(struct pci_dev * dev)3835 static int serial_pci_is_class_communication(struct pci_dev *dev)
3836 {
3837 /*
3838 * If it is not a communications device or the programming
3839 * interface is greater than 6, give up.
3840 */
3841 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3842 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MULTISERIAL) &&
3843 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3844 (dev->class & 0xff) > 6)
3845 return -ENODEV;
3846
3847 return 0;
3848 }
3849
3850 /*
3851 * Given a complete unknown PCI device, try to use some heuristics to
3852 * guess what the configuration might be, based on the pitiful PCI
3853 * serial specs. Returns 0 on success, -ENODEV on failure.
3854 */
3855 static int
serial_pci_guess_board(struct pci_dev * dev,struct pciserial_board * board)3856 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
3857 {
3858 int num_iomem, num_port, first_port = -1, i;
3859 int rc;
3860
3861 rc = serial_pci_is_class_communication(dev);
3862 if (rc)
3863 return rc;
3864
3865 /*
3866 * Should we try to make guesses for multiport serial devices later?
3867 */
3868 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_MULTISERIAL)
3869 return -ENODEV;
3870
3871 num_iomem = num_port = 0;
3872 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
3873 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3874 num_port++;
3875 if (first_port == -1)
3876 first_port = i;
3877 }
3878 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3879 num_iomem++;
3880 }
3881
3882 /*
3883 * If there is 1 or 0 iomem regions, and exactly one port,
3884 * use it. We guess the number of ports based on the IO
3885 * region size.
3886 */
3887 if (num_iomem <= 1 && num_port == 1) {
3888 board->flags = first_port;
3889 board->num_ports = pci_resource_len(dev, first_port) / 8;
3890 return 0;
3891 }
3892
3893 /*
3894 * Now guess if we've got a board which indexes by BARs.
3895 * Each IO BAR should be 8 bytes, and they should follow
3896 * consecutively.
3897 */
3898 first_port = -1;
3899 num_port = 0;
3900 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
3901 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3902 pci_resource_len(dev, i) == 8 &&
3903 (first_port == -1 || (first_port + num_port) == i)) {
3904 num_port++;
3905 if (first_port == -1)
3906 first_port = i;
3907 }
3908 }
3909
3910 if (num_port > 1) {
3911 board->flags = first_port | FL_BASE_BARS;
3912 board->num_ports = num_port;
3913 return 0;
3914 }
3915
3916 return -ENODEV;
3917 }
3918
3919 static inline int
serial_pci_matches(const struct pciserial_board * board,const struct pciserial_board * guessed)3920 serial_pci_matches(const struct pciserial_board *board,
3921 const struct pciserial_board *guessed)
3922 {
3923 return
3924 board->num_ports == guessed->num_ports &&
3925 board->base_baud == guessed->base_baud &&
3926 board->uart_offset == guessed->uart_offset &&
3927 board->reg_shift == guessed->reg_shift &&
3928 board->first_offset == guessed->first_offset;
3929 }
3930
3931 struct serial_private *
pciserial_init_ports(struct pci_dev * dev,const struct pciserial_board * board)3932 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
3933 {
3934 struct uart_8250_port uart;
3935 struct serial_private *priv;
3936 struct pci_serial_quirk *quirk;
3937 int rc, nr_ports, i;
3938
3939 nr_ports = board->num_ports;
3940
3941 /*
3942 * Find an init and setup quirks.
3943 */
3944 quirk = find_quirk(dev);
3945
3946 /*
3947 * Run the new-style initialization function.
3948 * The initialization function returns:
3949 * <0 - error
3950 * 0 - use board->num_ports
3951 * >0 - number of ports
3952 */
3953 if (quirk->init) {
3954 rc = quirk->init(dev);
3955 if (rc < 0) {
3956 priv = ERR_PTR(rc);
3957 goto err_out;
3958 }
3959 if (rc)
3960 nr_ports = rc;
3961 }
3962
3963 priv = kzalloc(sizeof(struct serial_private) +
3964 sizeof(unsigned int) * nr_ports,
3965 GFP_KERNEL);
3966 if (!priv) {
3967 priv = ERR_PTR(-ENOMEM);
3968 goto err_deinit;
3969 }
3970
3971 priv->dev = dev;
3972 priv->quirk = quirk;
3973
3974 memset(&uart, 0, sizeof(uart));
3975 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
3976 uart.port.uartclk = board->base_baud * 16;
3977
3978 if (board->flags & FL_NOIRQ) {
3979 uart.port.irq = 0;
3980 } else {
3981 if (pci_match_id(pci_use_msi, dev)) {
3982 dev_dbg(&dev->dev, "Using MSI(-X) interrupts\n");
3983 pci_set_master(dev);
3984 uart.port.flags &= ~UPF_SHARE_IRQ;
3985 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_ALL_TYPES);
3986 } else {
3987 dev_dbg(&dev->dev, "Using legacy interrupts\n");
3988 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_LEGACY);
3989 }
3990 if (rc < 0) {
3991 kfree(priv);
3992 priv = ERR_PTR(rc);
3993 goto err_deinit;
3994 }
3995
3996 uart.port.irq = pci_irq_vector(dev, 0);
3997 }
3998
3999 uart.port.dev = &dev->dev;
4000
4001 for (i = 0; i < nr_ports; i++) {
4002 if (quirk->setup(priv, board, &uart, i))
4003 break;
4004
4005 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
4006 uart.port.iobase, uart.port.irq, uart.port.iotype);
4007
4008 priv->line[i] = serial8250_register_8250_port(&uart);
4009 if (priv->line[i] < 0) {
4010 dev_err(&dev->dev,
4011 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
4012 uart.port.iobase, uart.port.irq,
4013 uart.port.iotype, priv->line[i]);
4014 break;
4015 }
4016 }
4017 priv->nr = i;
4018 priv->board = board;
4019 return priv;
4020
4021 err_deinit:
4022 if (quirk->exit)
4023 quirk->exit(dev);
4024 err_out:
4025 return priv;
4026 }
4027 EXPORT_SYMBOL_GPL(pciserial_init_ports);
4028
pciserial_detach_ports(struct serial_private * priv)4029 static void pciserial_detach_ports(struct serial_private *priv)
4030 {
4031 struct pci_serial_quirk *quirk;
4032 int i;
4033
4034 for (i = 0; i < priv->nr; i++)
4035 serial8250_unregister_port(priv->line[i]);
4036
4037 /*
4038 * Find the exit quirks.
4039 */
4040 quirk = find_quirk(priv->dev);
4041 if (quirk->exit)
4042 quirk->exit(priv->dev);
4043 }
4044
pciserial_remove_ports(struct serial_private * priv)4045 void pciserial_remove_ports(struct serial_private *priv)
4046 {
4047 pciserial_detach_ports(priv);
4048 kfree(priv);
4049 }
4050 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
4051
pciserial_suspend_ports(struct serial_private * priv)4052 void pciserial_suspend_ports(struct serial_private *priv)
4053 {
4054 int i;
4055
4056 for (i = 0; i < priv->nr; i++)
4057 if (priv->line[i] >= 0)
4058 serial8250_suspend_port(priv->line[i]);
4059
4060 /*
4061 * Ensure that every init quirk is properly torn down
4062 */
4063 if (priv->quirk->exit)
4064 priv->quirk->exit(priv->dev);
4065 }
4066 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
4067
pciserial_resume_ports(struct serial_private * priv)4068 void pciserial_resume_ports(struct serial_private *priv)
4069 {
4070 int i;
4071
4072 /*
4073 * Ensure that the board is correctly configured.
4074 */
4075 if (priv->quirk->init)
4076 priv->quirk->init(priv->dev);
4077
4078 for (i = 0; i < priv->nr; i++)
4079 if (priv->line[i] >= 0)
4080 serial8250_resume_port(priv->line[i]);
4081 }
4082 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
4083
4084 /*
4085 * Probe one serial board. Unfortunately, there is no rhyme nor reason
4086 * to the arrangement of serial ports on a PCI card.
4087 */
4088 static int
pciserial_init_one(struct pci_dev * dev,const struct pci_device_id * ent)4089 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
4090 {
4091 struct pci_serial_quirk *quirk;
4092 struct serial_private *priv;
4093 const struct pciserial_board *board;
4094 const struct pci_device_id *exclude;
4095 struct pciserial_board tmp;
4096 int rc;
4097
4098 quirk = find_quirk(dev);
4099 if (quirk->probe) {
4100 rc = quirk->probe(dev);
4101 if (rc)
4102 return rc;
4103 }
4104
4105 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
4106 dev_err(&dev->dev, "invalid driver_data: %ld\n",
4107 ent->driver_data);
4108 return -EINVAL;
4109 }
4110
4111 board = &pci_boards[ent->driver_data];
4112
4113 exclude = pci_match_id(blacklist, dev);
4114 if (exclude)
4115 return -ENODEV;
4116
4117 rc = pcim_enable_device(dev);
4118 pci_save_state(dev);
4119 if (rc)
4120 return rc;
4121
4122 if (ent->driver_data == pbn_default) {
4123 /*
4124 * Use a copy of the pci_board entry for this;
4125 * avoid changing entries in the table.
4126 */
4127 memcpy(&tmp, board, sizeof(struct pciserial_board));
4128 board = &tmp;
4129
4130 /*
4131 * We matched one of our class entries. Try to
4132 * determine the parameters of this board.
4133 */
4134 rc = serial_pci_guess_board(dev, &tmp);
4135 if (rc)
4136 return rc;
4137 } else {
4138 /*
4139 * We matched an explicit entry. If we are able to
4140 * detect this boards settings with our heuristic,
4141 * then we no longer need this entry.
4142 */
4143 memcpy(&tmp, &pci_boards[pbn_default],
4144 sizeof(struct pciserial_board));
4145 rc = serial_pci_guess_board(dev, &tmp);
4146 if (rc == 0 && serial_pci_matches(board, &tmp))
4147 moan_device("Redundant entry in serial pci_table.",
4148 dev);
4149 }
4150
4151 priv = pciserial_init_ports(dev, board);
4152 if (IS_ERR(priv))
4153 return PTR_ERR(priv);
4154
4155 pci_set_drvdata(dev, priv);
4156 return 0;
4157 }
4158
pciserial_remove_one(struct pci_dev * dev)4159 static void pciserial_remove_one(struct pci_dev *dev)
4160 {
4161 struct serial_private *priv = pci_get_drvdata(dev);
4162
4163 pciserial_remove_ports(priv);
4164 }
4165
4166 #ifdef CONFIG_PM_SLEEP
pciserial_suspend_one(struct device * dev)4167 static int pciserial_suspend_one(struct device *dev)
4168 {
4169 struct serial_private *priv = dev_get_drvdata(dev);
4170
4171 if (priv)
4172 pciserial_suspend_ports(priv);
4173
4174 return 0;
4175 }
4176
pciserial_resume_one(struct device * dev)4177 static int pciserial_resume_one(struct device *dev)
4178 {
4179 struct pci_dev *pdev = to_pci_dev(dev);
4180 struct serial_private *priv = pci_get_drvdata(pdev);
4181 int err;
4182
4183 if (priv) {
4184 /*
4185 * The device may have been disabled. Re-enable it.
4186 */
4187 err = pci_enable_device(pdev);
4188 /* FIXME: We cannot simply error out here */
4189 if (err)
4190 dev_err(dev, "Unable to re-enable ports, trying to continue.\n");
4191 pciserial_resume_ports(priv);
4192 }
4193 return 0;
4194 }
4195 #endif
4196
4197 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one,
4198 pciserial_resume_one);
4199
4200 static const struct pci_device_id serial_pci_tbl[] = {
4201 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
4202 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
4203 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
4204 pbn_b2_8_921600 },
4205 /* Advantech also use 0x3618 and 0xf618 */
4206 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
4207 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4208 pbn_b0_4_921600 },
4209 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
4210 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4211 pbn_b0_4_921600 },
4212 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4213 PCI_SUBVENDOR_ID_CONNECT_TECH,
4214 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4215 pbn_b1_8_1382400 },
4216 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4217 PCI_SUBVENDOR_ID_CONNECT_TECH,
4218 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4219 pbn_b1_4_1382400 },
4220 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4221 PCI_SUBVENDOR_ID_CONNECT_TECH,
4222 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4223 pbn_b1_2_1382400 },
4224 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4225 PCI_SUBVENDOR_ID_CONNECT_TECH,
4226 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4227 pbn_b1_8_1382400 },
4228 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4229 PCI_SUBVENDOR_ID_CONNECT_TECH,
4230 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4231 pbn_b1_4_1382400 },
4232 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4233 PCI_SUBVENDOR_ID_CONNECT_TECH,
4234 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4235 pbn_b1_2_1382400 },
4236 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4237 PCI_SUBVENDOR_ID_CONNECT_TECH,
4238 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
4239 pbn_b1_8_921600 },
4240 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4241 PCI_SUBVENDOR_ID_CONNECT_TECH,
4242 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
4243 pbn_b1_8_921600 },
4244 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4245 PCI_SUBVENDOR_ID_CONNECT_TECH,
4246 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
4247 pbn_b1_4_921600 },
4248 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4249 PCI_SUBVENDOR_ID_CONNECT_TECH,
4250 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
4251 pbn_b1_4_921600 },
4252 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4253 PCI_SUBVENDOR_ID_CONNECT_TECH,
4254 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
4255 pbn_b1_2_921600 },
4256 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4257 PCI_SUBVENDOR_ID_CONNECT_TECH,
4258 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
4259 pbn_b1_8_921600 },
4260 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4261 PCI_SUBVENDOR_ID_CONNECT_TECH,
4262 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
4263 pbn_b1_8_921600 },
4264 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4265 PCI_SUBVENDOR_ID_CONNECT_TECH,
4266 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
4267 pbn_b1_4_921600 },
4268 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4269 PCI_SUBVENDOR_ID_CONNECT_TECH,
4270 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
4271 pbn_b1_2_1250000 },
4272 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4273 PCI_SUBVENDOR_ID_CONNECT_TECH,
4274 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
4275 pbn_b0_2_1843200 },
4276 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4277 PCI_SUBVENDOR_ID_CONNECT_TECH,
4278 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
4279 pbn_b0_4_1843200 },
4280 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4281 PCI_VENDOR_ID_AFAVLAB,
4282 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
4283 pbn_b0_4_1152000 },
4284 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
4285 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4286 pbn_b2_bt_1_115200 },
4287 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
4288 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4289 pbn_b2_bt_2_115200 },
4290 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
4291 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4292 pbn_b2_bt_4_115200 },
4293 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
4294 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4295 pbn_b2_bt_2_115200 },
4296 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
4297 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4298 pbn_b2_bt_4_115200 },
4299 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
4300 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4301 pbn_b2_8_115200 },
4302 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4303 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4304 pbn_b2_8_460800 },
4305 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4306 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4307 pbn_b2_8_115200 },
4308
4309 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4310 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4311 pbn_b2_bt_2_115200 },
4312 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4313 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4314 pbn_b2_bt_2_921600 },
4315 /*
4316 * VScom SPCOM800, from sl@s.pl
4317 */
4318 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4319 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4320 pbn_b2_8_921600 },
4321 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
4322 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4323 pbn_b2_4_921600 },
4324 /* Unknown card - subdevice 0x1584 */
4325 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4326 PCI_VENDOR_ID_PLX,
4327 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
4328 pbn_b2_4_115200 },
4329 /* Unknown card - subdevice 0x1588 */
4330 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4331 PCI_VENDOR_ID_PLX,
4332 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4333 pbn_b2_8_115200 },
4334 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4335 PCI_SUBVENDOR_ID_KEYSPAN,
4336 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4337 pbn_panacom },
4338 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4339 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4340 pbn_panacom4 },
4341 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4342 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4343 pbn_panacom2 },
4344 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4345 PCI_VENDOR_ID_ESDGMBH,
4346 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4347 pbn_b2_4_115200 },
4348 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4349 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4350 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
4351 pbn_b2_4_460800 },
4352 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4353 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4354 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
4355 pbn_b2_8_460800 },
4356 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4357 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4358 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
4359 pbn_b2_16_460800 },
4360 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4361 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4362 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
4363 pbn_b2_16_460800 },
4364 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4365 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4366 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
4367 pbn_b2_4_460800 },
4368 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4369 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4370 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
4371 pbn_b2_8_460800 },
4372 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4373 PCI_SUBVENDOR_ID_EXSYS,
4374 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
4375 pbn_b2_4_115200 },
4376 /*
4377 * Megawolf Romulus PCI Serial Card, from Mike Hudson
4378 * (Exoray@isys.ca)
4379 */
4380 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4381 0x10b5, 0x106a, 0, 0,
4382 pbn_plx_romulus },
4383 /*
4384 * EndRun Technologies. PCI express device range.
4385 * EndRun PTP/1588 has 2 Native UARTs.
4386 */
4387 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
4388 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4389 pbn_endrun_2_4000000 },
4390 /*
4391 * Quatech cards. These actually have configurable clocks but for
4392 * now we just use the default.
4393 *
4394 * 100 series are RS232, 200 series RS422,
4395 */
4396 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4397 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4398 pbn_b1_4_115200 },
4399 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4400 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4401 pbn_b1_2_115200 },
4402 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4403 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4404 pbn_b2_2_115200 },
4405 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4406 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4407 pbn_b1_2_115200 },
4408 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4409 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4410 pbn_b2_2_115200 },
4411 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4412 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4413 pbn_b1_4_115200 },
4414 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4415 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4416 pbn_b1_8_115200 },
4417 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4418 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4419 pbn_b1_8_115200 },
4420 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4421 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4422 pbn_b1_4_115200 },
4423 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4424 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4425 pbn_b1_2_115200 },
4426 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4427 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4428 pbn_b1_4_115200 },
4429 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4430 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4431 pbn_b1_2_115200 },
4432 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4433 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4434 pbn_b2_4_115200 },
4435 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4436 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4437 pbn_b2_2_115200 },
4438 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4439 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4440 pbn_b2_1_115200 },
4441 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4442 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4443 pbn_b2_4_115200 },
4444 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4445 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4446 pbn_b2_2_115200 },
4447 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4448 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4449 pbn_b2_1_115200 },
4450 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4451 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4452 pbn_b0_8_115200 },
4453
4454 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
4455 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4456 0, 0,
4457 pbn_b0_4_921600 },
4458 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4459 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4460 0, 0,
4461 pbn_b0_4_1152000 },
4462 { PCI_VENDOR_ID_OXSEMI, 0x9505,
4463 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4464 pbn_b0_bt_2_921600 },
4465
4466 /*
4467 * The below card is a little controversial since it is the
4468 * subject of a PCI vendor/device ID clash. (See
4469 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4470 * For now just used the hex ID 0x950a.
4471 */
4472 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4473 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4474 0, 0, pbn_b0_2_115200 },
4475 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4476 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4477 0, 0, pbn_b0_2_115200 },
4478 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4479 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4480 pbn_b0_2_1130000 },
4481 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4482 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4483 pbn_b0_1_921600 },
4484 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4485 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4486 pbn_b0_4_115200 },
4487 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4488 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4489 pbn_b0_bt_2_921600 },
4490 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4491 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4492 pbn_b2_8_1152000 },
4493
4494 /*
4495 * Oxford Semiconductor Inc. Tornado PCI express device range.
4496 */
4497 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
4498 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4499 pbn_b0_1_4000000 },
4500 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
4501 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4502 pbn_b0_1_4000000 },
4503 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
4504 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4505 pbn_oxsemi_1_4000000 },
4506 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
4507 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4508 pbn_oxsemi_1_4000000 },
4509 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
4510 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4511 pbn_b0_1_4000000 },
4512 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
4513 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4514 pbn_b0_1_4000000 },
4515 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
4516 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4517 pbn_oxsemi_1_4000000 },
4518 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
4519 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4520 pbn_oxsemi_1_4000000 },
4521 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
4522 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4523 pbn_b0_1_4000000 },
4524 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
4525 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4526 pbn_b0_1_4000000 },
4527 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
4528 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4529 pbn_b0_1_4000000 },
4530 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
4531 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4532 pbn_b0_1_4000000 },
4533 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
4534 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4535 pbn_oxsemi_2_4000000 },
4536 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
4537 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4538 pbn_oxsemi_2_4000000 },
4539 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
4540 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4541 pbn_oxsemi_4_4000000 },
4542 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
4543 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4544 pbn_oxsemi_4_4000000 },
4545 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
4546 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4547 pbn_oxsemi_8_4000000 },
4548 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
4549 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4550 pbn_oxsemi_8_4000000 },
4551 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
4552 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4553 pbn_oxsemi_1_4000000 },
4554 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
4555 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4556 pbn_oxsemi_1_4000000 },
4557 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
4558 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4559 pbn_oxsemi_1_4000000 },
4560 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
4561 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4562 pbn_oxsemi_1_4000000 },
4563 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
4564 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4565 pbn_oxsemi_1_4000000 },
4566 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
4567 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4568 pbn_oxsemi_1_4000000 },
4569 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
4570 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4571 pbn_oxsemi_1_4000000 },
4572 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
4573 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4574 pbn_oxsemi_1_4000000 },
4575 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
4576 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4577 pbn_oxsemi_1_4000000 },
4578 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
4579 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4580 pbn_oxsemi_1_4000000 },
4581 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
4582 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4583 pbn_oxsemi_1_4000000 },
4584 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
4585 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4586 pbn_oxsemi_1_4000000 },
4587 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
4588 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4589 pbn_oxsemi_1_4000000 },
4590 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
4591 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4592 pbn_oxsemi_1_4000000 },
4593 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
4594 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4595 pbn_oxsemi_1_4000000 },
4596 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
4597 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4598 pbn_oxsemi_1_4000000 },
4599 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
4600 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4601 pbn_oxsemi_1_4000000 },
4602 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
4603 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4604 pbn_oxsemi_1_4000000 },
4605 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
4606 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4607 pbn_oxsemi_1_4000000 },
4608 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
4609 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4610 pbn_oxsemi_1_4000000 },
4611 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
4612 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4613 pbn_oxsemi_1_4000000 },
4614 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
4615 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4616 pbn_oxsemi_1_4000000 },
4617 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
4618 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4619 pbn_oxsemi_1_4000000 },
4620 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
4621 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4622 pbn_oxsemi_1_4000000 },
4623 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
4624 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4625 pbn_oxsemi_1_4000000 },
4626 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
4627 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4628 pbn_oxsemi_1_4000000 },
4629 /*
4630 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4631 */
4632 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4633 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4634 pbn_oxsemi_1_4000000 },
4635 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4636 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4637 pbn_oxsemi_2_4000000 },
4638 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4639 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4640 pbn_oxsemi_4_4000000 },
4641 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4642 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4643 pbn_oxsemi_8_4000000 },
4644
4645 /*
4646 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4647 */
4648 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4649 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4650 pbn_oxsemi_2_4000000 },
4651
4652 /*
4653 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4654 * from skokodyn@yahoo.com
4655 */
4656 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4657 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4658 pbn_sbsxrsio },
4659 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4660 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4661 pbn_sbsxrsio },
4662 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4663 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4664 pbn_sbsxrsio },
4665 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4666 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4667 pbn_sbsxrsio },
4668
4669 /*
4670 * Digitan DS560-558, from jimd@esoft.com
4671 */
4672 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4673 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4674 pbn_b1_1_115200 },
4675
4676 /*
4677 * Titan Electronic cards
4678 * The 400L and 800L have a custom setup quirk.
4679 */
4680 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4681 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4682 pbn_b0_1_921600 },
4683 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4684 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4685 pbn_b0_2_921600 },
4686 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4687 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4688 pbn_b0_4_921600 },
4689 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4690 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4691 pbn_b0_4_921600 },
4692 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4693 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4694 pbn_b1_1_921600 },
4695 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4696 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4697 pbn_b1_bt_2_921600 },
4698 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4699 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4700 pbn_b0_bt_4_921600 },
4701 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4702 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4703 pbn_b0_bt_8_921600 },
4704 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4705 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4706 pbn_b4_bt_2_921600 },
4707 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4708 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4709 pbn_b4_bt_4_921600 },
4710 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4711 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4712 pbn_b4_bt_8_921600 },
4713 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4714 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4715 pbn_b0_4_921600 },
4716 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4717 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4718 pbn_b0_4_921600 },
4719 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4720 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4721 pbn_b0_4_921600 },
4722 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4723 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4724 pbn_oxsemi_1_4000000 },
4725 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4726 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4727 pbn_oxsemi_2_4000000 },
4728 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4729 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4730 pbn_oxsemi_4_4000000 },
4731 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4732 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4733 pbn_oxsemi_8_4000000 },
4734 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4735 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4736 pbn_oxsemi_2_4000000 },
4737 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4738 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4739 pbn_oxsemi_2_4000000 },
4740 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4741 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4742 pbn_b0_bt_2_921600 },
4743 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4744 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4745 pbn_b0_4_921600 },
4746 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4747 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4748 pbn_b0_4_921600 },
4749 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4750 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4751 pbn_b0_4_921600 },
4752 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4753 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4754 pbn_b0_4_921600 },
4755
4756 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4757 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4758 pbn_b2_1_460800 },
4759 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4760 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4761 pbn_b2_1_460800 },
4762 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4763 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4764 pbn_b2_1_460800 },
4765 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4766 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4767 pbn_b2_bt_2_921600 },
4768 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4769 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4770 pbn_b2_bt_2_921600 },
4771 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4772 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4773 pbn_b2_bt_2_921600 },
4774 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4775 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4776 pbn_b2_bt_4_921600 },
4777 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4778 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4779 pbn_b2_bt_4_921600 },
4780 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4781 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4782 pbn_b2_bt_4_921600 },
4783 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4784 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4785 pbn_b0_1_921600 },
4786 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4787 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4788 pbn_b0_1_921600 },
4789 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4790 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4791 pbn_b0_1_921600 },
4792 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4793 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4794 pbn_b0_bt_2_921600 },
4795 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4796 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4797 pbn_b0_bt_2_921600 },
4798 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4799 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4800 pbn_b0_bt_2_921600 },
4801 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4802 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4803 pbn_b0_bt_4_921600 },
4804 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4805 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4806 pbn_b0_bt_4_921600 },
4807 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4808 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4809 pbn_b0_bt_4_921600 },
4810 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4811 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4812 pbn_b0_bt_8_921600 },
4813 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4814 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4815 pbn_b0_bt_8_921600 },
4816 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4817 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4818 pbn_b0_bt_8_921600 },
4819
4820 /*
4821 * Computone devices submitted by Doug McNash dmcnash@computone.com
4822 */
4823 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4824 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4825 0, 0, pbn_computone_4 },
4826 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4827 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4828 0, 0, pbn_computone_8 },
4829 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4830 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4831 0, 0, pbn_computone_6 },
4832
4833 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4834 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4835 pbn_oxsemi },
4836 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4837 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4838 pbn_b0_bt_1_921600 },
4839
4840 /*
4841 * Sunix PCI serial boards
4842 */
4843 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4844 PCI_VENDOR_ID_SUNIX, 0x0001, 0, 0,
4845 pbn_sunix_pci_1s },
4846 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4847 PCI_VENDOR_ID_SUNIX, 0x0002, 0, 0,
4848 pbn_sunix_pci_2s },
4849 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4850 PCI_VENDOR_ID_SUNIX, 0x0004, 0, 0,
4851 pbn_sunix_pci_4s },
4852 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4853 PCI_VENDOR_ID_SUNIX, 0x0084, 0, 0,
4854 pbn_sunix_pci_4s },
4855 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4856 PCI_VENDOR_ID_SUNIX, 0x0008, 0, 0,
4857 pbn_sunix_pci_8s },
4858 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4859 PCI_VENDOR_ID_SUNIX, 0x0088, 0, 0,
4860 pbn_sunix_pci_8s },
4861 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4862 PCI_VENDOR_ID_SUNIX, 0x0010, 0, 0,
4863 pbn_sunix_pci_16s },
4864
4865 /*
4866 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4867 */
4868 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4869 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4870 pbn_b0_bt_8_115200 },
4871 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4872 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4873 pbn_b0_bt_8_115200 },
4874
4875 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4876 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4877 pbn_b0_bt_2_115200 },
4878 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4879 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4880 pbn_b0_bt_2_115200 },
4881 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4882 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4883 pbn_b0_bt_2_115200 },
4884 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4885 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4886 pbn_b0_bt_2_115200 },
4887 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4888 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4889 pbn_b0_bt_2_115200 },
4890 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4891 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4892 pbn_b0_bt_4_460800 },
4893 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4894 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4895 pbn_b0_bt_4_460800 },
4896 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4897 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4898 pbn_b0_bt_2_460800 },
4899 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4900 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4901 pbn_b0_bt_2_460800 },
4902 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4903 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4904 pbn_b0_bt_2_460800 },
4905 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4906 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4907 pbn_b0_bt_1_115200 },
4908 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4909 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4910 pbn_b0_bt_1_460800 },
4911
4912 /*
4913 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4914 * Cards are identified by their subsystem vendor IDs, which
4915 * (in hex) match the model number.
4916 *
4917 * Note that JC140x are RS422/485 cards which require ox950
4918 * ACR = 0x10, and as such are not currently fully supported.
4919 */
4920 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4921 0x1204, 0x0004, 0, 0,
4922 pbn_b0_4_921600 },
4923 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4924 0x1208, 0x0004, 0, 0,
4925 pbn_b0_4_921600 },
4926 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4927 0x1402, 0x0002, 0, 0,
4928 pbn_b0_2_921600 }, */
4929 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4930 0x1404, 0x0004, 0, 0,
4931 pbn_b0_4_921600 }, */
4932 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
4933 0x1208, 0x0004, 0, 0,
4934 pbn_b0_4_921600 },
4935
4936 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4937 0x1204, 0x0004, 0, 0,
4938 pbn_b0_4_921600 },
4939 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4940 0x1208, 0x0004, 0, 0,
4941 pbn_b0_4_921600 },
4942 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
4943 0x1208, 0x0004, 0, 0,
4944 pbn_b0_4_921600 },
4945 /*
4946 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
4947 */
4948 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
4949 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4950 pbn_b1_1_1382400 },
4951
4952 /*
4953 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
4954 */
4955 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
4956 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4957 pbn_b1_1_1382400 },
4958
4959 /*
4960 * RAStel 2 port modem, gerg@moreton.com.au
4961 */
4962 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
4963 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4964 pbn_b2_bt_2_115200 },
4965
4966 /*
4967 * EKF addition for i960 Boards form EKF with serial port
4968 */
4969 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
4970 0xE4BF, PCI_ANY_ID, 0, 0,
4971 pbn_intel_i960 },
4972
4973 /*
4974 * Xircom Cardbus/Ethernet combos
4975 */
4976 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
4977 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4978 pbn_b0_1_115200 },
4979 /*
4980 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
4981 */
4982 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
4983 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4984 pbn_b0_1_115200 },
4985
4986 /*
4987 * Untested PCI modems, sent in from various folks...
4988 */
4989
4990 /*
4991 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
4992 */
4993 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
4994 0x1048, 0x1500, 0, 0,
4995 pbn_b1_1_115200 },
4996
4997 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
4998 0xFF00, 0, 0, 0,
4999 pbn_sgi_ioc3 },
5000
5001 /*
5002 * HP Diva card
5003 */
5004 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5005 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
5006 pbn_b1_1_115200 },
5007 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5008 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5009 pbn_b0_5_115200 },
5010 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
5011 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5012 pbn_b2_1_115200 },
5013 /* HPE PCI serial device */
5014 { PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL,
5015 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5016 pbn_b1_1_115200 },
5017
5018 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
5019 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5020 pbn_b3_2_115200 },
5021 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
5022 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5023 pbn_b3_4_115200 },
5024 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
5025 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5026 pbn_b3_8_115200 },
5027 /*
5028 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
5029 */
5030 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7951,
5031 PCI_ANY_ID, PCI_ANY_ID,
5032 0,
5033 0, pbn_pericom_PI7C9X7951 },
5034 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7952,
5035 PCI_ANY_ID, PCI_ANY_ID,
5036 0,
5037 0, pbn_pericom_PI7C9X7952 },
5038 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7954,
5039 PCI_ANY_ID, PCI_ANY_ID,
5040 0,
5041 0, pbn_pericom_PI7C9X7954 },
5042 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7958,
5043 PCI_ANY_ID, PCI_ANY_ID,
5044 0,
5045 0, pbn_pericom_PI7C9X7958 },
5046 /*
5047 * ACCES I/O Products quad
5048 */
5049 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB,
5050 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5051 pbn_pericom_PI7C9X7952 },
5052 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S,
5053 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5054 pbn_pericom_PI7C9X7952 },
5055 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB,
5056 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5057 pbn_pericom_PI7C9X7954 },
5058 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S,
5059 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5060 pbn_pericom_PI7C9X7954 },
5061 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB,
5062 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5063 pbn_pericom_PI7C9X7952 },
5064 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2,
5065 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5066 pbn_pericom_PI7C9X7952 },
5067 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB,
5068 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5069 pbn_pericom_PI7C9X7954 },
5070 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4,
5071 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5072 pbn_pericom_PI7C9X7954 },
5073 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB,
5074 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5075 pbn_pericom_PI7C9X7952 },
5076 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM,
5077 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5078 pbn_pericom_PI7C9X7952 },
5079 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB,
5080 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5081 pbn_pericom_PI7C9X7954 },
5082 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM,
5083 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5084 pbn_pericom_PI7C9X7954 },
5085 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1,
5086 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5087 pbn_pericom_PI7C9X7951 },
5088 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2,
5089 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5090 pbn_pericom_PI7C9X7952 },
5091 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2,
5092 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5093 pbn_pericom_PI7C9X7952 },
5094 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4,
5095 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5096 pbn_pericom_PI7C9X7954 },
5097 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4,
5098 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5099 pbn_pericom_PI7C9X7954 },
5100 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S,
5101 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5102 pbn_pericom_PI7C9X7952 },
5103 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S,
5104 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5105 pbn_pericom_PI7C9X7954 },
5106 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2,
5107 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5108 pbn_pericom_PI7C9X7952 },
5109 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2,
5110 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5111 pbn_pericom_PI7C9X7952 },
5112 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4,
5113 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5114 pbn_pericom_PI7C9X7954 },
5115 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4,
5116 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5117 pbn_pericom_PI7C9X7954 },
5118 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM,
5119 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5120 pbn_pericom_PI7C9X7952 },
5121 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4,
5122 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5123 pbn_pericom_PI7C9X7954 },
5124 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4,
5125 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5126 pbn_pericom_PI7C9X7954 },
5127 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8,
5128 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5129 pbn_pericom_PI7C9X7958 },
5130 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8,
5131 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5132 pbn_pericom_PI7C9X7958 },
5133 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4,
5134 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5135 pbn_pericom_PI7C9X7954 },
5136 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8,
5137 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5138 pbn_pericom_PI7C9X7958 },
5139 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM,
5140 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5141 pbn_pericom_PI7C9X7954 },
5142 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM,
5143 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5144 pbn_pericom_PI7C9X7958 },
5145 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM,
5146 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5147 pbn_pericom_PI7C9X7954 },
5148 /*
5149 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
5150 */
5151 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
5152 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5153 pbn_b0_1_115200 },
5154 /*
5155 * ITE
5156 */
5157 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
5158 PCI_ANY_ID, PCI_ANY_ID,
5159 0, 0,
5160 pbn_b1_bt_1_115200 },
5161
5162 /*
5163 * IntaShield IS-200
5164 */
5165 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
5166 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
5167 pbn_b2_2_115200 },
5168 /*
5169 * IntaShield IS-400
5170 */
5171 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
5172 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
5173 pbn_b2_4_115200 },
5174 /* Brainboxes Devices */
5175 /*
5176 * Brainboxes UC-101
5177 */
5178 { PCI_VENDOR_ID_INTASHIELD, 0x0BA1,
5179 PCI_ANY_ID, PCI_ANY_ID,
5180 0, 0,
5181 pbn_b2_2_115200 },
5182 /*
5183 * Brainboxes UC-235/246
5184 */
5185 { PCI_VENDOR_ID_INTASHIELD, 0x0AA1,
5186 PCI_ANY_ID, PCI_ANY_ID,
5187 0, 0,
5188 pbn_b2_1_115200 },
5189 /*
5190 * Brainboxes UC-257
5191 */
5192 { PCI_VENDOR_ID_INTASHIELD, 0x0861,
5193 PCI_ANY_ID, PCI_ANY_ID,
5194 0, 0,
5195 pbn_b2_2_115200 },
5196 /*
5197 * Brainboxes UC-260/271/701/756
5198 */
5199 { PCI_VENDOR_ID_INTASHIELD, 0x0D21,
5200 PCI_ANY_ID, PCI_ANY_ID,
5201 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
5202 pbn_b2_4_115200 },
5203 { PCI_VENDOR_ID_INTASHIELD, 0x0E34,
5204 PCI_ANY_ID, PCI_ANY_ID,
5205 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
5206 pbn_b2_4_115200 },
5207 /*
5208 * Brainboxes UC-268
5209 */
5210 { PCI_VENDOR_ID_INTASHIELD, 0x0841,
5211 PCI_ANY_ID, PCI_ANY_ID,
5212 0, 0,
5213 pbn_b2_4_115200 },
5214 /*
5215 * Brainboxes UC-275/279
5216 */
5217 { PCI_VENDOR_ID_INTASHIELD, 0x0881,
5218 PCI_ANY_ID, PCI_ANY_ID,
5219 0, 0,
5220 pbn_b2_8_115200 },
5221 /*
5222 * Brainboxes UC-302
5223 */
5224 { PCI_VENDOR_ID_INTASHIELD, 0x08E1,
5225 PCI_ANY_ID, PCI_ANY_ID,
5226 0, 0,
5227 pbn_b2_2_115200 },
5228 /*
5229 * Brainboxes UC-310
5230 */
5231 { PCI_VENDOR_ID_INTASHIELD, 0x08C1,
5232 PCI_ANY_ID, PCI_ANY_ID,
5233 0, 0,
5234 pbn_b2_2_115200 },
5235 /*
5236 * Brainboxes UC-313
5237 */
5238 { PCI_VENDOR_ID_INTASHIELD, 0x08A3,
5239 PCI_ANY_ID, PCI_ANY_ID,
5240 0, 0,
5241 pbn_b2_2_115200 },
5242 /*
5243 * Brainboxes UC-320/324
5244 */
5245 { PCI_VENDOR_ID_INTASHIELD, 0x0A61,
5246 PCI_ANY_ID, PCI_ANY_ID,
5247 0, 0,
5248 pbn_b2_1_115200 },
5249 /*
5250 * Brainboxes UC-346
5251 */
5252 { PCI_VENDOR_ID_INTASHIELD, 0x0B02,
5253 PCI_ANY_ID, PCI_ANY_ID,
5254 0, 0,
5255 pbn_b2_4_115200 },
5256 /*
5257 * Brainboxes UC-357
5258 */
5259 { PCI_VENDOR_ID_INTASHIELD, 0x0A81,
5260 PCI_ANY_ID, PCI_ANY_ID,
5261 0, 0,
5262 pbn_b2_2_115200 },
5263 { PCI_VENDOR_ID_INTASHIELD, 0x0A83,
5264 PCI_ANY_ID, PCI_ANY_ID,
5265 0, 0,
5266 pbn_b2_2_115200 },
5267 /*
5268 * Brainboxes UC-368
5269 */
5270 { PCI_VENDOR_ID_INTASHIELD, 0x0C41,
5271 PCI_ANY_ID, PCI_ANY_ID,
5272 0, 0,
5273 pbn_b2_4_115200 },
5274 /*
5275 * Brainboxes UC-420/431
5276 */
5277 { PCI_VENDOR_ID_INTASHIELD, 0x0921,
5278 PCI_ANY_ID, PCI_ANY_ID,
5279 0, 0,
5280 pbn_b2_4_115200 },
5281 /*
5282 * Perle PCI-RAS cards
5283 */
5284 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5285 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
5286 0, 0, pbn_b2_4_921600 },
5287 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5288 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
5289 0, 0, pbn_b2_8_921600 },
5290
5291 /*
5292 * Mainpine series cards: Fairly standard layout but fools
5293 * parts of the autodetect in some cases and uses otherwise
5294 * unmatched communications subclasses in the PCI Express case
5295 */
5296
5297 { /* RockForceDUO */
5298 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5299 PCI_VENDOR_ID_MAINPINE, 0x0200,
5300 0, 0, pbn_b0_2_115200 },
5301 { /* RockForceQUATRO */
5302 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5303 PCI_VENDOR_ID_MAINPINE, 0x0300,
5304 0, 0, pbn_b0_4_115200 },
5305 { /* RockForceDUO+ */
5306 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5307 PCI_VENDOR_ID_MAINPINE, 0x0400,
5308 0, 0, pbn_b0_2_115200 },
5309 { /* RockForceQUATRO+ */
5310 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5311 PCI_VENDOR_ID_MAINPINE, 0x0500,
5312 0, 0, pbn_b0_4_115200 },
5313 { /* RockForce+ */
5314 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5315 PCI_VENDOR_ID_MAINPINE, 0x0600,
5316 0, 0, pbn_b0_2_115200 },
5317 { /* RockForce+ */
5318 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5319 PCI_VENDOR_ID_MAINPINE, 0x0700,
5320 0, 0, pbn_b0_4_115200 },
5321 { /* RockForceOCTO+ */
5322 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5323 PCI_VENDOR_ID_MAINPINE, 0x0800,
5324 0, 0, pbn_b0_8_115200 },
5325 { /* RockForceDUO+ */
5326 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5327 PCI_VENDOR_ID_MAINPINE, 0x0C00,
5328 0, 0, pbn_b0_2_115200 },
5329 { /* RockForceQUARTRO+ */
5330 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5331 PCI_VENDOR_ID_MAINPINE, 0x0D00,
5332 0, 0, pbn_b0_4_115200 },
5333 { /* RockForceOCTO+ */
5334 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5335 PCI_VENDOR_ID_MAINPINE, 0x1D00,
5336 0, 0, pbn_b0_8_115200 },
5337 { /* RockForceD1 */
5338 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5339 PCI_VENDOR_ID_MAINPINE, 0x2000,
5340 0, 0, pbn_b0_1_115200 },
5341 { /* RockForceF1 */
5342 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5343 PCI_VENDOR_ID_MAINPINE, 0x2100,
5344 0, 0, pbn_b0_1_115200 },
5345 { /* RockForceD2 */
5346 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5347 PCI_VENDOR_ID_MAINPINE, 0x2200,
5348 0, 0, pbn_b0_2_115200 },
5349 { /* RockForceF2 */
5350 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5351 PCI_VENDOR_ID_MAINPINE, 0x2300,
5352 0, 0, pbn_b0_2_115200 },
5353 { /* RockForceD4 */
5354 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5355 PCI_VENDOR_ID_MAINPINE, 0x2400,
5356 0, 0, pbn_b0_4_115200 },
5357 { /* RockForceF4 */
5358 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5359 PCI_VENDOR_ID_MAINPINE, 0x2500,
5360 0, 0, pbn_b0_4_115200 },
5361 { /* RockForceD8 */
5362 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5363 PCI_VENDOR_ID_MAINPINE, 0x2600,
5364 0, 0, pbn_b0_8_115200 },
5365 { /* RockForceF8 */
5366 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5367 PCI_VENDOR_ID_MAINPINE, 0x2700,
5368 0, 0, pbn_b0_8_115200 },
5369 { /* IQ Express D1 */
5370 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5371 PCI_VENDOR_ID_MAINPINE, 0x3000,
5372 0, 0, pbn_b0_1_115200 },
5373 { /* IQ Express F1 */
5374 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5375 PCI_VENDOR_ID_MAINPINE, 0x3100,
5376 0, 0, pbn_b0_1_115200 },
5377 { /* IQ Express D2 */
5378 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5379 PCI_VENDOR_ID_MAINPINE, 0x3200,
5380 0, 0, pbn_b0_2_115200 },
5381 { /* IQ Express F2 */
5382 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5383 PCI_VENDOR_ID_MAINPINE, 0x3300,
5384 0, 0, pbn_b0_2_115200 },
5385 { /* IQ Express D4 */
5386 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5387 PCI_VENDOR_ID_MAINPINE, 0x3400,
5388 0, 0, pbn_b0_4_115200 },
5389 { /* IQ Express F4 */
5390 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5391 PCI_VENDOR_ID_MAINPINE, 0x3500,
5392 0, 0, pbn_b0_4_115200 },
5393 { /* IQ Express D8 */
5394 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5395 PCI_VENDOR_ID_MAINPINE, 0x3C00,
5396 0, 0, pbn_b0_8_115200 },
5397 { /* IQ Express F8 */
5398 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5399 PCI_VENDOR_ID_MAINPINE, 0x3D00,
5400 0, 0, pbn_b0_8_115200 },
5401
5402
5403 /*
5404 * PA Semi PA6T-1682M on-chip UART
5405 */
5406 { PCI_VENDOR_ID_PASEMI, 0xa004,
5407 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5408 pbn_pasemi_1682M },
5409
5410 /*
5411 * National Instruments
5412 */
5413 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
5414 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5415 pbn_b1_16_115200 },
5416 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
5417 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5418 pbn_b1_8_115200 },
5419 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
5420 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5421 pbn_b1_bt_4_115200 },
5422 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
5423 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5424 pbn_b1_bt_2_115200 },
5425 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
5426 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5427 pbn_b1_bt_4_115200 },
5428 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
5429 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5430 pbn_b1_bt_2_115200 },
5431 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
5432 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5433 pbn_b1_16_115200 },
5434 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
5435 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5436 pbn_b1_8_115200 },
5437 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
5438 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5439 pbn_b1_bt_4_115200 },
5440 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
5441 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5442 pbn_b1_bt_2_115200 },
5443 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
5444 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5445 pbn_b1_bt_4_115200 },
5446 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
5447 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5448 pbn_b1_bt_2_115200 },
5449 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
5450 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5451 pbn_ni8430_2 },
5452 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
5453 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5454 pbn_ni8430_2 },
5455 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
5456 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5457 pbn_ni8430_4 },
5458 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
5459 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5460 pbn_ni8430_4 },
5461 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
5462 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5463 pbn_ni8430_8 },
5464 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
5465 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5466 pbn_ni8430_8 },
5467 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
5468 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5469 pbn_ni8430_16 },
5470 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
5471 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5472 pbn_ni8430_16 },
5473 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
5474 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5475 pbn_ni8430_2 },
5476 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
5477 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5478 pbn_ni8430_2 },
5479 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
5480 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5481 pbn_ni8430_4 },
5482 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
5483 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5484 pbn_ni8430_4 },
5485
5486 /*
5487 * MOXA
5488 */
5489 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102E,
5490 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5491 pbn_moxa8250_2p },
5492 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102EL,
5493 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5494 pbn_moxa8250_2p },
5495 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP104EL_A,
5496 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5497 pbn_moxa8250_4p },
5498 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP114EL,
5499 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5500 pbn_moxa8250_4p },
5501 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_A,
5502 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5503 pbn_moxa8250_8p },
5504 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_B,
5505 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5506 pbn_moxa8250_8p },
5507 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118EL_A,
5508 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5509 pbn_moxa8250_8p },
5510 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118E_A_I,
5511 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5512 pbn_moxa8250_8p },
5513 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP132EL,
5514 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5515 pbn_moxa8250_2p },
5516 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP134EL_A,
5517 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5518 pbn_moxa8250_4p },
5519 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP138E_A,
5520 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5521 pbn_moxa8250_8p },
5522 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP168EL_A,
5523 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5524 pbn_moxa8250_8p },
5525
5526 /*
5527 * ADDI-DATA GmbH communication cards <info@addi-data.com>
5528 */
5529 { PCI_VENDOR_ID_ADDIDATA,
5530 PCI_DEVICE_ID_ADDIDATA_APCI7500,
5531 PCI_ANY_ID,
5532 PCI_ANY_ID,
5533 0,
5534 0,
5535 pbn_b0_4_115200 },
5536
5537 { PCI_VENDOR_ID_ADDIDATA,
5538 PCI_DEVICE_ID_ADDIDATA_APCI7420,
5539 PCI_ANY_ID,
5540 PCI_ANY_ID,
5541 0,
5542 0,
5543 pbn_b0_2_115200 },
5544
5545 { PCI_VENDOR_ID_ADDIDATA,
5546 PCI_DEVICE_ID_ADDIDATA_APCI7300,
5547 PCI_ANY_ID,
5548 PCI_ANY_ID,
5549 0,
5550 0,
5551 pbn_b0_1_115200 },
5552
5553 { PCI_VENDOR_ID_AMCC,
5554 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
5555 PCI_ANY_ID,
5556 PCI_ANY_ID,
5557 0,
5558 0,
5559 pbn_b1_8_115200 },
5560
5561 { PCI_VENDOR_ID_ADDIDATA,
5562 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5563 PCI_ANY_ID,
5564 PCI_ANY_ID,
5565 0,
5566 0,
5567 pbn_b0_4_115200 },
5568
5569 { PCI_VENDOR_ID_ADDIDATA,
5570 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5571 PCI_ANY_ID,
5572 PCI_ANY_ID,
5573 0,
5574 0,
5575 pbn_b0_2_115200 },
5576
5577 { PCI_VENDOR_ID_ADDIDATA,
5578 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5579 PCI_ANY_ID,
5580 PCI_ANY_ID,
5581 0,
5582 0,
5583 pbn_b0_1_115200 },
5584
5585 { PCI_VENDOR_ID_ADDIDATA,
5586 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5587 PCI_ANY_ID,
5588 PCI_ANY_ID,
5589 0,
5590 0,
5591 pbn_b0_4_115200 },
5592
5593 { PCI_VENDOR_ID_ADDIDATA,
5594 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5595 PCI_ANY_ID,
5596 PCI_ANY_ID,
5597 0,
5598 0,
5599 pbn_b0_2_115200 },
5600
5601 { PCI_VENDOR_ID_ADDIDATA,
5602 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5603 PCI_ANY_ID,
5604 PCI_ANY_ID,
5605 0,
5606 0,
5607 pbn_b0_1_115200 },
5608
5609 { PCI_VENDOR_ID_ADDIDATA,
5610 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5611 PCI_ANY_ID,
5612 PCI_ANY_ID,
5613 0,
5614 0,
5615 pbn_b0_8_115200 },
5616
5617 { PCI_VENDOR_ID_ADDIDATA,
5618 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5619 PCI_ANY_ID,
5620 PCI_ANY_ID,
5621 0,
5622 0,
5623 pbn_ADDIDATA_PCIe_4_3906250 },
5624
5625 { PCI_VENDOR_ID_ADDIDATA,
5626 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5627 PCI_ANY_ID,
5628 PCI_ANY_ID,
5629 0,
5630 0,
5631 pbn_ADDIDATA_PCIe_2_3906250 },
5632
5633 { PCI_VENDOR_ID_ADDIDATA,
5634 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5635 PCI_ANY_ID,
5636 PCI_ANY_ID,
5637 0,
5638 0,
5639 pbn_ADDIDATA_PCIe_1_3906250 },
5640
5641 { PCI_VENDOR_ID_ADDIDATA,
5642 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5643 PCI_ANY_ID,
5644 PCI_ANY_ID,
5645 0,
5646 0,
5647 pbn_ADDIDATA_PCIe_8_3906250 },
5648
5649 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5650 PCI_VENDOR_ID_IBM, 0x0299,
5651 0, 0, pbn_b0_bt_2_115200 },
5652
5653 /*
5654 * other NetMos 9835 devices are most likely handled by the
5655 * parport_serial driver, check drivers/parport/parport_serial.c
5656 * before adding them here.
5657 */
5658
5659 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5660 0xA000, 0x1000,
5661 0, 0, pbn_b0_1_115200 },
5662
5663 /* the 9901 is a rebranded 9912 */
5664 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5665 0xA000, 0x1000,
5666 0, 0, pbn_b0_1_115200 },
5667
5668 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5669 0xA000, 0x1000,
5670 0, 0, pbn_b0_1_115200 },
5671
5672 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5673 0xA000, 0x1000,
5674 0, 0, pbn_b0_1_115200 },
5675
5676 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5677 0xA000, 0x1000,
5678 0, 0, pbn_b0_1_115200 },
5679
5680 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5681 0xA000, 0x3002,
5682 0, 0, pbn_NETMOS9900_2s_115200 },
5683
5684 /*
5685 * Best Connectivity and Rosewill PCI Multi I/O cards
5686 */
5687
5688 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5689 0xA000, 0x1000,
5690 0, 0, pbn_b0_1_115200 },
5691
5692 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5693 0xA000, 0x3002,
5694 0, 0, pbn_b0_bt_2_115200 },
5695
5696 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5697 0xA000, 0x3004,
5698 0, 0, pbn_b0_bt_4_115200 },
5699 /* Intel CE4100 */
5700 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5701 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5702 pbn_ce4100_1_115200 },
5703
5704 /*
5705 * Cronyx Omega PCI
5706 */
5707 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5708 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5709 pbn_omegapci },
5710
5711 /*
5712 * Broadcom TruManage
5713 */
5714 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5715 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5716 pbn_brcm_trumanage },
5717
5718 /*
5719 * AgeStar as-prs2-009
5720 */
5721 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5722 PCI_ANY_ID, PCI_ANY_ID,
5723 0, 0, pbn_b0_bt_2_115200 },
5724
5725 /*
5726 * WCH CH353 series devices: The 2S1P is handled by parport_serial
5727 * so not listed here.
5728 */
5729 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5730 PCI_ANY_ID, PCI_ANY_ID,
5731 0, 0, pbn_b0_bt_4_115200 },
5732
5733 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5734 PCI_ANY_ID, PCI_ANY_ID,
5735 0, 0, pbn_b0_bt_2_115200 },
5736
5737 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH355_4S,
5738 PCI_ANY_ID, PCI_ANY_ID,
5739 0, 0, pbn_b0_bt_4_115200 },
5740
5741 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S,
5742 PCI_ANY_ID, PCI_ANY_ID,
5743 0, 0, pbn_wch382_2 },
5744
5745 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S,
5746 PCI_ANY_ID, PCI_ANY_ID,
5747 0, 0, pbn_wch384_4 },
5748
5749 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_8S,
5750 PCI_ANY_ID, PCI_ANY_ID,
5751 0, 0, pbn_wch384_8 },
5752 /*
5753 * Realtek RealManage
5754 */
5755 { PCI_VENDOR_ID_REALTEK, 0x816a,
5756 PCI_ANY_ID, PCI_ANY_ID,
5757 0, 0, pbn_b0_1_115200 },
5758
5759 { PCI_VENDOR_ID_REALTEK, 0x816b,
5760 PCI_ANY_ID, PCI_ANY_ID,
5761 0, 0, pbn_b0_1_115200 },
5762
5763 /* Fintek PCI serial cards */
5764 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5765 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5766 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5767 { PCI_DEVICE(0x1c29, 0x1204), .driver_data = pbn_fintek_F81504A },
5768 { PCI_DEVICE(0x1c29, 0x1208), .driver_data = pbn_fintek_F81508A },
5769 { PCI_DEVICE(0x1c29, 0x1212), .driver_data = pbn_fintek_F81512A },
5770
5771 /* MKS Tenta SCOM-080x serial cards */
5772 { PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 },
5773 { PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 },
5774
5775 /* Amazon PCI serial device */
5776 { PCI_DEVICE(0x1d0f, 0x8250), .driver_data = pbn_b0_1_115200 },
5777
5778 /*
5779 * These entries match devices with class COMMUNICATION_SERIAL,
5780 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5781 */
5782 { PCI_ANY_ID, PCI_ANY_ID,
5783 PCI_ANY_ID, PCI_ANY_ID,
5784 PCI_CLASS_COMMUNICATION_SERIAL << 8,
5785 0xffff00, pbn_default },
5786 { PCI_ANY_ID, PCI_ANY_ID,
5787 PCI_ANY_ID, PCI_ANY_ID,
5788 PCI_CLASS_COMMUNICATION_MODEM << 8,
5789 0xffff00, pbn_default },
5790 { PCI_ANY_ID, PCI_ANY_ID,
5791 PCI_ANY_ID, PCI_ANY_ID,
5792 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5793 0xffff00, pbn_default },
5794 { 0, }
5795 };
5796
serial8250_io_error_detected(struct pci_dev * dev,pci_channel_state_t state)5797 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5798 pci_channel_state_t state)
5799 {
5800 struct serial_private *priv = pci_get_drvdata(dev);
5801
5802 if (state == pci_channel_io_perm_failure)
5803 return PCI_ERS_RESULT_DISCONNECT;
5804
5805 if (priv)
5806 pciserial_detach_ports(priv);
5807
5808 pci_disable_device(dev);
5809
5810 return PCI_ERS_RESULT_NEED_RESET;
5811 }
5812
serial8250_io_slot_reset(struct pci_dev * dev)5813 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5814 {
5815 int rc;
5816
5817 rc = pci_enable_device(dev);
5818
5819 if (rc)
5820 return PCI_ERS_RESULT_DISCONNECT;
5821
5822 pci_restore_state(dev);
5823 pci_save_state(dev);
5824
5825 return PCI_ERS_RESULT_RECOVERED;
5826 }
5827
serial8250_io_resume(struct pci_dev * dev)5828 static void serial8250_io_resume(struct pci_dev *dev)
5829 {
5830 struct serial_private *priv = pci_get_drvdata(dev);
5831 struct serial_private *new;
5832
5833 if (!priv)
5834 return;
5835
5836 new = pciserial_init_ports(dev, priv->board);
5837 if (!IS_ERR(new)) {
5838 pci_set_drvdata(dev, new);
5839 kfree(priv);
5840 }
5841 }
5842
5843 static const struct pci_error_handlers serial8250_err_handler = {
5844 .error_detected = serial8250_io_error_detected,
5845 .slot_reset = serial8250_io_slot_reset,
5846 .resume = serial8250_io_resume,
5847 };
5848
5849 static struct pci_driver serial_pci_driver = {
5850 .name = "serial",
5851 .probe = pciserial_init_one,
5852 .remove = pciserial_remove_one,
5853 .driver = {
5854 .pm = &pciserial_pm_ops,
5855 },
5856 .id_table = serial_pci_tbl,
5857 .err_handler = &serial8250_err_handler,
5858 };
5859
5860 module_pci_driver(serial_pci_driver);
5861
5862 MODULE_LICENSE("GPL");
5863 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5864 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
5865