1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * xHCI host controller driver PCI Bus Glue.
4 *
5 * Copyright (C) 2008 Intel Corp.
6 *
7 * Author: Sarah Sharp
8 * Some code borrowed from the Linux EHCI driver.
9 */
10
11 #include <linux/pci.h>
12 #include <linux/slab.h>
13 #include <linux/module.h>
14 #include <linux/acpi.h>
15 #include <linux/reset.h>
16
17 #include "xhci.h"
18 #include "xhci-trace.h"
19 #include "xhci-pci.h"
20
21 #define SSIC_PORT_NUM 2
22 #define SSIC_PORT_CFG2 0x880c
23 #define SSIC_PORT_CFG2_OFFSET 0x30
24 #define PROG_DONE (1 << 30)
25 #define SSIC_PORT_UNUSED (1 << 31)
26 #define SPARSE_DISABLE_BIT 17
27 #define SPARSE_CNTL_ENABLE 0xC12C
28
29 /* Device for a quirk */
30 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73
31 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000
32 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009
33 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1100 0x1100
34 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400
35
36 #define PCI_VENDOR_ID_ETRON 0x1b6f
37 #define PCI_DEVICE_ID_EJ168 0x7023
38
39 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31
40 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31
41 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1
42 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5
43 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f
44 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f
45 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8
46 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8
47 #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8
48 #define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0
49 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI 0x15b5
50 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI 0x15b6
51 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI 0x15c1
52 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI 0x15db
53 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI 0x15d4
54 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI 0x15e9
55 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI 0x15ec
56 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI 0x15f0
57 #define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI 0x8a13
58 #define PCI_DEVICE_ID_INTEL_CML_XHCI 0xa3af
59 #define PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI 0x9a13
60 #define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI 0x1138
61 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_XHCI 0x461e
62
63 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9
64 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba
65 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb
66 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc
67 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_1 0x161a
68 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_2 0x161b
69 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_3 0x161d
70 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_4 0x161e
71 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_5 0x15d6
72 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_6 0x15d7
73 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_7 0x161c
74 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_8 0x161f
75
76 #define PCI_DEVICE_ID_ASMEDIA_1042_XHCI 0x1042
77 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142
78 #define PCI_DEVICE_ID_ASMEDIA_1142_XHCI 0x1242
79 #define PCI_DEVICE_ID_ASMEDIA_2142_XHCI 0x2142
80 #define PCI_DEVICE_ID_ASMEDIA_3242_XHCI 0x3242
81
82 static const char hcd_name[] = "xhci_hcd";
83
84 static struct hc_driver __read_mostly xhci_pci_hc_driver;
85
86 static int xhci_pci_setup(struct usb_hcd *hcd);
87
88 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
89 .reset = xhci_pci_setup,
90 };
91
92 /* called after powerup, by probe or system-pm "wakeup" */
xhci_pci_reinit(struct xhci_hcd * xhci,struct pci_dev * pdev)93 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
94 {
95 /*
96 * TODO: Implement finding debug ports later.
97 * TODO: see if there are any quirks that need to be added to handle
98 * new extended capabilities.
99 */
100
101 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
102 if (!pci_set_mwi(pdev))
103 xhci_dbg(xhci, "MWI active\n");
104
105 xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
106 return 0;
107 }
108
xhci_pci_quirks(struct device * dev,struct xhci_hcd * xhci)109 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
110 {
111 struct pci_dev *pdev = to_pci_dev(dev);
112 struct xhci_driver_data *driver_data;
113 const struct pci_device_id *id;
114
115 id = pci_match_id(pdev->driver->id_table, pdev);
116
117 if (id && id->driver_data) {
118 driver_data = (struct xhci_driver_data *)id->driver_data;
119 xhci->quirks |= driver_data->quirks;
120 }
121
122 /* Look for vendor-specific quirks */
123 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
124 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
125 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
126 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
127 pdev->revision == 0x0) {
128 xhci->quirks |= XHCI_RESET_EP_QUIRK;
129 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
130 "QUIRK: Fresco Logic xHC needs configure"
131 " endpoint cmd after reset endpoint");
132 }
133 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
134 pdev->revision == 0x4) {
135 xhci->quirks |= XHCI_SLOW_SUSPEND;
136 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
137 "QUIRK: Fresco Logic xHC revision %u"
138 "must be suspended extra slowly",
139 pdev->revision);
140 }
141 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
142 xhci->quirks |= XHCI_BROKEN_STREAMS;
143 /* Fresco Logic confirms: all revisions of this chip do not
144 * support MSI, even though some of them claim to in their PCI
145 * capabilities.
146 */
147 xhci->quirks |= XHCI_BROKEN_MSI;
148 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
149 "QUIRK: Fresco Logic revision %u "
150 "has broken MSI implementation",
151 pdev->revision);
152 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
153 }
154
155 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
156 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
157 xhci->quirks |= XHCI_BROKEN_STREAMS;
158
159 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
160 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1100)
161 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
162
163 if (pdev->vendor == PCI_VENDOR_ID_NEC)
164 xhci->quirks |= XHCI_NEC_HOST;
165
166 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
167 xhci->quirks |= XHCI_AMD_0x96_HOST;
168
169 /* AMD PLL quirk */
170 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check())
171 xhci->quirks |= XHCI_AMD_PLL_FIX;
172
173 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
174 (pdev->device == 0x145c ||
175 pdev->device == 0x15e0 ||
176 pdev->device == 0x15e1 ||
177 pdev->device == 0x43bb))
178 xhci->quirks |= XHCI_SUSPEND_DELAY;
179
180 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
181 (pdev->device == 0x15e0 || pdev->device == 0x15e1))
182 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND;
183
184 if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5) {
185 xhci->quirks |= XHCI_DISABLE_SPARSE;
186 xhci->quirks |= XHCI_RESET_ON_RESUME;
187 }
188
189 if (pdev->vendor == PCI_VENDOR_ID_AMD)
190 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
191
192 if ((pdev->vendor == PCI_VENDOR_ID_AMD) &&
193 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) ||
194 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) ||
195 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) ||
196 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1)))
197 xhci->quirks |= XHCI_U2_DISABLE_WAKE;
198
199 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
200 xhci->quirks |= XHCI_LPM_SUPPORT;
201 xhci->quirks |= XHCI_INTEL_HOST;
202 xhci->quirks |= XHCI_AVOID_BEI;
203 }
204 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
205 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
206 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
207 xhci->limit_active_eps = 64;
208 xhci->quirks |= XHCI_SW_BW_CHECKING;
209 /*
210 * PPT desktop boards DH77EB and DH77DF will power back on after
211 * a few seconds of being shutdown. The fix for this is to
212 * switch the ports from xHCI to EHCI on shutdown. We can't use
213 * DMI information to find those particular boards (since each
214 * vendor will change the board name), so we have to key off all
215 * PPT chipsets.
216 */
217 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
218 }
219 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
220 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
221 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
222 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
223 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
224 }
225 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
226 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
227 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
228 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
229 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
230 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
231 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
232 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI ||
233 pdev->device == PCI_DEVICE_ID_INTEL_CML_XHCI)) {
234 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
235 }
236 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
237 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI)
238 xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
239 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
240 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
241 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
242 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI))
243 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW;
244 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
245 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
246 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
247 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
248 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
249 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI))
250 xhci->quirks |= XHCI_MISSING_CAS;
251
252 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
253 (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI ||
254 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI ||
255 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI ||
256 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI ||
257 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI ||
258 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI ||
259 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI ||
260 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI ||
261 pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI ||
262 pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI ||
263 pdev->device == PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI ||
264 pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_XHCI))
265 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
266
267 if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
268 pdev->device == PCI_DEVICE_ID_EJ168) {
269 xhci->quirks |= XHCI_RESET_ON_RESUME;
270 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
271 xhci->quirks |= XHCI_BROKEN_STREAMS;
272 }
273 if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
274 pdev->device == 0x0014) {
275 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
276 xhci->quirks |= XHCI_ZERO_64B_REGS;
277 }
278 if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
279 pdev->device == 0x0015) {
280 xhci->quirks |= XHCI_RESET_ON_RESUME;
281 xhci->quirks |= XHCI_ZERO_64B_REGS;
282 }
283 if (pdev->vendor == PCI_VENDOR_ID_VIA)
284 xhci->quirks |= XHCI_RESET_ON_RESUME;
285
286 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
287 if (pdev->vendor == PCI_VENDOR_ID_VIA &&
288 pdev->device == 0x3432)
289 xhci->quirks |= XHCI_BROKEN_STREAMS;
290
291 if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483) {
292 xhci->quirks |= XHCI_LPM_SUPPORT;
293 xhci->quirks |= XHCI_EP_CTX_BROKEN_DCS;
294 }
295
296 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
297 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI)
298 xhci->quirks |= XHCI_BROKEN_STREAMS;
299 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
300 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) {
301 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
302 xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
303 }
304 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
305 (pdev->device == PCI_DEVICE_ID_ASMEDIA_1142_XHCI ||
306 pdev->device == PCI_DEVICE_ID_ASMEDIA_2142_XHCI ||
307 pdev->device == PCI_DEVICE_ID_ASMEDIA_3242_XHCI))
308 xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
309
310 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
311 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
312 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL;
313
314 if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241)
315 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7;
316
317 if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM ||
318 pdev->vendor == PCI_VENDOR_ID_CAVIUM) &&
319 pdev->device == 0x9026)
320 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT;
321
322 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
323 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2 ||
324 pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4))
325 xhci->quirks |= XHCI_NO_SOFT_RETRY;
326
327 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
328 (pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_1 ||
329 pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_2 ||
330 pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_3 ||
331 pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_4 ||
332 pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_5 ||
333 pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_6 ||
334 pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_7 ||
335 pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_8))
336 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
337
338 if (xhci->quirks & XHCI_RESET_ON_RESUME)
339 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
340 "QUIRK: Resetting on resume");
341 }
342
343 #ifdef CONFIG_ACPI
xhci_pme_acpi_rtd3_enable(struct pci_dev * dev)344 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
345 {
346 static const guid_t intel_dsm_guid =
347 GUID_INIT(0xac340cb7, 0xe901, 0x45bf,
348 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23);
349 union acpi_object *obj;
350
351 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1,
352 NULL);
353 ACPI_FREE(obj);
354 }
355 #else
xhci_pme_acpi_rtd3_enable(struct pci_dev * dev)356 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
357 #endif /* CONFIG_ACPI */
358
359 /* called during probe() after chip reset completes */
xhci_pci_setup(struct usb_hcd * hcd)360 static int xhci_pci_setup(struct usb_hcd *hcd)
361 {
362 struct xhci_hcd *xhci;
363 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
364 int retval;
365
366 xhci = hcd_to_xhci(hcd);
367 if (!xhci->sbrn)
368 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
369
370 /* imod_interval is the interrupt moderation value in nanoseconds. */
371 xhci->imod_interval = 40000;
372
373 retval = xhci_gen_setup(hcd, xhci_pci_quirks);
374 if (retval)
375 return retval;
376
377 if (!usb_hcd_is_primary_hcd(hcd))
378 return 0;
379
380 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
381 xhci_pme_acpi_rtd3_enable(pdev);
382
383 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
384
385 /* Find any debug ports */
386 return xhci_pci_reinit(xhci, pdev);
387 }
388
389 /*
390 * We need to register our own PCI probe function (instead of the USB core's
391 * function) in order to create a second roothub under xHCI.
392 */
xhci_pci_probe(struct pci_dev * dev,const struct pci_device_id * id)393 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
394 {
395 int retval;
396 struct xhci_hcd *xhci;
397 struct usb_hcd *hcd;
398 struct xhci_driver_data *driver_data;
399 struct reset_control *reset;
400
401 driver_data = (struct xhci_driver_data *)id->driver_data;
402 if (driver_data && driver_data->quirks & XHCI_RENESAS_FW_QUIRK) {
403 retval = renesas_xhci_check_request_fw(dev, id);
404 if (retval)
405 return retval;
406 }
407
408 reset = devm_reset_control_get_optional_exclusive(&dev->dev, NULL);
409 if (IS_ERR(reset))
410 return PTR_ERR(reset);
411 reset_control_reset(reset);
412
413 /* Prevent runtime suspending between USB-2 and USB-3 initialization */
414 pm_runtime_get_noresume(&dev->dev);
415
416 /* Register the USB 2.0 roothub.
417 * FIXME: USB core must know to register the USB 2.0 roothub first.
418 * This is sort of silly, because we could just set the HCD driver flags
419 * to say USB 2.0, but I'm not sure what the implications would be in
420 * the other parts of the HCD code.
421 */
422 retval = usb_hcd_pci_probe(dev, id, &xhci_pci_hc_driver);
423
424 if (retval)
425 goto put_runtime_pm;
426
427 /* USB 2.0 roothub is stored in the PCI device now. */
428 hcd = dev_get_drvdata(&dev->dev);
429 xhci = hcd_to_xhci(hcd);
430 xhci->reset = reset;
431 xhci->shared_hcd = usb_create_shared_hcd(&xhci_pci_hc_driver, &dev->dev,
432 pci_name(dev), hcd);
433 if (!xhci->shared_hcd) {
434 retval = -ENOMEM;
435 goto dealloc_usb2_hcd;
436 }
437
438 retval = xhci_ext_cap_init(xhci);
439 if (retval)
440 goto put_usb3_hcd;
441
442 retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
443 IRQF_SHARED);
444 if (retval)
445 goto put_usb3_hcd;
446 /* Roothub already marked as USB 3.0 speed */
447
448 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
449 HCC_MAX_PSA(xhci->hcc_params) >= 4)
450 xhci->shared_hcd->can_do_streams = 1;
451
452 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
453 pm_runtime_put_noidle(&dev->dev);
454
455 if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
456 pm_runtime_allow(&dev->dev);
457
458 return 0;
459
460 put_usb3_hcd:
461 usb_put_hcd(xhci->shared_hcd);
462 dealloc_usb2_hcd:
463 usb_hcd_pci_remove(dev);
464 put_runtime_pm:
465 pm_runtime_put_noidle(&dev->dev);
466 return retval;
467 }
468
xhci_pci_remove(struct pci_dev * dev)469 static void xhci_pci_remove(struct pci_dev *dev)
470 {
471 struct xhci_hcd *xhci;
472
473 xhci = hcd_to_xhci(pci_get_drvdata(dev));
474 if (xhci->quirks & XHCI_RENESAS_FW_QUIRK)
475 renesas_xhci_pci_exit(dev);
476
477 xhci->xhc_state |= XHCI_STATE_REMOVING;
478
479 if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
480 pm_runtime_forbid(&dev->dev);
481
482 if (xhci->shared_hcd) {
483 usb_remove_hcd(xhci->shared_hcd);
484 usb_put_hcd(xhci->shared_hcd);
485 xhci->shared_hcd = NULL;
486 }
487
488 /* Workaround for spurious wakeups at shutdown with HSW */
489 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
490 pci_set_power_state(dev, PCI_D3hot);
491
492 usb_hcd_pci_remove(dev);
493 }
494
495 #ifdef CONFIG_PM
496 /*
497 * In some Intel xHCI controllers, in order to get D3 working,
498 * through a vendor specific SSIC CONFIG register at offset 0x883c,
499 * SSIC PORT need to be marked as "unused" before putting xHCI
500 * into D3. After D3 exit, the SSIC port need to be marked as "used".
501 * Without this change, xHCI might not enter D3 state.
502 */
xhci_ssic_port_unused_quirk(struct usb_hcd * hcd,bool suspend)503 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
504 {
505 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
506 u32 val;
507 void __iomem *reg;
508 int i;
509
510 for (i = 0; i < SSIC_PORT_NUM; i++) {
511 reg = (void __iomem *) xhci->cap_regs +
512 SSIC_PORT_CFG2 +
513 i * SSIC_PORT_CFG2_OFFSET;
514
515 /* Notify SSIC that SSIC profile programming is not done. */
516 val = readl(reg) & ~PROG_DONE;
517 writel(val, reg);
518
519 /* Mark SSIC port as unused(suspend) or used(resume) */
520 val = readl(reg);
521 if (suspend)
522 val |= SSIC_PORT_UNUSED;
523 else
524 val &= ~SSIC_PORT_UNUSED;
525 writel(val, reg);
526
527 /* Notify SSIC that SSIC profile programming is done */
528 val = readl(reg) | PROG_DONE;
529 writel(val, reg);
530 readl(reg);
531 }
532 }
533
534 /*
535 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
536 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
537 */
xhci_pme_quirk(struct usb_hcd * hcd)538 static void xhci_pme_quirk(struct usb_hcd *hcd)
539 {
540 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
541 void __iomem *reg;
542 u32 val;
543
544 reg = (void __iomem *) xhci->cap_regs + 0x80a4;
545 val = readl(reg);
546 writel(val | BIT(28), reg);
547 readl(reg);
548 }
549
xhci_sparse_control_quirk(struct usb_hcd * hcd)550 static void xhci_sparse_control_quirk(struct usb_hcd *hcd)
551 {
552 u32 reg;
553
554 reg = readl(hcd->regs + SPARSE_CNTL_ENABLE);
555 reg &= ~BIT(SPARSE_DISABLE_BIT);
556 writel(reg, hcd->regs + SPARSE_CNTL_ENABLE);
557 }
558
xhci_pci_suspend(struct usb_hcd * hcd,bool do_wakeup)559 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
560 {
561 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
562 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
563 int ret;
564
565 /*
566 * Systems with the TI redriver that loses port status change events
567 * need to have the registers polled during D3, so avoid D3cold.
568 */
569 if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
570 pci_d3cold_disable(pdev);
571
572 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
573 xhci_pme_quirk(hcd);
574
575 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
576 xhci_ssic_port_unused_quirk(hcd, true);
577
578 if (xhci->quirks & XHCI_DISABLE_SPARSE)
579 xhci_sparse_control_quirk(hcd);
580
581 ret = xhci_suspend(xhci, do_wakeup);
582 if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
583 xhci_ssic_port_unused_quirk(hcd, false);
584
585 return ret;
586 }
587
xhci_pci_resume(struct usb_hcd * hcd,bool hibernated)588 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
589 {
590 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
591 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
592 int retval = 0;
593
594 reset_control_reset(xhci->reset);
595
596 /* The BIOS on systems with the Intel Panther Point chipset may or may
597 * not support xHCI natively. That means that during system resume, it
598 * may switch the ports back to EHCI so that users can use their
599 * keyboard to select a kernel from GRUB after resume from hibernate.
600 *
601 * The BIOS is supposed to remember whether the OS had xHCI ports
602 * enabled before resume, and switch the ports back to xHCI when the
603 * BIOS/OS semaphore is written, but we all know we can't trust BIOS
604 * writers.
605 *
606 * Unconditionally switch the ports back to xHCI after a system resume.
607 * It should not matter whether the EHCI or xHCI controller is
608 * resumed first. It's enough to do the switchover in xHCI because
609 * USB core won't notice anything as the hub driver doesn't start
610 * running again until after all the devices (including both EHCI and
611 * xHCI host controllers) have been resumed.
612 */
613
614 if (pdev->vendor == PCI_VENDOR_ID_INTEL)
615 usb_enable_intel_xhci_ports(pdev);
616
617 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
618 xhci_ssic_port_unused_quirk(hcd, false);
619
620 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
621 xhci_pme_quirk(hcd);
622
623 retval = xhci_resume(xhci, hibernated);
624 return retval;
625 }
626
xhci_pci_shutdown(struct usb_hcd * hcd)627 static void xhci_pci_shutdown(struct usb_hcd *hcd)
628 {
629 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
630 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
631
632 xhci_shutdown(hcd);
633
634 /* Yet another workaround for spurious wakeups at shutdown with HSW */
635 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
636 pci_set_power_state(pdev, PCI_D3hot);
637 }
638 #endif /* CONFIG_PM */
639
640 /*-------------------------------------------------------------------------*/
641
642 static const struct xhci_driver_data reneses_data = {
643 .quirks = XHCI_RENESAS_FW_QUIRK,
644 .firmware = "renesas_usb_fw.mem",
645 };
646
647 /* PCI driver selection metadata; PCI hotplugging uses this */
648 static const struct pci_device_id pci_ids[] = {
649 { PCI_DEVICE(0x1912, 0x0014),
650 .driver_data = (unsigned long)&reneses_data,
651 },
652 { PCI_DEVICE(0x1912, 0x0015),
653 .driver_data = (unsigned long)&reneses_data,
654 },
655 /* handle any USB 3.0 xHCI controller */
656 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
657 },
658 { /* end: all zeroes */ }
659 };
660 MODULE_DEVICE_TABLE(pci, pci_ids);
661
662 /*
663 * Without CONFIG_USB_XHCI_PCI_RENESAS renesas_xhci_check_request_fw() won't
664 * load firmware, so don't encumber the xhci-pci driver with it.
665 */
666 #if IS_ENABLED(CONFIG_USB_XHCI_PCI_RENESAS)
667 MODULE_FIRMWARE("renesas_usb_fw.mem");
668 #endif
669
670 /* pci driver glue; this is a "new style" PCI driver module */
671 static struct pci_driver xhci_pci_driver = {
672 .name = hcd_name,
673 .id_table = pci_ids,
674
675 .probe = xhci_pci_probe,
676 .remove = xhci_pci_remove,
677 /* suspend and resume implemented later */
678
679 .shutdown = usb_hcd_pci_shutdown,
680 #ifdef CONFIG_PM
681 .driver = {
682 .pm = &usb_hcd_pci_pm_ops
683 },
684 #endif
685 };
686
xhci_pci_init(void)687 static int __init xhci_pci_init(void)
688 {
689 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
690 #ifdef CONFIG_PM
691 xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
692 xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
693 xhci_pci_hc_driver.shutdown = xhci_pci_shutdown;
694 #endif
695 return pci_register_driver(&xhci_pci_driver);
696 }
697 module_init(xhci_pci_init);
698
xhci_pci_exit(void)699 static void __exit xhci_pci_exit(void)
700 {
701 pci_unregister_driver(&xhci_pci_driver);
702 }
703 module_exit(xhci_pci_exit);
704
705 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
706 MODULE_LICENSE("GPL");
707