1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * smscufx.c -- Framebuffer driver for SMSC UFX USB controller
4 *
5 * Copyright (C) 2011 Steve Glendinning <steve.glendinning@shawell.net>
6 * Copyright (C) 2009 Roberto De Ioris <roberto@unbit.it>
7 * Copyright (C) 2009 Jaya Kumar <jayakumar.lkml@gmail.com>
8 * Copyright (C) 2009 Bernie Thompson <bernie@plugable.com>
9 *
10 * Based on udlfb, with work from Florian Echtler, Henrik Bjerregaard Pedersen,
11 * and others.
12 *
13 * Works well with Bernie Thompson's X DAMAGE patch to xf86-video-fbdev
14 * available from http://git.plugable.com
15 *
16 * Layout is based on skeletonfb by James Simmons and Geert Uytterhoeven,
17 * usb-skeleton by GregKH.
18 */
19
20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
21
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/init.h>
25 #include <linux/usb.h>
26 #include <linux/uaccess.h>
27 #include <linux/mm.h>
28 #include <linux/fb.h>
29 #include <linux/vmalloc.h>
30 #include <linux/slab.h>
31 #include <linux/delay.h>
32 #include "edid.h"
33
34 #define check_warn(status, fmt, args...) \
35 ({ if (status < 0) pr_warn(fmt, ##args); })
36
37 #define check_warn_return(status, fmt, args...) \
38 ({ if (status < 0) { pr_warn(fmt, ##args); return status; } })
39
40 #define check_warn_goto_error(status, fmt, args...) \
41 ({ if (status < 0) { pr_warn(fmt, ##args); goto error; } })
42
43 #define all_bits_set(x, bits) (((x) & (bits)) == (bits))
44
45 #define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0
46 #define USB_VENDOR_REQUEST_READ_REGISTER 0xA1
47
48 /*
49 * TODO: Propose standard fb.h ioctl for reporting damage,
50 * using _IOWR() and one of the existing area structs from fb.h
51 * Consider these ioctls deprecated, but they're still used by the
52 * DisplayLink X server as yet - need both to be modified in tandem
53 * when new ioctl(s) are ready.
54 */
55 #define UFX_IOCTL_RETURN_EDID (0xAD)
56 #define UFX_IOCTL_REPORT_DAMAGE (0xAA)
57
58 /* -BULK_SIZE as per usb-skeleton. Can we get full page and avoid overhead? */
59 #define BULK_SIZE (512)
60 #define MAX_TRANSFER (PAGE_SIZE*16 - BULK_SIZE)
61 #define WRITES_IN_FLIGHT (4)
62
63 #define GET_URB_TIMEOUT (HZ)
64 #define FREE_URB_TIMEOUT (HZ*2)
65
66 #define BPP 2
67
68 #define UFX_DEFIO_WRITE_DELAY 5 /* fb_deferred_io.delay in jiffies */
69 #define UFX_DEFIO_WRITE_DISABLE (HZ*60) /* "disable" with long delay */
70
71 struct dloarea {
72 int x, y;
73 int w, h;
74 };
75
76 struct urb_node {
77 struct list_head entry;
78 struct ufx_data *dev;
79 struct delayed_work release_urb_work;
80 struct urb *urb;
81 };
82
83 struct urb_list {
84 struct list_head list;
85 spinlock_t lock;
86 struct semaphore limit_sem;
87 int available;
88 int count;
89 size_t size;
90 };
91
92 struct ufx_data {
93 struct usb_device *udev;
94 struct device *gdev; /* &udev->dev */
95 struct fb_info *info;
96 struct urb_list urbs;
97 struct kref kref;
98 int fb_count;
99 bool virtualized; /* true when physical usb device not present */
100 struct delayed_work free_framebuffer_work;
101 atomic_t usb_active; /* 0 = update virtual buffer, but no usb traffic */
102 atomic_t lost_pixels; /* 1 = a render op failed. Need screen refresh */
103 u8 *edid; /* null until we read edid from hw or get from sysfs */
104 size_t edid_size;
105 u32 pseudo_palette[256];
106 };
107
108 static struct fb_fix_screeninfo ufx_fix = {
109 .id = "smscufx",
110 .type = FB_TYPE_PACKED_PIXELS,
111 .visual = FB_VISUAL_TRUECOLOR,
112 .xpanstep = 0,
113 .ypanstep = 0,
114 .ywrapstep = 0,
115 .accel = FB_ACCEL_NONE,
116 };
117
118 static const u32 smscufx_info_flags = FBINFO_DEFAULT | FBINFO_READS_FAST |
119 FBINFO_VIRTFB | FBINFO_HWACCEL_IMAGEBLIT | FBINFO_HWACCEL_FILLRECT |
120 FBINFO_HWACCEL_COPYAREA | FBINFO_MISC_ALWAYS_SETPAR;
121
122 static const struct usb_device_id id_table[] = {
123 {USB_DEVICE(0x0424, 0x9d00),},
124 {USB_DEVICE(0x0424, 0x9d01),},
125 {},
126 };
127 MODULE_DEVICE_TABLE(usb, id_table);
128
129 /* module options */
130 static bool console; /* Optionally allow fbcon to consume first framebuffer */
131 static bool fb_defio = true; /* Optionally enable fb_defio mmap support */
132
133 /* ufx keeps a list of urbs for efficient bulk transfers */
134 static void ufx_urb_completion(struct urb *urb);
135 static struct urb *ufx_get_urb(struct ufx_data *dev);
136 static int ufx_submit_urb(struct ufx_data *dev, struct urb * urb, size_t len);
137 static int ufx_alloc_urb_list(struct ufx_data *dev, int count, size_t size);
138 static void ufx_free_urb_list(struct ufx_data *dev);
139
140 static DEFINE_MUTEX(disconnect_mutex);
141
142 /* reads a control register */
ufx_reg_read(struct ufx_data * dev,u32 index,u32 * data)143 static int ufx_reg_read(struct ufx_data *dev, u32 index, u32 *data)
144 {
145 u32 *buf = kmalloc(4, GFP_KERNEL);
146 int ret;
147
148 BUG_ON(!dev);
149
150 if (!buf)
151 return -ENOMEM;
152
153 ret = usb_control_msg(dev->udev, usb_rcvctrlpipe(dev->udev, 0),
154 USB_VENDOR_REQUEST_READ_REGISTER,
155 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
156 00, index, buf, 4, USB_CTRL_GET_TIMEOUT);
157
158 le32_to_cpus(buf);
159 *data = *buf;
160 kfree(buf);
161
162 if (unlikely(ret < 0))
163 pr_warn("Failed to read register index 0x%08x\n", index);
164
165 return ret;
166 }
167
168 /* writes a control register */
ufx_reg_write(struct ufx_data * dev,u32 index,u32 data)169 static int ufx_reg_write(struct ufx_data *dev, u32 index, u32 data)
170 {
171 u32 *buf = kmalloc(4, GFP_KERNEL);
172 int ret;
173
174 BUG_ON(!dev);
175
176 if (!buf)
177 return -ENOMEM;
178
179 *buf = data;
180 cpu_to_le32s(buf);
181
182 ret = usb_control_msg(dev->udev, usb_sndctrlpipe(dev->udev, 0),
183 USB_VENDOR_REQUEST_WRITE_REGISTER,
184 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
185 00, index, buf, 4, USB_CTRL_SET_TIMEOUT);
186
187 kfree(buf);
188
189 if (unlikely(ret < 0))
190 pr_warn("Failed to write register index 0x%08x with value "
191 "0x%08x\n", index, data);
192
193 return ret;
194 }
195
ufx_reg_clear_and_set_bits(struct ufx_data * dev,u32 index,u32 bits_to_clear,u32 bits_to_set)196 static int ufx_reg_clear_and_set_bits(struct ufx_data *dev, u32 index,
197 u32 bits_to_clear, u32 bits_to_set)
198 {
199 u32 data;
200 int status = ufx_reg_read(dev, index, &data);
201 check_warn_return(status, "ufx_reg_clear_and_set_bits error reading "
202 "0x%x", index);
203
204 data &= (~bits_to_clear);
205 data |= bits_to_set;
206
207 status = ufx_reg_write(dev, index, data);
208 check_warn_return(status, "ufx_reg_clear_and_set_bits error writing "
209 "0x%x", index);
210
211 return 0;
212 }
213
ufx_reg_set_bits(struct ufx_data * dev,u32 index,u32 bits)214 static int ufx_reg_set_bits(struct ufx_data *dev, u32 index, u32 bits)
215 {
216 return ufx_reg_clear_and_set_bits(dev, index, 0, bits);
217 }
218
ufx_reg_clear_bits(struct ufx_data * dev,u32 index,u32 bits)219 static int ufx_reg_clear_bits(struct ufx_data *dev, u32 index, u32 bits)
220 {
221 return ufx_reg_clear_and_set_bits(dev, index, bits, 0);
222 }
223
ufx_lite_reset(struct ufx_data * dev)224 static int ufx_lite_reset(struct ufx_data *dev)
225 {
226 int status;
227 u32 value;
228
229 status = ufx_reg_write(dev, 0x3008, 0x00000001);
230 check_warn_return(status, "ufx_lite_reset error writing 0x3008");
231
232 status = ufx_reg_read(dev, 0x3008, &value);
233 check_warn_return(status, "ufx_lite_reset error reading 0x3008");
234
235 return (value == 0) ? 0 : -EIO;
236 }
237
238 /* If display is unblanked, then blank it */
ufx_blank(struct ufx_data * dev,bool wait)239 static int ufx_blank(struct ufx_data *dev, bool wait)
240 {
241 u32 dc_ctrl, dc_sts;
242 int i;
243
244 int status = ufx_reg_read(dev, 0x2004, &dc_sts);
245 check_warn_return(status, "ufx_blank error reading 0x2004");
246
247 status = ufx_reg_read(dev, 0x2000, &dc_ctrl);
248 check_warn_return(status, "ufx_blank error reading 0x2000");
249
250 /* return success if display is already blanked */
251 if ((dc_sts & 0x00000100) || (dc_ctrl & 0x00000100))
252 return 0;
253
254 /* request the DC to blank the display */
255 dc_ctrl |= 0x00000100;
256 status = ufx_reg_write(dev, 0x2000, dc_ctrl);
257 check_warn_return(status, "ufx_blank error writing 0x2000");
258
259 /* return success immediately if we don't have to wait */
260 if (!wait)
261 return 0;
262
263 for (i = 0; i < 250; i++) {
264 status = ufx_reg_read(dev, 0x2004, &dc_sts);
265 check_warn_return(status, "ufx_blank error reading 0x2004");
266
267 if (dc_sts & 0x00000100)
268 return 0;
269 }
270
271 /* timed out waiting for display to blank */
272 return -EIO;
273 }
274
275 /* If display is blanked, then unblank it */
ufx_unblank(struct ufx_data * dev,bool wait)276 static int ufx_unblank(struct ufx_data *dev, bool wait)
277 {
278 u32 dc_ctrl, dc_sts;
279 int i;
280
281 int status = ufx_reg_read(dev, 0x2004, &dc_sts);
282 check_warn_return(status, "ufx_unblank error reading 0x2004");
283
284 status = ufx_reg_read(dev, 0x2000, &dc_ctrl);
285 check_warn_return(status, "ufx_unblank error reading 0x2000");
286
287 /* return success if display is already unblanked */
288 if (((dc_sts & 0x00000100) == 0) || ((dc_ctrl & 0x00000100) == 0))
289 return 0;
290
291 /* request the DC to unblank the display */
292 dc_ctrl &= ~0x00000100;
293 status = ufx_reg_write(dev, 0x2000, dc_ctrl);
294 check_warn_return(status, "ufx_unblank error writing 0x2000");
295
296 /* return success immediately if we don't have to wait */
297 if (!wait)
298 return 0;
299
300 for (i = 0; i < 250; i++) {
301 status = ufx_reg_read(dev, 0x2004, &dc_sts);
302 check_warn_return(status, "ufx_unblank error reading 0x2004");
303
304 if ((dc_sts & 0x00000100) == 0)
305 return 0;
306 }
307
308 /* timed out waiting for display to unblank */
309 return -EIO;
310 }
311
312 /* If display is enabled, then disable it */
ufx_disable(struct ufx_data * dev,bool wait)313 static int ufx_disable(struct ufx_data *dev, bool wait)
314 {
315 u32 dc_ctrl, dc_sts;
316 int i;
317
318 int status = ufx_reg_read(dev, 0x2004, &dc_sts);
319 check_warn_return(status, "ufx_disable error reading 0x2004");
320
321 status = ufx_reg_read(dev, 0x2000, &dc_ctrl);
322 check_warn_return(status, "ufx_disable error reading 0x2000");
323
324 /* return success if display is already disabled */
325 if (((dc_sts & 0x00000001) == 0) || ((dc_ctrl & 0x00000001) == 0))
326 return 0;
327
328 /* request the DC to disable the display */
329 dc_ctrl &= ~(0x00000001);
330 status = ufx_reg_write(dev, 0x2000, dc_ctrl);
331 check_warn_return(status, "ufx_disable error writing 0x2000");
332
333 /* return success immediately if we don't have to wait */
334 if (!wait)
335 return 0;
336
337 for (i = 0; i < 250; i++) {
338 status = ufx_reg_read(dev, 0x2004, &dc_sts);
339 check_warn_return(status, "ufx_disable error reading 0x2004");
340
341 if ((dc_sts & 0x00000001) == 0)
342 return 0;
343 }
344
345 /* timed out waiting for display to disable */
346 return -EIO;
347 }
348
349 /* If display is disabled, then enable it */
ufx_enable(struct ufx_data * dev,bool wait)350 static int ufx_enable(struct ufx_data *dev, bool wait)
351 {
352 u32 dc_ctrl, dc_sts;
353 int i;
354
355 int status = ufx_reg_read(dev, 0x2004, &dc_sts);
356 check_warn_return(status, "ufx_enable error reading 0x2004");
357
358 status = ufx_reg_read(dev, 0x2000, &dc_ctrl);
359 check_warn_return(status, "ufx_enable error reading 0x2000");
360
361 /* return success if display is already enabled */
362 if ((dc_sts & 0x00000001) || (dc_ctrl & 0x00000001))
363 return 0;
364
365 /* request the DC to enable the display */
366 dc_ctrl |= 0x00000001;
367 status = ufx_reg_write(dev, 0x2000, dc_ctrl);
368 check_warn_return(status, "ufx_enable error writing 0x2000");
369
370 /* return success immediately if we don't have to wait */
371 if (!wait)
372 return 0;
373
374 for (i = 0; i < 250; i++) {
375 status = ufx_reg_read(dev, 0x2004, &dc_sts);
376 check_warn_return(status, "ufx_enable error reading 0x2004");
377
378 if (dc_sts & 0x00000001)
379 return 0;
380 }
381
382 /* timed out waiting for display to enable */
383 return -EIO;
384 }
385
ufx_config_sys_clk(struct ufx_data * dev)386 static int ufx_config_sys_clk(struct ufx_data *dev)
387 {
388 int status = ufx_reg_write(dev, 0x700C, 0x8000000F);
389 check_warn_return(status, "error writing 0x700C");
390
391 status = ufx_reg_write(dev, 0x7014, 0x0010024F);
392 check_warn_return(status, "error writing 0x7014");
393
394 status = ufx_reg_write(dev, 0x7010, 0x00000000);
395 check_warn_return(status, "error writing 0x7010");
396
397 status = ufx_reg_clear_bits(dev, 0x700C, 0x0000000A);
398 check_warn_return(status, "error clearing PLL1 bypass in 0x700C");
399 msleep(1);
400
401 status = ufx_reg_clear_bits(dev, 0x700C, 0x80000000);
402 check_warn_return(status, "error clearing output gate in 0x700C");
403
404 return 0;
405 }
406
ufx_config_ddr2(struct ufx_data * dev)407 static int ufx_config_ddr2(struct ufx_data *dev)
408 {
409 int status, i = 0;
410 u32 tmp;
411
412 status = ufx_reg_write(dev, 0x0004, 0x001F0F77);
413 check_warn_return(status, "error writing 0x0004");
414
415 status = ufx_reg_write(dev, 0x0008, 0xFFF00000);
416 check_warn_return(status, "error writing 0x0008");
417
418 status = ufx_reg_write(dev, 0x000C, 0x0FFF2222);
419 check_warn_return(status, "error writing 0x000C");
420
421 status = ufx_reg_write(dev, 0x0010, 0x00030814);
422 check_warn_return(status, "error writing 0x0010");
423
424 status = ufx_reg_write(dev, 0x0014, 0x00500019);
425 check_warn_return(status, "error writing 0x0014");
426
427 status = ufx_reg_write(dev, 0x0018, 0x020D0F15);
428 check_warn_return(status, "error writing 0x0018");
429
430 status = ufx_reg_write(dev, 0x001C, 0x02532305);
431 check_warn_return(status, "error writing 0x001C");
432
433 status = ufx_reg_write(dev, 0x0020, 0x0B030905);
434 check_warn_return(status, "error writing 0x0020");
435
436 status = ufx_reg_write(dev, 0x0024, 0x00000827);
437 check_warn_return(status, "error writing 0x0024");
438
439 status = ufx_reg_write(dev, 0x0028, 0x00000000);
440 check_warn_return(status, "error writing 0x0028");
441
442 status = ufx_reg_write(dev, 0x002C, 0x00000042);
443 check_warn_return(status, "error writing 0x002C");
444
445 status = ufx_reg_write(dev, 0x0030, 0x09520000);
446 check_warn_return(status, "error writing 0x0030");
447
448 status = ufx_reg_write(dev, 0x0034, 0x02223314);
449 check_warn_return(status, "error writing 0x0034");
450
451 status = ufx_reg_write(dev, 0x0038, 0x00430043);
452 check_warn_return(status, "error writing 0x0038");
453
454 status = ufx_reg_write(dev, 0x003C, 0xF00F000F);
455 check_warn_return(status, "error writing 0x003C");
456
457 status = ufx_reg_write(dev, 0x0040, 0xF380F00F);
458 check_warn_return(status, "error writing 0x0040");
459
460 status = ufx_reg_write(dev, 0x0044, 0xF00F0496);
461 check_warn_return(status, "error writing 0x0044");
462
463 status = ufx_reg_write(dev, 0x0048, 0x03080406);
464 check_warn_return(status, "error writing 0x0048");
465
466 status = ufx_reg_write(dev, 0x004C, 0x00001000);
467 check_warn_return(status, "error writing 0x004C");
468
469 status = ufx_reg_write(dev, 0x005C, 0x00000007);
470 check_warn_return(status, "error writing 0x005C");
471
472 status = ufx_reg_write(dev, 0x0100, 0x54F00012);
473 check_warn_return(status, "error writing 0x0100");
474
475 status = ufx_reg_write(dev, 0x0104, 0x00004012);
476 check_warn_return(status, "error writing 0x0104");
477
478 status = ufx_reg_write(dev, 0x0118, 0x40404040);
479 check_warn_return(status, "error writing 0x0118");
480
481 status = ufx_reg_write(dev, 0x0000, 0x00000001);
482 check_warn_return(status, "error writing 0x0000");
483
484 while (i++ < 500) {
485 status = ufx_reg_read(dev, 0x0000, &tmp);
486 check_warn_return(status, "error reading 0x0000");
487
488 if (all_bits_set(tmp, 0xC0000000))
489 return 0;
490 }
491
492 pr_err("DDR2 initialisation timed out, reg 0x0000=0x%08x", tmp);
493 return -ETIMEDOUT;
494 }
495
496 struct pll_values {
497 u32 div_r0;
498 u32 div_f0;
499 u32 div_q0;
500 u32 range0;
501 u32 div_r1;
502 u32 div_f1;
503 u32 div_q1;
504 u32 range1;
505 };
506
ufx_calc_range(u32 ref_freq)507 static u32 ufx_calc_range(u32 ref_freq)
508 {
509 if (ref_freq >= 88000000)
510 return 7;
511
512 if (ref_freq >= 54000000)
513 return 6;
514
515 if (ref_freq >= 34000000)
516 return 5;
517
518 if (ref_freq >= 21000000)
519 return 4;
520
521 if (ref_freq >= 13000000)
522 return 3;
523
524 if (ref_freq >= 8000000)
525 return 2;
526
527 return 1;
528 }
529
530 /* calculates PLL divider settings for a desired target frequency */
ufx_calc_pll_values(const u32 clk_pixel_pll,struct pll_values * asic_pll)531 static void ufx_calc_pll_values(const u32 clk_pixel_pll, struct pll_values *asic_pll)
532 {
533 const u32 ref_clk = 25000000;
534 u32 div_r0, div_f0, div_q0, div_r1, div_f1, div_q1;
535 u32 min_error = clk_pixel_pll;
536
537 for (div_r0 = 1; div_r0 <= 32; div_r0++) {
538 u32 ref_freq0 = ref_clk / div_r0;
539 if (ref_freq0 < 5000000)
540 break;
541
542 if (ref_freq0 > 200000000)
543 continue;
544
545 for (div_f0 = 1; div_f0 <= 256; div_f0++) {
546 u32 vco_freq0 = ref_freq0 * div_f0;
547
548 if (vco_freq0 < 350000000)
549 continue;
550
551 if (vco_freq0 > 700000000)
552 break;
553
554 for (div_q0 = 0; div_q0 < 7; div_q0++) {
555 u32 pllout_freq0 = vco_freq0 / (1 << div_q0);
556
557 if (pllout_freq0 < 5000000)
558 break;
559
560 if (pllout_freq0 > 200000000)
561 continue;
562
563 for (div_r1 = 1; div_r1 <= 32; div_r1++) {
564 u32 ref_freq1 = pllout_freq0 / div_r1;
565
566 if (ref_freq1 < 5000000)
567 break;
568
569 for (div_f1 = 1; div_f1 <= 256; div_f1++) {
570 u32 vco_freq1 = ref_freq1 * div_f1;
571
572 if (vco_freq1 < 350000000)
573 continue;
574
575 if (vco_freq1 > 700000000)
576 break;
577
578 for (div_q1 = 0; div_q1 < 7; div_q1++) {
579 u32 pllout_freq1 = vco_freq1 / (1 << div_q1);
580 int error = abs(pllout_freq1 - clk_pixel_pll);
581
582 if (pllout_freq1 < 5000000)
583 break;
584
585 if (pllout_freq1 > 700000000)
586 continue;
587
588 if (error < min_error) {
589 min_error = error;
590
591 /* final returned value is equal to calculated value - 1
592 * because a value of 0 = divide by 1 */
593 asic_pll->div_r0 = div_r0 - 1;
594 asic_pll->div_f0 = div_f0 - 1;
595 asic_pll->div_q0 = div_q0;
596 asic_pll->div_r1 = div_r1 - 1;
597 asic_pll->div_f1 = div_f1 - 1;
598 asic_pll->div_q1 = div_q1;
599
600 asic_pll->range0 = ufx_calc_range(ref_freq0);
601 asic_pll->range1 = ufx_calc_range(ref_freq1);
602
603 if (min_error == 0)
604 return;
605 }
606 }
607 }
608 }
609 }
610 }
611 }
612 }
613
614 /* sets analog bit PLL configuration values */
ufx_config_pix_clk(struct ufx_data * dev,u32 pixclock)615 static int ufx_config_pix_clk(struct ufx_data *dev, u32 pixclock)
616 {
617 struct pll_values asic_pll = {0};
618 u32 value, clk_pixel, clk_pixel_pll;
619 int status;
620
621 /* convert pixclock (in ps) to frequency (in Hz) */
622 clk_pixel = PICOS2KHZ(pixclock) * 1000;
623 pr_debug("pixclock %d ps = clk_pixel %d Hz", pixclock, clk_pixel);
624
625 /* clk_pixel = 1/2 clk_pixel_pll */
626 clk_pixel_pll = clk_pixel * 2;
627
628 ufx_calc_pll_values(clk_pixel_pll, &asic_pll);
629
630 /* Keep BYPASS and RESET signals asserted until configured */
631 status = ufx_reg_write(dev, 0x7000, 0x8000000F);
632 check_warn_return(status, "error writing 0x7000");
633
634 value = (asic_pll.div_f1 | (asic_pll.div_r1 << 8) |
635 (asic_pll.div_q1 << 16) | (asic_pll.range1 << 20));
636 status = ufx_reg_write(dev, 0x7008, value);
637 check_warn_return(status, "error writing 0x7008");
638
639 value = (asic_pll.div_f0 | (asic_pll.div_r0 << 8) |
640 (asic_pll.div_q0 << 16) | (asic_pll.range0 << 20));
641 status = ufx_reg_write(dev, 0x7004, value);
642 check_warn_return(status, "error writing 0x7004");
643
644 status = ufx_reg_clear_bits(dev, 0x7000, 0x00000005);
645 check_warn_return(status,
646 "error clearing PLL0 bypass bits in 0x7000");
647 msleep(1);
648
649 status = ufx_reg_clear_bits(dev, 0x7000, 0x0000000A);
650 check_warn_return(status,
651 "error clearing PLL1 bypass bits in 0x7000");
652 msleep(1);
653
654 status = ufx_reg_clear_bits(dev, 0x7000, 0x80000000);
655 check_warn_return(status, "error clearing gate bits in 0x7000");
656
657 return 0;
658 }
659
ufx_set_vid_mode(struct ufx_data * dev,struct fb_var_screeninfo * var)660 static int ufx_set_vid_mode(struct ufx_data *dev, struct fb_var_screeninfo *var)
661 {
662 u32 temp;
663 u16 h_total, h_active, h_blank_start, h_blank_end, h_sync_start, h_sync_end;
664 u16 v_total, v_active, v_blank_start, v_blank_end, v_sync_start, v_sync_end;
665
666 int status = ufx_reg_write(dev, 0x8028, 0);
667 check_warn_return(status, "ufx_set_vid_mode error disabling RGB pad");
668
669 status = ufx_reg_write(dev, 0x8024, 0);
670 check_warn_return(status, "ufx_set_vid_mode error disabling VDAC");
671
672 /* shut everything down before changing timing */
673 status = ufx_blank(dev, true);
674 check_warn_return(status, "ufx_set_vid_mode error blanking display");
675
676 status = ufx_disable(dev, true);
677 check_warn_return(status, "ufx_set_vid_mode error disabling display");
678
679 status = ufx_config_pix_clk(dev, var->pixclock);
680 check_warn_return(status, "ufx_set_vid_mode error configuring pixclock");
681
682 status = ufx_reg_write(dev, 0x2000, 0x00000104);
683 check_warn_return(status, "ufx_set_vid_mode error writing 0x2000");
684
685 /* set horizontal timings */
686 h_total = var->xres + var->right_margin + var->hsync_len + var->left_margin;
687 h_active = var->xres;
688 h_blank_start = var->xres + var->right_margin;
689 h_blank_end = var->xres + var->right_margin + var->hsync_len;
690 h_sync_start = var->xres + var->right_margin;
691 h_sync_end = var->xres + var->right_margin + var->hsync_len;
692
693 temp = ((h_total - 1) << 16) | (h_active - 1);
694 status = ufx_reg_write(dev, 0x2008, temp);
695 check_warn_return(status, "ufx_set_vid_mode error writing 0x2008");
696
697 temp = ((h_blank_start - 1) << 16) | (h_blank_end - 1);
698 status = ufx_reg_write(dev, 0x200C, temp);
699 check_warn_return(status, "ufx_set_vid_mode error writing 0x200C");
700
701 temp = ((h_sync_start - 1) << 16) | (h_sync_end - 1);
702 status = ufx_reg_write(dev, 0x2010, temp);
703 check_warn_return(status, "ufx_set_vid_mode error writing 0x2010");
704
705 /* set vertical timings */
706 v_total = var->upper_margin + var->yres + var->lower_margin + var->vsync_len;
707 v_active = var->yres;
708 v_blank_start = var->yres + var->lower_margin;
709 v_blank_end = var->yres + var->lower_margin + var->vsync_len;
710 v_sync_start = var->yres + var->lower_margin;
711 v_sync_end = var->yres + var->lower_margin + var->vsync_len;
712
713 temp = ((v_total - 1) << 16) | (v_active - 1);
714 status = ufx_reg_write(dev, 0x2014, temp);
715 check_warn_return(status, "ufx_set_vid_mode error writing 0x2014");
716
717 temp = ((v_blank_start - 1) << 16) | (v_blank_end - 1);
718 status = ufx_reg_write(dev, 0x2018, temp);
719 check_warn_return(status, "ufx_set_vid_mode error writing 0x2018");
720
721 temp = ((v_sync_start - 1) << 16) | (v_sync_end - 1);
722 status = ufx_reg_write(dev, 0x201C, temp);
723 check_warn_return(status, "ufx_set_vid_mode error writing 0x201C");
724
725 status = ufx_reg_write(dev, 0x2020, 0x00000000);
726 check_warn_return(status, "ufx_set_vid_mode error writing 0x2020");
727
728 status = ufx_reg_write(dev, 0x2024, 0x00000000);
729 check_warn_return(status, "ufx_set_vid_mode error writing 0x2024");
730
731 /* Set the frame length register (#pix * 2 bytes/pixel) */
732 temp = var->xres * var->yres * 2;
733 temp = (temp + 7) & (~0x7);
734 status = ufx_reg_write(dev, 0x2028, temp);
735 check_warn_return(status, "ufx_set_vid_mode error writing 0x2028");
736
737 /* enable desired output interface & disable others */
738 status = ufx_reg_write(dev, 0x2040, 0);
739 check_warn_return(status, "ufx_set_vid_mode error writing 0x2040");
740
741 status = ufx_reg_write(dev, 0x2044, 0);
742 check_warn_return(status, "ufx_set_vid_mode error writing 0x2044");
743
744 status = ufx_reg_write(dev, 0x2048, 0);
745 check_warn_return(status, "ufx_set_vid_mode error writing 0x2048");
746
747 /* set the sync polarities & enable bit */
748 temp = 0x00000001;
749 if (var->sync & FB_SYNC_HOR_HIGH_ACT)
750 temp |= 0x00000010;
751
752 if (var->sync & FB_SYNC_VERT_HIGH_ACT)
753 temp |= 0x00000008;
754
755 status = ufx_reg_write(dev, 0x2040, temp);
756 check_warn_return(status, "ufx_set_vid_mode error writing 0x2040");
757
758 /* start everything back up */
759 status = ufx_enable(dev, true);
760 check_warn_return(status, "ufx_set_vid_mode error enabling display");
761
762 /* Unblank the display */
763 status = ufx_unblank(dev, true);
764 check_warn_return(status, "ufx_set_vid_mode error unblanking display");
765
766 /* enable RGB pad */
767 status = ufx_reg_write(dev, 0x8028, 0x00000003);
768 check_warn_return(status, "ufx_set_vid_mode error enabling RGB pad");
769
770 /* enable VDAC */
771 status = ufx_reg_write(dev, 0x8024, 0x00000007);
772 check_warn_return(status, "ufx_set_vid_mode error enabling VDAC");
773
774 return 0;
775 }
776
ufx_ops_mmap(struct fb_info * info,struct vm_area_struct * vma)777 static int ufx_ops_mmap(struct fb_info *info, struct vm_area_struct *vma)
778 {
779 unsigned long start = vma->vm_start;
780 unsigned long size = vma->vm_end - vma->vm_start;
781 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
782 unsigned long page, pos;
783
784 if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))
785 return -EINVAL;
786 if (size > info->fix.smem_len)
787 return -EINVAL;
788 if (offset > info->fix.smem_len - size)
789 return -EINVAL;
790
791 pos = (unsigned long)info->fix.smem_start + offset;
792
793 pr_debug("mmap() framebuffer addr:%lu size:%lu\n",
794 pos, size);
795
796 while (size > 0) {
797 page = vmalloc_to_pfn((void *)pos);
798 if (remap_pfn_range(vma, start, page, PAGE_SIZE, PAGE_SHARED))
799 return -EAGAIN;
800
801 start += PAGE_SIZE;
802 pos += PAGE_SIZE;
803 if (size > PAGE_SIZE)
804 size -= PAGE_SIZE;
805 else
806 size = 0;
807 }
808
809 return 0;
810 }
811
ufx_raw_rect(struct ufx_data * dev,u16 * cmd,int x,int y,int width,int height)812 static void ufx_raw_rect(struct ufx_data *dev, u16 *cmd, int x, int y,
813 int width, int height)
814 {
815 size_t packed_line_len = ALIGN((width * 2), 4);
816 size_t packed_rect_len = packed_line_len * height;
817 int line;
818
819 BUG_ON(!dev);
820 BUG_ON(!dev->info);
821
822 /* command word */
823 *((u32 *)&cmd[0]) = cpu_to_le32(0x01);
824
825 /* length word */
826 *((u32 *)&cmd[2]) = cpu_to_le32(packed_rect_len + 16);
827
828 cmd[4] = cpu_to_le16(x);
829 cmd[5] = cpu_to_le16(y);
830 cmd[6] = cpu_to_le16(width);
831 cmd[7] = cpu_to_le16(height);
832
833 /* frame base address */
834 *((u32 *)&cmd[8]) = cpu_to_le32(0);
835
836 /* color mode and horizontal resolution */
837 cmd[10] = cpu_to_le16(0x4000 | dev->info->var.xres);
838
839 /* vertical resolution */
840 cmd[11] = cpu_to_le16(dev->info->var.yres);
841
842 /* packed data */
843 for (line = 0; line < height; line++) {
844 const int line_offset = dev->info->fix.line_length * (y + line);
845 const int byte_offset = line_offset + (x * BPP);
846 memcpy(&cmd[(24 + (packed_line_len * line)) / 2],
847 (char *)dev->info->fix.smem_start + byte_offset, width * BPP);
848 }
849 }
850
ufx_handle_damage(struct ufx_data * dev,int x,int y,int width,int height)851 static int ufx_handle_damage(struct ufx_data *dev, int x, int y,
852 int width, int height)
853 {
854 size_t packed_line_len = ALIGN((width * 2), 4);
855 int len, status, urb_lines, start_line = 0;
856
857 if ((width <= 0) || (height <= 0) ||
858 (x + width > dev->info->var.xres) ||
859 (y + height > dev->info->var.yres))
860 return -EINVAL;
861
862 if (!atomic_read(&dev->usb_active))
863 return 0;
864
865 while (start_line < height) {
866 struct urb *urb = ufx_get_urb(dev);
867 if (!urb) {
868 pr_warn("ufx_handle_damage unable to get urb");
869 return 0;
870 }
871
872 /* assume we have enough space to transfer at least one line */
873 BUG_ON(urb->transfer_buffer_length < (24 + (width * 2)));
874
875 /* calculate the maximum number of lines we could fit in */
876 urb_lines = (urb->transfer_buffer_length - 24) / packed_line_len;
877
878 /* but we might not need this many */
879 urb_lines = min(urb_lines, (height - start_line));
880
881 memset(urb->transfer_buffer, 0, urb->transfer_buffer_length);
882
883 ufx_raw_rect(dev, urb->transfer_buffer, x, (y + start_line), width, urb_lines);
884 len = 24 + (packed_line_len * urb_lines);
885
886 status = ufx_submit_urb(dev, urb, len);
887 check_warn_return(status, "Error submitting URB");
888
889 start_line += urb_lines;
890 }
891
892 return 0;
893 }
894
895 /* Path triggered by usermode clients who write to filesystem
896 * e.g. cat filename > /dev/fb1
897 * Not used by X Windows or text-mode console. But useful for testing.
898 * Slow because of extra copy and we must assume all pixels dirty. */
ufx_ops_write(struct fb_info * info,const char __user * buf,size_t count,loff_t * ppos)899 static ssize_t ufx_ops_write(struct fb_info *info, const char __user *buf,
900 size_t count, loff_t *ppos)
901 {
902 ssize_t result;
903 struct ufx_data *dev = info->par;
904 u32 offset = (u32) *ppos;
905
906 result = fb_sys_write(info, buf, count, ppos);
907
908 if (result > 0) {
909 int start = max((int)(offset / info->fix.line_length), 0);
910 int lines = min((u32)((result / info->fix.line_length) + 1),
911 (u32)info->var.yres);
912
913 ufx_handle_damage(dev, 0, start, info->var.xres, lines);
914 }
915
916 return result;
917 }
918
ufx_ops_copyarea(struct fb_info * info,const struct fb_copyarea * area)919 static void ufx_ops_copyarea(struct fb_info *info,
920 const struct fb_copyarea *area)
921 {
922
923 struct ufx_data *dev = info->par;
924
925 sys_copyarea(info, area);
926
927 ufx_handle_damage(dev, area->dx, area->dy,
928 area->width, area->height);
929 }
930
ufx_ops_imageblit(struct fb_info * info,const struct fb_image * image)931 static void ufx_ops_imageblit(struct fb_info *info,
932 const struct fb_image *image)
933 {
934 struct ufx_data *dev = info->par;
935
936 sys_imageblit(info, image);
937
938 ufx_handle_damage(dev, image->dx, image->dy,
939 image->width, image->height);
940 }
941
ufx_ops_fillrect(struct fb_info * info,const struct fb_fillrect * rect)942 static void ufx_ops_fillrect(struct fb_info *info,
943 const struct fb_fillrect *rect)
944 {
945 struct ufx_data *dev = info->par;
946
947 sys_fillrect(info, rect);
948
949 ufx_handle_damage(dev, rect->dx, rect->dy, rect->width,
950 rect->height);
951 }
952
953 /* NOTE: fb_defio.c is holding info->fbdefio.mutex
954 * Touching ANY framebuffer memory that triggers a page fault
955 * in fb_defio will cause a deadlock, when it also tries to
956 * grab the same mutex. */
ufx_dpy_deferred_io(struct fb_info * info,struct list_head * pagelist)957 static void ufx_dpy_deferred_io(struct fb_info *info,
958 struct list_head *pagelist)
959 {
960 struct page *cur;
961 struct fb_deferred_io *fbdefio = info->fbdefio;
962 struct ufx_data *dev = info->par;
963
964 if (!fb_defio)
965 return;
966
967 if (!atomic_read(&dev->usb_active))
968 return;
969
970 /* walk the written page list and render each to device */
971 list_for_each_entry(cur, &fbdefio->pagelist, lru) {
972 /* create a rectangle of full screen width that encloses the
973 * entire dirty framebuffer page */
974 const int x = 0;
975 const int width = dev->info->var.xres;
976 const int y = (cur->index << PAGE_SHIFT) / (width * 2);
977 int height = (PAGE_SIZE / (width * 2)) + 1;
978 height = min(height, (int)(dev->info->var.yres - y));
979
980 BUG_ON(y >= dev->info->var.yres);
981 BUG_ON((y + height) > dev->info->var.yres);
982
983 ufx_handle_damage(dev, x, y, width, height);
984 }
985 }
986
ufx_ops_ioctl(struct fb_info * info,unsigned int cmd,unsigned long arg)987 static int ufx_ops_ioctl(struct fb_info *info, unsigned int cmd,
988 unsigned long arg)
989 {
990 struct ufx_data *dev = info->par;
991 struct dloarea *area = NULL;
992
993 if (!atomic_read(&dev->usb_active))
994 return 0;
995
996 /* TODO: Update X server to get this from sysfs instead */
997 if (cmd == UFX_IOCTL_RETURN_EDID) {
998 u8 __user *edid = (u8 __user *)arg;
999 if (copy_to_user(edid, dev->edid, dev->edid_size))
1000 return -EFAULT;
1001 return 0;
1002 }
1003
1004 /* TODO: Help propose a standard fb.h ioctl to report mmap damage */
1005 if (cmd == UFX_IOCTL_REPORT_DAMAGE) {
1006 /* If we have a damage-aware client, turn fb_defio "off"
1007 * To avoid perf imact of unnecessary page fault handling.
1008 * Done by resetting the delay for this fb_info to a very
1009 * long period. Pages will become writable and stay that way.
1010 * Reset to normal value when all clients have closed this fb.
1011 */
1012 if (info->fbdefio)
1013 info->fbdefio->delay = UFX_DEFIO_WRITE_DISABLE;
1014
1015 area = (struct dloarea *)arg;
1016
1017 if (area->x < 0)
1018 area->x = 0;
1019
1020 if (area->x > info->var.xres)
1021 area->x = info->var.xres;
1022
1023 if (area->y < 0)
1024 area->y = 0;
1025
1026 if (area->y > info->var.yres)
1027 area->y = info->var.yres;
1028
1029 ufx_handle_damage(dev, area->x, area->y, area->w, area->h);
1030 }
1031
1032 return 0;
1033 }
1034
1035 /* taken from vesafb */
1036 static int
ufx_ops_setcolreg(unsigned regno,unsigned red,unsigned green,unsigned blue,unsigned transp,struct fb_info * info)1037 ufx_ops_setcolreg(unsigned regno, unsigned red, unsigned green,
1038 unsigned blue, unsigned transp, struct fb_info *info)
1039 {
1040 int err = 0;
1041
1042 if (regno >= info->cmap.len)
1043 return 1;
1044
1045 if (regno < 16) {
1046 if (info->var.red.offset == 10) {
1047 /* 1:5:5:5 */
1048 ((u32 *) (info->pseudo_palette))[regno] =
1049 ((red & 0xf800) >> 1) |
1050 ((green & 0xf800) >> 6) | ((blue & 0xf800) >> 11);
1051 } else {
1052 /* 0:5:6:5 */
1053 ((u32 *) (info->pseudo_palette))[regno] =
1054 ((red & 0xf800)) |
1055 ((green & 0xfc00) >> 5) | ((blue & 0xf800) >> 11);
1056 }
1057 }
1058
1059 return err;
1060 }
1061
1062 /* It's common for several clients to have framebuffer open simultaneously.
1063 * e.g. both fbcon and X. Makes things interesting.
1064 * Assumes caller is holding info->lock (for open and release at least) */
ufx_ops_open(struct fb_info * info,int user)1065 static int ufx_ops_open(struct fb_info *info, int user)
1066 {
1067 struct ufx_data *dev = info->par;
1068
1069 /* fbcon aggressively connects to first framebuffer it finds,
1070 * preventing other clients (X) from working properly. Usually
1071 * not what the user wants. Fail by default with option to enable. */
1072 if (user == 0 && !console)
1073 return -EBUSY;
1074
1075 mutex_lock(&disconnect_mutex);
1076
1077 /* If the USB device is gone, we don't accept new opens */
1078 if (dev->virtualized) {
1079 mutex_unlock(&disconnect_mutex);
1080 return -ENODEV;
1081 }
1082
1083 dev->fb_count++;
1084
1085 kref_get(&dev->kref);
1086
1087 if (fb_defio && (info->fbdefio == NULL)) {
1088 /* enable defio at last moment if not disabled by client */
1089
1090 struct fb_deferred_io *fbdefio;
1091
1092 fbdefio = kzalloc(sizeof(*fbdefio), GFP_KERNEL);
1093 if (fbdefio) {
1094 fbdefio->delay = UFX_DEFIO_WRITE_DELAY;
1095 fbdefio->deferred_io = ufx_dpy_deferred_io;
1096 }
1097
1098 info->fbdefio = fbdefio;
1099 fb_deferred_io_init(info);
1100 }
1101
1102 pr_debug("open /dev/fb%d user=%d fb_info=%p count=%d",
1103 info->node, user, info, dev->fb_count);
1104
1105 mutex_unlock(&disconnect_mutex);
1106
1107 return 0;
1108 }
1109
1110 /*
1111 * Called when all client interfaces to start transactions have been disabled,
1112 * and all references to our device instance (ufx_data) are released.
1113 * Every transaction must have a reference, so we know are fully spun down
1114 */
ufx_free(struct kref * kref)1115 static void ufx_free(struct kref *kref)
1116 {
1117 struct ufx_data *dev = container_of(kref, struct ufx_data, kref);
1118
1119 /* this function will wait for all in-flight urbs to complete */
1120 if (dev->urbs.count > 0)
1121 ufx_free_urb_list(dev);
1122
1123 pr_debug("freeing ufx_data %p", dev);
1124
1125 kfree(dev);
1126 }
1127
ufx_release_urb_work(struct work_struct * work)1128 static void ufx_release_urb_work(struct work_struct *work)
1129 {
1130 struct urb_node *unode = container_of(work, struct urb_node,
1131 release_urb_work.work);
1132
1133 up(&unode->dev->urbs.limit_sem);
1134 }
1135
ufx_free_framebuffer_work(struct work_struct * work)1136 static void ufx_free_framebuffer_work(struct work_struct *work)
1137 {
1138 struct ufx_data *dev = container_of(work, struct ufx_data,
1139 free_framebuffer_work.work);
1140 struct fb_info *info = dev->info;
1141 int node = info->node;
1142
1143 unregister_framebuffer(info);
1144
1145 if (info->cmap.len != 0)
1146 fb_dealloc_cmap(&info->cmap);
1147 if (info->monspecs.modedb)
1148 fb_destroy_modedb(info->monspecs.modedb);
1149 vfree(info->screen_base);
1150
1151 fb_destroy_modelist(&info->modelist);
1152
1153 dev->info = NULL;
1154
1155 /* Assume info structure is freed after this point */
1156 framebuffer_release(info);
1157
1158 pr_debug("fb_info for /dev/fb%d has been freed", node);
1159
1160 /* ref taken in probe() as part of registering framebfufer */
1161 kref_put(&dev->kref, ufx_free);
1162 }
1163
1164 /*
1165 * Assumes caller is holding info->lock mutex (for open and release at least)
1166 */
ufx_ops_release(struct fb_info * info,int user)1167 static int ufx_ops_release(struct fb_info *info, int user)
1168 {
1169 struct ufx_data *dev = info->par;
1170
1171 dev->fb_count--;
1172
1173 /* We can't free fb_info here - fbmem will touch it when we return */
1174 if (dev->virtualized && (dev->fb_count == 0))
1175 schedule_delayed_work(&dev->free_framebuffer_work, HZ);
1176
1177 if ((dev->fb_count == 0) && (info->fbdefio)) {
1178 fb_deferred_io_cleanup(info);
1179 kfree(info->fbdefio);
1180 info->fbdefio = NULL;
1181 }
1182
1183 pr_debug("released /dev/fb%d user=%d count=%d",
1184 info->node, user, dev->fb_count);
1185
1186 kref_put(&dev->kref, ufx_free);
1187
1188 return 0;
1189 }
1190
1191 /* Check whether a video mode is supported by the chip
1192 * We start from monitor's modes, so don't need to filter that here */
ufx_is_valid_mode(struct fb_videomode * mode,struct fb_info * info)1193 static int ufx_is_valid_mode(struct fb_videomode *mode,
1194 struct fb_info *info)
1195 {
1196 if ((mode->xres * mode->yres) > (2048 * 1152)) {
1197 pr_debug("%dx%d too many pixels",
1198 mode->xres, mode->yres);
1199 return 0;
1200 }
1201
1202 if (mode->pixclock < 5000) {
1203 pr_debug("%dx%d %dps pixel clock too fast",
1204 mode->xres, mode->yres, mode->pixclock);
1205 return 0;
1206 }
1207
1208 pr_debug("%dx%d (pixclk %dps %dMHz) valid mode", mode->xres, mode->yres,
1209 mode->pixclock, (1000000 / mode->pixclock));
1210 return 1;
1211 }
1212
ufx_var_color_format(struct fb_var_screeninfo * var)1213 static void ufx_var_color_format(struct fb_var_screeninfo *var)
1214 {
1215 const struct fb_bitfield red = { 11, 5, 0 };
1216 const struct fb_bitfield green = { 5, 6, 0 };
1217 const struct fb_bitfield blue = { 0, 5, 0 };
1218
1219 var->bits_per_pixel = 16;
1220 var->red = red;
1221 var->green = green;
1222 var->blue = blue;
1223 }
1224
ufx_ops_check_var(struct fb_var_screeninfo * var,struct fb_info * info)1225 static int ufx_ops_check_var(struct fb_var_screeninfo *var,
1226 struct fb_info *info)
1227 {
1228 struct fb_videomode mode;
1229
1230 /* TODO: support dynamically changing framebuffer size */
1231 if ((var->xres * var->yres * 2) > info->fix.smem_len)
1232 return -EINVAL;
1233
1234 /* set device-specific elements of var unrelated to mode */
1235 ufx_var_color_format(var);
1236
1237 fb_var_to_videomode(&mode, var);
1238
1239 if (!ufx_is_valid_mode(&mode, info))
1240 return -EINVAL;
1241
1242 return 0;
1243 }
1244
ufx_ops_set_par(struct fb_info * info)1245 static int ufx_ops_set_par(struct fb_info *info)
1246 {
1247 struct ufx_data *dev = info->par;
1248 int result;
1249 u16 *pix_framebuffer;
1250 int i;
1251
1252 pr_debug("set_par mode %dx%d", info->var.xres, info->var.yres);
1253 result = ufx_set_vid_mode(dev, &info->var);
1254
1255 if ((result == 0) && (dev->fb_count == 0)) {
1256 /* paint greenscreen */
1257 pix_framebuffer = (u16 *) info->screen_base;
1258 for (i = 0; i < info->fix.smem_len / 2; i++)
1259 pix_framebuffer[i] = 0x37e6;
1260
1261 ufx_handle_damage(dev, 0, 0, info->var.xres, info->var.yres);
1262 }
1263
1264 /* re-enable defio if previously disabled by damage tracking */
1265 if (info->fbdefio)
1266 info->fbdefio->delay = UFX_DEFIO_WRITE_DELAY;
1267
1268 return result;
1269 }
1270
1271 /* In order to come back from full DPMS off, we need to set the mode again */
ufx_ops_blank(int blank_mode,struct fb_info * info)1272 static int ufx_ops_blank(int blank_mode, struct fb_info *info)
1273 {
1274 struct ufx_data *dev = info->par;
1275 ufx_set_vid_mode(dev, &info->var);
1276 return 0;
1277 }
1278
1279 static const struct fb_ops ufx_ops = {
1280 .owner = THIS_MODULE,
1281 .fb_read = fb_sys_read,
1282 .fb_write = ufx_ops_write,
1283 .fb_setcolreg = ufx_ops_setcolreg,
1284 .fb_fillrect = ufx_ops_fillrect,
1285 .fb_copyarea = ufx_ops_copyarea,
1286 .fb_imageblit = ufx_ops_imageblit,
1287 .fb_mmap = ufx_ops_mmap,
1288 .fb_ioctl = ufx_ops_ioctl,
1289 .fb_open = ufx_ops_open,
1290 .fb_release = ufx_ops_release,
1291 .fb_blank = ufx_ops_blank,
1292 .fb_check_var = ufx_ops_check_var,
1293 .fb_set_par = ufx_ops_set_par,
1294 };
1295
1296 /* Assumes &info->lock held by caller
1297 * Assumes no active clients have framebuffer open */
ufx_realloc_framebuffer(struct ufx_data * dev,struct fb_info * info)1298 static int ufx_realloc_framebuffer(struct ufx_data *dev, struct fb_info *info)
1299 {
1300 int old_len = info->fix.smem_len;
1301 int new_len;
1302 unsigned char *old_fb = info->screen_base;
1303 unsigned char *new_fb;
1304
1305 pr_debug("Reallocating framebuffer. Addresses will change!");
1306
1307 new_len = info->fix.line_length * info->var.yres;
1308
1309 if (PAGE_ALIGN(new_len) > old_len) {
1310 /*
1311 * Alloc system memory for virtual framebuffer
1312 */
1313 new_fb = vmalloc(new_len);
1314 if (!new_fb)
1315 return -ENOMEM;
1316
1317 if (info->screen_base) {
1318 memcpy(new_fb, old_fb, old_len);
1319 vfree(info->screen_base);
1320 }
1321
1322 info->screen_base = new_fb;
1323 info->fix.smem_len = PAGE_ALIGN(new_len);
1324 info->fix.smem_start = (unsigned long) new_fb;
1325 info->flags = smscufx_info_flags;
1326 }
1327 return 0;
1328 }
1329
1330 /* sets up I2C Controller for 100 Kbps, std. speed, 7-bit addr, master,
1331 * restart enabled, but no start byte, enable controller */
ufx_i2c_init(struct ufx_data * dev)1332 static int ufx_i2c_init(struct ufx_data *dev)
1333 {
1334 u32 tmp;
1335
1336 /* disable the controller before it can be reprogrammed */
1337 int status = ufx_reg_write(dev, 0x106C, 0x00);
1338 check_warn_return(status, "failed to disable I2C");
1339
1340 /* Setup the clock count registers
1341 * (12+1) = 13 clks @ 2.5 MHz = 5.2 uS */
1342 status = ufx_reg_write(dev, 0x1018, 12);
1343 check_warn_return(status, "error writing 0x1018");
1344
1345 /* (6+8) = 14 clks @ 2.5 MHz = 5.6 uS */
1346 status = ufx_reg_write(dev, 0x1014, 6);
1347 check_warn_return(status, "error writing 0x1014");
1348
1349 status = ufx_reg_read(dev, 0x1000, &tmp);
1350 check_warn_return(status, "error reading 0x1000");
1351
1352 /* set speed to std mode */
1353 tmp &= ~(0x06);
1354 tmp |= 0x02;
1355
1356 /* 7-bit (not 10-bit) addressing */
1357 tmp &= ~(0x10);
1358
1359 /* enable restart conditions and master mode */
1360 tmp |= 0x21;
1361
1362 status = ufx_reg_write(dev, 0x1000, tmp);
1363 check_warn_return(status, "error writing 0x1000");
1364
1365 /* Set normal tx using target address 0 */
1366 status = ufx_reg_clear_and_set_bits(dev, 0x1004, 0xC00, 0x000);
1367 check_warn_return(status, "error setting TX mode bits in 0x1004");
1368
1369 /* Enable the controller */
1370 status = ufx_reg_write(dev, 0x106C, 0x01);
1371 check_warn_return(status, "failed to enable I2C");
1372
1373 return 0;
1374 }
1375
1376 /* sets the I2C port mux and target address */
ufx_i2c_configure(struct ufx_data * dev)1377 static int ufx_i2c_configure(struct ufx_data *dev)
1378 {
1379 int status = ufx_reg_write(dev, 0x106C, 0x00);
1380 check_warn_return(status, "failed to disable I2C");
1381
1382 status = ufx_reg_write(dev, 0x3010, 0x00000000);
1383 check_warn_return(status, "failed to write 0x3010");
1384
1385 /* A0h is std for any EDID, right shifted by one */
1386 status = ufx_reg_clear_and_set_bits(dev, 0x1004, 0x3FF, (0xA0 >> 1));
1387 check_warn_return(status, "failed to set TAR bits in 0x1004");
1388
1389 status = ufx_reg_write(dev, 0x106C, 0x01);
1390 check_warn_return(status, "failed to enable I2C");
1391
1392 return 0;
1393 }
1394
1395 /* wait for BUSY to clear, with a timeout of 50ms with 10ms sleeps. if no
1396 * monitor is connected, there is no error except for timeout */
ufx_i2c_wait_busy(struct ufx_data * dev)1397 static int ufx_i2c_wait_busy(struct ufx_data *dev)
1398 {
1399 u32 tmp;
1400 int i, status;
1401
1402 for (i = 0; i < 15; i++) {
1403 status = ufx_reg_read(dev, 0x1100, &tmp);
1404 check_warn_return(status, "0x1100 read failed");
1405
1406 /* if BUSY is clear, check for error */
1407 if ((tmp & 0x80000000) == 0) {
1408 if (tmp & 0x20000000) {
1409 pr_warn("I2C read failed, 0x1100=0x%08x", tmp);
1410 return -EIO;
1411 }
1412
1413 return 0;
1414 }
1415
1416 /* perform the first 10 retries without delay */
1417 if (i >= 10)
1418 msleep(10);
1419 }
1420
1421 pr_warn("I2C access timed out, resetting I2C hardware");
1422 status = ufx_reg_write(dev, 0x1100, 0x40000000);
1423 check_warn_return(status, "0x1100 write failed");
1424
1425 return -ETIMEDOUT;
1426 }
1427
1428 /* reads a 128-byte EDID block from the currently selected port and TAR */
ufx_read_edid(struct ufx_data * dev,u8 * edid,int edid_len)1429 static int ufx_read_edid(struct ufx_data *dev, u8 *edid, int edid_len)
1430 {
1431 int i, j, status;
1432 u32 *edid_u32 = (u32 *)edid;
1433
1434 BUG_ON(edid_len != EDID_LENGTH);
1435
1436 status = ufx_i2c_configure(dev);
1437 if (status < 0) {
1438 pr_err("ufx_i2c_configure failed");
1439 return status;
1440 }
1441
1442 memset(edid, 0xff, EDID_LENGTH);
1443
1444 /* Read the 128-byte EDID as 2 bursts of 64 bytes */
1445 for (i = 0; i < 2; i++) {
1446 u32 temp = 0x28070000 | (63 << 20) | (((u32)(i * 64)) << 8);
1447 status = ufx_reg_write(dev, 0x1100, temp);
1448 check_warn_return(status, "Failed to write 0x1100");
1449
1450 temp |= 0x80000000;
1451 status = ufx_reg_write(dev, 0x1100, temp);
1452 check_warn_return(status, "Failed to write 0x1100");
1453
1454 status = ufx_i2c_wait_busy(dev);
1455 check_warn_return(status, "Timeout waiting for I2C BUSY to clear");
1456
1457 for (j = 0; j < 16; j++) {
1458 u32 data_reg_addr = 0x1110 + (j * 4);
1459 status = ufx_reg_read(dev, data_reg_addr, edid_u32++);
1460 check_warn_return(status, "Error reading i2c data");
1461 }
1462 }
1463
1464 /* all FF's in the first 16 bytes indicates nothing is connected */
1465 for (i = 0; i < 16; i++) {
1466 if (edid[i] != 0xFF) {
1467 pr_debug("edid data read successfully");
1468 return EDID_LENGTH;
1469 }
1470 }
1471
1472 pr_warn("edid data contains all 0xff");
1473 return -ETIMEDOUT;
1474 }
1475
1476 /* 1) use sw default
1477 * 2) Parse into various fb_info structs
1478 * 3) Allocate virtual framebuffer memory to back highest res mode
1479 *
1480 * Parses EDID into three places used by various parts of fbdev:
1481 * fb_var_screeninfo contains the timing of the monitor's preferred mode
1482 * fb_info.monspecs is full parsed EDID info, including monspecs.modedb
1483 * fb_info.modelist is a linked list of all monitor & VESA modes which work
1484 *
1485 * If EDID is not readable/valid, then modelist is all VESA modes,
1486 * monspecs is NULL, and fb_var_screeninfo is set to safe VESA mode
1487 * Returns 0 if successful */
ufx_setup_modes(struct ufx_data * dev,struct fb_info * info,char * default_edid,size_t default_edid_size)1488 static int ufx_setup_modes(struct ufx_data *dev, struct fb_info *info,
1489 char *default_edid, size_t default_edid_size)
1490 {
1491 const struct fb_videomode *default_vmode = NULL;
1492 u8 *edid;
1493 int i, result = 0, tries = 3;
1494
1495 if (info->dev) /* only use mutex if info has been registered */
1496 mutex_lock(&info->lock);
1497
1498 edid = kmalloc(EDID_LENGTH, GFP_KERNEL);
1499 if (!edid) {
1500 result = -ENOMEM;
1501 goto error;
1502 }
1503
1504 fb_destroy_modelist(&info->modelist);
1505 memset(&info->monspecs, 0, sizeof(info->monspecs));
1506
1507 /* Try to (re)read EDID from hardware first
1508 * EDID data may return, but not parse as valid
1509 * Try again a few times, in case of e.g. analog cable noise */
1510 while (tries--) {
1511 i = ufx_read_edid(dev, edid, EDID_LENGTH);
1512
1513 if (i >= EDID_LENGTH)
1514 fb_edid_to_monspecs(edid, &info->monspecs);
1515
1516 if (info->monspecs.modedb_len > 0) {
1517 dev->edid = edid;
1518 dev->edid_size = i;
1519 break;
1520 }
1521 }
1522
1523 /* If that fails, use a previously returned EDID if available */
1524 if (info->monspecs.modedb_len == 0) {
1525 pr_err("Unable to get valid EDID from device/display\n");
1526
1527 if (dev->edid) {
1528 fb_edid_to_monspecs(dev->edid, &info->monspecs);
1529 if (info->monspecs.modedb_len > 0)
1530 pr_err("Using previously queried EDID\n");
1531 }
1532 }
1533
1534 /* If that fails, use the default EDID we were handed */
1535 if (info->monspecs.modedb_len == 0) {
1536 if (default_edid_size >= EDID_LENGTH) {
1537 fb_edid_to_monspecs(default_edid, &info->monspecs);
1538 if (info->monspecs.modedb_len > 0) {
1539 memcpy(edid, default_edid, default_edid_size);
1540 dev->edid = edid;
1541 dev->edid_size = default_edid_size;
1542 pr_err("Using default/backup EDID\n");
1543 }
1544 }
1545 }
1546
1547 /* If we've got modes, let's pick a best default mode */
1548 if (info->monspecs.modedb_len > 0) {
1549
1550 for (i = 0; i < info->monspecs.modedb_len; i++) {
1551 if (ufx_is_valid_mode(&info->monspecs.modedb[i], info))
1552 fb_add_videomode(&info->monspecs.modedb[i],
1553 &info->modelist);
1554 else /* if we've removed top/best mode */
1555 info->monspecs.misc &= ~FB_MISC_1ST_DETAIL;
1556 }
1557
1558 default_vmode = fb_find_best_display(&info->monspecs,
1559 &info->modelist);
1560 }
1561
1562 /* If everything else has failed, fall back to safe default mode */
1563 if (default_vmode == NULL) {
1564
1565 struct fb_videomode fb_vmode = {0};
1566
1567 /* Add the standard VESA modes to our modelist
1568 * Since we don't have EDID, there may be modes that
1569 * overspec monitor and/or are incorrect aspect ratio, etc.
1570 * But at least the user has a chance to choose
1571 */
1572 for (i = 0; i < VESA_MODEDB_SIZE; i++) {
1573 if (ufx_is_valid_mode((struct fb_videomode *)
1574 &vesa_modes[i], info))
1575 fb_add_videomode(&vesa_modes[i],
1576 &info->modelist);
1577 }
1578
1579 /* default to resolution safe for projectors
1580 * (since they are most common case without EDID)
1581 */
1582 fb_vmode.xres = 800;
1583 fb_vmode.yres = 600;
1584 fb_vmode.refresh = 60;
1585 default_vmode = fb_find_nearest_mode(&fb_vmode,
1586 &info->modelist);
1587 }
1588
1589 /* If we have good mode and no active clients */
1590 if ((default_vmode != NULL) && (dev->fb_count == 0)) {
1591
1592 fb_videomode_to_var(&info->var, default_vmode);
1593 ufx_var_color_format(&info->var);
1594
1595 /* with mode size info, we can now alloc our framebuffer */
1596 memcpy(&info->fix, &ufx_fix, sizeof(ufx_fix));
1597 info->fix.line_length = info->var.xres *
1598 (info->var.bits_per_pixel / 8);
1599
1600 result = ufx_realloc_framebuffer(dev, info);
1601
1602 } else
1603 result = -EINVAL;
1604
1605 error:
1606 if (edid && (dev->edid != edid))
1607 kfree(edid);
1608
1609 if (info->dev)
1610 mutex_unlock(&info->lock);
1611
1612 return result;
1613 }
1614
ufx_usb_probe(struct usb_interface * interface,const struct usb_device_id * id)1615 static int ufx_usb_probe(struct usb_interface *interface,
1616 const struct usb_device_id *id)
1617 {
1618 struct usb_device *usbdev;
1619 struct ufx_data *dev;
1620 struct fb_info *info;
1621 int retval;
1622 u32 id_rev, fpga_rev;
1623
1624 /* usb initialization */
1625 usbdev = interface_to_usbdev(interface);
1626 BUG_ON(!usbdev);
1627
1628 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1629 if (dev == NULL) {
1630 dev_err(&usbdev->dev, "ufx_usb_probe: failed alloc of dev struct\n");
1631 return -ENOMEM;
1632 }
1633
1634 /* we need to wait for both usb and fbdev to spin down on disconnect */
1635 kref_init(&dev->kref); /* matching kref_put in usb .disconnect fn */
1636 kref_get(&dev->kref); /* matching kref_put in free_framebuffer_work */
1637
1638 dev->udev = usbdev;
1639 dev->gdev = &usbdev->dev; /* our generic struct device * */
1640 usb_set_intfdata(interface, dev);
1641
1642 dev_dbg(dev->gdev, "%s %s - serial #%s\n",
1643 usbdev->manufacturer, usbdev->product, usbdev->serial);
1644 dev_dbg(dev->gdev, "vid_%04x&pid_%04x&rev_%04x driver's ufx_data struct at %p\n",
1645 le16_to_cpu(usbdev->descriptor.idVendor),
1646 le16_to_cpu(usbdev->descriptor.idProduct),
1647 le16_to_cpu(usbdev->descriptor.bcdDevice), dev);
1648 dev_dbg(dev->gdev, "console enable=%d\n", console);
1649 dev_dbg(dev->gdev, "fb_defio enable=%d\n", fb_defio);
1650
1651 if (!ufx_alloc_urb_list(dev, WRITES_IN_FLIGHT, MAX_TRANSFER)) {
1652 dev_err(dev->gdev, "ufx_alloc_urb_list failed\n");
1653 goto e_nomem;
1654 }
1655
1656 /* We don't register a new USB class. Our client interface is fbdev */
1657
1658 /* allocates framebuffer driver structure, not framebuffer memory */
1659 info = framebuffer_alloc(0, &usbdev->dev);
1660 if (!info)
1661 goto e_nomem;
1662
1663 dev->info = info;
1664 info->par = dev;
1665 info->pseudo_palette = dev->pseudo_palette;
1666 info->fbops = &ufx_ops;
1667
1668 retval = fb_alloc_cmap(&info->cmap, 256, 0);
1669 if (retval < 0) {
1670 dev_err(dev->gdev, "fb_alloc_cmap failed %x\n", retval);
1671 goto destroy_modedb;
1672 }
1673
1674 INIT_DELAYED_WORK(&dev->free_framebuffer_work,
1675 ufx_free_framebuffer_work);
1676
1677 INIT_LIST_HEAD(&info->modelist);
1678
1679 retval = ufx_reg_read(dev, 0x3000, &id_rev);
1680 check_warn_goto_error(retval, "error %d reading 0x3000 register from device", retval);
1681 dev_dbg(dev->gdev, "ID_REV register value 0x%08x", id_rev);
1682
1683 retval = ufx_reg_read(dev, 0x3004, &fpga_rev);
1684 check_warn_goto_error(retval, "error %d reading 0x3004 register from device", retval);
1685 dev_dbg(dev->gdev, "FPGA_REV register value 0x%08x", fpga_rev);
1686
1687 dev_dbg(dev->gdev, "resetting device");
1688 retval = ufx_lite_reset(dev);
1689 check_warn_goto_error(retval, "error %d resetting device", retval);
1690
1691 dev_dbg(dev->gdev, "configuring system clock");
1692 retval = ufx_config_sys_clk(dev);
1693 check_warn_goto_error(retval, "error %d configuring system clock", retval);
1694
1695 dev_dbg(dev->gdev, "configuring DDR2 controller");
1696 retval = ufx_config_ddr2(dev);
1697 check_warn_goto_error(retval, "error %d initialising DDR2 controller", retval);
1698
1699 dev_dbg(dev->gdev, "configuring I2C controller");
1700 retval = ufx_i2c_init(dev);
1701 check_warn_goto_error(retval, "error %d initialising I2C controller", retval);
1702
1703 dev_dbg(dev->gdev, "selecting display mode");
1704 retval = ufx_setup_modes(dev, info, NULL, 0);
1705 check_warn_goto_error(retval, "unable to find common mode for display and adapter");
1706
1707 retval = ufx_reg_set_bits(dev, 0x4000, 0x00000001);
1708 check_warn_goto_error(retval, "error %d enabling graphics engine", retval);
1709
1710 /* ready to begin using device */
1711 atomic_set(&dev->usb_active, 1);
1712
1713 dev_dbg(dev->gdev, "checking var");
1714 retval = ufx_ops_check_var(&info->var, info);
1715 check_warn_goto_error(retval, "error %d ufx_ops_check_var", retval);
1716
1717 dev_dbg(dev->gdev, "setting par");
1718 retval = ufx_ops_set_par(info);
1719 check_warn_goto_error(retval, "error %d ufx_ops_set_par", retval);
1720
1721 dev_dbg(dev->gdev, "registering framebuffer");
1722 retval = register_framebuffer(info);
1723 check_warn_goto_error(retval, "error %d register_framebuffer", retval);
1724
1725 dev_info(dev->gdev, "SMSC UDX USB device /dev/fb%d attached. %dx%d resolution."
1726 " Using %dK framebuffer memory\n", info->node,
1727 info->var.xres, info->var.yres, info->fix.smem_len >> 10);
1728
1729 return 0;
1730
1731 error:
1732 fb_dealloc_cmap(&info->cmap);
1733 destroy_modedb:
1734 fb_destroy_modedb(info->monspecs.modedb);
1735 vfree(info->screen_base);
1736 fb_destroy_modelist(&info->modelist);
1737 framebuffer_release(info);
1738 put_ref:
1739 kref_put(&dev->kref, ufx_free); /* ref for framebuffer */
1740 kref_put(&dev->kref, ufx_free); /* last ref from kref_init */
1741 return retval;
1742
1743 e_nomem:
1744 retval = -ENOMEM;
1745 goto put_ref;
1746 }
1747
ufx_usb_disconnect(struct usb_interface * interface)1748 static void ufx_usb_disconnect(struct usb_interface *interface)
1749 {
1750 struct ufx_data *dev;
1751
1752 mutex_lock(&disconnect_mutex);
1753
1754 dev = usb_get_intfdata(interface);
1755
1756 pr_debug("USB disconnect starting\n");
1757
1758 /* we virtualize until all fb clients release. Then we free */
1759 dev->virtualized = true;
1760
1761 /* When non-active we'll update virtual framebuffer, but no new urbs */
1762 atomic_set(&dev->usb_active, 0);
1763
1764 usb_set_intfdata(interface, NULL);
1765
1766 /* if clients still have us open, will be freed on last close */
1767 if (dev->fb_count == 0)
1768 schedule_delayed_work(&dev->free_framebuffer_work, 0);
1769
1770 /* release reference taken by kref_init in probe() */
1771 kref_put(&dev->kref, ufx_free);
1772
1773 /* consider ufx_data freed */
1774
1775 mutex_unlock(&disconnect_mutex);
1776 }
1777
1778 static struct usb_driver ufx_driver = {
1779 .name = "smscufx",
1780 .probe = ufx_usb_probe,
1781 .disconnect = ufx_usb_disconnect,
1782 .id_table = id_table,
1783 };
1784
1785 module_usb_driver(ufx_driver);
1786
ufx_urb_completion(struct urb * urb)1787 static void ufx_urb_completion(struct urb *urb)
1788 {
1789 struct urb_node *unode = urb->context;
1790 struct ufx_data *dev = unode->dev;
1791 unsigned long flags;
1792
1793 /* sync/async unlink faults aren't errors */
1794 if (urb->status) {
1795 if (!(urb->status == -ENOENT ||
1796 urb->status == -ECONNRESET ||
1797 urb->status == -ESHUTDOWN)) {
1798 pr_err("%s - nonzero write bulk status received: %d\n",
1799 __func__, urb->status);
1800 atomic_set(&dev->lost_pixels, 1);
1801 }
1802 }
1803
1804 urb->transfer_buffer_length = dev->urbs.size; /* reset to actual */
1805
1806 spin_lock_irqsave(&dev->urbs.lock, flags);
1807 list_add_tail(&unode->entry, &dev->urbs.list);
1808 dev->urbs.available++;
1809 spin_unlock_irqrestore(&dev->urbs.lock, flags);
1810
1811 /* When using fb_defio, we deadlock if up() is called
1812 * while another is waiting. So queue to another process */
1813 if (fb_defio)
1814 schedule_delayed_work(&unode->release_urb_work, 0);
1815 else
1816 up(&dev->urbs.limit_sem);
1817 }
1818
ufx_free_urb_list(struct ufx_data * dev)1819 static void ufx_free_urb_list(struct ufx_data *dev)
1820 {
1821 int count = dev->urbs.count;
1822 struct list_head *node;
1823 struct urb_node *unode;
1824 struct urb *urb;
1825 int ret;
1826 unsigned long flags;
1827
1828 pr_debug("Waiting for completes and freeing all render urbs\n");
1829
1830 /* keep waiting and freeing, until we've got 'em all */
1831 while (count--) {
1832 /* Getting interrupted means a leak, but ok at shutdown*/
1833 ret = down_interruptible(&dev->urbs.limit_sem);
1834 if (ret)
1835 break;
1836
1837 spin_lock_irqsave(&dev->urbs.lock, flags);
1838
1839 node = dev->urbs.list.next; /* have reserved one with sem */
1840 list_del_init(node);
1841
1842 spin_unlock_irqrestore(&dev->urbs.lock, flags);
1843
1844 unode = list_entry(node, struct urb_node, entry);
1845 urb = unode->urb;
1846
1847 /* Free each separately allocated piece */
1848 usb_free_coherent(urb->dev, dev->urbs.size,
1849 urb->transfer_buffer, urb->transfer_dma);
1850 usb_free_urb(urb);
1851 kfree(node);
1852 }
1853 }
1854
ufx_alloc_urb_list(struct ufx_data * dev,int count,size_t size)1855 static int ufx_alloc_urb_list(struct ufx_data *dev, int count, size_t size)
1856 {
1857 int i = 0;
1858 struct urb *urb;
1859 struct urb_node *unode;
1860 char *buf;
1861
1862 spin_lock_init(&dev->urbs.lock);
1863
1864 dev->urbs.size = size;
1865 INIT_LIST_HEAD(&dev->urbs.list);
1866
1867 while (i < count) {
1868 unode = kzalloc(sizeof(*unode), GFP_KERNEL);
1869 if (!unode)
1870 break;
1871 unode->dev = dev;
1872
1873 INIT_DELAYED_WORK(&unode->release_urb_work,
1874 ufx_release_urb_work);
1875
1876 urb = usb_alloc_urb(0, GFP_KERNEL);
1877 if (!urb) {
1878 kfree(unode);
1879 break;
1880 }
1881 unode->urb = urb;
1882
1883 buf = usb_alloc_coherent(dev->udev, size, GFP_KERNEL,
1884 &urb->transfer_dma);
1885 if (!buf) {
1886 kfree(unode);
1887 usb_free_urb(urb);
1888 break;
1889 }
1890
1891 /* urb->transfer_buffer_length set to actual before submit */
1892 usb_fill_bulk_urb(urb, dev->udev, usb_sndbulkpipe(dev->udev, 1),
1893 buf, size, ufx_urb_completion, unode);
1894 urb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP;
1895
1896 list_add_tail(&unode->entry, &dev->urbs.list);
1897
1898 i++;
1899 }
1900
1901 sema_init(&dev->urbs.limit_sem, i);
1902 dev->urbs.count = i;
1903 dev->urbs.available = i;
1904
1905 pr_debug("allocated %d %d byte urbs\n", i, (int) size);
1906
1907 return i;
1908 }
1909
ufx_get_urb(struct ufx_data * dev)1910 static struct urb *ufx_get_urb(struct ufx_data *dev)
1911 {
1912 int ret = 0;
1913 struct list_head *entry;
1914 struct urb_node *unode;
1915 struct urb *urb = NULL;
1916 unsigned long flags;
1917
1918 /* Wait for an in-flight buffer to complete and get re-queued */
1919 ret = down_timeout(&dev->urbs.limit_sem, GET_URB_TIMEOUT);
1920 if (ret) {
1921 atomic_set(&dev->lost_pixels, 1);
1922 pr_warn("wait for urb interrupted: %x available: %d\n",
1923 ret, dev->urbs.available);
1924 goto error;
1925 }
1926
1927 spin_lock_irqsave(&dev->urbs.lock, flags);
1928
1929 BUG_ON(list_empty(&dev->urbs.list)); /* reserved one with limit_sem */
1930 entry = dev->urbs.list.next;
1931 list_del_init(entry);
1932 dev->urbs.available--;
1933
1934 spin_unlock_irqrestore(&dev->urbs.lock, flags);
1935
1936 unode = list_entry(entry, struct urb_node, entry);
1937 urb = unode->urb;
1938
1939 error:
1940 return urb;
1941 }
1942
ufx_submit_urb(struct ufx_data * dev,struct urb * urb,size_t len)1943 static int ufx_submit_urb(struct ufx_data *dev, struct urb *urb, size_t len)
1944 {
1945 int ret;
1946
1947 BUG_ON(len > dev->urbs.size);
1948
1949 urb->transfer_buffer_length = len; /* set to actual payload len */
1950 ret = usb_submit_urb(urb, GFP_KERNEL);
1951 if (ret) {
1952 ufx_urb_completion(urb); /* because no one else will */
1953 atomic_set(&dev->lost_pixels, 1);
1954 pr_err("usb_submit_urb error %x\n", ret);
1955 }
1956 return ret;
1957 }
1958
1959 module_param(console, bool, S_IWUSR | S_IRUSR | S_IWGRP | S_IRGRP);
1960 MODULE_PARM_DESC(console, "Allow fbcon to be used on this display");
1961
1962 module_param(fb_defio, bool, S_IWUSR | S_IRUSR | S_IWGRP | S_IRGRP);
1963 MODULE_PARM_DESC(fb_defio, "Enable fb_defio mmap support");
1964
1965 MODULE_AUTHOR("Steve Glendinning <steve.glendinning@shawell.net>");
1966 MODULE_DESCRIPTION("SMSC UFX kernel framebuffer driver");
1967 MODULE_LICENSE("GPL");
1968