1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 *
4 * Implementation of primary ALSA driver code base for NVIDIA Tegra HDA.
5 */
6
7 #include <linux/clk.h>
8 #include <linux/clocksource.h>
9 #include <linux/completion.h>
10 #include <linux/delay.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/init.h>
13 #include <linux/interrupt.h>
14 #include <linux/io.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/moduleparam.h>
18 #include <linux/mutex.h>
19 #include <linux/of_device.h>
20 #include <linux/slab.h>
21 #include <linux/time.h>
22 #include <linux/string.h>
23 #include <linux/pm_runtime.h>
24
25 #include <sound/core.h>
26 #include <sound/initval.h>
27
28 #include <sound/hda_codec.h>
29 #include "hda_controller.h"
30
31 /* Defines for Nvidia Tegra HDA support */
32 #define HDA_BAR0 0x8000
33
34 #define HDA_CFG_CMD 0x1004
35 #define HDA_CFG_BAR0 0x1010
36
37 #define HDA_ENABLE_IO_SPACE (1 << 0)
38 #define HDA_ENABLE_MEM_SPACE (1 << 1)
39 #define HDA_ENABLE_BUS_MASTER (1 << 2)
40 #define HDA_ENABLE_SERR (1 << 8)
41 #define HDA_DISABLE_INTR (1 << 10)
42 #define HDA_BAR0_INIT_PROGRAM 0xFFFFFFFF
43 #define HDA_BAR0_FINAL_PROGRAM (1 << 14)
44
45 /* IPFS */
46 #define HDA_IPFS_CONFIG 0x180
47 #define HDA_IPFS_EN_FPCI 0x1
48
49 #define HDA_IPFS_FPCI_BAR0 0x80
50 #define HDA_FPCI_BAR0_START 0x40
51
52 #define HDA_IPFS_INTR_MASK 0x188
53 #define HDA_IPFS_EN_INTR (1 << 16)
54
55 /* FPCI */
56 #define FPCI_DBG_CFG_2 0x10F4
57 #define FPCI_GCAP_NSDO_SHIFT 18
58 #define FPCI_GCAP_NSDO_MASK (0x3 << FPCI_GCAP_NSDO_SHIFT)
59
60 /* max number of SDs */
61 #define NUM_CAPTURE_SD 1
62 #define NUM_PLAYBACK_SD 1
63
64 /*
65 * Tegra194 does not reflect correct number of SDO lines. Below macro
66 * is used to update the GCAP register to workaround the issue.
67 */
68 #define TEGRA194_NUM_SDO_LINES 4
69
70 struct hda_tegra {
71 struct azx chip;
72 struct device *dev;
73 struct clk *hda_clk;
74 struct clk *hda2codec_2x_clk;
75 struct clk *hda2hdmi_clk;
76 void __iomem *regs;
77 struct work_struct probe_work;
78 };
79
80 #ifdef CONFIG_PM
81 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
82 module_param(power_save, bint, 0644);
83 MODULE_PARM_DESC(power_save,
84 "Automatic power-saving timeout (in seconds, 0 = disable).");
85 #else
86 #define power_save 0
87 #endif
88
89 static const struct hda_controller_ops hda_tegra_ops; /* nothing special */
90
hda_tegra_init(struct hda_tegra * hda)91 static void hda_tegra_init(struct hda_tegra *hda)
92 {
93 u32 v;
94
95 /* Enable PCI access */
96 v = readl(hda->regs + HDA_IPFS_CONFIG);
97 v |= HDA_IPFS_EN_FPCI;
98 writel(v, hda->regs + HDA_IPFS_CONFIG);
99
100 /* Enable MEM/IO space and bus master */
101 v = readl(hda->regs + HDA_CFG_CMD);
102 v &= ~HDA_DISABLE_INTR;
103 v |= HDA_ENABLE_MEM_SPACE | HDA_ENABLE_IO_SPACE |
104 HDA_ENABLE_BUS_MASTER | HDA_ENABLE_SERR;
105 writel(v, hda->regs + HDA_CFG_CMD);
106
107 writel(HDA_BAR0_INIT_PROGRAM, hda->regs + HDA_CFG_BAR0);
108 writel(HDA_BAR0_FINAL_PROGRAM, hda->regs + HDA_CFG_BAR0);
109 writel(HDA_FPCI_BAR0_START, hda->regs + HDA_IPFS_FPCI_BAR0);
110
111 v = readl(hda->regs + HDA_IPFS_INTR_MASK);
112 v |= HDA_IPFS_EN_INTR;
113 writel(v, hda->regs + HDA_IPFS_INTR_MASK);
114 }
115
hda_tegra_enable_clocks(struct hda_tegra * data)116 static int hda_tegra_enable_clocks(struct hda_tegra *data)
117 {
118 int rc;
119
120 rc = clk_prepare_enable(data->hda_clk);
121 if (rc)
122 return rc;
123 rc = clk_prepare_enable(data->hda2codec_2x_clk);
124 if (rc)
125 goto disable_hda;
126 rc = clk_prepare_enable(data->hda2hdmi_clk);
127 if (rc)
128 goto disable_codec_2x;
129
130 return 0;
131
132 disable_codec_2x:
133 clk_disable_unprepare(data->hda2codec_2x_clk);
134 disable_hda:
135 clk_disable_unprepare(data->hda_clk);
136 return rc;
137 }
138
hda_tegra_disable_clocks(struct hda_tegra * data)139 static void hda_tegra_disable_clocks(struct hda_tegra *data)
140 {
141 clk_disable_unprepare(data->hda2hdmi_clk);
142 clk_disable_unprepare(data->hda2codec_2x_clk);
143 clk_disable_unprepare(data->hda_clk);
144 }
145
146 /*
147 * power management
148 */
hda_tegra_suspend(struct device * dev)149 static int __maybe_unused hda_tegra_suspend(struct device *dev)
150 {
151 struct snd_card *card = dev_get_drvdata(dev);
152 int rc;
153
154 rc = pm_runtime_force_suspend(dev);
155 if (rc < 0)
156 return rc;
157 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
158
159 return 0;
160 }
161
hda_tegra_resume(struct device * dev)162 static int __maybe_unused hda_tegra_resume(struct device *dev)
163 {
164 struct snd_card *card = dev_get_drvdata(dev);
165 int rc;
166
167 rc = pm_runtime_force_resume(dev);
168 if (rc < 0)
169 return rc;
170 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
171
172 return 0;
173 }
174
hda_tegra_runtime_suspend(struct device * dev)175 static int __maybe_unused hda_tegra_runtime_suspend(struct device *dev)
176 {
177 struct snd_card *card = dev_get_drvdata(dev);
178 struct azx *chip = card->private_data;
179 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
180
181 if (chip && chip->running) {
182 /* enable controller wake up event */
183 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
184 STATESTS_INT_MASK);
185
186 azx_stop_chip(chip);
187 azx_enter_link_reset(chip);
188 }
189 hda_tegra_disable_clocks(hda);
190
191 return 0;
192 }
193
hda_tegra_runtime_resume(struct device * dev)194 static int __maybe_unused hda_tegra_runtime_resume(struct device *dev)
195 {
196 struct snd_card *card = dev_get_drvdata(dev);
197 struct azx *chip = card->private_data;
198 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
199 int rc;
200
201 rc = hda_tegra_enable_clocks(hda);
202 if (rc != 0)
203 return rc;
204 if (chip && chip->running) {
205 hda_tegra_init(hda);
206 azx_init_chip(chip, 1);
207 /* disable controller wake up event*/
208 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
209 ~STATESTS_INT_MASK);
210 }
211
212 return 0;
213 }
214
215 static const struct dev_pm_ops hda_tegra_pm = {
216 SET_SYSTEM_SLEEP_PM_OPS(hda_tegra_suspend, hda_tegra_resume)
217 SET_RUNTIME_PM_OPS(hda_tegra_runtime_suspend,
218 hda_tegra_runtime_resume,
219 NULL)
220 };
221
hda_tegra_dev_disconnect(struct snd_device * device)222 static int hda_tegra_dev_disconnect(struct snd_device *device)
223 {
224 struct azx *chip = device->device_data;
225
226 chip->bus.shutdown = 1;
227 return 0;
228 }
229
230 /*
231 * destructor
232 */
hda_tegra_dev_free(struct snd_device * device)233 static int hda_tegra_dev_free(struct snd_device *device)
234 {
235 struct azx *chip = device->device_data;
236 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
237
238 cancel_work_sync(&hda->probe_work);
239 if (azx_bus(chip)->chip_init) {
240 azx_stop_all_streams(chip);
241 azx_stop_chip(chip);
242 }
243
244 azx_free_stream_pages(chip);
245 azx_free_streams(chip);
246 snd_hdac_bus_exit(azx_bus(chip));
247
248 return 0;
249 }
250
hda_tegra_init_chip(struct azx * chip,struct platform_device * pdev)251 static int hda_tegra_init_chip(struct azx *chip, struct platform_device *pdev)
252 {
253 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
254 struct hdac_bus *bus = azx_bus(chip);
255 struct device *dev = hda->dev;
256 struct resource *res;
257
258 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
259 hda->regs = devm_ioremap_resource(dev, res);
260 if (IS_ERR(hda->regs))
261 return PTR_ERR(hda->regs);
262
263 bus->remap_addr = hda->regs + HDA_BAR0;
264 bus->addr = res->start + HDA_BAR0;
265
266 hda_tegra_init(hda);
267
268 return 0;
269 }
270
hda_tegra_init_clk(struct hda_tegra * hda)271 static int hda_tegra_init_clk(struct hda_tegra *hda)
272 {
273 struct device *dev = hda->dev;
274
275 hda->hda_clk = devm_clk_get(dev, "hda");
276 if (IS_ERR(hda->hda_clk)) {
277 dev_err(dev, "failed to get hda clock\n");
278 return PTR_ERR(hda->hda_clk);
279 }
280 hda->hda2codec_2x_clk = devm_clk_get(dev, "hda2codec_2x");
281 if (IS_ERR(hda->hda2codec_2x_clk)) {
282 dev_err(dev, "failed to get hda2codec_2x clock\n");
283 return PTR_ERR(hda->hda2codec_2x_clk);
284 }
285 hda->hda2hdmi_clk = devm_clk_get(dev, "hda2hdmi");
286 if (IS_ERR(hda->hda2hdmi_clk)) {
287 dev_err(dev, "failed to get hda2hdmi clock\n");
288 return PTR_ERR(hda->hda2hdmi_clk);
289 }
290
291 return 0;
292 }
293
hda_tegra_first_init(struct azx * chip,struct platform_device * pdev)294 static int hda_tegra_first_init(struct azx *chip, struct platform_device *pdev)
295 {
296 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
297 struct hdac_bus *bus = azx_bus(chip);
298 struct snd_card *card = chip->card;
299 int err;
300 unsigned short gcap;
301 int irq_id = platform_get_irq(pdev, 0);
302 const char *sname, *drv_name = "tegra-hda";
303 struct device_node *np = pdev->dev.of_node;
304
305 if (irq_id < 0)
306 return irq_id;
307
308 err = hda_tegra_init_chip(chip, pdev);
309 if (err)
310 return err;
311
312 err = devm_request_irq(chip->card->dev, irq_id, azx_interrupt,
313 IRQF_SHARED, KBUILD_MODNAME, chip);
314 if (err) {
315 dev_err(chip->card->dev,
316 "unable to request IRQ %d, disabling device\n",
317 irq_id);
318 return err;
319 }
320 bus->irq = irq_id;
321 bus->dma_stop_delay = 100;
322 card->sync_irq = bus->irq;
323
324 /*
325 * Tegra194 has 4 SDO lines and the STRIPE can be used to
326 * indicate how many of the SDO lines the stream should be
327 * striped. But GCAP register does not reflect the true
328 * capability of HW. Below workaround helps to fix this.
329 *
330 * GCAP_NSDO is bits 19:18 in T_AZA_DBG_CFG_2,
331 * 0 for 1 SDO, 1 for 2 SDO, 2 for 4 SDO lines.
332 */
333 if (of_device_is_compatible(np, "nvidia,tegra194-hda")) {
334 u32 val;
335
336 dev_info(card->dev, "Override SDO lines to %u\n",
337 TEGRA194_NUM_SDO_LINES);
338
339 val = readl(hda->regs + FPCI_DBG_CFG_2) & ~FPCI_GCAP_NSDO_MASK;
340 val |= (TEGRA194_NUM_SDO_LINES >> 1) << FPCI_GCAP_NSDO_SHIFT;
341 writel(val, hda->regs + FPCI_DBG_CFG_2);
342 }
343
344 gcap = azx_readw(chip, GCAP);
345 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
346
347 chip->align_buffer_size = 1;
348
349 /* read number of streams from GCAP register instead of using
350 * hardcoded value
351 */
352 chip->capture_streams = (gcap >> 8) & 0x0f;
353 chip->playback_streams = (gcap >> 12) & 0x0f;
354 if (!chip->playback_streams && !chip->capture_streams) {
355 /* gcap didn't give any info, switching to old method */
356 chip->playback_streams = NUM_PLAYBACK_SD;
357 chip->capture_streams = NUM_CAPTURE_SD;
358 }
359 chip->capture_index_offset = 0;
360 chip->playback_index_offset = chip->capture_streams;
361 chip->num_streams = chip->playback_streams + chip->capture_streams;
362
363 /* initialize streams */
364 err = azx_init_streams(chip);
365 if (err < 0) {
366 dev_err(card->dev, "failed to initialize streams: %d\n", err);
367 return err;
368 }
369
370 err = azx_alloc_stream_pages(chip);
371 if (err < 0) {
372 dev_err(card->dev, "failed to allocate stream pages: %d\n",
373 err);
374 return err;
375 }
376
377 /* initialize chip */
378 azx_init_chip(chip, 1);
379
380 /*
381 * Playback (for 44.1K/48K, 2-channel, 16-bps) fails with
382 * 4 SDO lines due to legacy design limitation. Following
383 * is, from HD Audio Specification (Revision 1.0a), used to
384 * control striping of the stream across multiple SDO lines
385 * for sample rates <= 48K.
386 *
387 * { ((num_channels * bits_per_sample) / number of SDOs) >= 8 }
388 *
389 * Due to legacy design issue it is recommended that above
390 * ratio must be greater than 8. Since number of SDO lines is
391 * in powers of 2, next available ratio is 16 which can be
392 * used as a limiting factor here.
393 */
394 if (of_device_is_compatible(np, "nvidia,tegra30-hda"))
395 chip->bus.core.sdo_limit = 16;
396
397 /* codec detection */
398 if (!bus->codec_mask) {
399 dev_err(card->dev, "no codecs found!\n");
400 return -ENODEV;
401 }
402
403 /* driver name */
404 strncpy(card->driver, drv_name, sizeof(card->driver));
405 /* shortname for card */
406 sname = of_get_property(np, "nvidia,model", NULL);
407 if (!sname)
408 sname = drv_name;
409 if (strlen(sname) > sizeof(card->shortname))
410 dev_info(card->dev, "truncating shortname for card\n");
411 strncpy(card->shortname, sname, sizeof(card->shortname));
412
413 /* longname for card */
414 snprintf(card->longname, sizeof(card->longname),
415 "%s at 0x%lx irq %i",
416 card->shortname, bus->addr, bus->irq);
417
418 return 0;
419 }
420
421 /*
422 * constructor
423 */
424
425 static void hda_tegra_probe_work(struct work_struct *work);
426
hda_tegra_create(struct snd_card * card,unsigned int driver_caps,struct hda_tegra * hda)427 static int hda_tegra_create(struct snd_card *card,
428 unsigned int driver_caps,
429 struct hda_tegra *hda)
430 {
431 static const struct snd_device_ops ops = {
432 .dev_disconnect = hda_tegra_dev_disconnect,
433 .dev_free = hda_tegra_dev_free,
434 };
435 struct azx *chip;
436 int err;
437
438 chip = &hda->chip;
439
440 mutex_init(&chip->open_mutex);
441 chip->card = card;
442 chip->ops = &hda_tegra_ops;
443 chip->driver_caps = driver_caps;
444 chip->driver_type = driver_caps & 0xff;
445 chip->dev_index = 0;
446 INIT_LIST_HEAD(&chip->pcm_list);
447
448 chip->codec_probe_mask = -1;
449
450 chip->single_cmd = false;
451 chip->snoop = true;
452
453 INIT_WORK(&hda->probe_work, hda_tegra_probe_work);
454
455 err = azx_bus_init(chip, NULL);
456 if (err < 0)
457 return err;
458
459 chip->bus.core.sync_write = 0;
460 chip->bus.core.needs_damn_long_delay = 1;
461 chip->bus.core.aligned_mmio = 1;
462
463 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
464 if (err < 0) {
465 dev_err(card->dev, "Error creating device\n");
466 return err;
467 }
468
469 return 0;
470 }
471
472 static const struct of_device_id hda_tegra_match[] = {
473 { .compatible = "nvidia,tegra30-hda" },
474 { .compatible = "nvidia,tegra194-hda" },
475 {},
476 };
477 MODULE_DEVICE_TABLE(of, hda_tegra_match);
478
hda_tegra_probe(struct platform_device * pdev)479 static int hda_tegra_probe(struct platform_device *pdev)
480 {
481 const unsigned int driver_flags = AZX_DCAPS_CORBRP_SELF_CLEAR |
482 AZX_DCAPS_PM_RUNTIME;
483 struct snd_card *card;
484 struct azx *chip;
485 struct hda_tegra *hda;
486 int err;
487
488 hda = devm_kzalloc(&pdev->dev, sizeof(*hda), GFP_KERNEL);
489 if (!hda)
490 return -ENOMEM;
491 hda->dev = &pdev->dev;
492 chip = &hda->chip;
493
494 err = snd_card_new(&pdev->dev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
495 THIS_MODULE, 0, &card);
496 if (err < 0) {
497 dev_err(&pdev->dev, "Error creating card!\n");
498 return err;
499 }
500
501 err = hda_tegra_init_clk(hda);
502 if (err < 0)
503 goto out_free;
504
505 err = hda_tegra_create(card, driver_flags, hda);
506 if (err < 0)
507 goto out_free;
508 card->private_data = chip;
509
510 dev_set_drvdata(&pdev->dev, card);
511
512 pm_runtime_enable(hda->dev);
513 if (!azx_has_pm_runtime(chip))
514 pm_runtime_forbid(hda->dev);
515
516 schedule_work(&hda->probe_work);
517
518 return 0;
519
520 out_free:
521 snd_card_free(card);
522 return err;
523 }
524
hda_tegra_probe_work(struct work_struct * work)525 static void hda_tegra_probe_work(struct work_struct *work)
526 {
527 struct hda_tegra *hda = container_of(work, struct hda_tegra, probe_work);
528 struct azx *chip = &hda->chip;
529 struct platform_device *pdev = to_platform_device(hda->dev);
530 int err;
531
532 pm_runtime_get_sync(hda->dev);
533 err = hda_tegra_first_init(chip, pdev);
534 if (err < 0)
535 goto out_free;
536
537 /* create codec instances */
538 err = azx_probe_codecs(chip, 8);
539 if (err < 0)
540 goto out_free;
541
542 err = azx_codec_configure(chip);
543 if (err < 0)
544 goto out_free;
545
546 err = snd_card_register(chip->card);
547 if (err < 0)
548 goto out_free;
549
550 chip->running = 1;
551 snd_hda_set_power_save(&chip->bus, power_save * 1000);
552
553 out_free:
554 pm_runtime_put(hda->dev);
555 return; /* no error return from async probe */
556 }
557
hda_tegra_remove(struct platform_device * pdev)558 static int hda_tegra_remove(struct platform_device *pdev)
559 {
560 int ret;
561
562 ret = snd_card_free(dev_get_drvdata(&pdev->dev));
563 pm_runtime_disable(&pdev->dev);
564
565 return ret;
566 }
567
hda_tegra_shutdown(struct platform_device * pdev)568 static void hda_tegra_shutdown(struct platform_device *pdev)
569 {
570 struct snd_card *card = dev_get_drvdata(&pdev->dev);
571 struct azx *chip;
572
573 if (!card)
574 return;
575 chip = card->private_data;
576 if (chip && chip->running)
577 azx_stop_chip(chip);
578 }
579
580 static struct platform_driver tegra_platform_hda = {
581 .driver = {
582 .name = "tegra-hda",
583 .pm = &hda_tegra_pm,
584 .of_match_table = hda_tegra_match,
585 },
586 .probe = hda_tegra_probe,
587 .remove = hda_tegra_remove,
588 .shutdown = hda_tegra_shutdown,
589 };
590 module_platform_driver(tegra_platform_hda);
591
592 MODULE_DESCRIPTION("Tegra HDA bus driver");
593 MODULE_LICENSE("GPL v2");
594