1 // SPDX-License-Identifier: GPL-2.0-only
2 //
3 // rt5682.c -- RT5682 ALSA SoC audio component driver
4 //
5 // Copyright 2018 Realtek Semiconductor Corp.
6 // Author: Bard Liao <bardliao@realtek.com>
7 //
8
9 #include <linux/module.h>
10 #include <linux/moduleparam.h>
11 #include <linux/init.h>
12 #include <linux/delay.h>
13 #include <linux/pm.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/platform_device.h>
16 #include <linux/spi/spi.h>
17 #include <linux/acpi.h>
18 #include <linux/gpio.h>
19 #include <linux/of_gpio.h>
20 #include <linux/mutex.h>
21 #include <sound/core.h>
22 #include <sound/pcm.h>
23 #include <sound/pcm_params.h>
24 #include <sound/jack.h>
25 #include <sound/soc.h>
26 #include <sound/soc-dapm.h>
27 #include <sound/initval.h>
28 #include <sound/tlv.h>
29 #include <sound/rt5682.h>
30
31 #include "rl6231.h"
32 #include "rt5682.h"
33
34 const char *rt5682_supply_names[RT5682_NUM_SUPPLIES] = {
35 "AVDD",
36 "MICVDD",
37 "VBAT",
38 };
39 EXPORT_SYMBOL_GPL(rt5682_supply_names);
40
41 static const struct reg_sequence patch_list[] = {
42 {RT5682_HP_IMP_SENS_CTRL_19, 0x1000},
43 {RT5682_DAC_ADC_DIG_VOL1, 0xa020},
44 {RT5682_I2C_CTRL, 0x000f},
45 {RT5682_PLL2_INTERNAL, 0x8266},
46 {RT5682_SAR_IL_CMD_3, 0x8365},
47 {RT5682_SAR_IL_CMD_6, 0x0180},
48 };
49
rt5682_apply_patch_list(struct rt5682_priv * rt5682,struct device * dev)50 void rt5682_apply_patch_list(struct rt5682_priv *rt5682, struct device *dev)
51 {
52 int ret;
53
54 ret = regmap_multi_reg_write(rt5682->regmap, patch_list,
55 ARRAY_SIZE(patch_list));
56 if (ret)
57 dev_warn(dev, "Failed to apply regmap patch: %d\n", ret);
58 }
59 EXPORT_SYMBOL_GPL(rt5682_apply_patch_list);
60
61 const struct reg_default rt5682_reg[RT5682_REG_NUM] = {
62 {0x0002, 0x8080},
63 {0x0003, 0x8000},
64 {0x0005, 0x0000},
65 {0x0006, 0x0000},
66 {0x0008, 0x800f},
67 {0x000b, 0x0000},
68 {0x0010, 0x4040},
69 {0x0011, 0x0000},
70 {0x0012, 0x1404},
71 {0x0013, 0x1000},
72 {0x0014, 0xa00a},
73 {0x0015, 0x0404},
74 {0x0016, 0x0404},
75 {0x0019, 0xafaf},
76 {0x001c, 0x2f2f},
77 {0x001f, 0x0000},
78 {0x0022, 0x5757},
79 {0x0023, 0x0039},
80 {0x0024, 0x000b},
81 {0x0026, 0xc0c4},
82 {0x0029, 0x8080},
83 {0x002a, 0xa0a0},
84 {0x002b, 0x0300},
85 {0x0030, 0x0000},
86 {0x003c, 0x0080},
87 {0x0044, 0x0c0c},
88 {0x0049, 0x0000},
89 {0x0061, 0x0000},
90 {0x0062, 0x0000},
91 {0x0063, 0x003f},
92 {0x0064, 0x0000},
93 {0x0065, 0x0000},
94 {0x0066, 0x0030},
95 {0x0067, 0x0000},
96 {0x006b, 0x0000},
97 {0x006c, 0x0000},
98 {0x006d, 0x2200},
99 {0x006e, 0x0a10},
100 {0x0070, 0x8000},
101 {0x0071, 0x8000},
102 {0x0073, 0x0000},
103 {0x0074, 0x0000},
104 {0x0075, 0x0002},
105 {0x0076, 0x0001},
106 {0x0079, 0x0000},
107 {0x007a, 0x0000},
108 {0x007b, 0x0000},
109 {0x007c, 0x0100},
110 {0x007e, 0x0000},
111 {0x0080, 0x0000},
112 {0x0081, 0x0000},
113 {0x0082, 0x0000},
114 {0x0083, 0x0000},
115 {0x0084, 0x0000},
116 {0x0085, 0x0000},
117 {0x0086, 0x0005},
118 {0x0087, 0x0000},
119 {0x0088, 0x0000},
120 {0x008c, 0x0003},
121 {0x008d, 0x0000},
122 {0x008e, 0x0060},
123 {0x008f, 0x1000},
124 {0x0091, 0x0c26},
125 {0x0092, 0x0073},
126 {0x0093, 0x0000},
127 {0x0094, 0x0080},
128 {0x0098, 0x0000},
129 {0x009a, 0x0000},
130 {0x009b, 0x0000},
131 {0x009c, 0x0000},
132 {0x009d, 0x0000},
133 {0x009e, 0x100c},
134 {0x009f, 0x0000},
135 {0x00a0, 0x0000},
136 {0x00a3, 0x0002},
137 {0x00a4, 0x0001},
138 {0x00ae, 0x2040},
139 {0x00af, 0x0000},
140 {0x00b6, 0x0000},
141 {0x00b7, 0x0000},
142 {0x00b8, 0x0000},
143 {0x00b9, 0x0002},
144 {0x00be, 0x0000},
145 {0x00c0, 0x0160},
146 {0x00c1, 0x82a0},
147 {0x00c2, 0x0000},
148 {0x00d0, 0x0000},
149 {0x00d1, 0x2244},
150 {0x00d2, 0x3300},
151 {0x00d3, 0x2200},
152 {0x00d4, 0x0000},
153 {0x00d9, 0x0009},
154 {0x00da, 0x0000},
155 {0x00db, 0x0000},
156 {0x00dc, 0x00c0},
157 {0x00dd, 0x2220},
158 {0x00de, 0x3131},
159 {0x00df, 0x3131},
160 {0x00e0, 0x3131},
161 {0x00e2, 0x0000},
162 {0x00e3, 0x4000},
163 {0x00e4, 0x0aa0},
164 {0x00e5, 0x3131},
165 {0x00e6, 0x3131},
166 {0x00e7, 0x3131},
167 {0x00e8, 0x3131},
168 {0x00ea, 0xb320},
169 {0x00eb, 0x0000},
170 {0x00f0, 0x0000},
171 {0x00f1, 0x00d0},
172 {0x00f2, 0x00d0},
173 {0x00f6, 0x0000},
174 {0x00fa, 0x0000},
175 {0x00fb, 0x0000},
176 {0x00fc, 0x0000},
177 {0x00fd, 0x0000},
178 {0x00fe, 0x10ec},
179 {0x00ff, 0x6530},
180 {0x0100, 0xa0a0},
181 {0x010b, 0x0000},
182 {0x010c, 0xae00},
183 {0x010d, 0xaaa0},
184 {0x010e, 0x8aa2},
185 {0x010f, 0x02a2},
186 {0x0110, 0xc000},
187 {0x0111, 0x04a2},
188 {0x0112, 0x2800},
189 {0x0113, 0x0000},
190 {0x0117, 0x0100},
191 {0x0125, 0x0410},
192 {0x0132, 0x6026},
193 {0x0136, 0x5555},
194 {0x0138, 0x3700},
195 {0x013a, 0x2000},
196 {0x013b, 0x2000},
197 {0x013c, 0x2005},
198 {0x013f, 0x0000},
199 {0x0142, 0x0000},
200 {0x0145, 0x0002},
201 {0x0146, 0x0000},
202 {0x0147, 0x0000},
203 {0x0148, 0x0000},
204 {0x0149, 0x0000},
205 {0x0150, 0x79a1},
206 {0x0156, 0xaaaa},
207 {0x0160, 0x4ec0},
208 {0x0161, 0x0080},
209 {0x0162, 0x0200},
210 {0x0163, 0x0800},
211 {0x0164, 0x0000},
212 {0x0165, 0x0000},
213 {0x0166, 0x0000},
214 {0x0167, 0x000f},
215 {0x0168, 0x000f},
216 {0x0169, 0x0021},
217 {0x0190, 0x413d},
218 {0x0194, 0x0000},
219 {0x0195, 0x0000},
220 {0x0197, 0x0022},
221 {0x0198, 0x0000},
222 {0x0199, 0x0000},
223 {0x01af, 0x0000},
224 {0x01b0, 0x0400},
225 {0x01b1, 0x0000},
226 {0x01b2, 0x0000},
227 {0x01b3, 0x0000},
228 {0x01b4, 0x0000},
229 {0x01b5, 0x0000},
230 {0x01b6, 0x01c3},
231 {0x01b7, 0x02a0},
232 {0x01b8, 0x03e9},
233 {0x01b9, 0x1389},
234 {0x01ba, 0xc351},
235 {0x01bb, 0x0009},
236 {0x01bc, 0x0018},
237 {0x01bd, 0x002a},
238 {0x01be, 0x004c},
239 {0x01bf, 0x0097},
240 {0x01c0, 0x433d},
241 {0x01c2, 0x0000},
242 {0x01c3, 0x0000},
243 {0x01c4, 0x0000},
244 {0x01c5, 0x0000},
245 {0x01c6, 0x0000},
246 {0x01c7, 0x0000},
247 {0x01c8, 0x40af},
248 {0x01c9, 0x0702},
249 {0x01ca, 0x0000},
250 {0x01cb, 0x0000},
251 {0x01cc, 0x5757},
252 {0x01cd, 0x5757},
253 {0x01ce, 0x5757},
254 {0x01cf, 0x5757},
255 {0x01d0, 0x5757},
256 {0x01d1, 0x5757},
257 {0x01d2, 0x5757},
258 {0x01d3, 0x5757},
259 {0x01d4, 0x5757},
260 {0x01d5, 0x5757},
261 {0x01d6, 0x0000},
262 {0x01d7, 0x0008},
263 {0x01d8, 0x0029},
264 {0x01d9, 0x3333},
265 {0x01da, 0x0000},
266 {0x01db, 0x0004},
267 {0x01dc, 0x0000},
268 {0x01de, 0x7c00},
269 {0x01df, 0x0320},
270 {0x01e0, 0x06a1},
271 {0x01e1, 0x0000},
272 {0x01e2, 0x0000},
273 {0x01e3, 0x0000},
274 {0x01e4, 0x0000},
275 {0x01e6, 0x0001},
276 {0x01e7, 0x0000},
277 {0x01e8, 0x0000},
278 {0x01ea, 0x0000},
279 {0x01eb, 0x0000},
280 {0x01ec, 0x0000},
281 {0x01ed, 0x0000},
282 {0x01ee, 0x0000},
283 {0x01ef, 0x0000},
284 {0x01f0, 0x0000},
285 {0x01f1, 0x0000},
286 {0x01f2, 0x0000},
287 {0x01f3, 0x0000},
288 {0x01f4, 0x0000},
289 {0x0210, 0x6297},
290 {0x0211, 0xa005},
291 {0x0212, 0x824c},
292 {0x0213, 0xf7ff},
293 {0x0214, 0xf24c},
294 {0x0215, 0x0102},
295 {0x0216, 0x00a3},
296 {0x0217, 0x0048},
297 {0x0218, 0xa2c0},
298 {0x0219, 0x0400},
299 {0x021a, 0x00c8},
300 {0x021b, 0x00c0},
301 {0x021c, 0x0000},
302 {0x0250, 0x4500},
303 {0x0251, 0x40b3},
304 {0x0252, 0x0000},
305 {0x0253, 0x0000},
306 {0x0254, 0x0000},
307 {0x0255, 0x0000},
308 {0x0256, 0x0000},
309 {0x0257, 0x0000},
310 {0x0258, 0x0000},
311 {0x0259, 0x0000},
312 {0x025a, 0x0005},
313 {0x0270, 0x0000},
314 {0x02ff, 0x0110},
315 {0x0300, 0x001f},
316 {0x0301, 0x032c},
317 {0x0302, 0x5f21},
318 {0x0303, 0x4000},
319 {0x0304, 0x4000},
320 {0x0305, 0x06d5},
321 {0x0306, 0x8000},
322 {0x0307, 0x0700},
323 {0x0310, 0x4560},
324 {0x0311, 0xa4a8},
325 {0x0312, 0x7418},
326 {0x0313, 0x0000},
327 {0x0314, 0x0006},
328 {0x0315, 0xffff},
329 {0x0316, 0xc400},
330 {0x0317, 0x0000},
331 {0x03c0, 0x7e00},
332 {0x03c1, 0x8000},
333 {0x03c2, 0x8000},
334 {0x03c3, 0x8000},
335 {0x03c4, 0x8000},
336 {0x03c5, 0x8000},
337 {0x03c6, 0x8000},
338 {0x03c7, 0x8000},
339 {0x03c8, 0x8000},
340 {0x03c9, 0x8000},
341 {0x03ca, 0x8000},
342 {0x03cb, 0x8000},
343 {0x03cc, 0x8000},
344 {0x03d0, 0x0000},
345 {0x03d1, 0x0000},
346 {0x03d2, 0x0000},
347 {0x03d3, 0x0000},
348 {0x03d4, 0x2000},
349 {0x03d5, 0x2000},
350 {0x03d6, 0x0000},
351 {0x03d7, 0x0000},
352 {0x03d8, 0x2000},
353 {0x03d9, 0x2000},
354 {0x03da, 0x2000},
355 {0x03db, 0x2000},
356 {0x03dc, 0x0000},
357 {0x03dd, 0x0000},
358 {0x03de, 0x0000},
359 {0x03df, 0x2000},
360 {0x03e0, 0x0000},
361 {0x03e1, 0x0000},
362 {0x03e2, 0x0000},
363 {0x03e3, 0x0000},
364 {0x03e4, 0x0000},
365 {0x03e5, 0x0000},
366 {0x03e6, 0x0000},
367 {0x03e7, 0x0000},
368 {0x03e8, 0x0000},
369 {0x03e9, 0x0000},
370 {0x03ea, 0x0000},
371 {0x03eb, 0x0000},
372 {0x03ec, 0x0000},
373 {0x03ed, 0x0000},
374 {0x03ee, 0x0000},
375 {0x03ef, 0x0000},
376 {0x03f0, 0x0800},
377 {0x03f1, 0x0800},
378 {0x03f2, 0x0800},
379 {0x03f3, 0x0800},
380 };
381 EXPORT_SYMBOL_GPL(rt5682_reg);
382
rt5682_volatile_register(struct device * dev,unsigned int reg)383 bool rt5682_volatile_register(struct device *dev, unsigned int reg)
384 {
385 switch (reg) {
386 case RT5682_RESET:
387 case RT5682_CBJ_CTRL_2:
388 case RT5682_INT_ST_1:
389 case RT5682_4BTN_IL_CMD_1:
390 case RT5682_AJD1_CTRL:
391 case RT5682_HP_CALIB_CTRL_1:
392 case RT5682_DEVICE_ID:
393 case RT5682_I2C_MODE:
394 case RT5682_HP_CALIB_CTRL_10:
395 case RT5682_EFUSE_CTRL_2:
396 case RT5682_JD_TOP_VC_VTRL:
397 case RT5682_HP_IMP_SENS_CTRL_19:
398 case RT5682_IL_CMD_1:
399 case RT5682_SAR_IL_CMD_2:
400 case RT5682_SAR_IL_CMD_4:
401 case RT5682_SAR_IL_CMD_10:
402 case RT5682_SAR_IL_CMD_11:
403 case RT5682_EFUSE_CTRL_6...RT5682_EFUSE_CTRL_11:
404 case RT5682_HP_CALIB_STA_1...RT5682_HP_CALIB_STA_11:
405 return true;
406 default:
407 return false;
408 }
409 }
410 EXPORT_SYMBOL_GPL(rt5682_volatile_register);
411
rt5682_readable_register(struct device * dev,unsigned int reg)412 bool rt5682_readable_register(struct device *dev, unsigned int reg)
413 {
414 switch (reg) {
415 case RT5682_RESET:
416 case RT5682_VERSION_ID:
417 case RT5682_VENDOR_ID:
418 case RT5682_DEVICE_ID:
419 case RT5682_HP_CTRL_1:
420 case RT5682_HP_CTRL_2:
421 case RT5682_HPL_GAIN:
422 case RT5682_HPR_GAIN:
423 case RT5682_I2C_CTRL:
424 case RT5682_CBJ_BST_CTRL:
425 case RT5682_CBJ_CTRL_1:
426 case RT5682_CBJ_CTRL_2:
427 case RT5682_CBJ_CTRL_3:
428 case RT5682_CBJ_CTRL_4:
429 case RT5682_CBJ_CTRL_5:
430 case RT5682_CBJ_CTRL_6:
431 case RT5682_CBJ_CTRL_7:
432 case RT5682_DAC1_DIG_VOL:
433 case RT5682_STO1_ADC_DIG_VOL:
434 case RT5682_STO1_ADC_BOOST:
435 case RT5682_HP_IMP_GAIN_1:
436 case RT5682_HP_IMP_GAIN_2:
437 case RT5682_SIDETONE_CTRL:
438 case RT5682_STO1_ADC_MIXER:
439 case RT5682_AD_DA_MIXER:
440 case RT5682_STO1_DAC_MIXER:
441 case RT5682_A_DAC1_MUX:
442 case RT5682_DIG_INF2_DATA:
443 case RT5682_REC_MIXER:
444 case RT5682_CAL_REC:
445 case RT5682_ALC_BACK_GAIN:
446 case RT5682_PWR_DIG_1:
447 case RT5682_PWR_DIG_2:
448 case RT5682_PWR_ANLG_1:
449 case RT5682_PWR_ANLG_2:
450 case RT5682_PWR_ANLG_3:
451 case RT5682_PWR_MIXER:
452 case RT5682_PWR_VOL:
453 case RT5682_CLK_DET:
454 case RT5682_RESET_LPF_CTRL:
455 case RT5682_RESET_HPF_CTRL:
456 case RT5682_DMIC_CTRL_1:
457 case RT5682_I2S1_SDP:
458 case RT5682_I2S2_SDP:
459 case RT5682_ADDA_CLK_1:
460 case RT5682_ADDA_CLK_2:
461 case RT5682_I2S1_F_DIV_CTRL_1:
462 case RT5682_I2S1_F_DIV_CTRL_2:
463 case RT5682_TDM_CTRL:
464 case RT5682_TDM_ADDA_CTRL_1:
465 case RT5682_TDM_ADDA_CTRL_2:
466 case RT5682_DATA_SEL_CTRL_1:
467 case RT5682_TDM_TCON_CTRL:
468 case RT5682_GLB_CLK:
469 case RT5682_PLL_CTRL_1:
470 case RT5682_PLL_CTRL_2:
471 case RT5682_PLL_TRACK_1:
472 case RT5682_PLL_TRACK_2:
473 case RT5682_PLL_TRACK_3:
474 case RT5682_PLL_TRACK_4:
475 case RT5682_PLL_TRACK_5:
476 case RT5682_PLL_TRACK_6:
477 case RT5682_PLL_TRACK_11:
478 case RT5682_SDW_REF_CLK:
479 case RT5682_DEPOP_1:
480 case RT5682_DEPOP_2:
481 case RT5682_HP_CHARGE_PUMP_1:
482 case RT5682_HP_CHARGE_PUMP_2:
483 case RT5682_MICBIAS_1:
484 case RT5682_MICBIAS_2:
485 case RT5682_PLL_TRACK_12:
486 case RT5682_PLL_TRACK_14:
487 case RT5682_PLL2_CTRL_1:
488 case RT5682_PLL2_CTRL_2:
489 case RT5682_PLL2_CTRL_3:
490 case RT5682_PLL2_CTRL_4:
491 case RT5682_RC_CLK_CTRL:
492 case RT5682_I2S_M_CLK_CTRL_1:
493 case RT5682_I2S2_F_DIV_CTRL_1:
494 case RT5682_I2S2_F_DIV_CTRL_2:
495 case RT5682_EQ_CTRL_1:
496 case RT5682_EQ_CTRL_2:
497 case RT5682_IRQ_CTRL_1:
498 case RT5682_IRQ_CTRL_2:
499 case RT5682_IRQ_CTRL_3:
500 case RT5682_IRQ_CTRL_4:
501 case RT5682_INT_ST_1:
502 case RT5682_GPIO_CTRL_1:
503 case RT5682_GPIO_CTRL_2:
504 case RT5682_GPIO_CTRL_3:
505 case RT5682_HP_AMP_DET_CTRL_1:
506 case RT5682_HP_AMP_DET_CTRL_2:
507 case RT5682_MID_HP_AMP_DET:
508 case RT5682_LOW_HP_AMP_DET:
509 case RT5682_DELAY_BUF_CTRL:
510 case RT5682_SV_ZCD_1:
511 case RT5682_SV_ZCD_2:
512 case RT5682_IL_CMD_1:
513 case RT5682_IL_CMD_2:
514 case RT5682_IL_CMD_3:
515 case RT5682_IL_CMD_4:
516 case RT5682_IL_CMD_5:
517 case RT5682_IL_CMD_6:
518 case RT5682_4BTN_IL_CMD_1:
519 case RT5682_4BTN_IL_CMD_2:
520 case RT5682_4BTN_IL_CMD_3:
521 case RT5682_4BTN_IL_CMD_4:
522 case RT5682_4BTN_IL_CMD_5:
523 case RT5682_4BTN_IL_CMD_6:
524 case RT5682_4BTN_IL_CMD_7:
525 case RT5682_ADC_STO1_HP_CTRL_1:
526 case RT5682_ADC_STO1_HP_CTRL_2:
527 case RT5682_AJD1_CTRL:
528 case RT5682_JD1_THD:
529 case RT5682_JD2_THD:
530 case RT5682_JD_CTRL_1:
531 case RT5682_DUMMY_1:
532 case RT5682_DUMMY_2:
533 case RT5682_DUMMY_3:
534 case RT5682_DAC_ADC_DIG_VOL1:
535 case RT5682_BIAS_CUR_CTRL_2:
536 case RT5682_BIAS_CUR_CTRL_3:
537 case RT5682_BIAS_CUR_CTRL_4:
538 case RT5682_BIAS_CUR_CTRL_5:
539 case RT5682_BIAS_CUR_CTRL_6:
540 case RT5682_BIAS_CUR_CTRL_7:
541 case RT5682_BIAS_CUR_CTRL_8:
542 case RT5682_BIAS_CUR_CTRL_9:
543 case RT5682_BIAS_CUR_CTRL_10:
544 case RT5682_VREF_REC_OP_FB_CAP_CTRL:
545 case RT5682_CHARGE_PUMP_1:
546 case RT5682_DIG_IN_CTRL_1:
547 case RT5682_PAD_DRIVING_CTRL:
548 case RT5682_SOFT_RAMP_DEPOP:
549 case RT5682_CHOP_DAC:
550 case RT5682_CHOP_ADC:
551 case RT5682_CALIB_ADC_CTRL:
552 case RT5682_VOL_TEST:
553 case RT5682_SPKVDD_DET_STA:
554 case RT5682_TEST_MODE_CTRL_1:
555 case RT5682_TEST_MODE_CTRL_2:
556 case RT5682_TEST_MODE_CTRL_3:
557 case RT5682_TEST_MODE_CTRL_4:
558 case RT5682_TEST_MODE_CTRL_5:
559 case RT5682_PLL1_INTERNAL:
560 case RT5682_PLL2_INTERNAL:
561 case RT5682_STO_NG2_CTRL_1:
562 case RT5682_STO_NG2_CTRL_2:
563 case RT5682_STO_NG2_CTRL_3:
564 case RT5682_STO_NG2_CTRL_4:
565 case RT5682_STO_NG2_CTRL_5:
566 case RT5682_STO_NG2_CTRL_6:
567 case RT5682_STO_NG2_CTRL_7:
568 case RT5682_STO_NG2_CTRL_8:
569 case RT5682_STO_NG2_CTRL_9:
570 case RT5682_STO_NG2_CTRL_10:
571 case RT5682_STO1_DAC_SIL_DET:
572 case RT5682_SIL_PSV_CTRL1:
573 case RT5682_SIL_PSV_CTRL2:
574 case RT5682_SIL_PSV_CTRL3:
575 case RT5682_SIL_PSV_CTRL4:
576 case RT5682_SIL_PSV_CTRL5:
577 case RT5682_HP_IMP_SENS_CTRL_01:
578 case RT5682_HP_IMP_SENS_CTRL_02:
579 case RT5682_HP_IMP_SENS_CTRL_03:
580 case RT5682_HP_IMP_SENS_CTRL_04:
581 case RT5682_HP_IMP_SENS_CTRL_05:
582 case RT5682_HP_IMP_SENS_CTRL_06:
583 case RT5682_HP_IMP_SENS_CTRL_07:
584 case RT5682_HP_IMP_SENS_CTRL_08:
585 case RT5682_HP_IMP_SENS_CTRL_09:
586 case RT5682_HP_IMP_SENS_CTRL_10:
587 case RT5682_HP_IMP_SENS_CTRL_11:
588 case RT5682_HP_IMP_SENS_CTRL_12:
589 case RT5682_HP_IMP_SENS_CTRL_13:
590 case RT5682_HP_IMP_SENS_CTRL_14:
591 case RT5682_HP_IMP_SENS_CTRL_15:
592 case RT5682_HP_IMP_SENS_CTRL_16:
593 case RT5682_HP_IMP_SENS_CTRL_17:
594 case RT5682_HP_IMP_SENS_CTRL_18:
595 case RT5682_HP_IMP_SENS_CTRL_19:
596 case RT5682_HP_IMP_SENS_CTRL_20:
597 case RT5682_HP_IMP_SENS_CTRL_21:
598 case RT5682_HP_IMP_SENS_CTRL_22:
599 case RT5682_HP_IMP_SENS_CTRL_23:
600 case RT5682_HP_IMP_SENS_CTRL_24:
601 case RT5682_HP_IMP_SENS_CTRL_25:
602 case RT5682_HP_IMP_SENS_CTRL_26:
603 case RT5682_HP_IMP_SENS_CTRL_27:
604 case RT5682_HP_IMP_SENS_CTRL_28:
605 case RT5682_HP_IMP_SENS_CTRL_29:
606 case RT5682_HP_IMP_SENS_CTRL_30:
607 case RT5682_HP_IMP_SENS_CTRL_31:
608 case RT5682_HP_IMP_SENS_CTRL_32:
609 case RT5682_HP_IMP_SENS_CTRL_33:
610 case RT5682_HP_IMP_SENS_CTRL_34:
611 case RT5682_HP_IMP_SENS_CTRL_35:
612 case RT5682_HP_IMP_SENS_CTRL_36:
613 case RT5682_HP_IMP_SENS_CTRL_37:
614 case RT5682_HP_IMP_SENS_CTRL_38:
615 case RT5682_HP_IMP_SENS_CTRL_39:
616 case RT5682_HP_IMP_SENS_CTRL_40:
617 case RT5682_HP_IMP_SENS_CTRL_41:
618 case RT5682_HP_IMP_SENS_CTRL_42:
619 case RT5682_HP_IMP_SENS_CTRL_43:
620 case RT5682_HP_LOGIC_CTRL_1:
621 case RT5682_HP_LOGIC_CTRL_2:
622 case RT5682_HP_LOGIC_CTRL_3:
623 case RT5682_HP_CALIB_CTRL_1:
624 case RT5682_HP_CALIB_CTRL_2:
625 case RT5682_HP_CALIB_CTRL_3:
626 case RT5682_HP_CALIB_CTRL_4:
627 case RT5682_HP_CALIB_CTRL_5:
628 case RT5682_HP_CALIB_CTRL_6:
629 case RT5682_HP_CALIB_CTRL_7:
630 case RT5682_HP_CALIB_CTRL_9:
631 case RT5682_HP_CALIB_CTRL_10:
632 case RT5682_HP_CALIB_CTRL_11:
633 case RT5682_HP_CALIB_STA_1:
634 case RT5682_HP_CALIB_STA_2:
635 case RT5682_HP_CALIB_STA_3:
636 case RT5682_HP_CALIB_STA_4:
637 case RT5682_HP_CALIB_STA_5:
638 case RT5682_HP_CALIB_STA_6:
639 case RT5682_HP_CALIB_STA_7:
640 case RT5682_HP_CALIB_STA_8:
641 case RT5682_HP_CALIB_STA_9:
642 case RT5682_HP_CALIB_STA_10:
643 case RT5682_HP_CALIB_STA_11:
644 case RT5682_SAR_IL_CMD_1:
645 case RT5682_SAR_IL_CMD_2:
646 case RT5682_SAR_IL_CMD_3:
647 case RT5682_SAR_IL_CMD_4:
648 case RT5682_SAR_IL_CMD_5:
649 case RT5682_SAR_IL_CMD_6:
650 case RT5682_SAR_IL_CMD_7:
651 case RT5682_SAR_IL_CMD_8:
652 case RT5682_SAR_IL_CMD_9:
653 case RT5682_SAR_IL_CMD_10:
654 case RT5682_SAR_IL_CMD_11:
655 case RT5682_SAR_IL_CMD_12:
656 case RT5682_SAR_IL_CMD_13:
657 case RT5682_EFUSE_CTRL_1:
658 case RT5682_EFUSE_CTRL_2:
659 case RT5682_EFUSE_CTRL_3:
660 case RT5682_EFUSE_CTRL_4:
661 case RT5682_EFUSE_CTRL_5:
662 case RT5682_EFUSE_CTRL_6:
663 case RT5682_EFUSE_CTRL_7:
664 case RT5682_EFUSE_CTRL_8:
665 case RT5682_EFUSE_CTRL_9:
666 case RT5682_EFUSE_CTRL_10:
667 case RT5682_EFUSE_CTRL_11:
668 case RT5682_JD_TOP_VC_VTRL:
669 case RT5682_DRC1_CTRL_0:
670 case RT5682_DRC1_CTRL_1:
671 case RT5682_DRC1_CTRL_2:
672 case RT5682_DRC1_CTRL_3:
673 case RT5682_DRC1_CTRL_4:
674 case RT5682_DRC1_CTRL_5:
675 case RT5682_DRC1_CTRL_6:
676 case RT5682_DRC1_HARD_LMT_CTRL_1:
677 case RT5682_DRC1_HARD_LMT_CTRL_2:
678 case RT5682_DRC1_PRIV_1:
679 case RT5682_DRC1_PRIV_2:
680 case RT5682_DRC1_PRIV_3:
681 case RT5682_DRC1_PRIV_4:
682 case RT5682_DRC1_PRIV_5:
683 case RT5682_DRC1_PRIV_6:
684 case RT5682_DRC1_PRIV_7:
685 case RT5682_DRC1_PRIV_8:
686 case RT5682_EQ_AUTO_RCV_CTRL1:
687 case RT5682_EQ_AUTO_RCV_CTRL2:
688 case RT5682_EQ_AUTO_RCV_CTRL3:
689 case RT5682_EQ_AUTO_RCV_CTRL4:
690 case RT5682_EQ_AUTO_RCV_CTRL5:
691 case RT5682_EQ_AUTO_RCV_CTRL6:
692 case RT5682_EQ_AUTO_RCV_CTRL7:
693 case RT5682_EQ_AUTO_RCV_CTRL8:
694 case RT5682_EQ_AUTO_RCV_CTRL9:
695 case RT5682_EQ_AUTO_RCV_CTRL10:
696 case RT5682_EQ_AUTO_RCV_CTRL11:
697 case RT5682_EQ_AUTO_RCV_CTRL12:
698 case RT5682_EQ_AUTO_RCV_CTRL13:
699 case RT5682_ADC_L_EQ_LPF1_A1:
700 case RT5682_R_EQ_LPF1_A1:
701 case RT5682_L_EQ_LPF1_H0:
702 case RT5682_R_EQ_LPF1_H0:
703 case RT5682_L_EQ_BPF1_A1:
704 case RT5682_R_EQ_BPF1_A1:
705 case RT5682_L_EQ_BPF1_A2:
706 case RT5682_R_EQ_BPF1_A2:
707 case RT5682_L_EQ_BPF1_H0:
708 case RT5682_R_EQ_BPF1_H0:
709 case RT5682_L_EQ_BPF2_A1:
710 case RT5682_R_EQ_BPF2_A1:
711 case RT5682_L_EQ_BPF2_A2:
712 case RT5682_R_EQ_BPF2_A2:
713 case RT5682_L_EQ_BPF2_H0:
714 case RT5682_R_EQ_BPF2_H0:
715 case RT5682_L_EQ_BPF3_A1:
716 case RT5682_R_EQ_BPF3_A1:
717 case RT5682_L_EQ_BPF3_A2:
718 case RT5682_R_EQ_BPF3_A2:
719 case RT5682_L_EQ_BPF3_H0:
720 case RT5682_R_EQ_BPF3_H0:
721 case RT5682_L_EQ_BPF4_A1:
722 case RT5682_R_EQ_BPF4_A1:
723 case RT5682_L_EQ_BPF4_A2:
724 case RT5682_R_EQ_BPF4_A2:
725 case RT5682_L_EQ_BPF4_H0:
726 case RT5682_R_EQ_BPF4_H0:
727 case RT5682_L_EQ_HPF1_A1:
728 case RT5682_R_EQ_HPF1_A1:
729 case RT5682_L_EQ_HPF1_H0:
730 case RT5682_R_EQ_HPF1_H0:
731 case RT5682_L_EQ_PRE_VOL:
732 case RT5682_R_EQ_PRE_VOL:
733 case RT5682_L_EQ_POST_VOL:
734 case RT5682_R_EQ_POST_VOL:
735 case RT5682_I2C_MODE:
736 return true;
737 default:
738 return false;
739 }
740 }
741 EXPORT_SYMBOL_GPL(rt5682_readable_register);
742
743 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
744 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
745 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
746
747 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
748 static const DECLARE_TLV_DB_RANGE(bst_tlv,
749 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
750 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
751 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
752 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
753 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
754 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
755 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
756 );
757
758 /* Interface data select */
759 static const char * const rt5682_data_select[] = {
760 "L/R", "R/L", "L/L", "R/R"
761 };
762
763 static SOC_ENUM_SINGLE_DECL(rt5682_if2_adc_enum,
764 RT5682_DIG_INF2_DATA, RT5682_IF2_ADC_SEL_SFT, rt5682_data_select);
765
766 static SOC_ENUM_SINGLE_DECL(rt5682_if1_01_adc_enum,
767 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC1_SEL_SFT, rt5682_data_select);
768
769 static SOC_ENUM_SINGLE_DECL(rt5682_if1_23_adc_enum,
770 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC2_SEL_SFT, rt5682_data_select);
771
772 static SOC_ENUM_SINGLE_DECL(rt5682_if1_45_adc_enum,
773 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC3_SEL_SFT, rt5682_data_select);
774
775 static SOC_ENUM_SINGLE_DECL(rt5682_if1_67_adc_enum,
776 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC4_SEL_SFT, rt5682_data_select);
777
778 static const struct snd_kcontrol_new rt5682_if2_adc_swap_mux =
779 SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5682_if2_adc_enum);
780
781 static const struct snd_kcontrol_new rt5682_if1_01_adc_swap_mux =
782 SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5682_if1_01_adc_enum);
783
784 static const struct snd_kcontrol_new rt5682_if1_23_adc_swap_mux =
785 SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5682_if1_23_adc_enum);
786
787 static const struct snd_kcontrol_new rt5682_if1_45_adc_swap_mux =
788 SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5682_if1_45_adc_enum);
789
790 static const struct snd_kcontrol_new rt5682_if1_67_adc_swap_mux =
791 SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5682_if1_67_adc_enum);
792
793 static const char * const rt5682_dac_select[] = {
794 "IF1", "SOUND"
795 };
796
797 static SOC_ENUM_SINGLE_DECL(rt5682_dacl_enum,
798 RT5682_AD_DA_MIXER, RT5682_DAC1_L_SEL_SFT, rt5682_dac_select);
799
800 static const struct snd_kcontrol_new rt5682_dac_l_mux =
801 SOC_DAPM_ENUM("DAC L Mux", rt5682_dacl_enum);
802
803 static SOC_ENUM_SINGLE_DECL(rt5682_dacr_enum,
804 RT5682_AD_DA_MIXER, RT5682_DAC1_R_SEL_SFT, rt5682_dac_select);
805
806 static const struct snd_kcontrol_new rt5682_dac_r_mux =
807 SOC_DAPM_ENUM("DAC R Mux", rt5682_dacr_enum);
808
rt5682_reset(struct rt5682_priv * rt5682)809 void rt5682_reset(struct rt5682_priv *rt5682)
810 {
811 regmap_write(rt5682->regmap, RT5682_RESET, 0);
812 if (!rt5682->is_sdw)
813 regmap_write(rt5682->regmap, RT5682_I2C_MODE, 1);
814 }
815 EXPORT_SYMBOL_GPL(rt5682_reset);
816
817 /**
818 * rt5682_sel_asrc_clk_src - select ASRC clock source for a set of filters
819 * @component: SoC audio component device.
820 * @filter_mask: mask of filters.
821 * @clk_src: clock source
822 *
823 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5682 can
824 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
825 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
826 * ASRC function will track i2s clock and generate a corresponding system clock
827 * for codec. This function provides an API to select the clock source for a
828 * set of filters specified by the mask. And the component driver will turn on
829 * ASRC for these filters if ASRC is selected as their clock source.
830 */
rt5682_sel_asrc_clk_src(struct snd_soc_component * component,unsigned int filter_mask,unsigned int clk_src)831 int rt5682_sel_asrc_clk_src(struct snd_soc_component *component,
832 unsigned int filter_mask, unsigned int clk_src)
833 {
834 switch (clk_src) {
835 case RT5682_CLK_SEL_SYS:
836 case RT5682_CLK_SEL_I2S1_ASRC:
837 case RT5682_CLK_SEL_I2S2_ASRC:
838 break;
839
840 default:
841 return -EINVAL;
842 }
843
844 if (filter_mask & RT5682_DA_STEREO1_FILTER) {
845 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_2,
846 RT5682_FILTER_CLK_SEL_MASK,
847 clk_src << RT5682_FILTER_CLK_SEL_SFT);
848 }
849
850 if (filter_mask & RT5682_AD_STEREO1_FILTER) {
851 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_3,
852 RT5682_FILTER_CLK_SEL_MASK,
853 clk_src << RT5682_FILTER_CLK_SEL_SFT);
854 }
855
856 return 0;
857 }
858 EXPORT_SYMBOL_GPL(rt5682_sel_asrc_clk_src);
859
rt5682_button_detect(struct snd_soc_component * component)860 static int rt5682_button_detect(struct snd_soc_component *component)
861 {
862 int btn_type, val;
863
864 val = snd_soc_component_read(component, RT5682_4BTN_IL_CMD_1);
865 btn_type = val & 0xfff0;
866 snd_soc_component_write(component, RT5682_4BTN_IL_CMD_1, val);
867 dev_dbg(component->dev, "%s btn_type=%x\n", __func__, btn_type);
868 snd_soc_component_update_bits(component,
869 RT5682_SAR_IL_CMD_2, 0x10, 0x10);
870
871 return btn_type;
872 }
873
rt5682_enable_push_button_irq(struct snd_soc_component * component,bool enable)874 static void rt5682_enable_push_button_irq(struct snd_soc_component *component,
875 bool enable)
876 {
877 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
878
879 if (enable) {
880 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
881 RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_EN);
882 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13,
883 RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_BTN);
884 snd_soc_component_write(component, RT5682_IL_CMD_1, 0x0040);
885 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
886 RT5682_4BTN_IL_MASK | RT5682_4BTN_IL_RST_MASK,
887 RT5682_4BTN_IL_EN | RT5682_4BTN_IL_NOR);
888 if (rt5682->is_sdw)
889 snd_soc_component_update_bits(component,
890 RT5682_IRQ_CTRL_3,
891 RT5682_IL_IRQ_MASK | RT5682_IL_IRQ_TYPE_MASK,
892 RT5682_IL_IRQ_EN | RT5682_IL_IRQ_PUL);
893 else
894 snd_soc_component_update_bits(component,
895 RT5682_IRQ_CTRL_3, RT5682_IL_IRQ_MASK,
896 RT5682_IL_IRQ_EN);
897 } else {
898 snd_soc_component_update_bits(component, RT5682_IRQ_CTRL_3,
899 RT5682_IL_IRQ_MASK, RT5682_IL_IRQ_DIS);
900 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
901 RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_DIS);
902 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
903 RT5682_4BTN_IL_MASK, RT5682_4BTN_IL_DIS);
904 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
905 RT5682_4BTN_IL_RST_MASK, RT5682_4BTN_IL_RST);
906 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13,
907 RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_TYPE);
908 }
909 }
910
911 /**
912 * rt5682_headset_detect - Detect headset.
913 * @component: SoC audio component device.
914 * @jack_insert: Jack insert or not.
915 *
916 * Detect whether is headset or not when jack inserted.
917 *
918 * Returns detect status.
919 */
rt5682_headset_detect(struct snd_soc_component * component,int jack_insert)920 int rt5682_headset_detect(struct snd_soc_component *component, int jack_insert)
921 {
922 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
923 struct snd_soc_dapm_context *dapm = &component->dapm;
924 unsigned int val, count;
925
926 if (jack_insert) {
927 snd_soc_dapm_mutex_lock(dapm);
928
929 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
930 RT5682_PWR_VREF2 | RT5682_PWR_MB,
931 RT5682_PWR_VREF2 | RT5682_PWR_MB);
932 snd_soc_component_update_bits(component,
933 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0);
934 usleep_range(15000, 20000);
935 snd_soc_component_update_bits(component,
936 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, RT5682_PWR_FV2);
937 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,
938 RT5682_PWR_CBJ, RT5682_PWR_CBJ);
939 snd_soc_component_update_bits(component,
940 RT5682_HP_CHARGE_PUMP_1,
941 RT5682_OSW_L_MASK | RT5682_OSW_R_MASK, 0);
942 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
943 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_HIGH);
944
945 count = 0;
946 val = snd_soc_component_read(component, RT5682_CBJ_CTRL_2)
947 & RT5682_JACK_TYPE_MASK;
948 while (val == 0 && count < 50) {
949 usleep_range(10000, 15000);
950 val = snd_soc_component_read(component,
951 RT5682_CBJ_CTRL_2) & RT5682_JACK_TYPE_MASK;
952 count++;
953 }
954
955 switch (val) {
956 case 0x1:
957 case 0x2:
958 rt5682->jack_type = SND_JACK_HEADSET;
959 rt5682_enable_push_button_irq(component, true);
960 break;
961 default:
962 rt5682->jack_type = SND_JACK_HEADPHONE;
963 break;
964 }
965
966 snd_soc_component_update_bits(component,
967 RT5682_HP_CHARGE_PUMP_1,
968 RT5682_OSW_L_MASK | RT5682_OSW_R_MASK,
969 RT5682_OSW_L_EN | RT5682_OSW_R_EN);
970 snd_soc_component_update_bits(component, RT5682_MICBIAS_2,
971 RT5682_PWR_CLK25M_MASK | RT5682_PWR_CLK1M_MASK,
972 RT5682_PWR_CLK25M_PU | RT5682_PWR_CLK1M_PU);
973
974 snd_soc_dapm_mutex_unlock(dapm);
975 } else {
976 rt5682_enable_push_button_irq(component, false);
977 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
978 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_LOW);
979 if (!snd_soc_dapm_get_pin_status(dapm, "MICBIAS") &&
980 !snd_soc_dapm_get_pin_status(dapm, "PLL1") &&
981 !snd_soc_dapm_get_pin_status(dapm, "PLL2B"))
982 snd_soc_component_update_bits(component,
983 RT5682_PWR_ANLG_1, RT5682_PWR_MB, 0);
984 if (!snd_soc_dapm_get_pin_status(dapm, "Vref2") &&
985 !snd_soc_dapm_get_pin_status(dapm, "PLL1") &&
986 !snd_soc_dapm_get_pin_status(dapm, "PLL2B"))
987 snd_soc_component_update_bits(component,
988 RT5682_PWR_ANLG_1, RT5682_PWR_VREF2, 0);
989 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,
990 RT5682_PWR_CBJ, 0);
991 snd_soc_component_update_bits(component, RT5682_MICBIAS_2,
992 RT5682_PWR_CLK25M_MASK | RT5682_PWR_CLK1M_MASK,
993 RT5682_PWR_CLK25M_PD | RT5682_PWR_CLK1M_PD);
994
995 rt5682->jack_type = 0;
996 }
997
998 dev_dbg(component->dev, "jack_type = %d\n", rt5682->jack_type);
999 return rt5682->jack_type;
1000 }
1001 EXPORT_SYMBOL_GPL(rt5682_headset_detect);
1002
rt5682_set_jack_detect(struct snd_soc_component * component,struct snd_soc_jack * hs_jack,void * data)1003 static int rt5682_set_jack_detect(struct snd_soc_component *component,
1004 struct snd_soc_jack *hs_jack, void *data)
1005 {
1006 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1007
1008 rt5682->hs_jack = hs_jack;
1009
1010 if (!hs_jack) {
1011 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1012 RT5682_JD1_EN_MASK, RT5682_JD1_DIS);
1013 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1014 RT5682_POW_JDH | RT5682_POW_JDL, 0);
1015 cancel_delayed_work_sync(&rt5682->jack_detect_work);
1016
1017 return 0;
1018 }
1019
1020 if (!rt5682->is_sdw) {
1021 switch (rt5682->pdata.jd_src) {
1022 case RT5682_JD1:
1023 snd_soc_component_update_bits(component,
1024 RT5682_CBJ_CTRL_2, RT5682_EXT_JD_SRC,
1025 RT5682_EXT_JD_SRC_MANUAL);
1026 snd_soc_component_write(component, RT5682_CBJ_CTRL_1,
1027 0xd042);
1028 snd_soc_component_update_bits(component,
1029 RT5682_CBJ_CTRL_3, RT5682_CBJ_IN_BUF_EN,
1030 RT5682_CBJ_IN_BUF_EN);
1031 snd_soc_component_update_bits(component,
1032 RT5682_SAR_IL_CMD_1, RT5682_SAR_POW_MASK,
1033 RT5682_SAR_POW_EN);
1034 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
1035 RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_IRQ);
1036 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1037 RT5682_POW_IRQ | RT5682_POW_JDH |
1038 RT5682_POW_ANA, RT5682_POW_IRQ |
1039 RT5682_POW_JDH | RT5682_POW_ANA);
1040 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_2,
1041 RT5682_PWR_JDH, RT5682_PWR_JDH);
1042 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1043 RT5682_JD1_EN_MASK | RT5682_JD1_POL_MASK,
1044 RT5682_JD1_EN | RT5682_JD1_POL_NOR);
1045 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_4,
1046 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1047 rt5682->pdata.btndet_delay));
1048 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_5,
1049 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1050 rt5682->pdata.btndet_delay));
1051 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_6,
1052 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1053 rt5682->pdata.btndet_delay));
1054 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_7,
1055 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1056 rt5682->pdata.btndet_delay));
1057 mod_delayed_work(system_power_efficient_wq,
1058 &rt5682->jack_detect_work,
1059 msecs_to_jiffies(250));
1060 break;
1061
1062 case RT5682_JD_NULL:
1063 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1064 RT5682_JD1_EN_MASK, RT5682_JD1_DIS);
1065 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1066 RT5682_POW_JDH | RT5682_POW_JDL, 0);
1067 break;
1068
1069 default:
1070 dev_warn(component->dev, "Wrong JD source\n");
1071 break;
1072 }
1073 }
1074
1075 return 0;
1076 }
1077
rt5682_jack_detect_handler(struct work_struct * work)1078 void rt5682_jack_detect_handler(struct work_struct *work)
1079 {
1080 struct rt5682_priv *rt5682 =
1081 container_of(work, struct rt5682_priv, jack_detect_work.work);
1082 int val, btn_type;
1083
1084 while (!rt5682->component)
1085 usleep_range(10000, 15000);
1086
1087 while (!rt5682->component->card->instantiated)
1088 usleep_range(10000, 15000);
1089
1090 mutex_lock(&rt5682->calibrate_mutex);
1091
1092 val = snd_soc_component_read(rt5682->component, RT5682_AJD1_CTRL)
1093 & RT5682_JDH_RS_MASK;
1094 if (!val) {
1095 /* jack in */
1096 if (rt5682->jack_type == 0) {
1097 /* jack was out, report jack type */
1098 rt5682->jack_type =
1099 rt5682_headset_detect(rt5682->component, 1);
1100 } else if ((rt5682->jack_type & SND_JACK_HEADSET) ==
1101 SND_JACK_HEADSET) {
1102 /* jack is already in, report button event */
1103 rt5682->jack_type = SND_JACK_HEADSET;
1104 btn_type = rt5682_button_detect(rt5682->component);
1105 /**
1106 * rt5682 can report three kinds of button behavior,
1107 * one click, double click and hold. However,
1108 * currently we will report button pressed/released
1109 * event. So all the three button behaviors are
1110 * treated as button pressed.
1111 */
1112 switch (btn_type) {
1113 case 0x8000:
1114 case 0x4000:
1115 case 0x2000:
1116 rt5682->jack_type |= SND_JACK_BTN_0;
1117 break;
1118 case 0x1000:
1119 case 0x0800:
1120 case 0x0400:
1121 rt5682->jack_type |= SND_JACK_BTN_1;
1122 break;
1123 case 0x0200:
1124 case 0x0100:
1125 case 0x0080:
1126 rt5682->jack_type |= SND_JACK_BTN_2;
1127 break;
1128 case 0x0040:
1129 case 0x0020:
1130 case 0x0010:
1131 rt5682->jack_type |= SND_JACK_BTN_3;
1132 break;
1133 case 0x0000: /* unpressed */
1134 break;
1135 default:
1136 dev_err(rt5682->component->dev,
1137 "Unexpected button code 0x%04x\n",
1138 btn_type);
1139 break;
1140 }
1141 }
1142 } else {
1143 /* jack out */
1144 rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0);
1145 }
1146
1147 snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type,
1148 SND_JACK_HEADSET |
1149 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1150 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1151
1152 if (!rt5682->is_sdw) {
1153 if (rt5682->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1154 SND_JACK_BTN_2 | SND_JACK_BTN_3))
1155 schedule_delayed_work(&rt5682->jd_check_work, 0);
1156 else
1157 cancel_delayed_work_sync(&rt5682->jd_check_work);
1158 }
1159
1160 mutex_unlock(&rt5682->calibrate_mutex);
1161 }
1162 EXPORT_SYMBOL_GPL(rt5682_jack_detect_handler);
1163
1164 static const struct snd_kcontrol_new rt5682_snd_controls[] = {
1165 /* DAC Digital Volume */
1166 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5682_DAC1_DIG_VOL,
1167 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 87, 0, dac_vol_tlv),
1168
1169 /* IN Boost Volume */
1170 SOC_SINGLE_TLV("CBJ Boost Volume", RT5682_CBJ_BST_CTRL,
1171 RT5682_BST_CBJ_SFT, 8, 0, bst_tlv),
1172
1173 /* ADC Digital Volume Control */
1174 SOC_DOUBLE("STO1 ADC Capture Switch", RT5682_STO1_ADC_DIG_VOL,
1175 RT5682_L_MUTE_SFT, RT5682_R_MUTE_SFT, 1, 1),
1176 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5682_STO1_ADC_DIG_VOL,
1177 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
1178
1179 /* ADC Boost Volume Control */
1180 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5682_STO1_ADC_BOOST,
1181 RT5682_STO1_ADC_L_BST_SFT, RT5682_STO1_ADC_R_BST_SFT,
1182 3, 0, adc_bst_tlv),
1183 };
1184
rt5682_div_sel(struct rt5682_priv * rt5682,int target,const int div[],int size)1185 static int rt5682_div_sel(struct rt5682_priv *rt5682,
1186 int target, const int div[], int size)
1187 {
1188 int i;
1189
1190 if (rt5682->sysclk < target) {
1191 dev_err(rt5682->component->dev,
1192 "sysclk rate %d is too low\n", rt5682->sysclk);
1193 return 0;
1194 }
1195
1196 for (i = 0; i < size - 1; i++) {
1197 dev_dbg(rt5682->component->dev, "div[%d]=%d\n", i, div[i]);
1198 if (target * div[i] == rt5682->sysclk)
1199 return i;
1200 if (target * div[i + 1] > rt5682->sysclk) {
1201 dev_dbg(rt5682->component->dev,
1202 "can't find div for sysclk %d\n",
1203 rt5682->sysclk);
1204 return i;
1205 }
1206 }
1207
1208 if (target * div[i] < rt5682->sysclk)
1209 dev_err(rt5682->component->dev,
1210 "sysclk rate %d is too high\n", rt5682->sysclk);
1211
1212 return size - 1;
1213 }
1214
1215 /**
1216 * set_dmic_clk - Set parameter of dmic.
1217 *
1218 * @w: DAPM widget.
1219 * @kcontrol: The kcontrol of this widget.
1220 * @event: Event id.
1221 *
1222 * Choose dmic clock between 1MHz and 3MHz.
1223 * It is better for clock to approximate 3MHz.
1224 */
set_dmic_clk(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1225 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
1226 struct snd_kcontrol *kcontrol, int event)
1227 {
1228 struct snd_soc_component *component =
1229 snd_soc_dapm_to_component(w->dapm);
1230 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1231 int idx = -EINVAL, dmic_clk_rate = 3072000;
1232 static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128};
1233
1234 if (rt5682->pdata.dmic_clk_rate)
1235 dmic_clk_rate = rt5682->pdata.dmic_clk_rate;
1236
1237 idx = rt5682_div_sel(rt5682, dmic_clk_rate, div, ARRAY_SIZE(div));
1238
1239 snd_soc_component_update_bits(component, RT5682_DMIC_CTRL_1,
1240 RT5682_DMIC_CLK_MASK, idx << RT5682_DMIC_CLK_SFT);
1241
1242 return 0;
1243 }
1244
set_filter_clk(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1245 static int set_filter_clk(struct snd_soc_dapm_widget *w,
1246 struct snd_kcontrol *kcontrol, int event)
1247 {
1248 struct snd_soc_component *component =
1249 snd_soc_dapm_to_component(w->dapm);
1250 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1251 int ref, val, reg, idx = -EINVAL;
1252 static const int div_f[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48};
1253 static const int div_o[] = {1, 2, 4, 6, 8, 12, 16, 24, 32, 48};
1254
1255 if (rt5682->is_sdw)
1256 return 0;
1257
1258 val = snd_soc_component_read(component, RT5682_GPIO_CTRL_1) &
1259 RT5682_GP4_PIN_MASK;
1260 if (w->shift == RT5682_PWR_ADC_S1F_BIT &&
1261 val == RT5682_GP4_PIN_ADCDAT2)
1262 ref = 256 * rt5682->lrck[RT5682_AIF2];
1263 else
1264 ref = 256 * rt5682->lrck[RT5682_AIF1];
1265
1266 idx = rt5682_div_sel(rt5682, ref, div_f, ARRAY_SIZE(div_f));
1267
1268 if (w->shift == RT5682_PWR_ADC_S1F_BIT)
1269 reg = RT5682_PLL_TRACK_3;
1270 else
1271 reg = RT5682_PLL_TRACK_2;
1272
1273 snd_soc_component_update_bits(component, reg,
1274 RT5682_FILTER_CLK_DIV_MASK, idx << RT5682_FILTER_CLK_DIV_SFT);
1275
1276 /* select over sample rate */
1277 for (idx = 0; idx < ARRAY_SIZE(div_o); idx++) {
1278 if (rt5682->sysclk <= 12288000 * div_o[idx])
1279 break;
1280 }
1281
1282 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1,
1283 RT5682_ADC_OSR_MASK | RT5682_DAC_OSR_MASK,
1284 (idx << RT5682_ADC_OSR_SFT) | (idx << RT5682_DAC_OSR_SFT));
1285
1286 return 0;
1287 }
1288
is_sys_clk_from_pll1(struct snd_soc_dapm_widget * w,struct snd_soc_dapm_widget * sink)1289 static int is_sys_clk_from_pll1(struct snd_soc_dapm_widget *w,
1290 struct snd_soc_dapm_widget *sink)
1291 {
1292 unsigned int val;
1293 struct snd_soc_component *component =
1294 snd_soc_dapm_to_component(w->dapm);
1295
1296 val = snd_soc_component_read(component, RT5682_GLB_CLK);
1297 val &= RT5682_SCLK_SRC_MASK;
1298 if (val == RT5682_SCLK_SRC_PLL1)
1299 return 1;
1300 else
1301 return 0;
1302 }
1303
is_sys_clk_from_pll2(struct snd_soc_dapm_widget * w,struct snd_soc_dapm_widget * sink)1304 static int is_sys_clk_from_pll2(struct snd_soc_dapm_widget *w,
1305 struct snd_soc_dapm_widget *sink)
1306 {
1307 unsigned int val;
1308 struct snd_soc_component *component =
1309 snd_soc_dapm_to_component(w->dapm);
1310
1311 val = snd_soc_component_read(component, RT5682_GLB_CLK);
1312 val &= RT5682_SCLK_SRC_MASK;
1313 if (val == RT5682_SCLK_SRC_PLL2)
1314 return 1;
1315 else
1316 return 0;
1317 }
1318
is_using_asrc(struct snd_soc_dapm_widget * w,struct snd_soc_dapm_widget * sink)1319 static int is_using_asrc(struct snd_soc_dapm_widget *w,
1320 struct snd_soc_dapm_widget *sink)
1321 {
1322 unsigned int reg, shift, val;
1323 struct snd_soc_component *component =
1324 snd_soc_dapm_to_component(w->dapm);
1325
1326 switch (w->shift) {
1327 case RT5682_ADC_STO1_ASRC_SFT:
1328 reg = RT5682_PLL_TRACK_3;
1329 shift = RT5682_FILTER_CLK_SEL_SFT;
1330 break;
1331 case RT5682_DAC_STO1_ASRC_SFT:
1332 reg = RT5682_PLL_TRACK_2;
1333 shift = RT5682_FILTER_CLK_SEL_SFT;
1334 break;
1335 default:
1336 return 0;
1337 }
1338
1339 val = (snd_soc_component_read(component, reg) >> shift) & 0xf;
1340 switch (val) {
1341 case RT5682_CLK_SEL_I2S1_ASRC:
1342 case RT5682_CLK_SEL_I2S2_ASRC:
1343 return 1;
1344 default:
1345 return 0;
1346 }
1347 }
1348
1349 /* Digital Mixer */
1350 static const struct snd_kcontrol_new rt5682_sto1_adc_l_mix[] = {
1351 SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER,
1352 RT5682_M_STO1_ADC_L1_SFT, 1, 1),
1353 SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER,
1354 RT5682_M_STO1_ADC_L2_SFT, 1, 1),
1355 };
1356
1357 static const struct snd_kcontrol_new rt5682_sto1_adc_r_mix[] = {
1358 SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER,
1359 RT5682_M_STO1_ADC_R1_SFT, 1, 1),
1360 SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER,
1361 RT5682_M_STO1_ADC_R2_SFT, 1, 1),
1362 };
1363
1364 static const struct snd_kcontrol_new rt5682_dac_l_mix[] = {
1365 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
1366 RT5682_M_ADCMIX_L_SFT, 1, 1),
1367 SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER,
1368 RT5682_M_DAC1_L_SFT, 1, 1),
1369 };
1370
1371 static const struct snd_kcontrol_new rt5682_dac_r_mix[] = {
1372 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
1373 RT5682_M_ADCMIX_R_SFT, 1, 1),
1374 SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER,
1375 RT5682_M_DAC1_R_SFT, 1, 1),
1376 };
1377
1378 static const struct snd_kcontrol_new rt5682_sto1_dac_l_mix[] = {
1379 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER,
1380 RT5682_M_DAC_L1_STO_L_SFT, 1, 1),
1381 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER,
1382 RT5682_M_DAC_R1_STO_L_SFT, 1, 1),
1383 };
1384
1385 static const struct snd_kcontrol_new rt5682_sto1_dac_r_mix[] = {
1386 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER,
1387 RT5682_M_DAC_L1_STO_R_SFT, 1, 1),
1388 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER,
1389 RT5682_M_DAC_R1_STO_R_SFT, 1, 1),
1390 };
1391
1392 /* Analog Input Mixer */
1393 static const struct snd_kcontrol_new rt5682_rec1_l_mix[] = {
1394 SOC_DAPM_SINGLE("CBJ Switch", RT5682_REC_MIXER,
1395 RT5682_M_CBJ_RM1_L_SFT, 1, 1),
1396 };
1397
1398 /* STO1 ADC1 Source */
1399 /* MX-26 [13] [5] */
1400 static const char * const rt5682_sto1_adc1_src[] = {
1401 "DAC MIX", "ADC"
1402 };
1403
1404 static SOC_ENUM_SINGLE_DECL(
1405 rt5682_sto1_adc1l_enum, RT5682_STO1_ADC_MIXER,
1406 RT5682_STO1_ADC1L_SRC_SFT, rt5682_sto1_adc1_src);
1407
1408 static const struct snd_kcontrol_new rt5682_sto1_adc1l_mux =
1409 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1l_enum);
1410
1411 static SOC_ENUM_SINGLE_DECL(
1412 rt5682_sto1_adc1r_enum, RT5682_STO1_ADC_MIXER,
1413 RT5682_STO1_ADC1R_SRC_SFT, rt5682_sto1_adc1_src);
1414
1415 static const struct snd_kcontrol_new rt5682_sto1_adc1r_mux =
1416 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1r_enum);
1417
1418 /* STO1 ADC Source */
1419 /* MX-26 [11:10] [3:2] */
1420 static const char * const rt5682_sto1_adc_src[] = {
1421 "ADC1 L", "ADC1 R"
1422 };
1423
1424 static SOC_ENUM_SINGLE_DECL(
1425 rt5682_sto1_adcl_enum, RT5682_STO1_ADC_MIXER,
1426 RT5682_STO1_ADCL_SRC_SFT, rt5682_sto1_adc_src);
1427
1428 static const struct snd_kcontrol_new rt5682_sto1_adcl_mux =
1429 SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5682_sto1_adcl_enum);
1430
1431 static SOC_ENUM_SINGLE_DECL(
1432 rt5682_sto1_adcr_enum, RT5682_STO1_ADC_MIXER,
1433 RT5682_STO1_ADCR_SRC_SFT, rt5682_sto1_adc_src);
1434
1435 static const struct snd_kcontrol_new rt5682_sto1_adcr_mux =
1436 SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5682_sto1_adcr_enum);
1437
1438 /* STO1 ADC2 Source */
1439 /* MX-26 [12] [4] */
1440 static const char * const rt5682_sto1_adc2_src[] = {
1441 "DAC MIX", "DMIC"
1442 };
1443
1444 static SOC_ENUM_SINGLE_DECL(
1445 rt5682_sto1_adc2l_enum, RT5682_STO1_ADC_MIXER,
1446 RT5682_STO1_ADC2L_SRC_SFT, rt5682_sto1_adc2_src);
1447
1448 static const struct snd_kcontrol_new rt5682_sto1_adc2l_mux =
1449 SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5682_sto1_adc2l_enum);
1450
1451 static SOC_ENUM_SINGLE_DECL(
1452 rt5682_sto1_adc2r_enum, RT5682_STO1_ADC_MIXER,
1453 RT5682_STO1_ADC2R_SRC_SFT, rt5682_sto1_adc2_src);
1454
1455 static const struct snd_kcontrol_new rt5682_sto1_adc2r_mux =
1456 SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5682_sto1_adc2r_enum);
1457
1458 /* MX-79 [6:4] I2S1 ADC data location */
1459 static const unsigned int rt5682_if1_adc_slot_values[] = {
1460 0,
1461 2,
1462 4,
1463 6,
1464 };
1465
1466 static const char * const rt5682_if1_adc_slot_src[] = {
1467 "Slot 0", "Slot 2", "Slot 4", "Slot 6"
1468 };
1469
1470 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_if1_adc_slot_enum,
1471 RT5682_TDM_CTRL, RT5682_TDM_ADC_LCA_SFT, RT5682_TDM_ADC_LCA_MASK,
1472 rt5682_if1_adc_slot_src, rt5682_if1_adc_slot_values);
1473
1474 static const struct snd_kcontrol_new rt5682_if1_adc_slot_mux =
1475 SOC_DAPM_ENUM("IF1 ADC Slot location", rt5682_if1_adc_slot_enum);
1476
1477 /* Analog DAC L1 Source, Analog DAC R1 Source*/
1478 /* MX-2B [4], MX-2B [0]*/
1479 static const char * const rt5682_alg_dac1_src[] = {
1480 "Stereo1 DAC Mixer", "DAC1"
1481 };
1482
1483 static SOC_ENUM_SINGLE_DECL(
1484 rt5682_alg_dac_l1_enum, RT5682_A_DAC1_MUX,
1485 RT5682_A_DACL1_SFT, rt5682_alg_dac1_src);
1486
1487 static const struct snd_kcontrol_new rt5682_alg_dac_l1_mux =
1488 SOC_DAPM_ENUM("Analog DAC L1 Source", rt5682_alg_dac_l1_enum);
1489
1490 static SOC_ENUM_SINGLE_DECL(
1491 rt5682_alg_dac_r1_enum, RT5682_A_DAC1_MUX,
1492 RT5682_A_DACR1_SFT, rt5682_alg_dac1_src);
1493
1494 static const struct snd_kcontrol_new rt5682_alg_dac_r1_mux =
1495 SOC_DAPM_ENUM("Analog DAC R1 Source", rt5682_alg_dac_r1_enum);
1496
1497 /* Out Switch */
1498 static const struct snd_kcontrol_new hpol_switch =
1499 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1,
1500 RT5682_L_MUTE_SFT, 1, 1);
1501 static const struct snd_kcontrol_new hpor_switch =
1502 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1,
1503 RT5682_R_MUTE_SFT, 1, 1);
1504
rt5682_hp_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1505 static int rt5682_hp_event(struct snd_soc_dapm_widget *w,
1506 struct snd_kcontrol *kcontrol, int event)
1507 {
1508 struct snd_soc_component *component =
1509 snd_soc_dapm_to_component(w->dapm);
1510
1511 switch (event) {
1512 case SND_SOC_DAPM_PRE_PMU:
1513 snd_soc_component_write(component,
1514 RT5682_HP_LOGIC_CTRL_2, 0x0012);
1515 snd_soc_component_write(component,
1516 RT5682_HP_CTRL_2, 0x6000);
1517 snd_soc_component_update_bits(component,
1518 RT5682_DEPOP_1, 0x60, 0x60);
1519 snd_soc_component_update_bits(component,
1520 RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0080);
1521 break;
1522
1523 case SND_SOC_DAPM_POST_PMD:
1524 snd_soc_component_update_bits(component,
1525 RT5682_DEPOP_1, 0x60, 0x0);
1526 snd_soc_component_write(component,
1527 RT5682_HP_CTRL_2, 0x0000);
1528 snd_soc_component_update_bits(component,
1529 RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0000);
1530 break;
1531 }
1532
1533 return 0;
1534 }
1535
set_dmic_power(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1536 static int set_dmic_power(struct snd_soc_dapm_widget *w,
1537 struct snd_kcontrol *kcontrol, int event)
1538 {
1539 struct snd_soc_component *component =
1540 snd_soc_dapm_to_component(w->dapm);
1541 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1542 unsigned int delay = 50, val;
1543
1544 if (rt5682->pdata.dmic_delay)
1545 delay = rt5682->pdata.dmic_delay;
1546
1547 switch (event) {
1548 case SND_SOC_DAPM_POST_PMU:
1549 val = snd_soc_component_read(component, RT5682_GLB_CLK);
1550 val &= RT5682_SCLK_SRC_MASK;
1551 if (val == RT5682_SCLK_SRC_PLL1 || val == RT5682_SCLK_SRC_PLL2)
1552 snd_soc_component_update_bits(component,
1553 RT5682_PWR_ANLG_1,
1554 RT5682_PWR_VREF2 | RT5682_PWR_MB,
1555 RT5682_PWR_VREF2 | RT5682_PWR_MB);
1556
1557 /*Add delay to avoid pop noise*/
1558 msleep(delay);
1559 break;
1560
1561 case SND_SOC_DAPM_POST_PMD:
1562 if (!rt5682->jack_type) {
1563 if (!snd_soc_dapm_get_pin_status(w->dapm, "MICBIAS"))
1564 snd_soc_component_update_bits(component,
1565 RT5682_PWR_ANLG_1, RT5682_PWR_MB, 0);
1566 if (!snd_soc_dapm_get_pin_status(w->dapm, "Vref2"))
1567 snd_soc_component_update_bits(component,
1568 RT5682_PWR_ANLG_1, RT5682_PWR_VREF2, 0);
1569 }
1570 break;
1571 }
1572
1573 return 0;
1574 }
1575
rt5682_set_verf(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1576 static int rt5682_set_verf(struct snd_soc_dapm_widget *w,
1577 struct snd_kcontrol *kcontrol, int event)
1578 {
1579 struct snd_soc_component *component =
1580 snd_soc_dapm_to_component(w->dapm);
1581
1582 switch (event) {
1583 case SND_SOC_DAPM_PRE_PMU:
1584 switch (w->shift) {
1585 case RT5682_PWR_VREF1_BIT:
1586 snd_soc_component_update_bits(component,
1587 RT5682_PWR_ANLG_1, RT5682_PWR_FV1, 0);
1588 break;
1589
1590 case RT5682_PWR_VREF2_BIT:
1591 snd_soc_component_update_bits(component,
1592 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0);
1593 break;
1594 }
1595 break;
1596
1597 case SND_SOC_DAPM_POST_PMU:
1598 usleep_range(15000, 20000);
1599 switch (w->shift) {
1600 case RT5682_PWR_VREF1_BIT:
1601 snd_soc_component_update_bits(component,
1602 RT5682_PWR_ANLG_1, RT5682_PWR_FV1,
1603 RT5682_PWR_FV1);
1604 break;
1605
1606 case RT5682_PWR_VREF2_BIT:
1607 snd_soc_component_update_bits(component,
1608 RT5682_PWR_ANLG_1, RT5682_PWR_FV2,
1609 RT5682_PWR_FV2);
1610 break;
1611 }
1612 break;
1613 }
1614
1615 return 0;
1616 }
1617
1618 static const unsigned int rt5682_adcdat_pin_values[] = {
1619 1,
1620 3,
1621 };
1622
1623 static const char * const rt5682_adcdat_pin_select[] = {
1624 "ADCDAT1",
1625 "ADCDAT2",
1626 };
1627
1628 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_adcdat_pin_enum,
1629 RT5682_GPIO_CTRL_1, RT5682_GP4_PIN_SFT, RT5682_GP4_PIN_MASK,
1630 rt5682_adcdat_pin_select, rt5682_adcdat_pin_values);
1631
1632 static const struct snd_kcontrol_new rt5682_adcdat_pin_ctrl =
1633 SOC_DAPM_ENUM("ADCDAT", rt5682_adcdat_pin_enum);
1634
1635 static const struct snd_soc_dapm_widget rt5682_dapm_widgets[] = {
1636 SND_SOC_DAPM_SUPPLY("LDO2", RT5682_PWR_ANLG_3, RT5682_PWR_LDO2_BIT,
1637 0, NULL, 0),
1638 SND_SOC_DAPM_SUPPLY("PLL1", RT5682_PWR_ANLG_3, RT5682_PWR_PLL_BIT,
1639 0, NULL, 0),
1640 SND_SOC_DAPM_SUPPLY("PLL2B", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2B_BIT,
1641 0, NULL, 0),
1642 SND_SOC_DAPM_SUPPLY("PLL2F", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2F_BIT,
1643 0, set_filter_clk, SND_SOC_DAPM_PRE_PMU),
1644 SND_SOC_DAPM_SUPPLY("Vref1", RT5682_PWR_ANLG_1, RT5682_PWR_VREF1_BIT, 0,
1645 rt5682_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1646 SND_SOC_DAPM_SUPPLY("Vref2", SND_SOC_NOPM, 0, 0, NULL, 0),
1647 SND_SOC_DAPM_SUPPLY("MICBIAS", SND_SOC_NOPM, 0, 0, NULL, 0),
1648
1649 /* ASRC */
1650 SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5682_PLL_TRACK_1,
1651 RT5682_DAC_STO1_ASRC_SFT, 0, NULL, 0),
1652 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5682_PLL_TRACK_1,
1653 RT5682_ADC_STO1_ASRC_SFT, 0, NULL, 0),
1654 SND_SOC_DAPM_SUPPLY_S("AD ASRC", 1, RT5682_PLL_TRACK_1,
1655 RT5682_AD_ASRC_SFT, 0, NULL, 0),
1656 SND_SOC_DAPM_SUPPLY_S("DA ASRC", 1, RT5682_PLL_TRACK_1,
1657 RT5682_DA_ASRC_SFT, 0, NULL, 0),
1658 SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5682_PLL_TRACK_1,
1659 RT5682_DMIC_ASRC_SFT, 0, NULL, 0),
1660
1661 /* Input Side */
1662 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5682_PWR_ANLG_2, RT5682_PWR_MB1_BIT,
1663 0, NULL, 0),
1664 SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5682_PWR_ANLG_2, RT5682_PWR_MB2_BIT,
1665 0, NULL, 0),
1666
1667 /* Input Lines */
1668 SND_SOC_DAPM_INPUT("DMIC L1"),
1669 SND_SOC_DAPM_INPUT("DMIC R1"),
1670
1671 SND_SOC_DAPM_INPUT("IN1P"),
1672
1673 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1674 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1675 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5682_DMIC_CTRL_1,
1676 RT5682_DMIC_1_EN_SFT, 0, set_dmic_power,
1677 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1678
1679 /* Boost */
1680 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM,
1681 0, 0, NULL, 0),
1682
1683 /* REC Mixer */
1684 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5682_rec1_l_mix,
1685 ARRAY_SIZE(rt5682_rec1_l_mix)),
1686 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5682_PWR_ANLG_2,
1687 RT5682_PWR_RM1_L_BIT, 0, NULL, 0),
1688
1689 /* ADCs */
1690 SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),
1691 SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),
1692
1693 SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5682_PWR_DIG_1,
1694 RT5682_PWR_ADC_L1_BIT, 0, NULL, 0),
1695 SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5682_PWR_DIG_1,
1696 RT5682_PWR_ADC_R1_BIT, 0, NULL, 0),
1697 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5682_CHOP_ADC,
1698 RT5682_CKGEN_ADC1_SFT, 0, NULL, 0),
1699
1700 /* ADC Mux */
1701 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1702 &rt5682_sto1_adc1l_mux),
1703 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1704 &rt5682_sto1_adc1r_mux),
1705 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1706 &rt5682_sto1_adc2l_mux),
1707 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1708 &rt5682_sto1_adc2r_mux),
1709 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
1710 &rt5682_sto1_adcl_mux),
1711 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
1712 &rt5682_sto1_adcr_mux),
1713 SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0,
1714 &rt5682_if1_adc_slot_mux),
1715
1716 /* ADC Mixer */
1717 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5682_PWR_DIG_2,
1718 RT5682_PWR_ADC_S1F_BIT, 0, set_filter_clk,
1719 SND_SOC_DAPM_PRE_PMU),
1720 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5682_STO1_ADC_DIG_VOL,
1721 RT5682_L_MUTE_SFT, 1, rt5682_sto1_adc_l_mix,
1722 ARRAY_SIZE(rt5682_sto1_adc_l_mix)),
1723 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5682_STO1_ADC_DIG_VOL,
1724 RT5682_R_MUTE_SFT, 1, rt5682_sto1_adc_r_mix,
1725 ARRAY_SIZE(rt5682_sto1_adc_r_mix)),
1726 SND_SOC_DAPM_SUPPLY("BTN Detection Mode", RT5682_SAR_IL_CMD_1,
1727 14, 1, NULL, 0),
1728
1729 /* ADC PGA */
1730 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1731
1732 /* Digital Interface */
1733 SND_SOC_DAPM_SUPPLY("I2S1", RT5682_PWR_DIG_1, RT5682_PWR_I2S1_BIT,
1734 0, NULL, 0),
1735 SND_SOC_DAPM_SUPPLY("I2S2", RT5682_PWR_DIG_1, RT5682_PWR_I2S2_BIT,
1736 0, NULL, 0),
1737 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1738 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1739 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1740 SND_SOC_DAPM_PGA("SOUND DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1741 SND_SOC_DAPM_PGA("SOUND DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1742
1743 /* Digital Interface Select */
1744 SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1745 &rt5682_if1_01_adc_swap_mux),
1746 SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1747 &rt5682_if1_23_adc_swap_mux),
1748 SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1749 &rt5682_if1_45_adc_swap_mux),
1750 SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1751 &rt5682_if1_67_adc_swap_mux),
1752 SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1753 &rt5682_if2_adc_swap_mux),
1754
1755 SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0,
1756 &rt5682_adcdat_pin_ctrl),
1757
1758 SND_SOC_DAPM_MUX("DAC L Mux", SND_SOC_NOPM, 0, 0,
1759 &rt5682_dac_l_mux),
1760 SND_SOC_DAPM_MUX("DAC R Mux", SND_SOC_NOPM, 0, 0,
1761 &rt5682_dac_r_mux),
1762
1763 /* Audio Interface */
1764 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0,
1765 RT5682_I2S1_SDP, RT5682_SEL_ADCDAT_SFT, 1),
1766 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0,
1767 RT5682_I2S2_SDP, RT5682_I2S2_PIN_CFG_SFT, 1),
1768 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1769 SND_SOC_DAPM_AIF_IN("SDWRX", "SDW Playback", 0, SND_SOC_NOPM, 0, 0),
1770 SND_SOC_DAPM_AIF_OUT("SDWTX", "SDW Capture", 0, SND_SOC_NOPM, 0, 0),
1771
1772 /* Output Side */
1773 /* DAC mixer before sound effect */
1774 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
1775 rt5682_dac_l_mix, ARRAY_SIZE(rt5682_dac_l_mix)),
1776 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
1777 rt5682_dac_r_mix, ARRAY_SIZE(rt5682_dac_r_mix)),
1778
1779 /* DAC channel Mux */
1780 SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0,
1781 &rt5682_alg_dac_l1_mux),
1782 SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0,
1783 &rt5682_alg_dac_r1_mux),
1784
1785 /* DAC Mixer */
1786 SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5682_PWR_DIG_2,
1787 RT5682_PWR_DAC_S1F_BIT, 0, set_filter_clk,
1788 SND_SOC_DAPM_PRE_PMU),
1789 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0,
1790 rt5682_sto1_dac_l_mix, ARRAY_SIZE(rt5682_sto1_dac_l_mix)),
1791 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0,
1792 rt5682_sto1_dac_r_mix, ARRAY_SIZE(rt5682_sto1_dac_r_mix)),
1793
1794 /* DACs */
1795 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5682_PWR_DIG_1,
1796 RT5682_PWR_DAC_L1_BIT, 0),
1797 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5682_PWR_DIG_1,
1798 RT5682_PWR_DAC_R1_BIT, 0),
1799 SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 3, RT5682_CHOP_DAC,
1800 RT5682_CKGEN_DAC1_SFT, 0, NULL, 0),
1801
1802 /* HPO */
1803 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5682_hp_event,
1804 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
1805
1806 SND_SOC_DAPM_SUPPLY("HP Amp L", RT5682_PWR_ANLG_1,
1807 RT5682_PWR_HA_L_BIT, 0, NULL, 0),
1808 SND_SOC_DAPM_SUPPLY("HP Amp R", RT5682_PWR_ANLG_1,
1809 RT5682_PWR_HA_R_BIT, 0, NULL, 0),
1810 SND_SOC_DAPM_SUPPLY_S("Charge Pump", 1, RT5682_DEPOP_1,
1811 RT5682_PUMP_EN_SFT, 0, NULL, 0),
1812 SND_SOC_DAPM_SUPPLY_S("Capless", 2, RT5682_DEPOP_1,
1813 RT5682_CAPLESS_EN_SFT, 0, NULL, 0),
1814
1815 SND_SOC_DAPM_SWITCH("HPOL Playback", SND_SOC_NOPM, 0, 0,
1816 &hpol_switch),
1817 SND_SOC_DAPM_SWITCH("HPOR Playback", SND_SOC_NOPM, 0, 0,
1818 &hpor_switch),
1819
1820 /* CLK DET */
1821 SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5682_CLK_DET,
1822 RT5682_SYS_CLK_DET_SFT, 0, NULL, 0),
1823 SND_SOC_DAPM_SUPPLY("CLKDET PLL1", RT5682_CLK_DET,
1824 RT5682_PLL1_CLK_DET_SFT, 0, NULL, 0),
1825 SND_SOC_DAPM_SUPPLY("CLKDET PLL2", RT5682_CLK_DET,
1826 RT5682_PLL2_CLK_DET_SFT, 0, NULL, 0),
1827 SND_SOC_DAPM_SUPPLY("CLKDET", RT5682_CLK_DET,
1828 RT5682_POW_CLK_DET_SFT, 0, NULL, 0),
1829
1830 /* Output Lines */
1831 SND_SOC_DAPM_OUTPUT("HPOL"),
1832 SND_SOC_DAPM_OUTPUT("HPOR"),
1833 };
1834
1835 static const struct snd_soc_dapm_route rt5682_dapm_routes[] = {
1836 /*PLL*/
1837 {"ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
1838 {"ADC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2},
1839 {"ADC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2},
1840 {"DAC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
1841 {"DAC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2},
1842 {"DAC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2},
1843
1844 /*ASRC*/
1845 {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
1846 {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc},
1847 {"ADC STO1 ASRC", NULL, "AD ASRC"},
1848 {"ADC STO1 ASRC", NULL, "DA ASRC"},
1849 {"ADC STO1 ASRC", NULL, "CLKDET"},
1850 {"DAC STO1 ASRC", NULL, "AD ASRC"},
1851 {"DAC STO1 ASRC", NULL, "DA ASRC"},
1852 {"DAC STO1 ASRC", NULL, "CLKDET"},
1853
1854 /*Vref*/
1855 {"MICBIAS1", NULL, "Vref1"},
1856 {"MICBIAS2", NULL, "Vref1"},
1857
1858 {"CLKDET SYS", NULL, "CLKDET"},
1859
1860 {"IN1P", NULL, "LDO2"},
1861
1862 {"BST1 CBJ", NULL, "IN1P"},
1863
1864 {"RECMIX1L", "CBJ Switch", "BST1 CBJ"},
1865 {"RECMIX1L", NULL, "RECMIX1L Power"},
1866
1867 {"ADC1 L", NULL, "RECMIX1L"},
1868 {"ADC1 L", NULL, "ADC1 L Power"},
1869 {"ADC1 L", NULL, "ADC1 clock"},
1870
1871 {"DMIC L1", NULL, "DMIC CLK"},
1872 {"DMIC L1", NULL, "DMIC1 Power"},
1873 {"DMIC R1", NULL, "DMIC CLK"},
1874 {"DMIC R1", NULL, "DMIC1 Power"},
1875 {"DMIC CLK", NULL, "DMIC ASRC"},
1876
1877 {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
1878 {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
1879 {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
1880 {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
1881
1882 {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
1883 {"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1884 {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"},
1885 {"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1886
1887 {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
1888 {"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1889 {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"},
1890 {"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1891
1892 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
1893 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
1894 {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"},
1895
1896 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
1897 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
1898 {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
1899
1900 {"ADC Stereo1 Filter", NULL, "BTN Detection Mode"},
1901
1902 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
1903 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
1904
1905 {"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1906 {"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1907 {"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1908 {"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1909 {"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1910 {"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1911 {"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1912 {"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1913 {"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1914 {"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1915 {"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1916 {"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1917 {"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1918 {"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1919 {"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1920 {"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1921
1922 {"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"},
1923 {"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"},
1924 {"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"},
1925 {"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"},
1926 {"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"},
1927 {"AIF1TX", NULL, "I2S1"},
1928 {"AIF1TX", NULL, "ADCDAT Mux"},
1929 {"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1930 {"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1931 {"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1932 {"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1933 {"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"},
1934 {"AIF2TX", NULL, "ADCDAT Mux"},
1935
1936 {"SDWTX", NULL, "PLL2B"},
1937 {"SDWTX", NULL, "PLL2F"},
1938 {"SDWTX", NULL, "ADCDAT Mux"},
1939
1940 {"IF1 DAC1 L", NULL, "AIF1RX"},
1941 {"IF1 DAC1 L", NULL, "I2S1"},
1942 {"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"},
1943 {"IF1 DAC1 R", NULL, "AIF1RX"},
1944 {"IF1 DAC1 R", NULL, "I2S1"},
1945 {"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"},
1946
1947 {"SOUND DAC L", NULL, "SDWRX"},
1948 {"SOUND DAC L", NULL, "DAC Stereo1 Filter"},
1949 {"SOUND DAC L", NULL, "PLL2B"},
1950 {"SOUND DAC L", NULL, "PLL2F"},
1951 {"SOUND DAC R", NULL, "SDWRX"},
1952 {"SOUND DAC R", NULL, "DAC Stereo1 Filter"},
1953 {"SOUND DAC R", NULL, "PLL2B"},
1954 {"SOUND DAC R", NULL, "PLL2F"},
1955
1956 {"DAC L Mux", "IF1", "IF1 DAC1 L"},
1957 {"DAC L Mux", "SOUND", "SOUND DAC L"},
1958 {"DAC R Mux", "IF1", "IF1 DAC1 R"},
1959 {"DAC R Mux", "SOUND", "SOUND DAC R"},
1960
1961 {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
1962 {"DAC1 MIXL", "DAC1 Switch", "DAC L Mux"},
1963 {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
1964 {"DAC1 MIXR", "DAC1 Switch", "DAC R Mux"},
1965
1966 {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
1967 {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
1968
1969 {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
1970 {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
1971
1972 {"DAC L1 Source", "DAC1", "DAC1 MIXL"},
1973 {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
1974 {"DAC R1 Source", "DAC1", "DAC1 MIXR"},
1975 {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
1976
1977 {"DAC L1", NULL, "DAC L1 Source"},
1978 {"DAC R1", NULL, "DAC R1 Source"},
1979
1980 {"DAC L1", NULL, "DAC 1 Clock"},
1981 {"DAC R1", NULL, "DAC 1 Clock"},
1982
1983 {"HP Amp", NULL, "DAC L1"},
1984 {"HP Amp", NULL, "DAC R1"},
1985 {"HP Amp", NULL, "HP Amp L"},
1986 {"HP Amp", NULL, "HP Amp R"},
1987 {"HP Amp", NULL, "Capless"},
1988 {"HP Amp", NULL, "Charge Pump"},
1989 {"HP Amp", NULL, "CLKDET SYS"},
1990 {"HP Amp", NULL, "Vref1"},
1991 {"HPOL Playback", "Switch", "HP Amp"},
1992 {"HPOR Playback", "Switch", "HP Amp"},
1993 {"HPOL", NULL, "HPOL Playback"},
1994 {"HPOR", NULL, "HPOR Playback"},
1995 };
1996
rt5682_set_tdm_slot(struct snd_soc_dai * dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)1997 static int rt5682_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
1998 unsigned int rx_mask, int slots, int slot_width)
1999 {
2000 struct snd_soc_component *component = dai->component;
2001 unsigned int cl, val = 0;
2002
2003 if (tx_mask || rx_mask)
2004 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2,
2005 RT5682_TDM_EN, RT5682_TDM_EN);
2006 else
2007 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2,
2008 RT5682_TDM_EN, 0);
2009
2010 switch (slots) {
2011 case 4:
2012 val |= RT5682_TDM_TX_CH_4;
2013 val |= RT5682_TDM_RX_CH_4;
2014 break;
2015 case 6:
2016 val |= RT5682_TDM_TX_CH_6;
2017 val |= RT5682_TDM_RX_CH_6;
2018 break;
2019 case 8:
2020 val |= RT5682_TDM_TX_CH_8;
2021 val |= RT5682_TDM_RX_CH_8;
2022 break;
2023 case 2:
2024 break;
2025 default:
2026 return -EINVAL;
2027 }
2028
2029 snd_soc_component_update_bits(component, RT5682_TDM_CTRL,
2030 RT5682_TDM_TX_CH_MASK | RT5682_TDM_RX_CH_MASK, val);
2031
2032 switch (slot_width) {
2033 case 8:
2034 if (tx_mask || rx_mask)
2035 return -EINVAL;
2036 cl = RT5682_I2S1_TX_CHL_8 | RT5682_I2S1_RX_CHL_8;
2037 break;
2038 case 16:
2039 val = RT5682_TDM_CL_16;
2040 cl = RT5682_I2S1_TX_CHL_16 | RT5682_I2S1_RX_CHL_16;
2041 break;
2042 case 20:
2043 val = RT5682_TDM_CL_20;
2044 cl = RT5682_I2S1_TX_CHL_20 | RT5682_I2S1_RX_CHL_20;
2045 break;
2046 case 24:
2047 val = RT5682_TDM_CL_24;
2048 cl = RT5682_I2S1_TX_CHL_24 | RT5682_I2S1_RX_CHL_24;
2049 break;
2050 case 32:
2051 val = RT5682_TDM_CL_32;
2052 cl = RT5682_I2S1_TX_CHL_32 | RT5682_I2S1_RX_CHL_32;
2053 break;
2054 default:
2055 return -EINVAL;
2056 }
2057
2058 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2059 RT5682_TDM_CL_MASK, val);
2060 snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2061 RT5682_I2S1_TX_CHL_MASK | RT5682_I2S1_RX_CHL_MASK, cl);
2062
2063 return 0;
2064 }
2065
rt5682_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)2066 static int rt5682_hw_params(struct snd_pcm_substream *substream,
2067 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2068 {
2069 struct snd_soc_component *component = dai->component;
2070 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2071 unsigned int len_1 = 0, len_2 = 0;
2072 int pre_div, frame_size;
2073
2074 rt5682->lrck[dai->id] = params_rate(params);
2075 pre_div = rl6231_get_clk_info(rt5682->sysclk, rt5682->lrck[dai->id]);
2076
2077 frame_size = snd_soc_params_to_frame_size(params);
2078 if (frame_size < 0) {
2079 dev_err(component->dev, "Unsupported frame size: %d\n",
2080 frame_size);
2081 return -EINVAL;
2082 }
2083
2084 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
2085 rt5682->lrck[dai->id], pre_div, dai->id);
2086
2087 switch (params_width(params)) {
2088 case 16:
2089 break;
2090 case 20:
2091 len_1 |= RT5682_I2S1_DL_20;
2092 len_2 |= RT5682_I2S2_DL_20;
2093 break;
2094 case 24:
2095 len_1 |= RT5682_I2S1_DL_24;
2096 len_2 |= RT5682_I2S2_DL_24;
2097 break;
2098 case 32:
2099 len_1 |= RT5682_I2S1_DL_32;
2100 len_2 |= RT5682_I2S2_DL_24;
2101 break;
2102 case 8:
2103 len_1 |= RT5682_I2S2_DL_8;
2104 len_2 |= RT5682_I2S2_DL_8;
2105 break;
2106 default:
2107 return -EINVAL;
2108 }
2109
2110 switch (dai->id) {
2111 case RT5682_AIF1:
2112 snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2113 RT5682_I2S1_DL_MASK, len_1);
2114 if (rt5682->master[RT5682_AIF1]) {
2115 snd_soc_component_update_bits(component,
2116 RT5682_ADDA_CLK_1, RT5682_I2S_M_DIV_MASK |
2117 RT5682_I2S_CLK_SRC_MASK,
2118 pre_div << RT5682_I2S_M_DIV_SFT |
2119 (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT);
2120 }
2121 if (params_channels(params) == 1) /* mono mode */
2122 snd_soc_component_update_bits(component,
2123 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK,
2124 RT5682_I2S1_MONO_EN);
2125 else
2126 snd_soc_component_update_bits(component,
2127 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK,
2128 RT5682_I2S1_MONO_DIS);
2129 break;
2130 case RT5682_AIF2:
2131 snd_soc_component_update_bits(component, RT5682_I2S2_SDP,
2132 RT5682_I2S2_DL_MASK, len_2);
2133 if (rt5682->master[RT5682_AIF2]) {
2134 snd_soc_component_update_bits(component,
2135 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_M_PD_MASK,
2136 pre_div << RT5682_I2S2_M_PD_SFT);
2137 }
2138 if (params_channels(params) == 1) /* mono mode */
2139 snd_soc_component_update_bits(component,
2140 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK,
2141 RT5682_I2S2_MONO_EN);
2142 else
2143 snd_soc_component_update_bits(component,
2144 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK,
2145 RT5682_I2S2_MONO_DIS);
2146 break;
2147 default:
2148 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2149 return -EINVAL;
2150 }
2151
2152 return 0;
2153 }
2154
rt5682_set_dai_fmt(struct snd_soc_dai * dai,unsigned int fmt)2155 static int rt5682_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2156 {
2157 struct snd_soc_component *component = dai->component;
2158 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2159 unsigned int reg_val = 0, tdm_ctrl = 0;
2160
2161 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2162 case SND_SOC_DAIFMT_CBM_CFM:
2163 rt5682->master[dai->id] = 1;
2164 break;
2165 case SND_SOC_DAIFMT_CBS_CFS:
2166 rt5682->master[dai->id] = 0;
2167 break;
2168 default:
2169 return -EINVAL;
2170 }
2171
2172 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2173 case SND_SOC_DAIFMT_NB_NF:
2174 break;
2175 case SND_SOC_DAIFMT_IB_NF:
2176 reg_val |= RT5682_I2S_BP_INV;
2177 tdm_ctrl |= RT5682_TDM_S_BP_INV;
2178 break;
2179 case SND_SOC_DAIFMT_NB_IF:
2180 if (dai->id == RT5682_AIF1)
2181 tdm_ctrl |= RT5682_TDM_S_LP_INV | RT5682_TDM_M_BP_INV;
2182 else
2183 return -EINVAL;
2184 break;
2185 case SND_SOC_DAIFMT_IB_IF:
2186 if (dai->id == RT5682_AIF1)
2187 tdm_ctrl |= RT5682_TDM_S_BP_INV | RT5682_TDM_S_LP_INV |
2188 RT5682_TDM_M_BP_INV | RT5682_TDM_M_LP_INV;
2189 else
2190 return -EINVAL;
2191 break;
2192 default:
2193 return -EINVAL;
2194 }
2195
2196 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2197 case SND_SOC_DAIFMT_I2S:
2198 break;
2199 case SND_SOC_DAIFMT_LEFT_J:
2200 reg_val |= RT5682_I2S_DF_LEFT;
2201 tdm_ctrl |= RT5682_TDM_DF_LEFT;
2202 break;
2203 case SND_SOC_DAIFMT_DSP_A:
2204 reg_val |= RT5682_I2S_DF_PCM_A;
2205 tdm_ctrl |= RT5682_TDM_DF_PCM_A;
2206 break;
2207 case SND_SOC_DAIFMT_DSP_B:
2208 reg_val |= RT5682_I2S_DF_PCM_B;
2209 tdm_ctrl |= RT5682_TDM_DF_PCM_B;
2210 break;
2211 default:
2212 return -EINVAL;
2213 }
2214
2215 switch (dai->id) {
2216 case RT5682_AIF1:
2217 snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2218 RT5682_I2S_DF_MASK, reg_val);
2219 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2220 RT5682_TDM_MS_MASK | RT5682_TDM_S_BP_MASK |
2221 RT5682_TDM_DF_MASK | RT5682_TDM_M_BP_MASK |
2222 RT5682_TDM_M_LP_MASK | RT5682_TDM_S_LP_MASK,
2223 tdm_ctrl | rt5682->master[dai->id]);
2224 break;
2225 case RT5682_AIF2:
2226 if (rt5682->master[dai->id] == 0)
2227 reg_val |= RT5682_I2S2_MS_S;
2228 snd_soc_component_update_bits(component, RT5682_I2S2_SDP,
2229 RT5682_I2S2_MS_MASK | RT5682_I2S_BP_MASK |
2230 RT5682_I2S_DF_MASK, reg_val);
2231 break;
2232 default:
2233 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2234 return -EINVAL;
2235 }
2236 return 0;
2237 }
2238
rt5682_set_component_sysclk(struct snd_soc_component * component,int clk_id,int source,unsigned int freq,int dir)2239 static int rt5682_set_component_sysclk(struct snd_soc_component *component,
2240 int clk_id, int source, unsigned int freq, int dir)
2241 {
2242 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2243 unsigned int reg_val = 0, src = 0;
2244
2245 if (freq == rt5682->sysclk && clk_id == rt5682->sysclk_src)
2246 return 0;
2247
2248 switch (clk_id) {
2249 case RT5682_SCLK_S_MCLK:
2250 reg_val |= RT5682_SCLK_SRC_MCLK;
2251 src = RT5682_CLK_SRC_MCLK;
2252 break;
2253 case RT5682_SCLK_S_PLL1:
2254 reg_val |= RT5682_SCLK_SRC_PLL1;
2255 src = RT5682_CLK_SRC_PLL1;
2256 break;
2257 case RT5682_SCLK_S_PLL2:
2258 reg_val |= RT5682_SCLK_SRC_PLL2;
2259 src = RT5682_CLK_SRC_PLL2;
2260 break;
2261 case RT5682_SCLK_S_RCCLK:
2262 reg_val |= RT5682_SCLK_SRC_RCCLK;
2263 src = RT5682_CLK_SRC_RCCLK;
2264 break;
2265 default:
2266 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
2267 return -EINVAL;
2268 }
2269 snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2270 RT5682_SCLK_SRC_MASK, reg_val);
2271
2272 if (rt5682->master[RT5682_AIF2]) {
2273 snd_soc_component_update_bits(component,
2274 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_SRC_MASK,
2275 src << RT5682_I2S2_SRC_SFT);
2276 }
2277
2278 rt5682->sysclk = freq;
2279 rt5682->sysclk_src = clk_id;
2280
2281 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
2282 freq, clk_id);
2283
2284 return 0;
2285 }
2286
rt5682_set_component_pll(struct snd_soc_component * component,int pll_id,int source,unsigned int freq_in,unsigned int freq_out)2287 static int rt5682_set_component_pll(struct snd_soc_component *component,
2288 int pll_id, int source, unsigned int freq_in,
2289 unsigned int freq_out)
2290 {
2291 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2292 struct rl6231_pll_code pll_code, pll2f_code, pll2b_code;
2293 unsigned int pll2_fout1, pll2_ps_val;
2294 int ret;
2295
2296 if (source == rt5682->pll_src[pll_id] &&
2297 freq_in == rt5682->pll_in[pll_id] &&
2298 freq_out == rt5682->pll_out[pll_id])
2299 return 0;
2300
2301 if (!freq_in || !freq_out) {
2302 dev_dbg(component->dev, "PLL disabled\n");
2303
2304 rt5682->pll_in[pll_id] = 0;
2305 rt5682->pll_out[pll_id] = 0;
2306 snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2307 RT5682_SCLK_SRC_MASK, RT5682_SCLK_SRC_MCLK);
2308 return 0;
2309 }
2310
2311 if (pll_id == RT5682_PLL2) {
2312 switch (source) {
2313 case RT5682_PLL2_S_MCLK:
2314 snd_soc_component_update_bits(component,
2315 RT5682_GLB_CLK, RT5682_PLL2_SRC_MASK,
2316 RT5682_PLL2_SRC_MCLK);
2317 break;
2318 default:
2319 dev_err(component->dev, "Unknown PLL2 Source %d\n",
2320 source);
2321 return -EINVAL;
2322 }
2323
2324 /**
2325 * PLL2 concatenates 2 PLL units.
2326 * We suggest the Fout of the front PLL is 3.84MHz.
2327 */
2328 pll2_fout1 = 3840000;
2329 ret = rl6231_pll_calc(freq_in, pll2_fout1, &pll2f_code);
2330 if (ret < 0) {
2331 dev_err(component->dev, "Unsupport input clock %d\n",
2332 freq_in);
2333 return ret;
2334 }
2335 dev_dbg(component->dev, "PLL2F: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n",
2336 freq_in, pll2_fout1,
2337 pll2f_code.m_bp,
2338 (pll2f_code.m_bp ? 0 : pll2f_code.m_code),
2339 pll2f_code.n_code, pll2f_code.k_code);
2340
2341 ret = rl6231_pll_calc(pll2_fout1, freq_out, &pll2b_code);
2342 if (ret < 0) {
2343 dev_err(component->dev, "Unsupport input clock %d\n",
2344 pll2_fout1);
2345 return ret;
2346 }
2347 dev_dbg(component->dev, "PLL2B: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n",
2348 pll2_fout1, freq_out,
2349 pll2b_code.m_bp,
2350 (pll2b_code.m_bp ? 0 : pll2b_code.m_code),
2351 pll2b_code.n_code, pll2b_code.k_code);
2352
2353 snd_soc_component_write(component, RT5682_PLL2_CTRL_1,
2354 pll2f_code.k_code << RT5682_PLL2F_K_SFT |
2355 pll2b_code.k_code << RT5682_PLL2B_K_SFT |
2356 pll2b_code.m_code);
2357 snd_soc_component_write(component, RT5682_PLL2_CTRL_2,
2358 pll2f_code.m_code << RT5682_PLL2F_M_SFT |
2359 pll2b_code.n_code);
2360 snd_soc_component_write(component, RT5682_PLL2_CTRL_3,
2361 pll2f_code.n_code << RT5682_PLL2F_N_SFT);
2362
2363 if (freq_out == 22579200)
2364 pll2_ps_val = 1 << RT5682_PLL2B_SEL_PS_SFT;
2365 else
2366 pll2_ps_val = 1 << RT5682_PLL2B_PS_BYP_SFT;
2367 snd_soc_component_update_bits(component, RT5682_PLL2_CTRL_4,
2368 RT5682_PLL2B_SEL_PS_MASK | RT5682_PLL2B_PS_BYP_MASK |
2369 RT5682_PLL2B_M_BP_MASK | RT5682_PLL2F_M_BP_MASK | 0xf,
2370 pll2_ps_val |
2371 (pll2b_code.m_bp ? 1 : 0) << RT5682_PLL2B_M_BP_SFT |
2372 (pll2f_code.m_bp ? 1 : 0) << RT5682_PLL2F_M_BP_SFT |
2373 0xf);
2374 } else {
2375 switch (source) {
2376 case RT5682_PLL1_S_MCLK:
2377 snd_soc_component_update_bits(component,
2378 RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK,
2379 RT5682_PLL1_SRC_MCLK);
2380 break;
2381 case RT5682_PLL1_S_BCLK1:
2382 snd_soc_component_update_bits(component,
2383 RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK,
2384 RT5682_PLL1_SRC_BCLK1);
2385 break;
2386 default:
2387 dev_err(component->dev, "Unknown PLL1 Source %d\n",
2388 source);
2389 return -EINVAL;
2390 }
2391
2392 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
2393 if (ret < 0) {
2394 dev_err(component->dev, "Unsupport input clock %d\n",
2395 freq_in);
2396 return ret;
2397 }
2398
2399 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
2400 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
2401 pll_code.n_code, pll_code.k_code);
2402
2403 snd_soc_component_write(component, RT5682_PLL_CTRL_1,
2404 pll_code.n_code << RT5682_PLL_N_SFT | pll_code.k_code);
2405 snd_soc_component_write(component, RT5682_PLL_CTRL_2,
2406 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5682_PLL_M_SFT |
2407 pll_code.m_bp << RT5682_PLL_M_BP_SFT | RT5682_PLL_RST);
2408 }
2409
2410 rt5682->pll_in[pll_id] = freq_in;
2411 rt5682->pll_out[pll_id] = freq_out;
2412 rt5682->pll_src[pll_id] = source;
2413
2414 return 0;
2415 }
2416
rt5682_set_bclk1_ratio(struct snd_soc_dai * dai,unsigned int ratio)2417 static int rt5682_set_bclk1_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2418 {
2419 struct snd_soc_component *component = dai->component;
2420 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2421
2422 rt5682->bclk[dai->id] = ratio;
2423
2424 switch (ratio) {
2425 case 256:
2426 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2427 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_256);
2428 break;
2429 case 128:
2430 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2431 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_128);
2432 break;
2433 case 64:
2434 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2435 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_64);
2436 break;
2437 case 32:
2438 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2439 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_32);
2440 break;
2441 default:
2442 dev_err(dai->dev, "Invalid bclk1 ratio %d\n", ratio);
2443 return -EINVAL;
2444 }
2445
2446 return 0;
2447 }
2448
rt5682_set_bclk2_ratio(struct snd_soc_dai * dai,unsigned int ratio)2449 static int rt5682_set_bclk2_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2450 {
2451 struct snd_soc_component *component = dai->component;
2452 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2453
2454 rt5682->bclk[dai->id] = ratio;
2455
2456 switch (ratio) {
2457 case 64:
2458 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2,
2459 RT5682_I2S2_BCLK_MS2_MASK,
2460 RT5682_I2S2_BCLK_MS2_64);
2461 break;
2462 case 32:
2463 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2,
2464 RT5682_I2S2_BCLK_MS2_MASK,
2465 RT5682_I2S2_BCLK_MS2_32);
2466 break;
2467 default:
2468 dev_err(dai->dev, "Invalid bclk2 ratio %d\n", ratio);
2469 return -EINVAL;
2470 }
2471
2472 return 0;
2473 }
2474
rt5682_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)2475 static int rt5682_set_bias_level(struct snd_soc_component *component,
2476 enum snd_soc_bias_level level)
2477 {
2478 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2479
2480 switch (level) {
2481 case SND_SOC_BIAS_PREPARE:
2482 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2483 RT5682_PWR_BG, RT5682_PWR_BG);
2484 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2485 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO,
2486 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO);
2487 break;
2488
2489 case SND_SOC_BIAS_STANDBY:
2490 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2491 RT5682_DIG_GATE_CTRL, RT5682_DIG_GATE_CTRL);
2492 break;
2493 case SND_SOC_BIAS_OFF:
2494 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2495 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO, 0);
2496 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2497 RT5682_PWR_BG, 0);
2498 break;
2499 case SND_SOC_BIAS_ON:
2500 break;
2501 }
2502
2503 return 0;
2504 }
2505
2506 #ifdef CONFIG_COMMON_CLK
2507 #define CLK_PLL2_FIN 48000000
2508 #define CLK_48 48000
2509 #define CLK_44 44100
2510
rt5682_clk_check(struct rt5682_priv * rt5682)2511 static bool rt5682_clk_check(struct rt5682_priv *rt5682)
2512 {
2513 if (!rt5682->master[RT5682_AIF1]) {
2514 dev_dbg(rt5682->component->dev, "sysclk/dai not set correctly\n");
2515 return false;
2516 }
2517 return true;
2518 }
2519
rt5682_wclk_prepare(struct clk_hw * hw)2520 static int rt5682_wclk_prepare(struct clk_hw *hw)
2521 {
2522 struct rt5682_priv *rt5682 =
2523 container_of(hw, struct rt5682_priv,
2524 dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2525 struct snd_soc_component *component = rt5682->component;
2526 struct snd_soc_dapm_context *dapm =
2527 snd_soc_component_get_dapm(component);
2528
2529 if (!rt5682_clk_check(rt5682))
2530 return -EINVAL;
2531
2532 snd_soc_dapm_mutex_lock(dapm);
2533
2534 snd_soc_dapm_force_enable_pin_unlocked(dapm, "MICBIAS");
2535 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
2536 RT5682_PWR_MB, RT5682_PWR_MB);
2537
2538 snd_soc_dapm_force_enable_pin_unlocked(dapm, "Vref2");
2539 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
2540 RT5682_PWR_VREF2 | RT5682_PWR_FV2,
2541 RT5682_PWR_VREF2);
2542 usleep_range(55000, 60000);
2543 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
2544 RT5682_PWR_FV2, RT5682_PWR_FV2);
2545
2546 snd_soc_dapm_force_enable_pin_unlocked(dapm, "I2S1");
2547 snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2F");
2548 snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2B");
2549 snd_soc_dapm_sync_unlocked(dapm);
2550
2551 snd_soc_dapm_mutex_unlock(dapm);
2552
2553 return 0;
2554 }
2555
rt5682_wclk_unprepare(struct clk_hw * hw)2556 static void rt5682_wclk_unprepare(struct clk_hw *hw)
2557 {
2558 struct rt5682_priv *rt5682 =
2559 container_of(hw, struct rt5682_priv,
2560 dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2561 struct snd_soc_component *component = rt5682->component;
2562 struct snd_soc_dapm_context *dapm =
2563 snd_soc_component_get_dapm(component);
2564
2565 if (!rt5682_clk_check(rt5682))
2566 return;
2567
2568 snd_soc_dapm_mutex_lock(dapm);
2569
2570 snd_soc_dapm_disable_pin_unlocked(dapm, "MICBIAS");
2571 snd_soc_dapm_disable_pin_unlocked(dapm, "Vref2");
2572 if (!rt5682->jack_type)
2573 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
2574 RT5682_PWR_VREF2 | RT5682_PWR_FV2 |
2575 RT5682_PWR_MB, 0);
2576
2577 snd_soc_dapm_disable_pin_unlocked(dapm, "I2S1");
2578 snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2F");
2579 snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2B");
2580 snd_soc_dapm_sync_unlocked(dapm);
2581
2582 snd_soc_dapm_mutex_unlock(dapm);
2583 }
2584
rt5682_wclk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)2585 static unsigned long rt5682_wclk_recalc_rate(struct clk_hw *hw,
2586 unsigned long parent_rate)
2587 {
2588 struct rt5682_priv *rt5682 =
2589 container_of(hw, struct rt5682_priv,
2590 dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2591 struct snd_soc_component *component = rt5682->component;
2592 const char * const clk_name = clk_hw_get_name(hw);
2593
2594 if (!rt5682_clk_check(rt5682))
2595 return 0;
2596 /*
2597 * Only accept to set wclk rate to 44.1k or 48kHz.
2598 */
2599 if (rt5682->lrck[RT5682_AIF1] != CLK_48 &&
2600 rt5682->lrck[RT5682_AIF1] != CLK_44) {
2601 dev_warn(component->dev, "%s: clk %s only support %d or %d Hz output\n",
2602 __func__, clk_name, CLK_44, CLK_48);
2603 return 0;
2604 }
2605
2606 return rt5682->lrck[RT5682_AIF1];
2607 }
2608
rt5682_wclk_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)2609 static long rt5682_wclk_round_rate(struct clk_hw *hw, unsigned long rate,
2610 unsigned long *parent_rate)
2611 {
2612 struct rt5682_priv *rt5682 =
2613 container_of(hw, struct rt5682_priv,
2614 dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2615 struct snd_soc_component *component = rt5682->component;
2616 const char * const clk_name = clk_hw_get_name(hw);
2617
2618 if (!rt5682_clk_check(rt5682))
2619 return -EINVAL;
2620 /*
2621 * Only accept to set wclk rate to 44.1k or 48kHz.
2622 * It will force to 48kHz if not both.
2623 */
2624 if (rate != CLK_48 && rate != CLK_44) {
2625 dev_warn(component->dev, "%s: clk %s only support %d or %d Hz output\n",
2626 __func__, clk_name, CLK_44, CLK_48);
2627 rate = CLK_48;
2628 }
2629
2630 return rate;
2631 }
2632
rt5682_wclk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)2633 static int rt5682_wclk_set_rate(struct clk_hw *hw, unsigned long rate,
2634 unsigned long parent_rate)
2635 {
2636 struct rt5682_priv *rt5682 =
2637 container_of(hw, struct rt5682_priv,
2638 dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2639 struct snd_soc_component *component = rt5682->component;
2640 struct clk *parent_clk;
2641 const char * const clk_name = clk_hw_get_name(hw);
2642 int pre_div;
2643 unsigned int clk_pll2_out;
2644
2645 if (!rt5682_clk_check(rt5682))
2646 return -EINVAL;
2647
2648 /*
2649 * Whether the wclk's parent clk (mclk) exists or not, please ensure
2650 * it is fixed or set to 48MHz before setting wclk rate. It's a
2651 * temporary limitation. Only accept 48MHz clk as the clk provider.
2652 *
2653 * It will set the codec anyway by assuming mclk is 48MHz.
2654 */
2655 parent_clk = clk_get_parent(hw->clk);
2656 if (!parent_clk)
2657 dev_warn(component->dev,
2658 "Parent mclk of wclk not acquired in driver. Please ensure mclk was provided as %d Hz.\n",
2659 CLK_PLL2_FIN);
2660
2661 if (parent_rate != CLK_PLL2_FIN)
2662 dev_warn(component->dev, "clk %s only support %d Hz input\n",
2663 clk_name, CLK_PLL2_FIN);
2664
2665 /*
2666 * To achieve the rate conversion from 48MHz to 44.1k or 48kHz,
2667 * PLL2 is needed.
2668 */
2669 clk_pll2_out = rate * 512;
2670 rt5682_set_component_pll(component, RT5682_PLL2, RT5682_PLL2_S_MCLK,
2671 CLK_PLL2_FIN, clk_pll2_out);
2672
2673 rt5682_set_component_sysclk(component, RT5682_SCLK_S_PLL2, 0,
2674 clk_pll2_out, SND_SOC_CLOCK_IN);
2675
2676 rt5682->lrck[RT5682_AIF1] = rate;
2677
2678 pre_div = rl6231_get_clk_info(rt5682->sysclk, rate);
2679
2680 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1,
2681 RT5682_I2S_M_DIV_MASK | RT5682_I2S_CLK_SRC_MASK,
2682 pre_div << RT5682_I2S_M_DIV_SFT |
2683 (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT);
2684
2685 return 0;
2686 }
2687
rt5682_bclk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)2688 static unsigned long rt5682_bclk_recalc_rate(struct clk_hw *hw,
2689 unsigned long parent_rate)
2690 {
2691 struct rt5682_priv *rt5682 =
2692 container_of(hw, struct rt5682_priv,
2693 dai_clks_hw[RT5682_DAI_BCLK_IDX]);
2694 struct snd_soc_component *component = rt5682->component;
2695 unsigned int bclks_per_wclk;
2696
2697 bclks_per_wclk = snd_soc_component_read(component, RT5682_TDM_TCON_CTRL);
2698
2699 switch (bclks_per_wclk & RT5682_TDM_BCLK_MS1_MASK) {
2700 case RT5682_TDM_BCLK_MS1_256:
2701 return parent_rate * 256;
2702 case RT5682_TDM_BCLK_MS1_128:
2703 return parent_rate * 128;
2704 case RT5682_TDM_BCLK_MS1_64:
2705 return parent_rate * 64;
2706 case RT5682_TDM_BCLK_MS1_32:
2707 return parent_rate * 32;
2708 default:
2709 return 0;
2710 }
2711 }
2712
rt5682_bclk_get_factor(unsigned long rate,unsigned long parent_rate)2713 static unsigned long rt5682_bclk_get_factor(unsigned long rate,
2714 unsigned long parent_rate)
2715 {
2716 unsigned long factor;
2717
2718 factor = rate / parent_rate;
2719 if (factor < 64)
2720 return 32;
2721 else if (factor < 128)
2722 return 64;
2723 else if (factor < 256)
2724 return 128;
2725 else
2726 return 256;
2727 }
2728
rt5682_bclk_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)2729 static long rt5682_bclk_round_rate(struct clk_hw *hw, unsigned long rate,
2730 unsigned long *parent_rate)
2731 {
2732 struct rt5682_priv *rt5682 =
2733 container_of(hw, struct rt5682_priv,
2734 dai_clks_hw[RT5682_DAI_BCLK_IDX]);
2735 unsigned long factor;
2736
2737 if (!*parent_rate || !rt5682_clk_check(rt5682))
2738 return -EINVAL;
2739
2740 /*
2741 * BCLK rates are set as a multiplier of WCLK in HW.
2742 * We don't allow changing the parent WCLK. We just do
2743 * some rounding down based on the parent WCLK rate
2744 * and find the appropriate multiplier of BCLK to
2745 * get the rounded down BCLK value.
2746 */
2747 factor = rt5682_bclk_get_factor(rate, *parent_rate);
2748
2749 return *parent_rate * factor;
2750 }
2751
rt5682_bclk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)2752 static int rt5682_bclk_set_rate(struct clk_hw *hw, unsigned long rate,
2753 unsigned long parent_rate)
2754 {
2755 struct rt5682_priv *rt5682 =
2756 container_of(hw, struct rt5682_priv,
2757 dai_clks_hw[RT5682_DAI_BCLK_IDX]);
2758 struct snd_soc_component *component = rt5682->component;
2759 struct snd_soc_dai *dai = NULL;
2760 unsigned long factor;
2761
2762 if (!rt5682_clk_check(rt5682))
2763 return -EINVAL;
2764
2765 factor = rt5682_bclk_get_factor(rate, parent_rate);
2766
2767 for_each_component_dais(component, dai)
2768 if (dai->id == RT5682_AIF1)
2769 break;
2770 if (!dai) {
2771 dev_err(component->dev, "dai %d not found in component\n",
2772 RT5682_AIF1);
2773 return -ENODEV;
2774 }
2775
2776 return rt5682_set_bclk1_ratio(dai, factor);
2777 }
2778
2779 static const struct clk_ops rt5682_dai_clk_ops[RT5682_DAI_NUM_CLKS] = {
2780 [RT5682_DAI_WCLK_IDX] = {
2781 .prepare = rt5682_wclk_prepare,
2782 .unprepare = rt5682_wclk_unprepare,
2783 .recalc_rate = rt5682_wclk_recalc_rate,
2784 .round_rate = rt5682_wclk_round_rate,
2785 .set_rate = rt5682_wclk_set_rate,
2786 },
2787 [RT5682_DAI_BCLK_IDX] = {
2788 .recalc_rate = rt5682_bclk_recalc_rate,
2789 .round_rate = rt5682_bclk_round_rate,
2790 .set_rate = rt5682_bclk_set_rate,
2791 },
2792 };
2793
rt5682_register_dai_clks(struct snd_soc_component * component)2794 static int rt5682_register_dai_clks(struct snd_soc_component *component)
2795 {
2796 struct device *dev = component->dev;
2797 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2798 struct rt5682_platform_data *pdata = &rt5682->pdata;
2799 struct clk_hw *dai_clk_hw;
2800 int i, ret;
2801
2802 for (i = 0; i < RT5682_DAI_NUM_CLKS; ++i) {
2803 struct clk_init_data init = { };
2804 struct clk_parent_data parent_data;
2805 const struct clk_hw *parent;
2806
2807 dai_clk_hw = &rt5682->dai_clks_hw[i];
2808
2809 switch (i) {
2810 case RT5682_DAI_WCLK_IDX:
2811 /* Make MCLK the parent of WCLK */
2812 if (rt5682->mclk) {
2813 parent_data = (struct clk_parent_data){
2814 .fw_name = "mclk",
2815 };
2816 init.parent_data = &parent_data;
2817 init.num_parents = 1;
2818 }
2819 break;
2820 case RT5682_DAI_BCLK_IDX:
2821 /* Make WCLK the parent of BCLK */
2822 parent = &rt5682->dai_clks_hw[RT5682_DAI_WCLK_IDX];
2823 init.parent_hws = &parent;
2824 init.num_parents = 1;
2825 break;
2826 default:
2827 dev_err(dev, "Invalid clock index\n");
2828 return -EINVAL;
2829 }
2830
2831 init.name = pdata->dai_clk_names[i];
2832 init.ops = &rt5682_dai_clk_ops[i];
2833 init.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_GATE;
2834 dai_clk_hw->init = &init;
2835
2836 ret = devm_clk_hw_register(dev, dai_clk_hw);
2837 if (ret) {
2838 dev_warn(dev, "Failed to register %s: %d\n",
2839 init.name, ret);
2840 return ret;
2841 }
2842
2843 if (dev->of_node) {
2844 devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
2845 dai_clk_hw);
2846 } else {
2847 ret = devm_clk_hw_register_clkdev(dev, dai_clk_hw,
2848 init.name,
2849 dev_name(dev));
2850 if (ret)
2851 return ret;
2852 }
2853 }
2854
2855 return 0;
2856 }
2857 #endif /* CONFIG_COMMON_CLK */
2858
rt5682_probe(struct snd_soc_component * component)2859 static int rt5682_probe(struct snd_soc_component *component)
2860 {
2861 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2862 struct sdw_slave *slave;
2863 unsigned long time;
2864 struct snd_soc_dapm_context *dapm = &component->dapm;
2865
2866 #ifdef CONFIG_COMMON_CLK
2867 int ret;
2868 #endif
2869 rt5682->component = component;
2870
2871 if (rt5682->is_sdw) {
2872 slave = rt5682->slave;
2873 time = wait_for_completion_timeout(
2874 &slave->initialization_complete,
2875 msecs_to_jiffies(RT5682_PROBE_TIMEOUT));
2876 if (!time) {
2877 dev_err(&slave->dev, "Initialization not complete, timed out\n");
2878 return -ETIMEDOUT;
2879 }
2880 } else {
2881 #ifdef CONFIG_COMMON_CLK
2882 /* Check if MCLK provided */
2883 rt5682->mclk = devm_clk_get(component->dev, "mclk");
2884 if (IS_ERR(rt5682->mclk)) {
2885 if (PTR_ERR(rt5682->mclk) != -ENOENT) {
2886 ret = PTR_ERR(rt5682->mclk);
2887 return ret;
2888 }
2889 rt5682->mclk = NULL;
2890 }
2891
2892 /* Register CCF DAI clock control */
2893 ret = rt5682_register_dai_clks(component);
2894 if (ret)
2895 return ret;
2896
2897 /* Initial setup for CCF */
2898 rt5682->lrck[RT5682_AIF1] = CLK_48;
2899 #endif
2900 }
2901
2902 snd_soc_dapm_disable_pin(dapm, "MICBIAS");
2903 snd_soc_dapm_disable_pin(dapm, "Vref2");
2904 snd_soc_dapm_sync(dapm);
2905 return 0;
2906 }
2907
rt5682_remove(struct snd_soc_component * component)2908 static void rt5682_remove(struct snd_soc_component *component)
2909 {
2910 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2911
2912 rt5682_reset(rt5682);
2913 }
2914
2915 #ifdef CONFIG_PM
rt5682_suspend(struct snd_soc_component * component)2916 static int rt5682_suspend(struct snd_soc_component *component)
2917 {
2918 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2919
2920 regcache_cache_only(rt5682->regmap, true);
2921 regcache_mark_dirty(rt5682->regmap);
2922 return 0;
2923 }
2924
rt5682_resume(struct snd_soc_component * component)2925 static int rt5682_resume(struct snd_soc_component *component)
2926 {
2927 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2928
2929 regcache_cache_only(rt5682->regmap, false);
2930 regcache_sync(rt5682->regmap);
2931
2932 mod_delayed_work(system_power_efficient_wq,
2933 &rt5682->jack_detect_work, msecs_to_jiffies(250));
2934
2935 return 0;
2936 }
2937 #else
2938 #define rt5682_suspend NULL
2939 #define rt5682_resume NULL
2940 #endif
2941
2942 const struct snd_soc_dai_ops rt5682_aif1_dai_ops = {
2943 .hw_params = rt5682_hw_params,
2944 .set_fmt = rt5682_set_dai_fmt,
2945 .set_tdm_slot = rt5682_set_tdm_slot,
2946 .set_bclk_ratio = rt5682_set_bclk1_ratio,
2947 };
2948 EXPORT_SYMBOL_GPL(rt5682_aif1_dai_ops);
2949
2950 const struct snd_soc_dai_ops rt5682_aif2_dai_ops = {
2951 .hw_params = rt5682_hw_params,
2952 .set_fmt = rt5682_set_dai_fmt,
2953 .set_bclk_ratio = rt5682_set_bclk2_ratio,
2954 };
2955 EXPORT_SYMBOL_GPL(rt5682_aif2_dai_ops);
2956
2957 const struct snd_soc_component_driver rt5682_soc_component_dev = {
2958 .probe = rt5682_probe,
2959 .remove = rt5682_remove,
2960 .suspend = rt5682_suspend,
2961 .resume = rt5682_resume,
2962 .set_bias_level = rt5682_set_bias_level,
2963 .controls = rt5682_snd_controls,
2964 .num_controls = ARRAY_SIZE(rt5682_snd_controls),
2965 .dapm_widgets = rt5682_dapm_widgets,
2966 .num_dapm_widgets = ARRAY_SIZE(rt5682_dapm_widgets),
2967 .dapm_routes = rt5682_dapm_routes,
2968 .num_dapm_routes = ARRAY_SIZE(rt5682_dapm_routes),
2969 .set_sysclk = rt5682_set_component_sysclk,
2970 .set_pll = rt5682_set_component_pll,
2971 .set_jack = rt5682_set_jack_detect,
2972 .use_pmdown_time = 1,
2973 .endianness = 1,
2974 .non_legacy_dai_naming = 1,
2975 };
2976 EXPORT_SYMBOL_GPL(rt5682_soc_component_dev);
2977
rt5682_parse_dt(struct rt5682_priv * rt5682,struct device * dev)2978 int rt5682_parse_dt(struct rt5682_priv *rt5682, struct device *dev)
2979 {
2980
2981 device_property_read_u32(dev, "realtek,dmic1-data-pin",
2982 &rt5682->pdata.dmic1_data_pin);
2983 device_property_read_u32(dev, "realtek,dmic1-clk-pin",
2984 &rt5682->pdata.dmic1_clk_pin);
2985 device_property_read_u32(dev, "realtek,jd-src",
2986 &rt5682->pdata.jd_src);
2987 device_property_read_u32(dev, "realtek,btndet-delay",
2988 &rt5682->pdata.btndet_delay);
2989 device_property_read_u32(dev, "realtek,dmic-clk-rate-hz",
2990 &rt5682->pdata.dmic_clk_rate);
2991 device_property_read_u32(dev, "realtek,dmic-delay-ms",
2992 &rt5682->pdata.dmic_delay);
2993
2994 rt5682->pdata.ldo1_en = of_get_named_gpio(dev->of_node,
2995 "realtek,ldo1-en-gpios", 0);
2996
2997 if (device_property_read_string_array(dev, "clock-output-names",
2998 rt5682->pdata.dai_clk_names,
2999 RT5682_DAI_NUM_CLKS) < 0)
3000 dev_warn(dev, "Using default DAI clk names: %s, %s\n",
3001 rt5682->pdata.dai_clk_names[RT5682_DAI_WCLK_IDX],
3002 rt5682->pdata.dai_clk_names[RT5682_DAI_BCLK_IDX]);
3003
3004 return 0;
3005 }
3006 EXPORT_SYMBOL_GPL(rt5682_parse_dt);
3007
rt5682_calibrate(struct rt5682_priv * rt5682)3008 void rt5682_calibrate(struct rt5682_priv *rt5682)
3009 {
3010 int value, count;
3011
3012 mutex_lock(&rt5682->calibrate_mutex);
3013
3014 rt5682_reset(rt5682);
3015 regmap_write(rt5682->regmap, RT5682_I2C_CTRL, 0x000f);
3016 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xa2af);
3017 usleep_range(15000, 20000);
3018 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xf2af);
3019 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0300);
3020 regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x8000);
3021 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0100);
3022 regmap_write(rt5682->regmap, RT5682_HP_IMP_SENS_CTRL_19, 0x3800);
3023 regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x3000);
3024 regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x7005);
3025 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0x686c);
3026 regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0d0d);
3027 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_2, 0x0321);
3028 regmap_write(rt5682->regmap, RT5682_HP_LOGIC_CTRL_2, 0x0004);
3029 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00);
3030 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_3, 0x06a1);
3031 regmap_write(rt5682->regmap, RT5682_A_DAC1_MUX, 0x0311);
3032 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00);
3033
3034 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0xfc00);
3035
3036 for (count = 0; count < 60; count++) {
3037 regmap_read(rt5682->regmap, RT5682_HP_CALIB_STA_1, &value);
3038 if (!(value & 0x8000))
3039 break;
3040
3041 usleep_range(10000, 10005);
3042 }
3043
3044 if (count >= 60)
3045 dev_err(rt5682->component->dev, "HP Calibration Failure\n");
3046
3047 /* restore settings */
3048 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0x002f);
3049 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0080);
3050 regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x0000);
3051 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0000);
3052 regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x2000);
3053 regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x2005);
3054 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0xc0c4);
3055 regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0c0c);
3056
3057 mutex_unlock(&rt5682->calibrate_mutex);
3058 }
3059 EXPORT_SYMBOL_GPL(rt5682_calibrate);
3060
3061 MODULE_DESCRIPTION("ASoC RT5682 driver");
3062 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
3063 MODULE_LICENSE("GPL v2");
3064