1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2019, Linaro Limited
3
4 #include <linux/clk.h>
5 #include <linux/clk-provider.h>
6 #include <linux/interrupt.h>
7 #include <linux/kernel.h>
8 #include <linux/mfd/wcd934x/registers.h>
9 #include <linux/mfd/wcd934x/wcd934x.h>
10 #include <linux/module.h>
11 #include <linux/mutex.h>
12 #include <linux/of_clk.h>
13 #include <linux/of.h>
14 #include <linux/platform_device.h>
15 #include <linux/regmap.h>
16 #include <linux/regulator/consumer.h>
17 #include <linux/slab.h>
18 #include <linux/slimbus.h>
19 #include <sound/pcm_params.h>
20 #include <sound/soc.h>
21 #include <sound/soc-dapm.h>
22 #include <sound/tlv.h>
23 #include "wcd-clsh-v2.h"
24
25 #define WCD934X_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
26 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
27 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
28 /* Fractional Rates */
29 #define WCD934X_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
30 SNDRV_PCM_RATE_176400)
31 #define WCD934X_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \
32 SNDRV_PCM_FMTBIT_S24_LE)
33
34 /* slave port water mark level
35 * (0: 6bytes, 1: 9bytes, 2: 12 bytes, 3: 15 bytes)
36 */
37 #define SLAVE_PORT_WATER_MARK_6BYTES 0
38 #define SLAVE_PORT_WATER_MARK_9BYTES 1
39 #define SLAVE_PORT_WATER_MARK_12BYTES 2
40 #define SLAVE_PORT_WATER_MARK_15BYTES 3
41 #define SLAVE_PORT_WATER_MARK_SHIFT 1
42 #define SLAVE_PORT_ENABLE 1
43 #define SLAVE_PORT_DISABLE 0
44 #define WCD934X_SLIM_WATER_MARK_VAL \
45 ((SLAVE_PORT_WATER_MARK_12BYTES << SLAVE_PORT_WATER_MARK_SHIFT) | \
46 (SLAVE_PORT_ENABLE))
47
48 #define WCD934X_SLIM_NUM_PORT_REG 3
49 #define WCD934X_SLIM_PGD_PORT_INT_TX_EN0 (WCD934X_SLIM_PGD_PORT_INT_EN0 + 2)
50 #define WCD934X_SLIM_IRQ_OVERFLOW BIT(0)
51 #define WCD934X_SLIM_IRQ_UNDERFLOW BIT(1)
52 #define WCD934X_SLIM_IRQ_PORT_CLOSED BIT(2)
53
54 #define WCD934X_MCLK_CLK_12P288MHZ 12288000
55 #define WCD934X_MCLK_CLK_9P6MHZ 9600000
56
57 /* Only valid for 9.6 MHz mclk */
58 #define WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ 2400000
59 #define WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ 4800000
60
61 /* Only valid for 12.288 MHz mclk */
62 #define WCD9XXX_DMIC_SAMPLE_RATE_4P096MHZ 4096000
63
64 #define WCD934X_DMIC_CLK_DIV_2 0x0
65 #define WCD934X_DMIC_CLK_DIV_3 0x1
66 #define WCD934X_DMIC_CLK_DIV_4 0x2
67 #define WCD934X_DMIC_CLK_DIV_6 0x3
68 #define WCD934X_DMIC_CLK_DIV_8 0x4
69 #define WCD934X_DMIC_CLK_DIV_16 0x5
70 #define WCD934X_DMIC_CLK_DRIVE_DEFAULT 0x02
71
72 #define TX_HPF_CUT_OFF_FREQ_MASK 0x60
73 #define CF_MIN_3DB_4HZ 0x0
74 #define CF_MIN_3DB_75HZ 0x1
75 #define CF_MIN_3DB_150HZ 0x2
76
77 #define WCD934X_RX_START 16
78 #define WCD934X_NUM_INTERPOLATORS 9
79 #define WCD934X_RX_PATH_CTL_OFFSET 20
80 #define WCD934X_MAX_VALID_ADC_MUX 13
81 #define WCD934X_INVALID_ADC_MUX 9
82
83 #define WCD934X_SLIM_RX_CH(p) \
84 {.port = p + WCD934X_RX_START, .shift = p,}
85
86 #define WCD934X_SLIM_TX_CH(p) \
87 {.port = p, .shift = p,}
88
89 /* Feature masks to distinguish codec version */
90 #define DSD_DISABLED_MASK 0
91 #define SLNQ_DISABLED_MASK 1
92
93 #define DSD_DISABLED BIT(DSD_DISABLED_MASK)
94 #define SLNQ_DISABLED BIT(SLNQ_DISABLED_MASK)
95
96 /* As fine version info cannot be retrieved before wcd probe.
97 * Define three coarse versions for possible future use before wcd probe.
98 */
99 #define WCD_VERSION_WCD9340_1_0 0x400
100 #define WCD_VERSION_WCD9341_1_0 0x410
101 #define WCD_VERSION_WCD9340_1_1 0x401
102 #define WCD_VERSION_WCD9341_1_1 0x411
103 #define WCD934X_AMIC_PWR_LEVEL_LP 0
104 #define WCD934X_AMIC_PWR_LEVEL_DEFAULT 1
105 #define WCD934X_AMIC_PWR_LEVEL_HP 2
106 #define WCD934X_AMIC_PWR_LEVEL_HYBRID 3
107 #define WCD934X_AMIC_PWR_LVL_MASK 0x60
108 #define WCD934X_AMIC_PWR_LVL_SHIFT 0x5
109
110 #define WCD934X_DEC_PWR_LVL_MASK 0x06
111 #define WCD934X_DEC_PWR_LVL_LP 0x02
112 #define WCD934X_DEC_PWR_LVL_HP 0x04
113 #define WCD934X_DEC_PWR_LVL_DF 0x00
114 #define WCD934X_DEC_PWR_LVL_HYBRID WCD934X_DEC_PWR_LVL_DF
115
116 #define WCD934X_DEF_MICBIAS_MV 1800
117 #define WCD934X_MAX_MICBIAS_MV 2850
118
119 #define WCD_IIR_FILTER_SIZE (sizeof(u32) * BAND_MAX)
120
121 #define WCD_IIR_FILTER_CTL(xname, iidx, bidx) \
122 { \
123 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
124 .info = wcd934x_iir_filter_info, \
125 .get = wcd934x_get_iir_band_audio_mixer, \
126 .put = wcd934x_put_iir_band_audio_mixer, \
127 .private_value = (unsigned long)&(struct wcd_iir_filter_ctl) { \
128 .iir_idx = iidx, \
129 .band_idx = bidx, \
130 .bytes_ext = {.max = WCD_IIR_FILTER_SIZE, }, \
131 } \
132 }
133
134 #define WCD934X_INTERPOLATOR_PATH(id) \
135 {"RX INT" #id "_1 MIX1 INP0", "RX0", "SLIM RX0"}, \
136 {"RX INT" #id "_1 MIX1 INP0", "RX1", "SLIM RX1"}, \
137 {"RX INT" #id "_1 MIX1 INP0", "RX2", "SLIM RX2"}, \
138 {"RX INT" #id "_1 MIX1 INP0", "RX3", "SLIM RX3"}, \
139 {"RX INT" #id "_1 MIX1 INP0", "RX4", "SLIM RX4"}, \
140 {"RX INT" #id "_1 MIX1 INP0", "RX5", "SLIM RX5"}, \
141 {"RX INT" #id "_1 MIX1 INP0", "RX6", "SLIM RX6"}, \
142 {"RX INT" #id "_1 MIX1 INP0", "RX7", "SLIM RX7"}, \
143 {"RX INT" #id "_1 MIX1 INP0", "IIR0", "IIR0"}, \
144 {"RX INT" #id "_1 MIX1 INP0", "IIR1", "IIR1"}, \
145 {"RX INT" #id "_1 MIX1 INP1", "RX0", "SLIM RX0"}, \
146 {"RX INT" #id "_1 MIX1 INP1", "RX1", "SLIM RX1"}, \
147 {"RX INT" #id "_1 MIX1 INP1", "RX2", "SLIM RX2"}, \
148 {"RX INT" #id "_1 MIX1 INP1", "RX3", "SLIM RX3"}, \
149 {"RX INT" #id "_1 MIX1 INP1", "RX4", "SLIM RX4"}, \
150 {"RX INT" #id "_1 MIX1 INP1", "RX5", "SLIM RX5"}, \
151 {"RX INT" #id "_1 MIX1 INP1", "RX6", "SLIM RX6"}, \
152 {"RX INT" #id "_1 MIX1 INP1", "RX7", "SLIM RX7"}, \
153 {"RX INT" #id "_1 MIX1 INP1", "IIR0", "IIR0"}, \
154 {"RX INT" #id "_1 MIX1 INP1", "IIR1", "IIR1"}, \
155 {"RX INT" #id "_1 MIX1 INP2", "RX0", "SLIM RX0"}, \
156 {"RX INT" #id "_1 MIX1 INP2", "RX1", "SLIM RX1"}, \
157 {"RX INT" #id "_1 MIX1 INP2", "RX2", "SLIM RX2"}, \
158 {"RX INT" #id "_1 MIX1 INP2", "RX3", "SLIM RX3"}, \
159 {"RX INT" #id "_1 MIX1 INP2", "RX4", "SLIM RX4"}, \
160 {"RX INT" #id "_1 MIX1 INP2", "RX5", "SLIM RX5"}, \
161 {"RX INT" #id "_1 MIX1 INP2", "RX6", "SLIM RX6"}, \
162 {"RX INT" #id "_1 MIX1 INP2", "RX7", "SLIM RX7"}, \
163 {"RX INT" #id "_1 MIX1 INP2", "IIR0", "IIR0"}, \
164 {"RX INT" #id "_1 MIX1 INP2", "IIR1", "IIR1"}, \
165 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP0"}, \
166 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP1"}, \
167 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP2"}, \
168 {"RX INT" #id "_2 MUX", "RX0", "SLIM RX0"}, \
169 {"RX INT" #id "_2 MUX", "RX1", "SLIM RX1"}, \
170 {"RX INT" #id "_2 MUX", "RX2", "SLIM RX2"}, \
171 {"RX INT" #id "_2 MUX", "RX3", "SLIM RX3"}, \
172 {"RX INT" #id "_2 MUX", "RX4", "SLIM RX4"}, \
173 {"RX INT" #id "_2 MUX", "RX5", "SLIM RX5"}, \
174 {"RX INT" #id "_2 MUX", "RX6", "SLIM RX6"}, \
175 {"RX INT" #id "_2 MUX", "RX7", "SLIM RX7"}, \
176 {"RX INT" #id "_2 MUX", NULL, "INT" #id "_CLK"}, \
177 {"RX INT" #id "_2 MUX", NULL, "DSMDEM" #id "_CLK"}, \
178 {"RX INT" #id "_2 INTERP", NULL, "RX INT" #id "_2 MUX"}, \
179 {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_2 INTERP"}, \
180 {"RX INT" #id "_1 INTERP", NULL, "RX INT" #id "_1 MIX1"}, \
181 {"RX INT" #id "_1 INTERP", NULL, "INT" #id "_CLK"}, \
182 {"RX INT" #id "_1 INTERP", NULL, "DSMDEM" #id "_CLK"}, \
183 {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_1 INTERP"}
184
185 #define WCD934X_INTERPOLATOR_MIX2(id) \
186 {"RX INT" #id " MIX2", NULL, "RX INT" #id " SEC MIX"}, \
187 {"RX INT" #id " MIX2", NULL, "RX INT" #id " MIX2 INP"}
188
189 #define WCD934X_SLIM_RX_AIF_PATH(id) \
190 {"SLIM RX"#id" MUX", "AIF1_PB", "AIF1 PB"}, \
191 {"SLIM RX"#id" MUX", "AIF2_PB", "AIF2 PB"}, \
192 {"SLIM RX"#id" MUX", "AIF3_PB", "AIF3 PB"}, \
193 {"SLIM RX"#id" MUX", "AIF4_PB", "AIF4 PB"}, \
194 {"SLIM RX"#id, NULL, "SLIM RX"#id" MUX"}
195
196 #define WCD934X_ADC_MUX(id) \
197 {"ADC MUX" #id, "DMIC", "DMIC MUX" #id }, \
198 {"ADC MUX" #id, "AMIC", "AMIC MUX" #id }, \
199 {"DMIC MUX" #id, "DMIC0", "DMIC0"}, \
200 {"DMIC MUX" #id, "DMIC1", "DMIC1"}, \
201 {"DMIC MUX" #id, "DMIC2", "DMIC2"}, \
202 {"DMIC MUX" #id, "DMIC3", "DMIC3"}, \
203 {"DMIC MUX" #id, "DMIC4", "DMIC4"}, \
204 {"DMIC MUX" #id, "DMIC5", "DMIC5"}, \
205 {"AMIC MUX" #id, "ADC1", "ADC1"}, \
206 {"AMIC MUX" #id, "ADC2", "ADC2"}, \
207 {"AMIC MUX" #id, "ADC3", "ADC3"}, \
208 {"AMIC MUX" #id, "ADC4", "ADC4"}
209
210 #define WCD934X_IIR_INP_MUX(id) \
211 {"IIR" #id, NULL, "IIR" #id " INP0 MUX"}, \
212 {"IIR" #id " INP0 MUX", "DEC0", "ADC MUX0"}, \
213 {"IIR" #id " INP0 MUX", "DEC1", "ADC MUX1"}, \
214 {"IIR" #id " INP0 MUX", "DEC2", "ADC MUX2"}, \
215 {"IIR" #id " INP0 MUX", "DEC3", "ADC MUX3"}, \
216 {"IIR" #id " INP0 MUX", "DEC4", "ADC MUX4"}, \
217 {"IIR" #id " INP0 MUX", "DEC5", "ADC MUX5"}, \
218 {"IIR" #id " INP0 MUX", "DEC6", "ADC MUX6"}, \
219 {"IIR" #id " INP0 MUX", "DEC7", "ADC MUX7"}, \
220 {"IIR" #id " INP0 MUX", "DEC8", "ADC MUX8"}, \
221 {"IIR" #id " INP0 MUX", "RX0", "SLIM RX0"}, \
222 {"IIR" #id " INP0 MUX", "RX1", "SLIM RX1"}, \
223 {"IIR" #id " INP0 MUX", "RX2", "SLIM RX2"}, \
224 {"IIR" #id " INP0 MUX", "RX3", "SLIM RX3"}, \
225 {"IIR" #id " INP0 MUX", "RX4", "SLIM RX4"}, \
226 {"IIR" #id " INP0 MUX", "RX5", "SLIM RX5"}, \
227 {"IIR" #id " INP0 MUX", "RX6", "SLIM RX6"}, \
228 {"IIR" #id " INP0 MUX", "RX7", "SLIM RX7"}, \
229 {"IIR" #id, NULL, "IIR" #id " INP1 MUX"}, \
230 {"IIR" #id " INP1 MUX", "DEC0", "ADC MUX0"}, \
231 {"IIR" #id " INP1 MUX", "DEC1", "ADC MUX1"}, \
232 {"IIR" #id " INP1 MUX", "DEC2", "ADC MUX2"}, \
233 {"IIR" #id " INP1 MUX", "DEC3", "ADC MUX3"}, \
234 {"IIR" #id " INP1 MUX", "DEC4", "ADC MUX4"}, \
235 {"IIR" #id " INP1 MUX", "DEC5", "ADC MUX5"}, \
236 {"IIR" #id " INP1 MUX", "DEC6", "ADC MUX6"}, \
237 {"IIR" #id " INP1 MUX", "DEC7", "ADC MUX7"}, \
238 {"IIR" #id " INP1 MUX", "DEC8", "ADC MUX8"}, \
239 {"IIR" #id " INP1 MUX", "RX0", "SLIM RX0"}, \
240 {"IIR" #id " INP1 MUX", "RX1", "SLIM RX1"}, \
241 {"IIR" #id " INP1 MUX", "RX2", "SLIM RX2"}, \
242 {"IIR" #id " INP1 MUX", "RX3", "SLIM RX3"}, \
243 {"IIR" #id " INP1 MUX", "RX4", "SLIM RX4"}, \
244 {"IIR" #id " INP1 MUX", "RX5", "SLIM RX5"}, \
245 {"IIR" #id " INP1 MUX", "RX6", "SLIM RX6"}, \
246 {"IIR" #id " INP1 MUX", "RX7", "SLIM RX7"}, \
247 {"IIR" #id, NULL, "IIR" #id " INP2 MUX"}, \
248 {"IIR" #id " INP2 MUX", "DEC0", "ADC MUX0"}, \
249 {"IIR" #id " INP2 MUX", "DEC1", "ADC MUX1"}, \
250 {"IIR" #id " INP2 MUX", "DEC2", "ADC MUX2"}, \
251 {"IIR" #id " INP2 MUX", "DEC3", "ADC MUX3"}, \
252 {"IIR" #id " INP2 MUX", "DEC4", "ADC MUX4"}, \
253 {"IIR" #id " INP2 MUX", "DEC5", "ADC MUX5"}, \
254 {"IIR" #id " INP2 MUX", "DEC6", "ADC MUX6"}, \
255 {"IIR" #id " INP2 MUX", "DEC7", "ADC MUX7"}, \
256 {"IIR" #id " INP2 MUX", "DEC8", "ADC MUX8"}, \
257 {"IIR" #id " INP2 MUX", "RX0", "SLIM RX0"}, \
258 {"IIR" #id " INP2 MUX", "RX1", "SLIM RX1"}, \
259 {"IIR" #id " INP2 MUX", "RX2", "SLIM RX2"}, \
260 {"IIR" #id " INP2 MUX", "RX3", "SLIM RX3"}, \
261 {"IIR" #id " INP2 MUX", "RX4", "SLIM RX4"}, \
262 {"IIR" #id " INP2 MUX", "RX5", "SLIM RX5"}, \
263 {"IIR" #id " INP2 MUX", "RX6", "SLIM RX6"}, \
264 {"IIR" #id " INP2 MUX", "RX7", "SLIM RX7"}, \
265 {"IIR" #id, NULL, "IIR" #id " INP3 MUX"}, \
266 {"IIR" #id " INP3 MUX", "DEC0", "ADC MUX0"}, \
267 {"IIR" #id " INP3 MUX", "DEC1", "ADC MUX1"}, \
268 {"IIR" #id " INP3 MUX", "DEC2", "ADC MUX2"}, \
269 {"IIR" #id " INP3 MUX", "DEC3", "ADC MUX3"}, \
270 {"IIR" #id " INP3 MUX", "DEC4", "ADC MUX4"}, \
271 {"IIR" #id " INP3 MUX", "DEC5", "ADC MUX5"}, \
272 {"IIR" #id " INP3 MUX", "DEC6", "ADC MUX6"}, \
273 {"IIR" #id " INP3 MUX", "DEC7", "ADC MUX7"}, \
274 {"IIR" #id " INP3 MUX", "DEC8", "ADC MUX8"}, \
275 {"IIR" #id " INP3 MUX", "RX0", "SLIM RX0"}, \
276 {"IIR" #id " INP3 MUX", "RX1", "SLIM RX1"}, \
277 {"IIR" #id " INP3 MUX", "RX2", "SLIM RX2"}, \
278 {"IIR" #id " INP3 MUX", "RX3", "SLIM RX3"}, \
279 {"IIR" #id " INP3 MUX", "RX4", "SLIM RX4"}, \
280 {"IIR" #id " INP3 MUX", "RX5", "SLIM RX5"}, \
281 {"IIR" #id " INP3 MUX", "RX6", "SLIM RX6"}, \
282 {"IIR" #id " INP3 MUX", "RX7", "SLIM RX7"}
283
284 #define WCD934X_SLIM_TX_AIF_PATH(id) \
285 {"AIF1_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id }, \
286 {"AIF2_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id }, \
287 {"AIF3_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id }, \
288 {"SLIM TX" #id, NULL, "CDC_IF TX" #id " MUX"}
289
290 enum {
291 MIC_BIAS_1 = 1,
292 MIC_BIAS_2,
293 MIC_BIAS_3,
294 MIC_BIAS_4
295 };
296
297 enum {
298 SIDO_SOURCE_INTERNAL,
299 SIDO_SOURCE_RCO_BG,
300 };
301
302 enum {
303 INTERP_EAR = 0,
304 INTERP_HPHL,
305 INTERP_HPHR,
306 INTERP_LO1,
307 INTERP_LO2,
308 INTERP_LO3_NA, /* LO3 not avalible in Tavil */
309 INTERP_LO4_NA,
310 INTERP_SPKR1, /*INT7 WSA Speakers via soundwire */
311 INTERP_SPKR2, /*INT8 WSA Speakers via soundwire */
312 INTERP_MAX,
313 };
314
315 enum {
316 WCD934X_RX0 = 0,
317 WCD934X_RX1,
318 WCD934X_RX2,
319 WCD934X_RX3,
320 WCD934X_RX4,
321 WCD934X_RX5,
322 WCD934X_RX6,
323 WCD934X_RX7,
324 WCD934X_RX8,
325 WCD934X_RX9,
326 WCD934X_RX10,
327 WCD934X_RX11,
328 WCD934X_RX12,
329 WCD934X_RX_MAX,
330 };
331
332 enum {
333 WCD934X_TX0 = 0,
334 WCD934X_TX1,
335 WCD934X_TX2,
336 WCD934X_TX3,
337 WCD934X_TX4,
338 WCD934X_TX5,
339 WCD934X_TX6,
340 WCD934X_TX7,
341 WCD934X_TX8,
342 WCD934X_TX9,
343 WCD934X_TX10,
344 WCD934X_TX11,
345 WCD934X_TX12,
346 WCD934X_TX13,
347 WCD934X_TX14,
348 WCD934X_TX15,
349 WCD934X_TX_MAX,
350 };
351
352 struct wcd934x_slim_ch {
353 u32 ch_num;
354 u16 port;
355 u16 shift;
356 struct list_head list;
357 };
358
359 static const struct wcd934x_slim_ch wcd934x_tx_chs[WCD934X_TX_MAX] = {
360 WCD934X_SLIM_TX_CH(0),
361 WCD934X_SLIM_TX_CH(1),
362 WCD934X_SLIM_TX_CH(2),
363 WCD934X_SLIM_TX_CH(3),
364 WCD934X_SLIM_TX_CH(4),
365 WCD934X_SLIM_TX_CH(5),
366 WCD934X_SLIM_TX_CH(6),
367 WCD934X_SLIM_TX_CH(7),
368 WCD934X_SLIM_TX_CH(8),
369 WCD934X_SLIM_TX_CH(9),
370 WCD934X_SLIM_TX_CH(10),
371 WCD934X_SLIM_TX_CH(11),
372 WCD934X_SLIM_TX_CH(12),
373 WCD934X_SLIM_TX_CH(13),
374 WCD934X_SLIM_TX_CH(14),
375 WCD934X_SLIM_TX_CH(15),
376 };
377
378 static const struct wcd934x_slim_ch wcd934x_rx_chs[WCD934X_RX_MAX] = {
379 WCD934X_SLIM_RX_CH(0), /* 16 */
380 WCD934X_SLIM_RX_CH(1), /* 17 */
381 WCD934X_SLIM_RX_CH(2),
382 WCD934X_SLIM_RX_CH(3),
383 WCD934X_SLIM_RX_CH(4),
384 WCD934X_SLIM_RX_CH(5),
385 WCD934X_SLIM_RX_CH(6),
386 WCD934X_SLIM_RX_CH(7),
387 WCD934X_SLIM_RX_CH(8),
388 WCD934X_SLIM_RX_CH(9),
389 WCD934X_SLIM_RX_CH(10),
390 WCD934X_SLIM_RX_CH(11),
391 WCD934X_SLIM_RX_CH(12),
392 };
393
394 /* Codec supports 2 IIR filters */
395 enum {
396 IIR0 = 0,
397 IIR1,
398 IIR_MAX,
399 };
400
401 /* Each IIR has 5 Filter Stages */
402 enum {
403 BAND1 = 0,
404 BAND2,
405 BAND3,
406 BAND4,
407 BAND5,
408 BAND_MAX,
409 };
410
411 enum {
412 COMPANDER_1, /* HPH_L */
413 COMPANDER_2, /* HPH_R */
414 COMPANDER_3, /* LO1_DIFF */
415 COMPANDER_4, /* LO2_DIFF */
416 COMPANDER_5, /* LO3_SE - not used in Tavil */
417 COMPANDER_6, /* LO4_SE - not used in Tavil */
418 COMPANDER_7, /* SWR SPK CH1 */
419 COMPANDER_8, /* SWR SPK CH2 */
420 COMPANDER_MAX,
421 };
422
423 enum {
424 AIF1_PB = 0,
425 AIF1_CAP,
426 AIF2_PB,
427 AIF2_CAP,
428 AIF3_PB,
429 AIF3_CAP,
430 AIF4_PB,
431 AIF4_VIFEED,
432 AIF4_MAD_TX,
433 NUM_CODEC_DAIS,
434 };
435
436 enum {
437 INTn_1_INP_SEL_ZERO = 0,
438 INTn_1_INP_SEL_DEC0,
439 INTn_1_INP_SEL_DEC1,
440 INTn_1_INP_SEL_IIR0,
441 INTn_1_INP_SEL_IIR1,
442 INTn_1_INP_SEL_RX0,
443 INTn_1_INP_SEL_RX1,
444 INTn_1_INP_SEL_RX2,
445 INTn_1_INP_SEL_RX3,
446 INTn_1_INP_SEL_RX4,
447 INTn_1_INP_SEL_RX5,
448 INTn_1_INP_SEL_RX6,
449 INTn_1_INP_SEL_RX7,
450 };
451
452 enum {
453 INTn_2_INP_SEL_ZERO = 0,
454 INTn_2_INP_SEL_RX0,
455 INTn_2_INP_SEL_RX1,
456 INTn_2_INP_SEL_RX2,
457 INTn_2_INP_SEL_RX3,
458 INTn_2_INP_SEL_RX4,
459 INTn_2_INP_SEL_RX5,
460 INTn_2_INP_SEL_RX6,
461 INTn_2_INP_SEL_RX7,
462 INTn_2_INP_SEL_PROXIMITY,
463 };
464
465 enum {
466 INTERP_MAIN_PATH,
467 INTERP_MIX_PATH,
468 };
469
470 struct interp_sample_rate {
471 int sample_rate;
472 int rate_val;
473 };
474
475 static struct interp_sample_rate sr_val_tbl[] = {
476 {8000, 0x0},
477 {16000, 0x1},
478 {32000, 0x3},
479 {48000, 0x4},
480 {96000, 0x5},
481 {192000, 0x6},
482 {384000, 0x7},
483 {44100, 0x9},
484 {88200, 0xA},
485 {176400, 0xB},
486 {352800, 0xC},
487 };
488
489 struct wcd_slim_codec_dai_data {
490 struct list_head slim_ch_list;
491 struct slim_stream_config sconfig;
492 struct slim_stream_runtime *sruntime;
493 };
494
495 static const struct regmap_range_cfg wcd934x_ifc_ranges[] = {
496 {
497 .name = "WCD9335-IFC-DEV",
498 .range_min = 0x0,
499 .range_max = 0xffff,
500 .selector_reg = 0x800,
501 .selector_mask = 0xfff,
502 .selector_shift = 0,
503 .window_start = 0x800,
504 .window_len = 0x400,
505 },
506 };
507
508 static struct regmap_config wcd934x_ifc_regmap_config = {
509 .reg_bits = 16,
510 .val_bits = 8,
511 .max_register = 0xffff,
512 .ranges = wcd934x_ifc_ranges,
513 .num_ranges = ARRAY_SIZE(wcd934x_ifc_ranges),
514 };
515
516 struct wcd934x_codec {
517 struct device *dev;
518 struct clk_hw hw;
519 struct clk *extclk;
520 struct regmap *regmap;
521 struct regmap *if_regmap;
522 struct slim_device *sdev;
523 struct slim_device *sidev;
524 struct wcd_clsh_ctrl *clsh_ctrl;
525 struct snd_soc_component *component;
526 struct wcd934x_slim_ch rx_chs[WCD934X_RX_MAX];
527 struct wcd934x_slim_ch tx_chs[WCD934X_TX_MAX];
528 struct wcd_slim_codec_dai_data dai[NUM_CODEC_DAIS];
529 int rate;
530 u32 version;
531 u32 hph_mode;
532 int num_rx_port;
533 int num_tx_port;
534 u32 tx_port_value[WCD934X_TX_MAX];
535 u32 rx_port_value[WCD934X_RX_MAX];
536 int sido_input_src;
537 int dmic_0_1_clk_cnt;
538 int dmic_2_3_clk_cnt;
539 int dmic_4_5_clk_cnt;
540 int dmic_sample_rate;
541 int comp_enabled[COMPANDER_MAX];
542 int sysclk_users;
543 struct mutex sysclk_mutex;
544 };
545
546 #define to_wcd934x_codec(_hw) container_of(_hw, struct wcd934x_codec, hw)
547
548 struct wcd_iir_filter_ctl {
549 unsigned int iir_idx;
550 unsigned int band_idx;
551 struct soc_bytes_ext bytes_ext;
552 };
553
554 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
555 static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
556 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
557 static const DECLARE_TLV_DB_SCALE(ear_pa_gain, 0, 150, 0);
558
559 /* Cutoff frequency for high pass filter */
560 static const char * const cf_text[] = {
561 "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ"
562 };
563
564 static const char * const rx_cf_text[] = {
565 "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ",
566 "CF_NEG_3DB_0P48HZ"
567 };
568
569 static const char * const rx_hph_mode_mux_text[] = {
570 "Class H Invalid", "Class-H Hi-Fi", "Class-H Low Power", "Class-AB",
571 "Class-H Hi-Fi Low Power"
572 };
573
574 static const char *const slim_rx_mux_text[] = {
575 "ZERO", "AIF1_PB", "AIF2_PB", "AIF3_PB", "AIF4_PB",
576 };
577
578 static const char * const rx_int0_7_mix_mux_text[] = {
579 "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5",
580 "RX6", "RX7", "PROXIMITY"
581 };
582
583 static const char * const rx_int_mix_mux_text[] = {
584 "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5",
585 "RX6", "RX7"
586 };
587
588 static const char * const rx_prim_mix_text[] = {
589 "ZERO", "DEC0", "DEC1", "IIR0", "IIR1", "RX0", "RX1", "RX2",
590 "RX3", "RX4", "RX5", "RX6", "RX7"
591 };
592
593 static const char * const rx_sidetone_mix_text[] = {
594 "ZERO", "SRC0", "SRC1", "SRC_SUM"
595 };
596
597 static const char * const iir_inp_mux_text[] = {
598 "ZERO", "DEC0", "DEC1", "DEC2", "DEC3", "DEC4", "DEC5", "DEC6",
599 "DEC7", "DEC8", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5", "RX6", "RX7"
600 };
601
602 static const char * const rx_int_dem_inp_mux_text[] = {
603 "NORMAL_DSM_OUT", "CLSH_DSM_OUT",
604 };
605
606 static const char * const rx_int0_1_interp_mux_text[] = {
607 "ZERO", "RX INT0_1 MIX1",
608 };
609
610 static const char * const rx_int1_1_interp_mux_text[] = {
611 "ZERO", "RX INT1_1 MIX1",
612 };
613
614 static const char * const rx_int2_1_interp_mux_text[] = {
615 "ZERO", "RX INT2_1 MIX1",
616 };
617
618 static const char * const rx_int3_1_interp_mux_text[] = {
619 "ZERO", "RX INT3_1 MIX1",
620 };
621
622 static const char * const rx_int4_1_interp_mux_text[] = {
623 "ZERO", "RX INT4_1 MIX1",
624 };
625
626 static const char * const rx_int7_1_interp_mux_text[] = {
627 "ZERO", "RX INT7_1 MIX1",
628 };
629
630 static const char * const rx_int8_1_interp_mux_text[] = {
631 "ZERO", "RX INT8_1 MIX1",
632 };
633
634 static const char * const rx_int0_2_interp_mux_text[] = {
635 "ZERO", "RX INT0_2 MUX",
636 };
637
638 static const char * const rx_int1_2_interp_mux_text[] = {
639 "ZERO", "RX INT1_2 MUX",
640 };
641
642 static const char * const rx_int2_2_interp_mux_text[] = {
643 "ZERO", "RX INT2_2 MUX",
644 };
645
646 static const char * const rx_int3_2_interp_mux_text[] = {
647 "ZERO", "RX INT3_2 MUX",
648 };
649
650 static const char * const rx_int4_2_interp_mux_text[] = {
651 "ZERO", "RX INT4_2 MUX",
652 };
653
654 static const char * const rx_int7_2_interp_mux_text[] = {
655 "ZERO", "RX INT7_2 MUX",
656 };
657
658 static const char * const rx_int8_2_interp_mux_text[] = {
659 "ZERO", "RX INT8_2 MUX",
660 };
661
662 static const char * const dmic_mux_text[] = {
663 "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5"
664 };
665
666 static const char * const amic_mux_text[] = {
667 "ZERO", "ADC1", "ADC2", "ADC3", "ADC4"
668 };
669
670 static const char * const amic4_5_sel_text[] = {
671 "AMIC4", "AMIC5"
672 };
673
674 static const char * const adc_mux_text[] = {
675 "DMIC", "AMIC", "ANC_FB_TUNE1", "ANC_FB_TUNE2"
676 };
677
678 static const char * const cdc_if_tx0_mux_text[] = {
679 "ZERO", "RX_MIX_TX0", "DEC0", "DEC0_192"
680 };
681
682 static const char * const cdc_if_tx1_mux_text[] = {
683 "ZERO", "RX_MIX_TX1", "DEC1", "DEC1_192"
684 };
685
686 static const char * const cdc_if_tx2_mux_text[] = {
687 "ZERO", "RX_MIX_TX2", "DEC2", "DEC2_192"
688 };
689
690 static const char * const cdc_if_tx3_mux_text[] = {
691 "ZERO", "RX_MIX_TX3", "DEC3", "DEC3_192"
692 };
693
694 static const char * const cdc_if_tx4_mux_text[] = {
695 "ZERO", "RX_MIX_TX4", "DEC4", "DEC4_192"
696 };
697
698 static const char * const cdc_if_tx5_mux_text[] = {
699 "ZERO", "RX_MIX_TX5", "DEC5", "DEC5_192"
700 };
701
702 static const char * const cdc_if_tx6_mux_text[] = {
703 "ZERO", "RX_MIX_TX6", "DEC6", "DEC6_192"
704 };
705
706 static const char * const cdc_if_tx7_mux_text[] = {
707 "ZERO", "RX_MIX_TX7", "DEC7", "DEC7_192"
708 };
709
710 static const char * const cdc_if_tx8_mux_text[] = {
711 "ZERO", "RX_MIX_TX8", "DEC8", "DEC8_192"
712 };
713
714 static const char * const cdc_if_tx9_mux_text[] = {
715 "ZERO", "DEC7", "DEC7_192"
716 };
717
718 static const char * const cdc_if_tx10_mux_text[] = {
719 "ZERO", "DEC6", "DEC6_192"
720 };
721
722 static const char * const cdc_if_tx11_mux_text[] = {
723 "DEC_0_5", "DEC_9_12", "MAD_AUDIO", "MAD_BRDCST"
724 };
725
726 static const char * const cdc_if_tx11_inp1_mux_text[] = {
727 "ZERO", "DEC0", "DEC1", "DEC2", "DEC3", "DEC4",
728 "DEC5", "RX_MIX_TX5", "DEC9_10", "DEC11_12"
729 };
730
731 static const char * const cdc_if_tx13_mux_text[] = {
732 "CDC_DEC_5", "MAD_BRDCST"
733 };
734
735 static const char * const cdc_if_tx13_inp1_mux_text[] = {
736 "ZERO", "DEC5", "DEC5_192"
737 };
738
739 static const struct soc_enum cf_dec0_enum =
740 SOC_ENUM_SINGLE(WCD934X_CDC_TX0_TX_PATH_CFG0, 5, 3, cf_text);
741
742 static const struct soc_enum cf_dec1_enum =
743 SOC_ENUM_SINGLE(WCD934X_CDC_TX1_TX_PATH_CFG0, 5, 3, cf_text);
744
745 static const struct soc_enum cf_dec2_enum =
746 SOC_ENUM_SINGLE(WCD934X_CDC_TX2_TX_PATH_CFG0, 5, 3, cf_text);
747
748 static const struct soc_enum cf_dec3_enum =
749 SOC_ENUM_SINGLE(WCD934X_CDC_TX3_TX_PATH_CFG0, 5, 3, cf_text);
750
751 static const struct soc_enum cf_dec4_enum =
752 SOC_ENUM_SINGLE(WCD934X_CDC_TX4_TX_PATH_CFG0, 5, 3, cf_text);
753
754 static const struct soc_enum cf_dec5_enum =
755 SOC_ENUM_SINGLE(WCD934X_CDC_TX5_TX_PATH_CFG0, 5, 3, cf_text);
756
757 static const struct soc_enum cf_dec6_enum =
758 SOC_ENUM_SINGLE(WCD934X_CDC_TX6_TX_PATH_CFG0, 5, 3, cf_text);
759
760 static const struct soc_enum cf_dec7_enum =
761 SOC_ENUM_SINGLE(WCD934X_CDC_TX7_TX_PATH_CFG0, 5, 3, cf_text);
762
763 static const struct soc_enum cf_dec8_enum =
764 SOC_ENUM_SINGLE(WCD934X_CDC_TX8_TX_PATH_CFG0, 5, 3, cf_text);
765
766 static const struct soc_enum cf_int0_1_enum =
767 SOC_ENUM_SINGLE(WCD934X_CDC_RX0_RX_PATH_CFG2, 0, 4, rx_cf_text);
768
769 static SOC_ENUM_SINGLE_DECL(cf_int0_2_enum, WCD934X_CDC_RX0_RX_PATH_MIX_CFG, 2,
770 rx_cf_text);
771
772 static const struct soc_enum cf_int1_1_enum =
773 SOC_ENUM_SINGLE(WCD934X_CDC_RX1_RX_PATH_CFG2, 0, 4, rx_cf_text);
774
775 static SOC_ENUM_SINGLE_DECL(cf_int1_2_enum, WCD934X_CDC_RX1_RX_PATH_MIX_CFG, 2,
776 rx_cf_text);
777
778 static const struct soc_enum cf_int2_1_enum =
779 SOC_ENUM_SINGLE(WCD934X_CDC_RX2_RX_PATH_CFG2, 0, 4, rx_cf_text);
780
781 static SOC_ENUM_SINGLE_DECL(cf_int2_2_enum, WCD934X_CDC_RX2_RX_PATH_MIX_CFG, 2,
782 rx_cf_text);
783
784 static const struct soc_enum cf_int3_1_enum =
785 SOC_ENUM_SINGLE(WCD934X_CDC_RX3_RX_PATH_CFG2, 0, 4, rx_cf_text);
786
787 static SOC_ENUM_SINGLE_DECL(cf_int3_2_enum, WCD934X_CDC_RX3_RX_PATH_MIX_CFG, 2,
788 rx_cf_text);
789
790 static const struct soc_enum cf_int4_1_enum =
791 SOC_ENUM_SINGLE(WCD934X_CDC_RX4_RX_PATH_CFG2, 0, 4, rx_cf_text);
792
793 static SOC_ENUM_SINGLE_DECL(cf_int4_2_enum, WCD934X_CDC_RX4_RX_PATH_MIX_CFG, 2,
794 rx_cf_text);
795
796 static const struct soc_enum cf_int7_1_enum =
797 SOC_ENUM_SINGLE(WCD934X_CDC_RX7_RX_PATH_CFG2, 0, 4, rx_cf_text);
798
799 static SOC_ENUM_SINGLE_DECL(cf_int7_2_enum, WCD934X_CDC_RX7_RX_PATH_MIX_CFG, 2,
800 rx_cf_text);
801
802 static const struct soc_enum cf_int8_1_enum =
803 SOC_ENUM_SINGLE(WCD934X_CDC_RX8_RX_PATH_CFG2, 0, 4, rx_cf_text);
804
805 static SOC_ENUM_SINGLE_DECL(cf_int8_2_enum, WCD934X_CDC_RX8_RX_PATH_MIX_CFG, 2,
806 rx_cf_text);
807
808 static const struct soc_enum rx_hph_mode_mux_enum =
809 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
810 rx_hph_mode_mux_text);
811
812 static const struct soc_enum slim_rx_mux_enum =
813 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim_rx_mux_text), slim_rx_mux_text);
814
815 static const struct soc_enum rx_int0_2_mux_chain_enum =
816 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG1, 0, 10,
817 rx_int0_7_mix_mux_text);
818
819 static const struct soc_enum rx_int1_2_mux_chain_enum =
820 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG1, 0, 9,
821 rx_int_mix_mux_text);
822
823 static const struct soc_enum rx_int2_2_mux_chain_enum =
824 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG1, 0, 9,
825 rx_int_mix_mux_text);
826
827 static const struct soc_enum rx_int3_2_mux_chain_enum =
828 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG1, 0, 9,
829 rx_int_mix_mux_text);
830
831 static const struct soc_enum rx_int4_2_mux_chain_enum =
832 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG1, 0, 9,
833 rx_int_mix_mux_text);
834
835 static const struct soc_enum rx_int7_2_mux_chain_enum =
836 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG1, 0, 10,
837 rx_int0_7_mix_mux_text);
838
839 static const struct soc_enum rx_int8_2_mux_chain_enum =
840 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG1, 0, 9,
841 rx_int_mix_mux_text);
842
843 static const struct soc_enum rx_int0_1_mix_inp0_chain_enum =
844 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG0, 0, 13,
845 rx_prim_mix_text);
846
847 static const struct soc_enum rx_int0_1_mix_inp1_chain_enum =
848 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG0, 4, 13,
849 rx_prim_mix_text);
850
851 static const struct soc_enum rx_int0_1_mix_inp2_chain_enum =
852 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG1, 4, 13,
853 rx_prim_mix_text);
854
855 static const struct soc_enum rx_int1_1_mix_inp0_chain_enum =
856 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG0, 0, 13,
857 rx_prim_mix_text);
858
859 static const struct soc_enum rx_int1_1_mix_inp1_chain_enum =
860 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG0, 4, 13,
861 rx_prim_mix_text);
862
863 static const struct soc_enum rx_int1_1_mix_inp2_chain_enum =
864 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG1, 4, 13,
865 rx_prim_mix_text);
866
867 static const struct soc_enum rx_int2_1_mix_inp0_chain_enum =
868 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG0, 0, 13,
869 rx_prim_mix_text);
870
871 static const struct soc_enum rx_int2_1_mix_inp1_chain_enum =
872 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG0, 4, 13,
873 rx_prim_mix_text);
874
875 static const struct soc_enum rx_int2_1_mix_inp2_chain_enum =
876 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG1, 4, 13,
877 rx_prim_mix_text);
878
879 static const struct soc_enum rx_int3_1_mix_inp0_chain_enum =
880 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG0, 0, 13,
881 rx_prim_mix_text);
882
883 static const struct soc_enum rx_int3_1_mix_inp1_chain_enum =
884 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG0, 4, 13,
885 rx_prim_mix_text);
886
887 static const struct soc_enum rx_int3_1_mix_inp2_chain_enum =
888 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG1, 4, 13,
889 rx_prim_mix_text);
890
891 static const struct soc_enum rx_int4_1_mix_inp0_chain_enum =
892 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG0, 0, 13,
893 rx_prim_mix_text);
894
895 static const struct soc_enum rx_int4_1_mix_inp1_chain_enum =
896 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG0, 4, 13,
897 rx_prim_mix_text);
898
899 static const struct soc_enum rx_int4_1_mix_inp2_chain_enum =
900 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG1, 4, 13,
901 rx_prim_mix_text);
902
903 static const struct soc_enum rx_int7_1_mix_inp0_chain_enum =
904 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG0, 0, 13,
905 rx_prim_mix_text);
906
907 static const struct soc_enum rx_int7_1_mix_inp1_chain_enum =
908 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG0, 4, 13,
909 rx_prim_mix_text);
910
911 static const struct soc_enum rx_int7_1_mix_inp2_chain_enum =
912 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG1, 4, 13,
913 rx_prim_mix_text);
914
915 static const struct soc_enum rx_int8_1_mix_inp0_chain_enum =
916 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG0, 0, 13,
917 rx_prim_mix_text);
918
919 static const struct soc_enum rx_int8_1_mix_inp1_chain_enum =
920 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG0, 4, 13,
921 rx_prim_mix_text);
922
923 static const struct soc_enum rx_int8_1_mix_inp2_chain_enum =
924 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG1, 4, 13,
925 rx_prim_mix_text);
926
927 static const struct soc_enum rx_int0_mix2_inp_mux_enum =
928 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 0, 4,
929 rx_sidetone_mix_text);
930
931 static const struct soc_enum rx_int1_mix2_inp_mux_enum =
932 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 2, 4,
933 rx_sidetone_mix_text);
934
935 static const struct soc_enum rx_int2_mix2_inp_mux_enum =
936 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 4, 4,
937 rx_sidetone_mix_text);
938
939 static const struct soc_enum rx_int3_mix2_inp_mux_enum =
940 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 6, 4,
941 rx_sidetone_mix_text);
942
943 static const struct soc_enum rx_int4_mix2_inp_mux_enum =
944 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG1, 0, 4,
945 rx_sidetone_mix_text);
946
947 static const struct soc_enum rx_int7_mix2_inp_mux_enum =
948 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG1, 2, 4,
949 rx_sidetone_mix_text);
950
951 static const struct soc_enum iir0_inp0_mux_enum =
952 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG0,
953 0, 18, iir_inp_mux_text);
954
955 static const struct soc_enum iir0_inp1_mux_enum =
956 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG1,
957 0, 18, iir_inp_mux_text);
958
959 static const struct soc_enum iir0_inp2_mux_enum =
960 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG2,
961 0, 18, iir_inp_mux_text);
962
963 static const struct soc_enum iir0_inp3_mux_enum =
964 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG3,
965 0, 18, iir_inp_mux_text);
966
967 static const struct soc_enum iir1_inp0_mux_enum =
968 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG0,
969 0, 18, iir_inp_mux_text);
970
971 static const struct soc_enum iir1_inp1_mux_enum =
972 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG1,
973 0, 18, iir_inp_mux_text);
974
975 static const struct soc_enum iir1_inp2_mux_enum =
976 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG2,
977 0, 18, iir_inp_mux_text);
978
979 static const struct soc_enum iir1_inp3_mux_enum =
980 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG3,
981 0, 18, iir_inp_mux_text);
982
983 static const struct soc_enum rx_int0_dem_inp_mux_enum =
984 SOC_ENUM_SINGLE(WCD934X_CDC_RX0_RX_PATH_SEC0, 0,
985 ARRAY_SIZE(rx_int_dem_inp_mux_text),
986 rx_int_dem_inp_mux_text);
987
988 static const struct soc_enum rx_int1_dem_inp_mux_enum =
989 SOC_ENUM_SINGLE(WCD934X_CDC_RX1_RX_PATH_SEC0, 0,
990 ARRAY_SIZE(rx_int_dem_inp_mux_text),
991 rx_int_dem_inp_mux_text);
992
993 static const struct soc_enum rx_int2_dem_inp_mux_enum =
994 SOC_ENUM_SINGLE(WCD934X_CDC_RX2_RX_PATH_SEC0, 0,
995 ARRAY_SIZE(rx_int_dem_inp_mux_text),
996 rx_int_dem_inp_mux_text);
997
998 static const struct soc_enum tx_adc_mux0_enum =
999 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0,
1000 ARRAY_SIZE(adc_mux_text), adc_mux_text);
1001 static const struct soc_enum tx_adc_mux1_enum =
1002 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0,
1003 ARRAY_SIZE(adc_mux_text), adc_mux_text);
1004 static const struct soc_enum tx_adc_mux2_enum =
1005 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0,
1006 ARRAY_SIZE(adc_mux_text), adc_mux_text);
1007 static const struct soc_enum tx_adc_mux3_enum =
1008 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0,
1009 ARRAY_SIZE(adc_mux_text), adc_mux_text);
1010 static const struct soc_enum tx_adc_mux4_enum =
1011 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 2,
1012 ARRAY_SIZE(adc_mux_text), adc_mux_text);
1013 static const struct soc_enum tx_adc_mux5_enum =
1014 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 2,
1015 ARRAY_SIZE(adc_mux_text), adc_mux_text);
1016 static const struct soc_enum tx_adc_mux6_enum =
1017 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 2,
1018 ARRAY_SIZE(adc_mux_text), adc_mux_text);
1019 static const struct soc_enum tx_adc_mux7_enum =
1020 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 2,
1021 ARRAY_SIZE(adc_mux_text), adc_mux_text);
1022 static const struct soc_enum tx_adc_mux8_enum =
1023 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 4,
1024 ARRAY_SIZE(adc_mux_text), adc_mux_text);
1025
1026 static const struct soc_enum rx_int0_1_interp_mux_enum =
1027 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2,
1028 rx_int0_1_interp_mux_text);
1029
1030 static const struct soc_enum rx_int1_1_interp_mux_enum =
1031 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2,
1032 rx_int1_1_interp_mux_text);
1033
1034 static const struct soc_enum rx_int2_1_interp_mux_enum =
1035 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2,
1036 rx_int2_1_interp_mux_text);
1037
1038 static const struct soc_enum rx_int3_1_interp_mux_enum =
1039 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int3_1_interp_mux_text);
1040
1041 static const struct soc_enum rx_int4_1_interp_mux_enum =
1042 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int4_1_interp_mux_text);
1043
1044 static const struct soc_enum rx_int7_1_interp_mux_enum =
1045 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int7_1_interp_mux_text);
1046
1047 static const struct soc_enum rx_int8_1_interp_mux_enum =
1048 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int8_1_interp_mux_text);
1049
1050 static const struct soc_enum rx_int0_2_interp_mux_enum =
1051 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int0_2_interp_mux_text);
1052
1053 static const struct soc_enum rx_int1_2_interp_mux_enum =
1054 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int1_2_interp_mux_text);
1055
1056 static const struct soc_enum rx_int2_2_interp_mux_enum =
1057 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int2_2_interp_mux_text);
1058
1059 static const struct soc_enum rx_int3_2_interp_mux_enum =
1060 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int3_2_interp_mux_text);
1061
1062 static const struct soc_enum rx_int4_2_interp_mux_enum =
1063 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int4_2_interp_mux_text);
1064
1065 static const struct soc_enum rx_int7_2_interp_mux_enum =
1066 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int7_2_interp_mux_text);
1067
1068 static const struct soc_enum rx_int8_2_interp_mux_enum =
1069 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int8_2_interp_mux_text);
1070
1071 static const struct soc_enum tx_dmic_mux0_enum =
1072 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 3, 7,
1073 dmic_mux_text);
1074
1075 static const struct soc_enum tx_dmic_mux1_enum =
1076 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 3, 7,
1077 dmic_mux_text);
1078
1079 static const struct soc_enum tx_dmic_mux2_enum =
1080 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 3, 7,
1081 dmic_mux_text);
1082
1083 static const struct soc_enum tx_dmic_mux3_enum =
1084 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 3, 7,
1085 dmic_mux_text);
1086
1087 static const struct soc_enum tx_dmic_mux4_enum =
1088 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 3, 7,
1089 dmic_mux_text);
1090
1091 static const struct soc_enum tx_dmic_mux5_enum =
1092 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 3, 7,
1093 dmic_mux_text);
1094
1095 static const struct soc_enum tx_dmic_mux6_enum =
1096 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 3, 7,
1097 dmic_mux_text);
1098
1099 static const struct soc_enum tx_dmic_mux7_enum =
1100 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 3, 7,
1101 dmic_mux_text);
1102
1103 static const struct soc_enum tx_dmic_mux8_enum =
1104 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 3, 7,
1105 dmic_mux_text);
1106
1107 static const struct soc_enum tx_amic_mux0_enum =
1108 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0, 5,
1109 amic_mux_text);
1110 static const struct soc_enum tx_amic_mux1_enum =
1111 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0, 5,
1112 amic_mux_text);
1113 static const struct soc_enum tx_amic_mux2_enum =
1114 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0, 5,
1115 amic_mux_text);
1116 static const struct soc_enum tx_amic_mux3_enum =
1117 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0, 5,
1118 amic_mux_text);
1119 static const struct soc_enum tx_amic_mux4_enum =
1120 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0, 5,
1121 amic_mux_text);
1122 static const struct soc_enum tx_amic_mux5_enum =
1123 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0, 5,
1124 amic_mux_text);
1125 static const struct soc_enum tx_amic_mux6_enum =
1126 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0, 5,
1127 amic_mux_text);
1128 static const struct soc_enum tx_amic_mux7_enum =
1129 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0, 5,
1130 amic_mux_text);
1131 static const struct soc_enum tx_amic_mux8_enum =
1132 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 0, 5,
1133 amic_mux_text);
1134
1135 static const struct soc_enum tx_amic4_5_enum =
1136 SOC_ENUM_SINGLE(WCD934X_TX_NEW_AMIC_4_5_SEL, 7, 2, amic4_5_sel_text);
1137
1138 static const struct soc_enum cdc_if_tx0_mux_enum =
1139 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 0,
1140 ARRAY_SIZE(cdc_if_tx0_mux_text), cdc_if_tx0_mux_text);
1141 static const struct soc_enum cdc_if_tx1_mux_enum =
1142 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 2,
1143 ARRAY_SIZE(cdc_if_tx1_mux_text), cdc_if_tx1_mux_text);
1144 static const struct soc_enum cdc_if_tx2_mux_enum =
1145 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 4,
1146 ARRAY_SIZE(cdc_if_tx2_mux_text), cdc_if_tx2_mux_text);
1147 static const struct soc_enum cdc_if_tx3_mux_enum =
1148 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 6,
1149 ARRAY_SIZE(cdc_if_tx3_mux_text), cdc_if_tx3_mux_text);
1150 static const struct soc_enum cdc_if_tx4_mux_enum =
1151 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 0,
1152 ARRAY_SIZE(cdc_if_tx4_mux_text), cdc_if_tx4_mux_text);
1153 static const struct soc_enum cdc_if_tx5_mux_enum =
1154 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 2,
1155 ARRAY_SIZE(cdc_if_tx5_mux_text), cdc_if_tx5_mux_text);
1156 static const struct soc_enum cdc_if_tx6_mux_enum =
1157 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 4,
1158 ARRAY_SIZE(cdc_if_tx6_mux_text), cdc_if_tx6_mux_text);
1159 static const struct soc_enum cdc_if_tx7_mux_enum =
1160 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 6,
1161 ARRAY_SIZE(cdc_if_tx7_mux_text), cdc_if_tx7_mux_text);
1162 static const struct soc_enum cdc_if_tx8_mux_enum =
1163 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 0,
1164 ARRAY_SIZE(cdc_if_tx8_mux_text), cdc_if_tx8_mux_text);
1165 static const struct soc_enum cdc_if_tx9_mux_enum =
1166 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 2,
1167 ARRAY_SIZE(cdc_if_tx9_mux_text), cdc_if_tx9_mux_text);
1168 static const struct soc_enum cdc_if_tx10_mux_enum =
1169 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 4,
1170 ARRAY_SIZE(cdc_if_tx10_mux_text), cdc_if_tx10_mux_text);
1171 static const struct soc_enum cdc_if_tx11_inp1_mux_enum =
1172 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3, 0,
1173 ARRAY_SIZE(cdc_if_tx11_inp1_mux_text),
1174 cdc_if_tx11_inp1_mux_text);
1175 static const struct soc_enum cdc_if_tx11_mux_enum =
1176 SOC_ENUM_SINGLE(WCD934X_DATA_HUB_SB_TX11_INP_CFG, 0,
1177 ARRAY_SIZE(cdc_if_tx11_mux_text), cdc_if_tx11_mux_text);
1178 static const struct soc_enum cdc_if_tx13_inp1_mux_enum =
1179 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3, 4,
1180 ARRAY_SIZE(cdc_if_tx13_inp1_mux_text),
1181 cdc_if_tx13_inp1_mux_text);
1182 static const struct soc_enum cdc_if_tx13_mux_enum =
1183 SOC_ENUM_SINGLE(WCD934X_DATA_HUB_SB_TX13_INP_CFG, 0,
1184 ARRAY_SIZE(cdc_if_tx13_mux_text), cdc_if_tx13_mux_text);
1185
wcd934x_set_sido_input_src(struct wcd934x_codec * wcd,int sido_src)1186 static int wcd934x_set_sido_input_src(struct wcd934x_codec *wcd, int sido_src)
1187 {
1188 if (sido_src == wcd->sido_input_src)
1189 return 0;
1190
1191 if (sido_src == SIDO_SOURCE_INTERNAL) {
1192 regmap_update_bits(wcd->regmap, WCD934X_ANA_BUCK_CTL,
1193 WCD934X_ANA_BUCK_HI_ACCU_EN_MASK, 0);
1194 usleep_range(100, 110);
1195 regmap_update_bits(wcd->regmap, WCD934X_ANA_BUCK_CTL,
1196 WCD934X_ANA_BUCK_HI_ACCU_PRE_ENX_MASK, 0x0);
1197 usleep_range(100, 110);
1198 regmap_update_bits(wcd->regmap, WCD934X_ANA_RCO,
1199 WCD934X_ANA_RCO_BG_EN_MASK, 0);
1200 usleep_range(100, 110);
1201 regmap_update_bits(wcd->regmap, WCD934X_ANA_BUCK_CTL,
1202 WCD934X_ANA_BUCK_PRE_EN1_MASK,
1203 WCD934X_ANA_BUCK_PRE_EN1_ENABLE);
1204 usleep_range(100, 110);
1205 regmap_update_bits(wcd->regmap, WCD934X_ANA_BUCK_CTL,
1206 WCD934X_ANA_BUCK_PRE_EN2_MASK,
1207 WCD934X_ANA_BUCK_PRE_EN2_ENABLE);
1208 usleep_range(100, 110);
1209 regmap_update_bits(wcd->regmap, WCD934X_ANA_BUCK_CTL,
1210 WCD934X_ANA_BUCK_HI_ACCU_EN_MASK,
1211 WCD934X_ANA_BUCK_HI_ACCU_ENABLE);
1212 usleep_range(100, 110);
1213 } else if (sido_src == SIDO_SOURCE_RCO_BG) {
1214 regmap_update_bits(wcd->regmap, WCD934X_ANA_RCO,
1215 WCD934X_ANA_RCO_BG_EN_MASK,
1216 WCD934X_ANA_RCO_BG_ENABLE);
1217 usleep_range(100, 110);
1218 }
1219 wcd->sido_input_src = sido_src;
1220
1221 return 0;
1222 }
1223
wcd934x_enable_ana_bias_and_sysclk(struct wcd934x_codec * wcd)1224 static int wcd934x_enable_ana_bias_and_sysclk(struct wcd934x_codec *wcd)
1225 {
1226 mutex_lock(&wcd->sysclk_mutex);
1227
1228 if (++wcd->sysclk_users != 1) {
1229 mutex_unlock(&wcd->sysclk_mutex);
1230 return 0;
1231 }
1232 mutex_unlock(&wcd->sysclk_mutex);
1233
1234 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1235 WCD934X_ANA_BIAS_EN_MASK,
1236 WCD934X_ANA_BIAS_EN);
1237 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1238 WCD934X_ANA_PRECHRG_EN_MASK,
1239 WCD934X_ANA_PRECHRG_EN);
1240 /*
1241 * 1ms delay is required after pre-charge is enabled
1242 * as per HW requirement
1243 */
1244 usleep_range(1000, 1100);
1245 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1246 WCD934X_ANA_PRECHRG_EN_MASK, 0);
1247 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1248 WCD934X_ANA_PRECHRG_MODE_MASK, 0);
1249
1250 /*
1251 * In data clock contrl register is changed
1252 * to CLK_SYS_MCLK_PRG
1253 */
1254
1255 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
1256 WCD934X_EXT_CLK_BUF_EN_MASK,
1257 WCD934X_EXT_CLK_BUF_EN);
1258 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
1259 WCD934X_EXT_CLK_DIV_RATIO_MASK,
1260 WCD934X_EXT_CLK_DIV_BY_2);
1261 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
1262 WCD934X_MCLK_SRC_MASK,
1263 WCD934X_MCLK_SRC_EXT_CLK);
1264 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
1265 WCD934X_MCLK_EN_MASK, WCD934X_MCLK_EN);
1266 regmap_update_bits(wcd->regmap,
1267 WCD934X_CDC_CLK_RST_CTRL_FS_CNT_CONTROL,
1268 WCD934X_CDC_FS_MCLK_CNT_EN_MASK,
1269 WCD934X_CDC_FS_MCLK_CNT_ENABLE);
1270 regmap_update_bits(wcd->regmap,
1271 WCD934X_CDC_CLK_RST_CTRL_MCLK_CONTROL,
1272 WCD934X_MCLK_EN_MASK,
1273 WCD934X_MCLK_EN);
1274 regmap_update_bits(wcd->regmap, WCD934X_CODEC_RPM_CLK_GATE,
1275 WCD934X_CODEC_RPM_CLK_GATE_MASK, 0x0);
1276 /*
1277 * 10us sleep is required after clock is enabled
1278 * as per HW requirement
1279 */
1280 usleep_range(10, 15);
1281
1282 wcd934x_set_sido_input_src(wcd, SIDO_SOURCE_RCO_BG);
1283
1284 return 0;
1285 }
1286
wcd934x_disable_ana_bias_and_syclk(struct wcd934x_codec * wcd)1287 static int wcd934x_disable_ana_bias_and_syclk(struct wcd934x_codec *wcd)
1288 {
1289 mutex_lock(&wcd->sysclk_mutex);
1290 if (--wcd->sysclk_users != 0) {
1291 mutex_unlock(&wcd->sysclk_mutex);
1292 return 0;
1293 }
1294 mutex_unlock(&wcd->sysclk_mutex);
1295
1296 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
1297 WCD934X_EXT_CLK_BUF_EN_MASK |
1298 WCD934X_MCLK_EN_MASK, 0x0);
1299 wcd934x_set_sido_input_src(wcd, SIDO_SOURCE_INTERNAL);
1300
1301 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1302 WCD934X_ANA_BIAS_EN_MASK, 0);
1303 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1304 WCD934X_ANA_PRECHRG_EN_MASK, 0);
1305
1306 return 0;
1307 }
1308
__wcd934x_cdc_mclk_enable(struct wcd934x_codec * wcd,bool enable)1309 static int __wcd934x_cdc_mclk_enable(struct wcd934x_codec *wcd, bool enable)
1310 {
1311 int ret = 0;
1312
1313 if (enable) {
1314 ret = clk_prepare_enable(wcd->extclk);
1315
1316 if (ret) {
1317 dev_err(wcd->dev, "%s: ext clk enable failed\n",
1318 __func__);
1319 return ret;
1320 }
1321 ret = wcd934x_enable_ana_bias_and_sysclk(wcd);
1322 } else {
1323 int val;
1324
1325 regmap_read(wcd->regmap, WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL,
1326 &val);
1327
1328 /* Don't disable clock if soundwire using it.*/
1329 if (val & WCD934X_CDC_SWR_CLK_EN_MASK)
1330 return 0;
1331
1332 wcd934x_disable_ana_bias_and_syclk(wcd);
1333 clk_disable_unprepare(wcd->extclk);
1334 }
1335
1336 return ret;
1337 }
1338
wcd934x_codec_enable_mclk(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)1339 static int wcd934x_codec_enable_mclk(struct snd_soc_dapm_widget *w,
1340 struct snd_kcontrol *kc, int event)
1341 {
1342 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
1343 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
1344
1345 switch (event) {
1346 case SND_SOC_DAPM_PRE_PMU:
1347 return __wcd934x_cdc_mclk_enable(wcd, true);
1348 case SND_SOC_DAPM_POST_PMD:
1349 return __wcd934x_cdc_mclk_enable(wcd, false);
1350 }
1351
1352 return 0;
1353 }
1354
wcd934x_get_version(struct wcd934x_codec * wcd)1355 static int wcd934x_get_version(struct wcd934x_codec *wcd)
1356 {
1357 int val1, val2, ver, ret;
1358 struct regmap *regmap;
1359 u16 id_minor;
1360 u32 version_mask = 0;
1361
1362 regmap = wcd->regmap;
1363 ver = 0;
1364
1365 ret = regmap_bulk_read(regmap, WCD934X_CHIP_TIER_CTRL_CHIP_ID_BYTE0,
1366 (u8 *)&id_minor, sizeof(u16));
1367
1368 if (ret)
1369 return ret;
1370
1371 regmap_read(regmap, WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT14, &val1);
1372 regmap_read(regmap, WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT15, &val2);
1373
1374 version_mask |= (!!((u8)val1 & 0x80)) << DSD_DISABLED_MASK;
1375 version_mask |= (!!((u8)val2 & 0x01)) << SLNQ_DISABLED_MASK;
1376
1377 switch (version_mask) {
1378 case DSD_DISABLED | SLNQ_DISABLED:
1379 if (id_minor == 0)
1380 ver = WCD_VERSION_WCD9340_1_0;
1381 else if (id_minor == 0x01)
1382 ver = WCD_VERSION_WCD9340_1_1;
1383 break;
1384 case SLNQ_DISABLED:
1385 if (id_minor == 0)
1386 ver = WCD_VERSION_WCD9341_1_0;
1387 else if (id_minor == 0x01)
1388 ver = WCD_VERSION_WCD9341_1_1;
1389 break;
1390 }
1391
1392 wcd->version = ver;
1393 dev_info(wcd->dev, "WCD934X Minor:0x%x Version:0x%x\n", id_minor, ver);
1394
1395 return 0;
1396 }
1397
wcd934x_enable_efuse_sensing(struct wcd934x_codec * wcd)1398 static void wcd934x_enable_efuse_sensing(struct wcd934x_codec *wcd)
1399 {
1400 int rc, val;
1401
1402 __wcd934x_cdc_mclk_enable(wcd, true);
1403
1404 regmap_update_bits(wcd->regmap,
1405 WCD934X_CHIP_TIER_CTRL_EFUSE_CTL,
1406 WCD934X_EFUSE_SENSE_STATE_MASK,
1407 WCD934X_EFUSE_SENSE_STATE_DEF);
1408 regmap_update_bits(wcd->regmap,
1409 WCD934X_CHIP_TIER_CTRL_EFUSE_CTL,
1410 WCD934X_EFUSE_SENSE_EN_MASK,
1411 WCD934X_EFUSE_SENSE_ENABLE);
1412 /*
1413 * 5ms sleep required after enabling efuse control
1414 * before checking the status.
1415 */
1416 usleep_range(5000, 5500);
1417 wcd934x_set_sido_input_src(wcd, SIDO_SOURCE_RCO_BG);
1418
1419 rc = regmap_read(wcd->regmap,
1420 WCD934X_CHIP_TIER_CTRL_EFUSE_STATUS, &val);
1421 if (rc || (!(val & 0x01)))
1422 WARN(1, "%s: Efuse sense is not complete val=%x, ret=%d\n",
1423 __func__, val, rc);
1424
1425 __wcd934x_cdc_mclk_enable(wcd, false);
1426 }
1427
wcd934x_swrm_clock(struct wcd934x_codec * wcd,bool enable)1428 static int wcd934x_swrm_clock(struct wcd934x_codec *wcd, bool enable)
1429 {
1430 if (enable) {
1431 __wcd934x_cdc_mclk_enable(wcd, true);
1432 regmap_update_bits(wcd->regmap,
1433 WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL,
1434 WCD934X_CDC_SWR_CLK_EN_MASK,
1435 WCD934X_CDC_SWR_CLK_ENABLE);
1436 } else {
1437 regmap_update_bits(wcd->regmap,
1438 WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL,
1439 WCD934X_CDC_SWR_CLK_EN_MASK, 0);
1440 __wcd934x_cdc_mclk_enable(wcd, false);
1441 }
1442
1443 return 0;
1444 }
1445
wcd934x_set_prim_interpolator_rate(struct snd_soc_dai * dai,u8 rate_val,u32 rate)1446 static int wcd934x_set_prim_interpolator_rate(struct snd_soc_dai *dai,
1447 u8 rate_val, u32 rate)
1448 {
1449 struct snd_soc_component *comp = dai->component;
1450 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
1451 struct wcd934x_slim_ch *ch;
1452 u8 cfg0, cfg1, inp0_sel, inp1_sel, inp2_sel;
1453 int inp, j;
1454
1455 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1456 inp = ch->shift + INTn_1_INP_SEL_RX0;
1457 /*
1458 * Loop through all interpolator MUX inputs and find out
1459 * to which interpolator input, the slim rx port
1460 * is connected
1461 */
1462 for (j = 0; j < WCD934X_NUM_INTERPOLATORS; j++) {
1463 /* Interpolators 5 and 6 are not aviliable in Tavil */
1464 if (j == INTERP_LO3_NA || j == INTERP_LO4_NA)
1465 continue;
1466
1467 cfg0 = snd_soc_component_read(comp,
1468 WCD934X_CDC_RX_INP_MUX_RX_INT_CFG0(j));
1469 cfg1 = snd_soc_component_read(comp,
1470 WCD934X_CDC_RX_INP_MUX_RX_INT_CFG1(j));
1471
1472 inp0_sel = cfg0 &
1473 WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1474 inp1_sel = (cfg0 >> 4) &
1475 WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1476 inp2_sel = (cfg1 >> 4) &
1477 WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1478
1479 if ((inp0_sel == inp) || (inp1_sel == inp) ||
1480 (inp2_sel == inp)) {
1481 /* rate is in Hz */
1482 /*
1483 * Ear and speaker primary path does not support
1484 * native sample rates
1485 */
1486 if ((j == INTERP_EAR || j == INTERP_SPKR1 ||
1487 j == INTERP_SPKR2) && rate == 44100)
1488 dev_err(wcd->dev,
1489 "Cannot set 44.1KHz on INT%d\n",
1490 j);
1491 else
1492 snd_soc_component_update_bits(comp,
1493 WCD934X_CDC_RX_PATH_CTL(j),
1494 WCD934X_CDC_MIX_PCM_RATE_MASK,
1495 rate_val);
1496 }
1497 }
1498 }
1499
1500 return 0;
1501 }
1502
wcd934x_set_mix_interpolator_rate(struct snd_soc_dai * dai,int rate_val,u32 rate)1503 static int wcd934x_set_mix_interpolator_rate(struct snd_soc_dai *dai,
1504 int rate_val, u32 rate)
1505 {
1506 struct snd_soc_component *component = dai->component;
1507 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
1508 struct wcd934x_slim_ch *ch;
1509 int val, j;
1510
1511 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1512 for (j = 0; j < WCD934X_NUM_INTERPOLATORS; j++) {
1513 /* Interpolators 5 and 6 are not aviliable in Tavil */
1514 if (j == INTERP_LO3_NA || j == INTERP_LO4_NA)
1515 continue;
1516 val = snd_soc_component_read(component,
1517 WCD934X_CDC_RX_INP_MUX_RX_INT_CFG1(j)) &
1518 WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1519
1520 if (val == (ch->shift + INTn_2_INP_SEL_RX0)) {
1521 /*
1522 * Ear mix path supports only 48, 96, 192,
1523 * 384KHz only
1524 */
1525 if ((j == INTERP_EAR) &&
1526 (rate_val < 0x4 ||
1527 rate_val > 0x7)) {
1528 dev_err(component->dev,
1529 "Invalid rate for AIF_PB DAI(%d)\n",
1530 dai->id);
1531 return -EINVAL;
1532 }
1533
1534 snd_soc_component_update_bits(component,
1535 WCD934X_CDC_RX_PATH_MIX_CTL(j),
1536 WCD934X_CDC_MIX_PCM_RATE_MASK,
1537 rate_val);
1538 }
1539 }
1540 }
1541
1542 return 0;
1543 }
1544
wcd934x_set_interpolator_rate(struct snd_soc_dai * dai,u32 sample_rate)1545 static int wcd934x_set_interpolator_rate(struct snd_soc_dai *dai,
1546 u32 sample_rate)
1547 {
1548 int rate_val = 0;
1549 int i, ret;
1550
1551 for (i = 0; i < ARRAY_SIZE(sr_val_tbl); i++) {
1552 if (sample_rate == sr_val_tbl[i].sample_rate) {
1553 rate_val = sr_val_tbl[i].rate_val;
1554 break;
1555 }
1556 }
1557 if ((i == ARRAY_SIZE(sr_val_tbl)) || (rate_val < 0)) {
1558 dev_err(dai->dev, "Unsupported sample rate: %d\n", sample_rate);
1559 return -EINVAL;
1560 }
1561
1562 ret = wcd934x_set_prim_interpolator_rate(dai, (u8)rate_val,
1563 sample_rate);
1564 if (ret)
1565 return ret;
1566 ret = wcd934x_set_mix_interpolator_rate(dai, (u8)rate_val,
1567 sample_rate);
1568 if (ret)
1569 return ret;
1570
1571 return ret;
1572 }
1573
wcd934x_set_decimator_rate(struct snd_soc_dai * dai,u8 rate_val,u32 rate)1574 static int wcd934x_set_decimator_rate(struct snd_soc_dai *dai,
1575 u8 rate_val, u32 rate)
1576 {
1577 struct snd_soc_component *comp = dai->component;
1578 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp);
1579 u8 shift = 0, shift_val = 0, tx_mux_sel;
1580 struct wcd934x_slim_ch *ch;
1581 int tx_port, tx_port_reg;
1582 int decimator = -1;
1583
1584 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1585 tx_port = ch->port;
1586 /* Find the SB TX MUX input - which decimator is connected */
1587 switch (tx_port) {
1588 case 0 ... 3:
1589 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0;
1590 shift = (tx_port << 1);
1591 shift_val = 0x03;
1592 break;
1593 case 4 ... 7:
1594 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1;
1595 shift = ((tx_port - 4) << 1);
1596 shift_val = 0x03;
1597 break;
1598 case 8 ... 10:
1599 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2;
1600 shift = ((tx_port - 8) << 1);
1601 shift_val = 0x03;
1602 break;
1603 case 11:
1604 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3;
1605 shift = 0;
1606 shift_val = 0x0F;
1607 break;
1608 case 13:
1609 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3;
1610 shift = 4;
1611 shift_val = 0x03;
1612 break;
1613 default:
1614 dev_err(wcd->dev, "Invalid SLIM TX%u port DAI ID:%d\n",
1615 tx_port, dai->id);
1616 return -EINVAL;
1617 }
1618
1619 tx_mux_sel = snd_soc_component_read(comp, tx_port_reg) &
1620 (shift_val << shift);
1621
1622 tx_mux_sel = tx_mux_sel >> shift;
1623 switch (tx_port) {
1624 case 0 ... 8:
1625 if ((tx_mux_sel == 0x2) || (tx_mux_sel == 0x3))
1626 decimator = tx_port;
1627 break;
1628 case 9 ... 10:
1629 if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2))
1630 decimator = ((tx_port == 9) ? 7 : 6);
1631 break;
1632 case 11:
1633 if ((tx_mux_sel >= 1) && (tx_mux_sel < 7))
1634 decimator = tx_mux_sel - 1;
1635 break;
1636 case 13:
1637 if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2))
1638 decimator = 5;
1639 break;
1640 default:
1641 dev_err(wcd->dev, "ERROR: Invalid tx_port: %d\n",
1642 tx_port);
1643 return -EINVAL;
1644 }
1645
1646 snd_soc_component_update_bits(comp,
1647 WCD934X_CDC_TX_PATH_CTL(decimator),
1648 WCD934X_CDC_TX_PATH_CTL_PCM_RATE_MASK,
1649 rate_val);
1650 }
1651
1652 return 0;
1653 }
1654
wcd934x_slim_set_hw_params(struct wcd934x_codec * wcd,struct wcd_slim_codec_dai_data * dai_data,int direction)1655 static int wcd934x_slim_set_hw_params(struct wcd934x_codec *wcd,
1656 struct wcd_slim_codec_dai_data *dai_data,
1657 int direction)
1658 {
1659 struct list_head *slim_ch_list = &dai_data->slim_ch_list;
1660 struct slim_stream_config *cfg = &dai_data->sconfig;
1661 struct wcd934x_slim_ch *ch;
1662 u16 payload = 0;
1663 int ret, i;
1664
1665 cfg->ch_count = 0;
1666 cfg->direction = direction;
1667 cfg->port_mask = 0;
1668
1669 /* Configure slave interface device */
1670 list_for_each_entry(ch, slim_ch_list, list) {
1671 cfg->ch_count++;
1672 payload |= 1 << ch->shift;
1673 cfg->port_mask |= BIT(ch->port);
1674 }
1675
1676 cfg->chs = kcalloc(cfg->ch_count, sizeof(unsigned int), GFP_KERNEL);
1677 if (!cfg->chs)
1678 return -ENOMEM;
1679
1680 i = 0;
1681 list_for_each_entry(ch, slim_ch_list, list) {
1682 cfg->chs[i++] = ch->ch_num;
1683 if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
1684 /* write to interface device */
1685 ret = regmap_write(wcd->if_regmap,
1686 WCD934X_SLIM_PGD_RX_PORT_MULTI_CHNL_0(ch->port),
1687 payload);
1688
1689 if (ret < 0)
1690 goto err;
1691
1692 /* configure the slave port for water mark and enable*/
1693 ret = regmap_write(wcd->if_regmap,
1694 WCD934X_SLIM_PGD_RX_PORT_CFG(ch->port),
1695 WCD934X_SLIM_WATER_MARK_VAL);
1696 if (ret < 0)
1697 goto err;
1698 } else {
1699 ret = regmap_write(wcd->if_regmap,
1700 WCD934X_SLIM_PGD_TX_PORT_MULTI_CHNL_0(ch->port),
1701 payload & 0x00FF);
1702 if (ret < 0)
1703 goto err;
1704
1705 /* ports 8,9 */
1706 ret = regmap_write(wcd->if_regmap,
1707 WCD934X_SLIM_PGD_TX_PORT_MULTI_CHNL_1(ch->port),
1708 (payload & 0xFF00) >> 8);
1709 if (ret < 0)
1710 goto err;
1711
1712 /* configure the slave port for water mark and enable*/
1713 ret = regmap_write(wcd->if_regmap,
1714 WCD934X_SLIM_PGD_TX_PORT_CFG(ch->port),
1715 WCD934X_SLIM_WATER_MARK_VAL);
1716
1717 if (ret < 0)
1718 goto err;
1719 }
1720 }
1721
1722 dai_data->sruntime = slim_stream_allocate(wcd->sdev, "WCD934x-SLIM");
1723
1724 return 0;
1725
1726 err:
1727 dev_err(wcd->dev, "Error Setting slim hw params\n");
1728 kfree(cfg->chs);
1729 cfg->chs = NULL;
1730
1731 return ret;
1732 }
1733
wcd934x_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)1734 static int wcd934x_hw_params(struct snd_pcm_substream *substream,
1735 struct snd_pcm_hw_params *params,
1736 struct snd_soc_dai *dai)
1737 {
1738 struct wcd934x_codec *wcd;
1739 int ret, tx_fs_rate = 0;
1740
1741 wcd = snd_soc_component_get_drvdata(dai->component);
1742
1743 switch (substream->stream) {
1744 case SNDRV_PCM_STREAM_PLAYBACK:
1745 ret = wcd934x_set_interpolator_rate(dai, params_rate(params));
1746 if (ret) {
1747 dev_err(wcd->dev, "cannot set sample rate: %u\n",
1748 params_rate(params));
1749 return ret;
1750 }
1751 switch (params_width(params)) {
1752 case 16 ... 24:
1753 wcd->dai[dai->id].sconfig.bps = params_width(params);
1754 break;
1755 default:
1756 dev_err(wcd->dev, "Invalid format 0x%x\n",
1757 params_width(params));
1758 return -EINVAL;
1759 }
1760 break;
1761
1762 case SNDRV_PCM_STREAM_CAPTURE:
1763 switch (params_rate(params)) {
1764 case 8000:
1765 tx_fs_rate = 0;
1766 break;
1767 case 16000:
1768 tx_fs_rate = 1;
1769 break;
1770 case 32000:
1771 tx_fs_rate = 3;
1772 break;
1773 case 48000:
1774 tx_fs_rate = 4;
1775 break;
1776 case 96000:
1777 tx_fs_rate = 5;
1778 break;
1779 case 192000:
1780 tx_fs_rate = 6;
1781 break;
1782 case 384000:
1783 tx_fs_rate = 7;
1784 break;
1785 default:
1786 dev_err(wcd->dev, "Invalid TX sample rate: %d\n",
1787 params_rate(params));
1788 return -EINVAL;
1789
1790 }
1791
1792 ret = wcd934x_set_decimator_rate(dai, tx_fs_rate,
1793 params_rate(params));
1794 if (ret < 0) {
1795 dev_err(wcd->dev, "Cannot set TX Decimator rate\n");
1796 return ret;
1797 }
1798 switch (params_width(params)) {
1799 case 16 ... 32:
1800 wcd->dai[dai->id].sconfig.bps = params_width(params);
1801 break;
1802 default:
1803 dev_err(wcd->dev, "Invalid format 0x%x\n",
1804 params_width(params));
1805 return -EINVAL;
1806 }
1807 break;
1808 default:
1809 dev_err(wcd->dev, "Invalid stream type %d\n",
1810 substream->stream);
1811 return -EINVAL;
1812 }
1813
1814 wcd->dai[dai->id].sconfig.rate = params_rate(params);
1815
1816 return wcd934x_slim_set_hw_params(wcd, &wcd->dai[dai->id], substream->stream);
1817 }
1818
wcd934x_hw_free(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)1819 static int wcd934x_hw_free(struct snd_pcm_substream *substream,
1820 struct snd_soc_dai *dai)
1821 {
1822 struct wcd_slim_codec_dai_data *dai_data;
1823 struct wcd934x_codec *wcd;
1824
1825 wcd = snd_soc_component_get_drvdata(dai->component);
1826
1827 dai_data = &wcd->dai[dai->id];
1828
1829 kfree(dai_data->sconfig.chs);
1830
1831 return 0;
1832 }
1833
wcd934x_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)1834 static int wcd934x_trigger(struct snd_pcm_substream *substream, int cmd,
1835 struct snd_soc_dai *dai)
1836 {
1837 struct wcd_slim_codec_dai_data *dai_data;
1838 struct wcd934x_codec *wcd;
1839 struct slim_stream_config *cfg;
1840
1841 wcd = snd_soc_component_get_drvdata(dai->component);
1842
1843 dai_data = &wcd->dai[dai->id];
1844
1845 switch (cmd) {
1846 case SNDRV_PCM_TRIGGER_START:
1847 case SNDRV_PCM_TRIGGER_RESUME:
1848 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1849 cfg = &dai_data->sconfig;
1850 slim_stream_prepare(dai_data->sruntime, cfg);
1851 slim_stream_enable(dai_data->sruntime);
1852 break;
1853 case SNDRV_PCM_TRIGGER_STOP:
1854 case SNDRV_PCM_TRIGGER_SUSPEND:
1855 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1856 slim_stream_unprepare(dai_data->sruntime);
1857 slim_stream_disable(dai_data->sruntime);
1858 break;
1859 default:
1860 break;
1861 }
1862
1863 return 0;
1864 }
1865
wcd934x_set_channel_map(struct snd_soc_dai * dai,unsigned int tx_num,unsigned int * tx_slot,unsigned int rx_num,unsigned int * rx_slot)1866 static int wcd934x_set_channel_map(struct snd_soc_dai *dai,
1867 unsigned int tx_num, unsigned int *tx_slot,
1868 unsigned int rx_num, unsigned int *rx_slot)
1869 {
1870 struct wcd934x_codec *wcd;
1871 int i;
1872
1873 wcd = snd_soc_component_get_drvdata(dai->component);
1874
1875 if (tx_num > WCD934X_TX_MAX || rx_num > WCD934X_RX_MAX) {
1876 dev_err(wcd->dev, "Invalid tx %d or rx %d channel count\n",
1877 tx_num, rx_num);
1878 return -EINVAL;
1879 }
1880
1881 if (!tx_slot || !rx_slot) {
1882 dev_err(wcd->dev, "Invalid tx_slot=%p, rx_slot=%p\n",
1883 tx_slot, rx_slot);
1884 return -EINVAL;
1885 }
1886
1887 wcd->num_rx_port = rx_num;
1888 for (i = 0; i < rx_num; i++) {
1889 wcd->rx_chs[i].ch_num = rx_slot[i];
1890 INIT_LIST_HEAD(&wcd->rx_chs[i].list);
1891 }
1892
1893 wcd->num_tx_port = tx_num;
1894 for (i = 0; i < tx_num; i++) {
1895 wcd->tx_chs[i].ch_num = tx_slot[i];
1896 INIT_LIST_HEAD(&wcd->tx_chs[i].list);
1897 }
1898
1899 return 0;
1900 }
1901
wcd934x_get_channel_map(struct snd_soc_dai * dai,unsigned int * tx_num,unsigned int * tx_slot,unsigned int * rx_num,unsigned int * rx_slot)1902 static int wcd934x_get_channel_map(struct snd_soc_dai *dai,
1903 unsigned int *tx_num, unsigned int *tx_slot,
1904 unsigned int *rx_num, unsigned int *rx_slot)
1905 {
1906 struct wcd934x_slim_ch *ch;
1907 struct wcd934x_codec *wcd;
1908 int i = 0;
1909
1910 wcd = snd_soc_component_get_drvdata(dai->component);
1911
1912 switch (dai->id) {
1913 case AIF1_PB:
1914 case AIF2_PB:
1915 case AIF3_PB:
1916 case AIF4_PB:
1917 if (!rx_slot || !rx_num) {
1918 dev_err(wcd->dev, "Invalid rx_slot %p or rx_num %p\n",
1919 rx_slot, rx_num);
1920 return -EINVAL;
1921 }
1922
1923 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list)
1924 rx_slot[i++] = ch->ch_num;
1925
1926 *rx_num = i;
1927 break;
1928 case AIF1_CAP:
1929 case AIF2_CAP:
1930 case AIF3_CAP:
1931 if (!tx_slot || !tx_num) {
1932 dev_err(wcd->dev, "Invalid tx_slot %p or tx_num %p\n",
1933 tx_slot, tx_num);
1934 return -EINVAL;
1935 }
1936
1937 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list)
1938 tx_slot[i++] = ch->ch_num;
1939
1940 *tx_num = i;
1941 break;
1942 default:
1943 dev_err(wcd->dev, "Invalid DAI ID %x\n", dai->id);
1944 break;
1945 }
1946
1947 return 0;
1948 }
1949
1950 static struct snd_soc_dai_ops wcd934x_dai_ops = {
1951 .hw_params = wcd934x_hw_params,
1952 .hw_free = wcd934x_hw_free,
1953 .trigger = wcd934x_trigger,
1954 .set_channel_map = wcd934x_set_channel_map,
1955 .get_channel_map = wcd934x_get_channel_map,
1956 };
1957
1958 static struct snd_soc_dai_driver wcd934x_slim_dais[] = {
1959 [0] = {
1960 .name = "wcd934x_rx1",
1961 .id = AIF1_PB,
1962 .playback = {
1963 .stream_name = "AIF1 Playback",
1964 .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
1965 .formats = WCD934X_FORMATS_S16_S24_LE,
1966 .rate_max = 192000,
1967 .rate_min = 8000,
1968 .channels_min = 1,
1969 .channels_max = 2,
1970 },
1971 .ops = &wcd934x_dai_ops,
1972 },
1973 [1] = {
1974 .name = "wcd934x_tx1",
1975 .id = AIF1_CAP,
1976 .capture = {
1977 .stream_name = "AIF1 Capture",
1978 .rates = WCD934X_RATES_MASK,
1979 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1980 .rate_min = 8000,
1981 .rate_max = 192000,
1982 .channels_min = 1,
1983 .channels_max = 4,
1984 },
1985 .ops = &wcd934x_dai_ops,
1986 },
1987 [2] = {
1988 .name = "wcd934x_rx2",
1989 .id = AIF2_PB,
1990 .playback = {
1991 .stream_name = "AIF2 Playback",
1992 .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
1993 .formats = WCD934X_FORMATS_S16_S24_LE,
1994 .rate_min = 8000,
1995 .rate_max = 192000,
1996 .channels_min = 1,
1997 .channels_max = 2,
1998 },
1999 .ops = &wcd934x_dai_ops,
2000 },
2001 [3] = {
2002 .name = "wcd934x_tx2",
2003 .id = AIF2_CAP,
2004 .capture = {
2005 .stream_name = "AIF2 Capture",
2006 .rates = WCD934X_RATES_MASK,
2007 .formats = SNDRV_PCM_FMTBIT_S16_LE,
2008 .rate_min = 8000,
2009 .rate_max = 192000,
2010 .channels_min = 1,
2011 .channels_max = 4,
2012 },
2013 .ops = &wcd934x_dai_ops,
2014 },
2015 [4] = {
2016 .name = "wcd934x_rx3",
2017 .id = AIF3_PB,
2018 .playback = {
2019 .stream_name = "AIF3 Playback",
2020 .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
2021 .formats = WCD934X_FORMATS_S16_S24_LE,
2022 .rate_min = 8000,
2023 .rate_max = 192000,
2024 .channels_min = 1,
2025 .channels_max = 2,
2026 },
2027 .ops = &wcd934x_dai_ops,
2028 },
2029 [5] = {
2030 .name = "wcd934x_tx3",
2031 .id = AIF3_CAP,
2032 .capture = {
2033 .stream_name = "AIF3 Capture",
2034 .rates = WCD934X_RATES_MASK,
2035 .formats = SNDRV_PCM_FMTBIT_S16_LE,
2036 .rate_min = 8000,
2037 .rate_max = 192000,
2038 .channels_min = 1,
2039 .channels_max = 4,
2040 },
2041 .ops = &wcd934x_dai_ops,
2042 },
2043 [6] = {
2044 .name = "wcd934x_rx4",
2045 .id = AIF4_PB,
2046 .playback = {
2047 .stream_name = "AIF4 Playback",
2048 .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
2049 .formats = WCD934X_FORMATS_S16_S24_LE,
2050 .rate_min = 8000,
2051 .rate_max = 192000,
2052 .channels_min = 1,
2053 .channels_max = 2,
2054 },
2055 .ops = &wcd934x_dai_ops,
2056 },
2057 };
2058
swclk_gate_enable(struct clk_hw * hw)2059 static int swclk_gate_enable(struct clk_hw *hw)
2060 {
2061 return wcd934x_swrm_clock(to_wcd934x_codec(hw), true);
2062 }
2063
swclk_gate_disable(struct clk_hw * hw)2064 static void swclk_gate_disable(struct clk_hw *hw)
2065 {
2066 wcd934x_swrm_clock(to_wcd934x_codec(hw), false);
2067 }
2068
swclk_gate_is_enabled(struct clk_hw * hw)2069 static int swclk_gate_is_enabled(struct clk_hw *hw)
2070 {
2071 struct wcd934x_codec *wcd = to_wcd934x_codec(hw);
2072 int ret, val;
2073
2074 regmap_read(wcd->regmap, WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL, &val);
2075 ret = val & WCD934X_CDC_SWR_CLK_EN_MASK;
2076
2077 return ret;
2078 }
2079
swclk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)2080 static unsigned long swclk_recalc_rate(struct clk_hw *hw,
2081 unsigned long parent_rate)
2082 {
2083 return parent_rate / 2;
2084 }
2085
2086 static const struct clk_ops swclk_gate_ops = {
2087 .prepare = swclk_gate_enable,
2088 .unprepare = swclk_gate_disable,
2089 .is_enabled = swclk_gate_is_enabled,
2090 .recalc_rate = swclk_recalc_rate,
2091
2092 };
2093
wcd934x_register_mclk_output(struct wcd934x_codec * wcd)2094 static struct clk *wcd934x_register_mclk_output(struct wcd934x_codec *wcd)
2095 {
2096 struct clk *parent = wcd->extclk;
2097 struct device *dev = wcd->dev;
2098 struct device_node *np = dev->parent->of_node;
2099 const char *parent_clk_name = NULL;
2100 const char *clk_name = "mclk";
2101 struct clk_hw *hw;
2102 struct clk_init_data init;
2103 int ret;
2104
2105 if (of_property_read_u32(np, "clock-frequency", &wcd->rate))
2106 return NULL;
2107
2108 parent_clk_name = __clk_get_name(parent);
2109
2110 of_property_read_string(np, "clock-output-names", &clk_name);
2111
2112 init.name = clk_name;
2113 init.ops = &swclk_gate_ops;
2114 init.flags = 0;
2115 init.parent_names = &parent_clk_name;
2116 init.num_parents = 1;
2117 wcd->hw.init = &init;
2118
2119 hw = &wcd->hw;
2120 ret = clk_hw_register(wcd->dev->parent, hw);
2121 if (ret)
2122 return ERR_PTR(ret);
2123
2124 of_clk_add_provider(np, of_clk_src_simple_get, hw->clk);
2125
2126 return NULL;
2127 }
2128
wcd934x_get_micbias_val(struct device * dev,const char * micbias)2129 static int wcd934x_get_micbias_val(struct device *dev, const char *micbias)
2130 {
2131 int mv;
2132
2133 if (of_property_read_u32(dev->parent->of_node, micbias, &mv)) {
2134 dev_err(dev, "%s value not found, using default\n", micbias);
2135 mv = WCD934X_DEF_MICBIAS_MV;
2136 } else {
2137 /* convert it to milli volts */
2138 mv = mv/1000;
2139 }
2140
2141 if (mv < 1000 || mv > 2850) {
2142 dev_err(dev, "%s value not in valid range, using default\n",
2143 micbias);
2144 mv = WCD934X_DEF_MICBIAS_MV;
2145 }
2146
2147 return (mv - 1000) / 50;
2148 }
2149
wcd934x_init_dmic(struct snd_soc_component * comp)2150 static int wcd934x_init_dmic(struct snd_soc_component *comp)
2151 {
2152 int vout_ctl_1, vout_ctl_2, vout_ctl_3, vout_ctl_4;
2153 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
2154 u32 def_dmic_rate, dmic_clk_drv;
2155
2156 vout_ctl_1 = wcd934x_get_micbias_val(comp->dev,
2157 "qcom,micbias1-microvolt");
2158 vout_ctl_2 = wcd934x_get_micbias_val(comp->dev,
2159 "qcom,micbias2-microvolt");
2160 vout_ctl_3 = wcd934x_get_micbias_val(comp->dev,
2161 "qcom,micbias3-microvolt");
2162 vout_ctl_4 = wcd934x_get_micbias_val(comp->dev,
2163 "qcom,micbias4-microvolt");
2164
2165 snd_soc_component_update_bits(comp, WCD934X_ANA_MICB1,
2166 WCD934X_MICB_VAL_MASK, vout_ctl_1);
2167 snd_soc_component_update_bits(comp, WCD934X_ANA_MICB2,
2168 WCD934X_MICB_VAL_MASK, vout_ctl_2);
2169 snd_soc_component_update_bits(comp, WCD934X_ANA_MICB3,
2170 WCD934X_MICB_VAL_MASK, vout_ctl_3);
2171 snd_soc_component_update_bits(comp, WCD934X_ANA_MICB4,
2172 WCD934X_MICB_VAL_MASK, vout_ctl_4);
2173
2174 if (wcd->rate == WCD934X_MCLK_CLK_9P6MHZ)
2175 def_dmic_rate = WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ;
2176 else
2177 def_dmic_rate = WCD9XXX_DMIC_SAMPLE_RATE_4P096MHZ;
2178
2179 wcd->dmic_sample_rate = def_dmic_rate;
2180
2181 dmic_clk_drv = 0;
2182 snd_soc_component_update_bits(comp, WCD934X_TEST_DEBUG_PAD_DRVCTL_0,
2183 0x0C, dmic_clk_drv << 2);
2184
2185 return 0;
2186 }
2187
wcd934x_hw_init(struct wcd934x_codec * wcd)2188 static void wcd934x_hw_init(struct wcd934x_codec *wcd)
2189 {
2190 struct regmap *rm = wcd->regmap;
2191
2192 /* set SPKR rate to FS_2P4_3P072 */
2193 regmap_update_bits(rm, WCD934X_CDC_RX7_RX_PATH_CFG1, 0x08, 0x08);
2194 regmap_update_bits(rm, WCD934X_CDC_RX8_RX_PATH_CFG1, 0x08, 0x08);
2195
2196 /* Take DMICs out of reset */
2197 regmap_update_bits(rm, WCD934X_CPE_SS_DMIC_CFG, 0x80, 0x00);
2198 }
2199
wcd934x_comp_init(struct snd_soc_component * component)2200 static int wcd934x_comp_init(struct snd_soc_component *component)
2201 {
2202 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
2203
2204 wcd934x_hw_init(wcd);
2205 wcd934x_enable_efuse_sensing(wcd);
2206 wcd934x_get_version(wcd);
2207
2208 return 0;
2209 }
2210
wcd934x_slim_irq_handler(int irq,void * data)2211 static irqreturn_t wcd934x_slim_irq_handler(int irq, void *data)
2212 {
2213 struct wcd934x_codec *wcd = data;
2214 unsigned long status = 0;
2215 int i, j, port_id;
2216 unsigned int val, int_val = 0;
2217 irqreturn_t ret = IRQ_NONE;
2218 bool tx;
2219 unsigned short reg = 0;
2220
2221 for (i = WCD934X_SLIM_PGD_PORT_INT_STATUS_RX_0, j = 0;
2222 i <= WCD934X_SLIM_PGD_PORT_INT_STATUS_TX_1; i++, j++) {
2223 regmap_read(wcd->if_regmap, i, &val);
2224 status |= ((u32)val << (8 * j));
2225 }
2226
2227 for_each_set_bit(j, &status, 32) {
2228 tx = false;
2229 port_id = j;
2230
2231 if (j >= 16) {
2232 tx = true;
2233 port_id = j - 16;
2234 }
2235
2236 regmap_read(wcd->if_regmap,
2237 WCD934X_SLIM_PGD_PORT_INT_RX_SOURCE0 + j, &val);
2238 if (val) {
2239 if (!tx)
2240 reg = WCD934X_SLIM_PGD_PORT_INT_EN0 +
2241 (port_id / 8);
2242 else
2243 reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 +
2244 (port_id / 8);
2245 regmap_read(wcd->if_regmap, reg, &int_val);
2246 }
2247
2248 if (val & WCD934X_SLIM_IRQ_OVERFLOW)
2249 dev_err_ratelimited(wcd->dev,
2250 "overflow error on %s port %d, value %x\n",
2251 (tx ? "TX" : "RX"), port_id, val);
2252
2253 if (val & WCD934X_SLIM_IRQ_UNDERFLOW)
2254 dev_err_ratelimited(wcd->dev,
2255 "underflow error on %s port %d, value %x\n",
2256 (tx ? "TX" : "RX"), port_id, val);
2257
2258 if ((val & WCD934X_SLIM_IRQ_OVERFLOW) ||
2259 (val & WCD934X_SLIM_IRQ_UNDERFLOW)) {
2260 if (!tx)
2261 reg = WCD934X_SLIM_PGD_PORT_INT_EN0 +
2262 (port_id / 8);
2263 else
2264 reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 +
2265 (port_id / 8);
2266 regmap_read(
2267 wcd->if_regmap, reg, &int_val);
2268 if (int_val & (1 << (port_id % 8))) {
2269 int_val = int_val ^ (1 << (port_id % 8));
2270 regmap_write(wcd->if_regmap,
2271 reg, int_val);
2272 }
2273 }
2274
2275 if (val & WCD934X_SLIM_IRQ_PORT_CLOSED)
2276 dev_err_ratelimited(wcd->dev,
2277 "Port Closed %s port %d, value %x\n",
2278 (tx ? "TX" : "RX"), port_id, val);
2279
2280 regmap_write(wcd->if_regmap,
2281 WCD934X_SLIM_PGD_PORT_INT_CLR_RX_0 + (j / 8),
2282 BIT(j % 8));
2283 ret = IRQ_HANDLED;
2284 }
2285
2286 return ret;
2287 }
2288
wcd934x_comp_probe(struct snd_soc_component * component)2289 static int wcd934x_comp_probe(struct snd_soc_component *component)
2290 {
2291 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
2292 int i;
2293
2294 snd_soc_component_init_regmap(component, wcd->regmap);
2295 wcd->component = component;
2296
2297 /* Class-H Init*/
2298 wcd->clsh_ctrl = wcd_clsh_ctrl_alloc(component, wcd->version);
2299 if (IS_ERR(wcd->clsh_ctrl))
2300 return PTR_ERR(wcd->clsh_ctrl);
2301
2302 /* Default HPH Mode to Class-H Low HiFi */
2303 wcd->hph_mode = CLS_H_LOHIFI;
2304
2305 wcd934x_comp_init(component);
2306
2307 for (i = 0; i < NUM_CODEC_DAIS; i++)
2308 INIT_LIST_HEAD(&wcd->dai[i].slim_ch_list);
2309
2310 wcd934x_init_dmic(component);
2311 return 0;
2312 }
2313
wcd934x_comp_remove(struct snd_soc_component * comp)2314 static void wcd934x_comp_remove(struct snd_soc_component *comp)
2315 {
2316 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
2317
2318 wcd_clsh_ctrl_free(wcd->clsh_ctrl);
2319 }
2320
wcd934x_comp_set_sysclk(struct snd_soc_component * comp,int clk_id,int source,unsigned int freq,int dir)2321 static int wcd934x_comp_set_sysclk(struct snd_soc_component *comp,
2322 int clk_id, int source,
2323 unsigned int freq, int dir)
2324 {
2325 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
2326 int val = WCD934X_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ;
2327
2328 wcd->rate = freq;
2329
2330 if (wcd->rate == WCD934X_MCLK_CLK_12P288MHZ)
2331 val = WCD934X_CODEC_RPM_CLK_MCLK_CFG_12P288MHZ;
2332
2333 snd_soc_component_update_bits(comp, WCD934X_CODEC_RPM_CLK_MCLK_CFG,
2334 WCD934X_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
2335 val);
2336
2337 return clk_set_rate(wcd->extclk, freq);
2338 }
2339
get_iir_band_coeff(struct snd_soc_component * component,int iir_idx,int band_idx,int coeff_idx)2340 static uint32_t get_iir_band_coeff(struct snd_soc_component *component,
2341 int iir_idx, int band_idx, int coeff_idx)
2342 {
2343 u32 value = 0;
2344 int reg, b2_reg;
2345
2346 /* Address does not automatically update if reading */
2347 reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL + 16 * iir_idx;
2348 b2_reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL + 16 * iir_idx;
2349
2350 snd_soc_component_write(component, reg,
2351 ((band_idx * BAND_MAX + coeff_idx) *
2352 sizeof(uint32_t)) & 0x7F);
2353
2354 value |= snd_soc_component_read(component, b2_reg);
2355 snd_soc_component_write(component, reg,
2356 ((band_idx * BAND_MAX + coeff_idx)
2357 * sizeof(uint32_t) + 1) & 0x7F);
2358
2359 value |= (snd_soc_component_read(component, b2_reg) << 8);
2360 snd_soc_component_write(component, reg,
2361 ((band_idx * BAND_MAX + coeff_idx)
2362 * sizeof(uint32_t) + 2) & 0x7F);
2363
2364 value |= (snd_soc_component_read(component, b2_reg) << 16);
2365 snd_soc_component_write(component, reg,
2366 ((band_idx * BAND_MAX + coeff_idx)
2367 * sizeof(uint32_t) + 3) & 0x7F);
2368
2369 /* Mask bits top 2 bits since they are reserved */
2370 value |= (snd_soc_component_read(component, b2_reg) << 24);
2371 return value;
2372 }
2373
set_iir_band_coeff(struct snd_soc_component * component,int iir_idx,int band_idx,uint32_t value)2374 static void set_iir_band_coeff(struct snd_soc_component *component,
2375 int iir_idx, int band_idx, uint32_t value)
2376 {
2377 int reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL + 16 * iir_idx;
2378
2379 snd_soc_component_write(component, reg, (value & 0xFF));
2380 snd_soc_component_write(component, reg, (value >> 8) & 0xFF);
2381 snd_soc_component_write(component, reg, (value >> 16) & 0xFF);
2382 /* Mask top 2 bits, 7-8 are reserved */
2383 snd_soc_component_write(component, reg, (value >> 24) & 0x3F);
2384 }
2385
wcd934x_put_iir_band_audio_mixer(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2386 static int wcd934x_put_iir_band_audio_mixer(
2387 struct snd_kcontrol *kcontrol,
2388 struct snd_ctl_elem_value *ucontrol)
2389 {
2390 struct snd_soc_component *component =
2391 snd_soc_kcontrol_component(kcontrol);
2392 struct wcd_iir_filter_ctl *ctl =
2393 (struct wcd_iir_filter_ctl *)kcontrol->private_value;
2394 struct soc_bytes_ext *params = &ctl->bytes_ext;
2395 int iir_idx = ctl->iir_idx;
2396 int band_idx = ctl->band_idx;
2397 u32 coeff[BAND_MAX];
2398 int reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL + 16 * iir_idx;
2399
2400 memcpy(&coeff[0], ucontrol->value.bytes.data, params->max);
2401
2402 /* Mask top bit it is reserved */
2403 /* Updates addr automatically for each B2 write */
2404 snd_soc_component_write(component, reg, (band_idx * BAND_MAX *
2405 sizeof(uint32_t)) & 0x7F);
2406
2407 set_iir_band_coeff(component, iir_idx, band_idx, coeff[0]);
2408 set_iir_band_coeff(component, iir_idx, band_idx, coeff[1]);
2409 set_iir_band_coeff(component, iir_idx, band_idx, coeff[2]);
2410 set_iir_band_coeff(component, iir_idx, band_idx, coeff[3]);
2411 set_iir_band_coeff(component, iir_idx, band_idx, coeff[4]);
2412
2413 return 0;
2414 }
2415
wcd934x_get_iir_band_audio_mixer(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2416 static int wcd934x_get_iir_band_audio_mixer(struct snd_kcontrol *kcontrol,
2417 struct snd_ctl_elem_value *ucontrol)
2418 {
2419 struct snd_soc_component *component =
2420 snd_soc_kcontrol_component(kcontrol);
2421 struct wcd_iir_filter_ctl *ctl =
2422 (struct wcd_iir_filter_ctl *)kcontrol->private_value;
2423 struct soc_bytes_ext *params = &ctl->bytes_ext;
2424 int iir_idx = ctl->iir_idx;
2425 int band_idx = ctl->band_idx;
2426 u32 coeff[BAND_MAX];
2427
2428 coeff[0] = get_iir_band_coeff(component, iir_idx, band_idx, 0);
2429 coeff[1] = get_iir_band_coeff(component, iir_idx, band_idx, 1);
2430 coeff[2] = get_iir_band_coeff(component, iir_idx, band_idx, 2);
2431 coeff[3] = get_iir_band_coeff(component, iir_idx, band_idx, 3);
2432 coeff[4] = get_iir_band_coeff(component, iir_idx, band_idx, 4);
2433
2434 memcpy(ucontrol->value.bytes.data, &coeff[0], params->max);
2435
2436 return 0;
2437 }
2438
wcd934x_iir_filter_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * ucontrol)2439 static int wcd934x_iir_filter_info(struct snd_kcontrol *kcontrol,
2440 struct snd_ctl_elem_info *ucontrol)
2441 {
2442 struct wcd_iir_filter_ctl *ctl =
2443 (struct wcd_iir_filter_ctl *)kcontrol->private_value;
2444 struct soc_bytes_ext *params = &ctl->bytes_ext;
2445
2446 ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES;
2447 ucontrol->count = params->max;
2448
2449 return 0;
2450 }
2451
wcd934x_compander_get(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)2452 static int wcd934x_compander_get(struct snd_kcontrol *kc,
2453 struct snd_ctl_elem_value *ucontrol)
2454 {
2455 struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
2456 int comp = ((struct soc_mixer_control *)kc->private_value)->shift;
2457 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
2458
2459 ucontrol->value.integer.value[0] = wcd->comp_enabled[comp];
2460
2461 return 0;
2462 }
2463
wcd934x_compander_set(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)2464 static int wcd934x_compander_set(struct snd_kcontrol *kc,
2465 struct snd_ctl_elem_value *ucontrol)
2466 {
2467 struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
2468 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
2469 int comp = ((struct soc_mixer_control *)kc->private_value)->shift;
2470 int value = ucontrol->value.integer.value[0];
2471 int sel;
2472
2473 if (wcd->comp_enabled[comp] == value)
2474 return 0;
2475
2476 wcd->comp_enabled[comp] = value;
2477 sel = value ? WCD934X_HPH_GAIN_SRC_SEL_COMPANDER :
2478 WCD934X_HPH_GAIN_SRC_SEL_REGISTER;
2479
2480 /* Any specific register configuration for compander */
2481 switch (comp) {
2482 case COMPANDER_1:
2483 /* Set Gain Source Select based on compander enable/disable */
2484 snd_soc_component_update_bits(component, WCD934X_HPH_L_EN,
2485 WCD934X_HPH_GAIN_SRC_SEL_MASK,
2486 sel);
2487 break;
2488 case COMPANDER_2:
2489 snd_soc_component_update_bits(component, WCD934X_HPH_R_EN,
2490 WCD934X_HPH_GAIN_SRC_SEL_MASK,
2491 sel);
2492 break;
2493 case COMPANDER_3:
2494 case COMPANDER_4:
2495 case COMPANDER_7:
2496 case COMPANDER_8:
2497 break;
2498 default:
2499 return 0;
2500 }
2501
2502 return 1;
2503 }
2504
wcd934x_rx_hph_mode_get(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)2505 static int wcd934x_rx_hph_mode_get(struct snd_kcontrol *kc,
2506 struct snd_ctl_elem_value *ucontrol)
2507 {
2508 struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
2509 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
2510
2511 ucontrol->value.enumerated.item[0] = wcd->hph_mode;
2512
2513 return 0;
2514 }
2515
wcd934x_rx_hph_mode_put(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)2516 static int wcd934x_rx_hph_mode_put(struct snd_kcontrol *kc,
2517 struct snd_ctl_elem_value *ucontrol)
2518 {
2519 struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
2520 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
2521 u32 mode_val;
2522
2523 mode_val = ucontrol->value.enumerated.item[0];
2524
2525 if (mode_val == 0) {
2526 dev_err(wcd->dev, "Invalid HPH Mode, default to ClSH HiFi\n");
2527 mode_val = CLS_H_LOHIFI;
2528 }
2529 wcd->hph_mode = mode_val;
2530
2531 return 0;
2532 }
2533
slim_rx_mux_get(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)2534 static int slim_rx_mux_get(struct snd_kcontrol *kc,
2535 struct snd_ctl_elem_value *ucontrol)
2536 {
2537 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc);
2538 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc);
2539 struct wcd934x_codec *wcd = dev_get_drvdata(dapm->dev);
2540
2541 ucontrol->value.enumerated.item[0] = wcd->rx_port_value[w->shift];
2542
2543 return 0;
2544 }
2545
slim_rx_mux_to_dai_id(int mux)2546 static int slim_rx_mux_to_dai_id(int mux)
2547 {
2548 int aif_id;
2549
2550 switch (mux) {
2551 case 1:
2552 aif_id = AIF1_PB;
2553 break;
2554 case 2:
2555 aif_id = AIF2_PB;
2556 break;
2557 case 3:
2558 aif_id = AIF3_PB;
2559 break;
2560 case 4:
2561 aif_id = AIF4_PB;
2562 break;
2563 default:
2564 aif_id = -1;
2565 break;
2566 }
2567
2568 return aif_id;
2569 }
2570
slim_rx_mux_put(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)2571 static int slim_rx_mux_put(struct snd_kcontrol *kc,
2572 struct snd_ctl_elem_value *ucontrol)
2573 {
2574 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc);
2575 struct wcd934x_codec *wcd = dev_get_drvdata(w->dapm->dev);
2576 struct soc_enum *e = (struct soc_enum *)kc->private_value;
2577 struct snd_soc_dapm_update *update = NULL;
2578 struct wcd934x_slim_ch *ch, *c;
2579 u32 port_id = w->shift;
2580 bool found = false;
2581 int mux_idx;
2582 int prev_mux_idx = wcd->rx_port_value[port_id];
2583 int aif_id;
2584
2585 mux_idx = ucontrol->value.enumerated.item[0];
2586
2587 if (mux_idx == prev_mux_idx)
2588 return 0;
2589
2590 switch(mux_idx) {
2591 case 0:
2592 aif_id = slim_rx_mux_to_dai_id(prev_mux_idx);
2593 if (aif_id < 0)
2594 return 0;
2595
2596 list_for_each_entry_safe(ch, c, &wcd->dai[aif_id].slim_ch_list, list) {
2597 if (ch->port == port_id + WCD934X_RX_START) {
2598 found = true;
2599 list_del_init(&ch->list);
2600 break;
2601 }
2602 }
2603 if (!found)
2604 return 0;
2605
2606 break;
2607 case 1 ... 4:
2608 aif_id = slim_rx_mux_to_dai_id(mux_idx);
2609 if (aif_id < 0)
2610 return 0;
2611
2612 if (list_empty(&wcd->rx_chs[port_id].list)) {
2613 list_add_tail(&wcd->rx_chs[port_id].list,
2614 &wcd->dai[aif_id].slim_ch_list);
2615 } else {
2616 dev_err(wcd->dev ,"SLIM_RX%d PORT is busy\n", port_id);
2617 return 0;
2618 }
2619 break;
2620
2621 default:
2622 dev_err(wcd->dev, "Unknown AIF %d\n", mux_idx);
2623 goto err;
2624 }
2625
2626 wcd->rx_port_value[port_id] = mux_idx;
2627 snd_soc_dapm_mux_update_power(w->dapm, kc, wcd->rx_port_value[port_id],
2628 e, update);
2629
2630 return 1;
2631 err:
2632 return -EINVAL;
2633 }
2634
wcd934x_int_dem_inp_mux_put(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)2635 static int wcd934x_int_dem_inp_mux_put(struct snd_kcontrol *kc,
2636 struct snd_ctl_elem_value *ucontrol)
2637 {
2638 struct soc_enum *e = (struct soc_enum *)kc->private_value;
2639 struct snd_soc_component *component;
2640 int reg, val, ret;
2641
2642 component = snd_soc_dapm_kcontrol_component(kc);
2643 val = ucontrol->value.enumerated.item[0];
2644 if (e->reg == WCD934X_CDC_RX0_RX_PATH_SEC0)
2645 reg = WCD934X_CDC_RX0_RX_PATH_CFG0;
2646 else if (e->reg == WCD934X_CDC_RX1_RX_PATH_SEC0)
2647 reg = WCD934X_CDC_RX1_RX_PATH_CFG0;
2648 else if (e->reg == WCD934X_CDC_RX2_RX_PATH_SEC0)
2649 reg = WCD934X_CDC_RX2_RX_PATH_CFG0;
2650 else
2651 return -EINVAL;
2652
2653 /* Set Look Ahead Delay */
2654 if (val)
2655 snd_soc_component_update_bits(component, reg,
2656 WCD934X_RX_DLY_ZN_EN_MASK,
2657 WCD934X_RX_DLY_ZN_ENABLE);
2658 else
2659 snd_soc_component_update_bits(component, reg,
2660 WCD934X_RX_DLY_ZN_EN_MASK,
2661 WCD934X_RX_DLY_ZN_DISABLE);
2662
2663 ret = snd_soc_dapm_put_enum_double(kc, ucontrol);
2664
2665 return ret;
2666 }
2667
wcd934x_dec_enum_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2668 static int wcd934x_dec_enum_put(struct snd_kcontrol *kcontrol,
2669 struct snd_ctl_elem_value *ucontrol)
2670 {
2671 struct snd_soc_component *comp;
2672 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
2673 unsigned int val;
2674 u16 mic_sel_reg = 0;
2675 u8 mic_sel;
2676
2677 comp = snd_soc_dapm_kcontrol_component(kcontrol);
2678
2679 val = ucontrol->value.enumerated.item[0];
2680 if (val > e->items - 1)
2681 return -EINVAL;
2682
2683 switch (e->reg) {
2684 case WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1:
2685 if (e->shift_l == 0)
2686 mic_sel_reg = WCD934X_CDC_TX0_TX_PATH_CFG0;
2687 else if (e->shift_l == 2)
2688 mic_sel_reg = WCD934X_CDC_TX4_TX_PATH_CFG0;
2689 else if (e->shift_l == 4)
2690 mic_sel_reg = WCD934X_CDC_TX8_TX_PATH_CFG0;
2691 break;
2692 case WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1:
2693 if (e->shift_l == 0)
2694 mic_sel_reg = WCD934X_CDC_TX1_TX_PATH_CFG0;
2695 else if (e->shift_l == 2)
2696 mic_sel_reg = WCD934X_CDC_TX5_TX_PATH_CFG0;
2697 break;
2698 case WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1:
2699 if (e->shift_l == 0)
2700 mic_sel_reg = WCD934X_CDC_TX2_TX_PATH_CFG0;
2701 else if (e->shift_l == 2)
2702 mic_sel_reg = WCD934X_CDC_TX6_TX_PATH_CFG0;
2703 break;
2704 case WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1:
2705 if (e->shift_l == 0)
2706 mic_sel_reg = WCD934X_CDC_TX3_TX_PATH_CFG0;
2707 else if (e->shift_l == 2)
2708 mic_sel_reg = WCD934X_CDC_TX7_TX_PATH_CFG0;
2709 break;
2710 default:
2711 dev_err(comp->dev, "%s: e->reg: 0x%x not expected\n",
2712 __func__, e->reg);
2713 return -EINVAL;
2714 }
2715
2716 /* ADC: 0, DMIC: 1 */
2717 mic_sel = val ? 0x0 : 0x1;
2718 if (mic_sel_reg)
2719 snd_soc_component_update_bits(comp, mic_sel_reg, BIT(7),
2720 mic_sel << 7);
2721
2722 return snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
2723 }
2724
2725 static const struct snd_kcontrol_new rx_int0_2_mux =
2726 SOC_DAPM_ENUM("RX INT0_2 MUX Mux", rx_int0_2_mux_chain_enum);
2727
2728 static const struct snd_kcontrol_new rx_int1_2_mux =
2729 SOC_DAPM_ENUM("RX INT1_2 MUX Mux", rx_int1_2_mux_chain_enum);
2730
2731 static const struct snd_kcontrol_new rx_int2_2_mux =
2732 SOC_DAPM_ENUM("RX INT2_2 MUX Mux", rx_int2_2_mux_chain_enum);
2733
2734 static const struct snd_kcontrol_new rx_int3_2_mux =
2735 SOC_DAPM_ENUM("RX INT3_2 MUX Mux", rx_int3_2_mux_chain_enum);
2736
2737 static const struct snd_kcontrol_new rx_int4_2_mux =
2738 SOC_DAPM_ENUM("RX INT4_2 MUX Mux", rx_int4_2_mux_chain_enum);
2739
2740 static const struct snd_kcontrol_new rx_int7_2_mux =
2741 SOC_DAPM_ENUM("RX INT7_2 MUX Mux", rx_int7_2_mux_chain_enum);
2742
2743 static const struct snd_kcontrol_new rx_int8_2_mux =
2744 SOC_DAPM_ENUM("RX INT8_2 MUX Mux", rx_int8_2_mux_chain_enum);
2745
2746 static const struct snd_kcontrol_new rx_int0_1_mix_inp0_mux =
2747 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP0 Mux", rx_int0_1_mix_inp0_chain_enum);
2748
2749 static const struct snd_kcontrol_new rx_int0_1_mix_inp1_mux =
2750 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP1 Mux", rx_int0_1_mix_inp1_chain_enum);
2751
2752 static const struct snd_kcontrol_new rx_int0_1_mix_inp2_mux =
2753 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP2 Mux", rx_int0_1_mix_inp2_chain_enum);
2754
2755 static const struct snd_kcontrol_new rx_int1_1_mix_inp0_mux =
2756 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP0 Mux", rx_int1_1_mix_inp0_chain_enum);
2757
2758 static const struct snd_kcontrol_new rx_int1_1_mix_inp1_mux =
2759 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP1 Mux", rx_int1_1_mix_inp1_chain_enum);
2760
2761 static const struct snd_kcontrol_new rx_int1_1_mix_inp2_mux =
2762 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP2 Mux", rx_int1_1_mix_inp2_chain_enum);
2763
2764 static const struct snd_kcontrol_new rx_int2_1_mix_inp0_mux =
2765 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP0 Mux", rx_int2_1_mix_inp0_chain_enum);
2766
2767 static const struct snd_kcontrol_new rx_int2_1_mix_inp1_mux =
2768 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP1 Mux", rx_int2_1_mix_inp1_chain_enum);
2769
2770 static const struct snd_kcontrol_new rx_int2_1_mix_inp2_mux =
2771 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP2 Mux", rx_int2_1_mix_inp2_chain_enum);
2772
2773 static const struct snd_kcontrol_new rx_int3_1_mix_inp0_mux =
2774 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP0 Mux", rx_int3_1_mix_inp0_chain_enum);
2775
2776 static const struct snd_kcontrol_new rx_int3_1_mix_inp1_mux =
2777 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP1 Mux", rx_int3_1_mix_inp1_chain_enum);
2778
2779 static const struct snd_kcontrol_new rx_int3_1_mix_inp2_mux =
2780 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP2 Mux", rx_int3_1_mix_inp2_chain_enum);
2781
2782 static const struct snd_kcontrol_new rx_int4_1_mix_inp0_mux =
2783 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP0 Mux", rx_int4_1_mix_inp0_chain_enum);
2784
2785 static const struct snd_kcontrol_new rx_int4_1_mix_inp1_mux =
2786 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP1 Mux", rx_int4_1_mix_inp1_chain_enum);
2787
2788 static const struct snd_kcontrol_new rx_int4_1_mix_inp2_mux =
2789 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP2 Mux", rx_int4_1_mix_inp2_chain_enum);
2790
2791 static const struct snd_kcontrol_new rx_int7_1_mix_inp0_mux =
2792 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP0 Mux", rx_int7_1_mix_inp0_chain_enum);
2793
2794 static const struct snd_kcontrol_new rx_int7_1_mix_inp1_mux =
2795 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP1 Mux", rx_int7_1_mix_inp1_chain_enum);
2796
2797 static const struct snd_kcontrol_new rx_int7_1_mix_inp2_mux =
2798 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP2 Mux", rx_int7_1_mix_inp2_chain_enum);
2799
2800 static const struct snd_kcontrol_new rx_int8_1_mix_inp0_mux =
2801 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP0 Mux", rx_int8_1_mix_inp0_chain_enum);
2802
2803 static const struct snd_kcontrol_new rx_int8_1_mix_inp1_mux =
2804 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP1 Mux", rx_int8_1_mix_inp1_chain_enum);
2805
2806 static const struct snd_kcontrol_new rx_int8_1_mix_inp2_mux =
2807 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP2 Mux", rx_int8_1_mix_inp2_chain_enum);
2808
2809 static const struct snd_kcontrol_new rx_int0_mix2_inp_mux =
2810 SOC_DAPM_ENUM("RX INT0 MIX2 INP Mux", rx_int0_mix2_inp_mux_enum);
2811
2812 static const struct snd_kcontrol_new rx_int1_mix2_inp_mux =
2813 SOC_DAPM_ENUM("RX INT1 MIX2 INP Mux", rx_int1_mix2_inp_mux_enum);
2814
2815 static const struct snd_kcontrol_new rx_int2_mix2_inp_mux =
2816 SOC_DAPM_ENUM("RX INT2 MIX2 INP Mux", rx_int2_mix2_inp_mux_enum);
2817
2818 static const struct snd_kcontrol_new rx_int3_mix2_inp_mux =
2819 SOC_DAPM_ENUM("RX INT3 MIX2 INP Mux", rx_int3_mix2_inp_mux_enum);
2820
2821 static const struct snd_kcontrol_new rx_int4_mix2_inp_mux =
2822 SOC_DAPM_ENUM("RX INT4 MIX2 INP Mux", rx_int4_mix2_inp_mux_enum);
2823
2824 static const struct snd_kcontrol_new rx_int7_mix2_inp_mux =
2825 SOC_DAPM_ENUM("RX INT7 MIX2 INP Mux", rx_int7_mix2_inp_mux_enum);
2826
2827 static const struct snd_kcontrol_new iir0_inp0_mux =
2828 SOC_DAPM_ENUM("IIR0 INP0 Mux", iir0_inp0_mux_enum);
2829 static const struct snd_kcontrol_new iir0_inp1_mux =
2830 SOC_DAPM_ENUM("IIR0 INP1 Mux", iir0_inp1_mux_enum);
2831 static const struct snd_kcontrol_new iir0_inp2_mux =
2832 SOC_DAPM_ENUM("IIR0 INP2 Mux", iir0_inp2_mux_enum);
2833 static const struct snd_kcontrol_new iir0_inp3_mux =
2834 SOC_DAPM_ENUM("IIR0 INP3 Mux", iir0_inp3_mux_enum);
2835
2836 static const struct snd_kcontrol_new iir1_inp0_mux =
2837 SOC_DAPM_ENUM("IIR1 INP0 Mux", iir1_inp0_mux_enum);
2838 static const struct snd_kcontrol_new iir1_inp1_mux =
2839 SOC_DAPM_ENUM("IIR1 INP1 Mux", iir1_inp1_mux_enum);
2840 static const struct snd_kcontrol_new iir1_inp2_mux =
2841 SOC_DAPM_ENUM("IIR1 INP2 Mux", iir1_inp2_mux_enum);
2842 static const struct snd_kcontrol_new iir1_inp3_mux =
2843 SOC_DAPM_ENUM("IIR1 INP3 Mux", iir1_inp3_mux_enum);
2844
2845 static const struct snd_kcontrol_new slim_rx_mux[WCD934X_RX_MAX] = {
2846 SOC_DAPM_ENUM_EXT("SLIM RX0 Mux", slim_rx_mux_enum,
2847 slim_rx_mux_get, slim_rx_mux_put),
2848 SOC_DAPM_ENUM_EXT("SLIM RX1 Mux", slim_rx_mux_enum,
2849 slim_rx_mux_get, slim_rx_mux_put),
2850 SOC_DAPM_ENUM_EXT("SLIM RX2 Mux", slim_rx_mux_enum,
2851 slim_rx_mux_get, slim_rx_mux_put),
2852 SOC_DAPM_ENUM_EXT("SLIM RX3 Mux", slim_rx_mux_enum,
2853 slim_rx_mux_get, slim_rx_mux_put),
2854 SOC_DAPM_ENUM_EXT("SLIM RX4 Mux", slim_rx_mux_enum,
2855 slim_rx_mux_get, slim_rx_mux_put),
2856 SOC_DAPM_ENUM_EXT("SLIM RX5 Mux", slim_rx_mux_enum,
2857 slim_rx_mux_get, slim_rx_mux_put),
2858 SOC_DAPM_ENUM_EXT("SLIM RX6 Mux", slim_rx_mux_enum,
2859 slim_rx_mux_get, slim_rx_mux_put),
2860 SOC_DAPM_ENUM_EXT("SLIM RX7 Mux", slim_rx_mux_enum,
2861 slim_rx_mux_get, slim_rx_mux_put),
2862 };
2863
2864 static const struct snd_kcontrol_new rx_int1_asrc_switch[] = {
2865 SOC_DAPM_SINGLE("HPHL Switch", SND_SOC_NOPM, 0, 1, 0),
2866 };
2867
2868 static const struct snd_kcontrol_new rx_int2_asrc_switch[] = {
2869 SOC_DAPM_SINGLE("HPHR Switch", SND_SOC_NOPM, 0, 1, 0),
2870 };
2871
2872 static const struct snd_kcontrol_new rx_int3_asrc_switch[] = {
2873 SOC_DAPM_SINGLE("LO1 Switch", SND_SOC_NOPM, 0, 1, 0),
2874 };
2875
2876 static const struct snd_kcontrol_new rx_int4_asrc_switch[] = {
2877 SOC_DAPM_SINGLE("LO2 Switch", SND_SOC_NOPM, 0, 1, 0),
2878 };
2879
2880 static const struct snd_kcontrol_new rx_int0_dem_inp_mux =
2881 SOC_DAPM_ENUM_EXT("RX INT0 DEM MUX Mux", rx_int0_dem_inp_mux_enum,
2882 snd_soc_dapm_get_enum_double,
2883 wcd934x_int_dem_inp_mux_put);
2884
2885 static const struct snd_kcontrol_new rx_int1_dem_inp_mux =
2886 SOC_DAPM_ENUM_EXT("RX INT1 DEM MUX Mux", rx_int1_dem_inp_mux_enum,
2887 snd_soc_dapm_get_enum_double,
2888 wcd934x_int_dem_inp_mux_put);
2889
2890 static const struct snd_kcontrol_new rx_int2_dem_inp_mux =
2891 SOC_DAPM_ENUM_EXT("RX INT2 DEM MUX Mux", rx_int2_dem_inp_mux_enum,
2892 snd_soc_dapm_get_enum_double,
2893 wcd934x_int_dem_inp_mux_put);
2894
2895 static const struct snd_kcontrol_new rx_int0_1_interp_mux =
2896 SOC_DAPM_ENUM("RX INT0_1 INTERP Mux", rx_int0_1_interp_mux_enum);
2897
2898 static const struct snd_kcontrol_new rx_int1_1_interp_mux =
2899 SOC_DAPM_ENUM("RX INT1_1 INTERP Mux", rx_int1_1_interp_mux_enum);
2900
2901 static const struct snd_kcontrol_new rx_int2_1_interp_mux =
2902 SOC_DAPM_ENUM("RX INT2_1 INTERP Mux", rx_int2_1_interp_mux_enum);
2903
2904 static const struct snd_kcontrol_new rx_int3_1_interp_mux =
2905 SOC_DAPM_ENUM("RX INT3_1 INTERP Mux", rx_int3_1_interp_mux_enum);
2906
2907 static const struct snd_kcontrol_new rx_int4_1_interp_mux =
2908 SOC_DAPM_ENUM("RX INT4_1 INTERP Mux", rx_int4_1_interp_mux_enum);
2909
2910 static const struct snd_kcontrol_new rx_int7_1_interp_mux =
2911 SOC_DAPM_ENUM("RX INT7_1 INTERP Mux", rx_int7_1_interp_mux_enum);
2912
2913 static const struct snd_kcontrol_new rx_int8_1_interp_mux =
2914 SOC_DAPM_ENUM("RX INT8_1 INTERP Mux", rx_int8_1_interp_mux_enum);
2915
2916 static const struct snd_kcontrol_new rx_int0_2_interp_mux =
2917 SOC_DAPM_ENUM("RX INT0_2 INTERP Mux", rx_int0_2_interp_mux_enum);
2918
2919 static const struct snd_kcontrol_new rx_int1_2_interp_mux =
2920 SOC_DAPM_ENUM("RX INT1_2 INTERP Mux", rx_int1_2_interp_mux_enum);
2921
2922 static const struct snd_kcontrol_new rx_int2_2_interp_mux =
2923 SOC_DAPM_ENUM("RX INT2_2 INTERP Mux", rx_int2_2_interp_mux_enum);
2924
2925 static const struct snd_kcontrol_new rx_int3_2_interp_mux =
2926 SOC_DAPM_ENUM("RX INT3_2 INTERP Mux", rx_int3_2_interp_mux_enum);
2927
2928 static const struct snd_kcontrol_new rx_int4_2_interp_mux =
2929 SOC_DAPM_ENUM("RX INT4_2 INTERP Mux", rx_int4_2_interp_mux_enum);
2930
2931 static const struct snd_kcontrol_new rx_int7_2_interp_mux =
2932 SOC_DAPM_ENUM("RX INT7_2 INTERP Mux", rx_int7_2_interp_mux_enum);
2933
2934 static const struct snd_kcontrol_new rx_int8_2_interp_mux =
2935 SOC_DAPM_ENUM("RX INT8_2 INTERP Mux", rx_int8_2_interp_mux_enum);
2936
2937 static const struct snd_kcontrol_new tx_dmic_mux0 =
2938 SOC_DAPM_ENUM("DMIC MUX0 Mux", tx_dmic_mux0_enum);
2939
2940 static const struct snd_kcontrol_new tx_dmic_mux1 =
2941 SOC_DAPM_ENUM("DMIC MUX1 Mux", tx_dmic_mux1_enum);
2942
2943 static const struct snd_kcontrol_new tx_dmic_mux2 =
2944 SOC_DAPM_ENUM("DMIC MUX2 Mux", tx_dmic_mux2_enum);
2945
2946 static const struct snd_kcontrol_new tx_dmic_mux3 =
2947 SOC_DAPM_ENUM("DMIC MUX3 Mux", tx_dmic_mux3_enum);
2948
2949 static const struct snd_kcontrol_new tx_dmic_mux4 =
2950 SOC_DAPM_ENUM("DMIC MUX4 Mux", tx_dmic_mux4_enum);
2951
2952 static const struct snd_kcontrol_new tx_dmic_mux5 =
2953 SOC_DAPM_ENUM("DMIC MUX5 Mux", tx_dmic_mux5_enum);
2954
2955 static const struct snd_kcontrol_new tx_dmic_mux6 =
2956 SOC_DAPM_ENUM("DMIC MUX6 Mux", tx_dmic_mux6_enum);
2957
2958 static const struct snd_kcontrol_new tx_dmic_mux7 =
2959 SOC_DAPM_ENUM("DMIC MUX7 Mux", tx_dmic_mux7_enum);
2960
2961 static const struct snd_kcontrol_new tx_dmic_mux8 =
2962 SOC_DAPM_ENUM("DMIC MUX8 Mux", tx_dmic_mux8_enum);
2963
2964 static const struct snd_kcontrol_new tx_amic_mux0 =
2965 SOC_DAPM_ENUM("AMIC MUX0 Mux", tx_amic_mux0_enum);
2966
2967 static const struct snd_kcontrol_new tx_amic_mux1 =
2968 SOC_DAPM_ENUM("AMIC MUX1 Mux", tx_amic_mux1_enum);
2969
2970 static const struct snd_kcontrol_new tx_amic_mux2 =
2971 SOC_DAPM_ENUM("AMIC MUX2 Mux", tx_amic_mux2_enum);
2972
2973 static const struct snd_kcontrol_new tx_amic_mux3 =
2974 SOC_DAPM_ENUM("AMIC MUX3 Mux", tx_amic_mux3_enum);
2975
2976 static const struct snd_kcontrol_new tx_amic_mux4 =
2977 SOC_DAPM_ENUM("AMIC MUX4 Mux", tx_amic_mux4_enum);
2978
2979 static const struct snd_kcontrol_new tx_amic_mux5 =
2980 SOC_DAPM_ENUM("AMIC MUX5 Mux", tx_amic_mux5_enum);
2981
2982 static const struct snd_kcontrol_new tx_amic_mux6 =
2983 SOC_DAPM_ENUM("AMIC MUX6 Mux", tx_amic_mux6_enum);
2984
2985 static const struct snd_kcontrol_new tx_amic_mux7 =
2986 SOC_DAPM_ENUM("AMIC MUX7 Mux", tx_amic_mux7_enum);
2987
2988 static const struct snd_kcontrol_new tx_amic_mux8 =
2989 SOC_DAPM_ENUM("AMIC MUX8 Mux", tx_amic_mux8_enum);
2990
2991 static const struct snd_kcontrol_new tx_amic4_5 =
2992 SOC_DAPM_ENUM("AMIC4_5 SEL Mux", tx_amic4_5_enum);
2993
2994 static const struct snd_kcontrol_new tx_adc_mux0_mux =
2995 SOC_DAPM_ENUM_EXT("ADC MUX0 Mux", tx_adc_mux0_enum,
2996 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
2997 static const struct snd_kcontrol_new tx_adc_mux1_mux =
2998 SOC_DAPM_ENUM_EXT("ADC MUX1 Mux", tx_adc_mux1_enum,
2999 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3000 static const struct snd_kcontrol_new tx_adc_mux2_mux =
3001 SOC_DAPM_ENUM_EXT("ADC MUX2 Mux", tx_adc_mux2_enum,
3002 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3003 static const struct snd_kcontrol_new tx_adc_mux3_mux =
3004 SOC_DAPM_ENUM_EXT("ADC MUX3 Mux", tx_adc_mux3_enum,
3005 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3006 static const struct snd_kcontrol_new tx_adc_mux4_mux =
3007 SOC_DAPM_ENUM_EXT("ADC MUX4 Mux", tx_adc_mux4_enum,
3008 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3009 static const struct snd_kcontrol_new tx_adc_mux5_mux =
3010 SOC_DAPM_ENUM_EXT("ADC MUX5 Mux", tx_adc_mux5_enum,
3011 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3012 static const struct snd_kcontrol_new tx_adc_mux6_mux =
3013 SOC_DAPM_ENUM_EXT("ADC MUX6 Mux", tx_adc_mux6_enum,
3014 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3015 static const struct snd_kcontrol_new tx_adc_mux7_mux =
3016 SOC_DAPM_ENUM_EXT("ADC MUX7 Mux", tx_adc_mux7_enum,
3017 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3018 static const struct snd_kcontrol_new tx_adc_mux8_mux =
3019 SOC_DAPM_ENUM_EXT("ADC MUX8 Mux", tx_adc_mux8_enum,
3020 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3021
3022 static const struct snd_kcontrol_new cdc_if_tx0_mux =
3023 SOC_DAPM_ENUM("CDC_IF TX0 MUX Mux", cdc_if_tx0_mux_enum);
3024 static const struct snd_kcontrol_new cdc_if_tx1_mux =
3025 SOC_DAPM_ENUM("CDC_IF TX1 MUX Mux", cdc_if_tx1_mux_enum);
3026 static const struct snd_kcontrol_new cdc_if_tx2_mux =
3027 SOC_DAPM_ENUM("CDC_IF TX2 MUX Mux", cdc_if_tx2_mux_enum);
3028 static const struct snd_kcontrol_new cdc_if_tx3_mux =
3029 SOC_DAPM_ENUM("CDC_IF TX3 MUX Mux", cdc_if_tx3_mux_enum);
3030 static const struct snd_kcontrol_new cdc_if_tx4_mux =
3031 SOC_DAPM_ENUM("CDC_IF TX4 MUX Mux", cdc_if_tx4_mux_enum);
3032 static const struct snd_kcontrol_new cdc_if_tx5_mux =
3033 SOC_DAPM_ENUM("CDC_IF TX5 MUX Mux", cdc_if_tx5_mux_enum);
3034 static const struct snd_kcontrol_new cdc_if_tx6_mux =
3035 SOC_DAPM_ENUM("CDC_IF TX6 MUX Mux", cdc_if_tx6_mux_enum);
3036 static const struct snd_kcontrol_new cdc_if_tx7_mux =
3037 SOC_DAPM_ENUM("CDC_IF TX7 MUX Mux", cdc_if_tx7_mux_enum);
3038 static const struct snd_kcontrol_new cdc_if_tx8_mux =
3039 SOC_DAPM_ENUM("CDC_IF TX8 MUX Mux", cdc_if_tx8_mux_enum);
3040 static const struct snd_kcontrol_new cdc_if_tx9_mux =
3041 SOC_DAPM_ENUM("CDC_IF TX9 MUX Mux", cdc_if_tx9_mux_enum);
3042 static const struct snd_kcontrol_new cdc_if_tx10_mux =
3043 SOC_DAPM_ENUM("CDC_IF TX10 MUX Mux", cdc_if_tx10_mux_enum);
3044 static const struct snd_kcontrol_new cdc_if_tx11_mux =
3045 SOC_DAPM_ENUM("CDC_IF TX11 MUX Mux", cdc_if_tx11_mux_enum);
3046 static const struct snd_kcontrol_new cdc_if_tx11_inp1_mux =
3047 SOC_DAPM_ENUM("CDC_IF TX11 INP1 MUX Mux", cdc_if_tx11_inp1_mux_enum);
3048 static const struct snd_kcontrol_new cdc_if_tx13_mux =
3049 SOC_DAPM_ENUM("CDC_IF TX13 MUX Mux", cdc_if_tx13_mux_enum);
3050 static const struct snd_kcontrol_new cdc_if_tx13_inp1_mux =
3051 SOC_DAPM_ENUM("CDC_IF TX13 INP1 MUX Mux", cdc_if_tx13_inp1_mux_enum);
3052
slim_tx_mixer_get(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)3053 static int slim_tx_mixer_get(struct snd_kcontrol *kc,
3054 struct snd_ctl_elem_value *ucontrol)
3055 {
3056 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc);
3057 struct wcd934x_codec *wcd = dev_get_drvdata(dapm->dev);
3058 struct soc_mixer_control *mixer =
3059 (struct soc_mixer_control *)kc->private_value;
3060 int port_id = mixer->shift;
3061
3062 ucontrol->value.integer.value[0] = wcd->tx_port_value[port_id];
3063
3064 return 0;
3065 }
3066
slim_tx_mixer_put(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)3067 static int slim_tx_mixer_put(struct snd_kcontrol *kc,
3068 struct snd_ctl_elem_value *ucontrol)
3069 {
3070 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kc);
3071 struct wcd934x_codec *wcd = dev_get_drvdata(widget->dapm->dev);
3072 struct snd_soc_dapm_update *update = NULL;
3073 struct soc_mixer_control *mixer =
3074 (struct soc_mixer_control *)kc->private_value;
3075 int enable = ucontrol->value.integer.value[0];
3076 struct wcd934x_slim_ch *ch, *c;
3077 int dai_id = widget->shift;
3078 int port_id = mixer->shift;
3079
3080 /* only add to the list if value not set */
3081 if (enable == wcd->tx_port_value[port_id])
3082 return 0;
3083
3084 if (enable) {
3085 if (list_empty(&wcd->tx_chs[port_id].list)) {
3086 list_add_tail(&wcd->tx_chs[port_id].list,
3087 &wcd->dai[dai_id].slim_ch_list);
3088 } else {
3089 dev_err(wcd->dev ,"SLIM_TX%d PORT is busy\n", port_id);
3090 return 0;
3091 }
3092 } else {
3093 bool found = false;
3094
3095 list_for_each_entry_safe(ch, c, &wcd->dai[dai_id].slim_ch_list, list) {
3096 if (ch->port == port_id) {
3097 found = true;
3098 list_del_init(&wcd->tx_chs[port_id].list);
3099 break;
3100 }
3101 }
3102 if (!found)
3103 return 0;
3104 }
3105
3106 wcd->tx_port_value[port_id] = enable;
3107 snd_soc_dapm_mixer_update_power(widget->dapm, kc, enable, update);
3108
3109 return 1;
3110 }
3111
3112 static const struct snd_kcontrol_new aif1_slim_cap_mixer[] = {
3113 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0,
3114 slim_tx_mixer_get, slim_tx_mixer_put),
3115 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0,
3116 slim_tx_mixer_get, slim_tx_mixer_put),
3117 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0,
3118 slim_tx_mixer_get, slim_tx_mixer_put),
3119 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0,
3120 slim_tx_mixer_get, slim_tx_mixer_put),
3121 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0,
3122 slim_tx_mixer_get, slim_tx_mixer_put),
3123 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0,
3124 slim_tx_mixer_get, slim_tx_mixer_put),
3125 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0,
3126 slim_tx_mixer_get, slim_tx_mixer_put),
3127 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0,
3128 slim_tx_mixer_get, slim_tx_mixer_put),
3129 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0,
3130 slim_tx_mixer_get, slim_tx_mixer_put),
3131 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0,
3132 slim_tx_mixer_get, slim_tx_mixer_put),
3133 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0,
3134 slim_tx_mixer_get, slim_tx_mixer_put),
3135 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0,
3136 slim_tx_mixer_get, slim_tx_mixer_put),
3137 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0,
3138 slim_tx_mixer_get, slim_tx_mixer_put),
3139 };
3140
3141 static const struct snd_kcontrol_new aif2_slim_cap_mixer[] = {
3142 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0,
3143 slim_tx_mixer_get, slim_tx_mixer_put),
3144 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0,
3145 slim_tx_mixer_get, slim_tx_mixer_put),
3146 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0,
3147 slim_tx_mixer_get, slim_tx_mixer_put),
3148 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0,
3149 slim_tx_mixer_get, slim_tx_mixer_put),
3150 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0,
3151 slim_tx_mixer_get, slim_tx_mixer_put),
3152 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0,
3153 slim_tx_mixer_get, slim_tx_mixer_put),
3154 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0,
3155 slim_tx_mixer_get, slim_tx_mixer_put),
3156 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0,
3157 slim_tx_mixer_get, slim_tx_mixer_put),
3158 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0,
3159 slim_tx_mixer_get, slim_tx_mixer_put),
3160 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0,
3161 slim_tx_mixer_get, slim_tx_mixer_put),
3162 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0,
3163 slim_tx_mixer_get, slim_tx_mixer_put),
3164 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0,
3165 slim_tx_mixer_get, slim_tx_mixer_put),
3166 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0,
3167 slim_tx_mixer_get, slim_tx_mixer_put),
3168 };
3169
3170 static const struct snd_kcontrol_new aif3_slim_cap_mixer[] = {
3171 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0,
3172 slim_tx_mixer_get, slim_tx_mixer_put),
3173 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0,
3174 slim_tx_mixer_get, slim_tx_mixer_put),
3175 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0,
3176 slim_tx_mixer_get, slim_tx_mixer_put),
3177 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0,
3178 slim_tx_mixer_get, slim_tx_mixer_put),
3179 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0,
3180 slim_tx_mixer_get, slim_tx_mixer_put),
3181 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0,
3182 slim_tx_mixer_get, slim_tx_mixer_put),
3183 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0,
3184 slim_tx_mixer_get, slim_tx_mixer_put),
3185 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0,
3186 slim_tx_mixer_get, slim_tx_mixer_put),
3187 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0,
3188 slim_tx_mixer_get, slim_tx_mixer_put),
3189 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0,
3190 slim_tx_mixer_get, slim_tx_mixer_put),
3191 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0,
3192 slim_tx_mixer_get, slim_tx_mixer_put),
3193 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0,
3194 slim_tx_mixer_get, slim_tx_mixer_put),
3195 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0,
3196 slim_tx_mixer_get, slim_tx_mixer_put),
3197 };
3198
3199 static const struct snd_kcontrol_new wcd934x_snd_controls[] = {
3200 /* Gain Controls */
3201 SOC_SINGLE_TLV("EAR PA Volume", WCD934X_ANA_EAR, 4, 4, 1, ear_pa_gain),
3202 SOC_SINGLE_TLV("HPHL Volume", WCD934X_HPH_L_EN, 0, 24, 1, line_gain),
3203 SOC_SINGLE_TLV("HPHR Volume", WCD934X_HPH_R_EN, 0, 24, 1, line_gain),
3204 SOC_SINGLE_TLV("LINEOUT1 Volume", WCD934X_DIFF_LO_LO1_COMPANDER,
3205 3, 16, 1, line_gain),
3206 SOC_SINGLE_TLV("LINEOUT2 Volume", WCD934X_DIFF_LO_LO2_COMPANDER,
3207 3, 16, 1, line_gain),
3208
3209 SOC_SINGLE_TLV("ADC1 Volume", WCD934X_ANA_AMIC1, 0, 20, 0, analog_gain),
3210 SOC_SINGLE_TLV("ADC2 Volume", WCD934X_ANA_AMIC2, 0, 20, 0, analog_gain),
3211 SOC_SINGLE_TLV("ADC3 Volume", WCD934X_ANA_AMIC3, 0, 20, 0, analog_gain),
3212 SOC_SINGLE_TLV("ADC4 Volume", WCD934X_ANA_AMIC4, 0, 20, 0, analog_gain),
3213
3214 SOC_SINGLE_S8_TLV("RX0 Digital Volume", WCD934X_CDC_RX0_RX_VOL_CTL,
3215 -84, 40, digital_gain), /* -84dB min - 40dB max */
3216 SOC_SINGLE_S8_TLV("RX1 Digital Volume", WCD934X_CDC_RX1_RX_VOL_CTL,
3217 -84, 40, digital_gain),
3218 SOC_SINGLE_S8_TLV("RX2 Digital Volume", WCD934X_CDC_RX2_RX_VOL_CTL,
3219 -84, 40, digital_gain),
3220 SOC_SINGLE_S8_TLV("RX3 Digital Volume", WCD934X_CDC_RX3_RX_VOL_CTL,
3221 -84, 40, digital_gain),
3222 SOC_SINGLE_S8_TLV("RX4 Digital Volume", WCD934X_CDC_RX4_RX_VOL_CTL,
3223 -84, 40, digital_gain),
3224 SOC_SINGLE_S8_TLV("RX7 Digital Volume", WCD934X_CDC_RX7_RX_VOL_CTL,
3225 -84, 40, digital_gain),
3226 SOC_SINGLE_S8_TLV("RX8 Digital Volume", WCD934X_CDC_RX8_RX_VOL_CTL,
3227 -84, 40, digital_gain),
3228 SOC_SINGLE_S8_TLV("RX0 Mix Digital Volume",
3229 WCD934X_CDC_RX0_RX_VOL_MIX_CTL,
3230 -84, 40, digital_gain),
3231 SOC_SINGLE_S8_TLV("RX1 Mix Digital Volume",
3232 WCD934X_CDC_RX1_RX_VOL_MIX_CTL,
3233 -84, 40, digital_gain),
3234 SOC_SINGLE_S8_TLV("RX2 Mix Digital Volume",
3235 WCD934X_CDC_RX2_RX_VOL_MIX_CTL,
3236 -84, 40, digital_gain),
3237 SOC_SINGLE_S8_TLV("RX3 Mix Digital Volume",
3238 WCD934X_CDC_RX3_RX_VOL_MIX_CTL,
3239 -84, 40, digital_gain),
3240 SOC_SINGLE_S8_TLV("RX4 Mix Digital Volume",
3241 WCD934X_CDC_RX4_RX_VOL_MIX_CTL,
3242 -84, 40, digital_gain),
3243 SOC_SINGLE_S8_TLV("RX7 Mix Digital Volume",
3244 WCD934X_CDC_RX7_RX_VOL_MIX_CTL,
3245 -84, 40, digital_gain),
3246 SOC_SINGLE_S8_TLV("RX8 Mix Digital Volume",
3247 WCD934X_CDC_RX8_RX_VOL_MIX_CTL,
3248 -84, 40, digital_gain),
3249
3250 SOC_SINGLE_S8_TLV("DEC0 Volume", WCD934X_CDC_TX0_TX_VOL_CTL,
3251 -84, 40, digital_gain),
3252 SOC_SINGLE_S8_TLV("DEC1 Volume", WCD934X_CDC_TX1_TX_VOL_CTL,
3253 -84, 40, digital_gain),
3254 SOC_SINGLE_S8_TLV("DEC2 Volume", WCD934X_CDC_TX2_TX_VOL_CTL,
3255 -84, 40, digital_gain),
3256 SOC_SINGLE_S8_TLV("DEC3 Volume", WCD934X_CDC_TX3_TX_VOL_CTL,
3257 -84, 40, digital_gain),
3258 SOC_SINGLE_S8_TLV("DEC4 Volume", WCD934X_CDC_TX4_TX_VOL_CTL,
3259 -84, 40, digital_gain),
3260 SOC_SINGLE_S8_TLV("DEC5 Volume", WCD934X_CDC_TX5_TX_VOL_CTL,
3261 -84, 40, digital_gain),
3262 SOC_SINGLE_S8_TLV("DEC6 Volume", WCD934X_CDC_TX6_TX_VOL_CTL,
3263 -84, 40, digital_gain),
3264 SOC_SINGLE_S8_TLV("DEC7 Volume", WCD934X_CDC_TX7_TX_VOL_CTL,
3265 -84, 40, digital_gain),
3266 SOC_SINGLE_S8_TLV("DEC8 Volume", WCD934X_CDC_TX8_TX_VOL_CTL,
3267 -84, 40, digital_gain),
3268
3269 SOC_SINGLE_S8_TLV("IIR0 INP0 Volume",
3270 WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL, -84, 40,
3271 digital_gain),
3272 SOC_SINGLE_S8_TLV("IIR0 INP1 Volume",
3273 WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B2_CTL, -84, 40,
3274 digital_gain),
3275 SOC_SINGLE_S8_TLV("IIR0 INP2 Volume",
3276 WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B3_CTL, -84, 40,
3277 digital_gain),
3278 SOC_SINGLE_S8_TLV("IIR0 INP3 Volume",
3279 WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B4_CTL, -84, 40,
3280 digital_gain),
3281 SOC_SINGLE_S8_TLV("IIR1 INP0 Volume",
3282 WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B1_CTL, -84, 40,
3283 digital_gain),
3284 SOC_SINGLE_S8_TLV("IIR1 INP1 Volume",
3285 WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B2_CTL, -84, 40,
3286 digital_gain),
3287 SOC_SINGLE_S8_TLV("IIR1 INP2 Volume",
3288 WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B3_CTL, -84, 40,
3289 digital_gain),
3290 SOC_SINGLE_S8_TLV("IIR1 INP3 Volume",
3291 WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B4_CTL, -84, 40,
3292 digital_gain),
3293
3294 SOC_ENUM("TX0 HPF cut off", cf_dec0_enum),
3295 SOC_ENUM("TX1 HPF cut off", cf_dec1_enum),
3296 SOC_ENUM("TX2 HPF cut off", cf_dec2_enum),
3297 SOC_ENUM("TX3 HPF cut off", cf_dec3_enum),
3298 SOC_ENUM("TX4 HPF cut off", cf_dec4_enum),
3299 SOC_ENUM("TX5 HPF cut off", cf_dec5_enum),
3300 SOC_ENUM("TX6 HPF cut off", cf_dec6_enum),
3301 SOC_ENUM("TX7 HPF cut off", cf_dec7_enum),
3302 SOC_ENUM("TX8 HPF cut off", cf_dec8_enum),
3303
3304 SOC_ENUM("RX INT0_1 HPF cut off", cf_int0_1_enum),
3305 SOC_ENUM("RX INT0_2 HPF cut off", cf_int0_2_enum),
3306 SOC_ENUM("RX INT1_1 HPF cut off", cf_int1_1_enum),
3307 SOC_ENUM("RX INT1_2 HPF cut off", cf_int1_2_enum),
3308 SOC_ENUM("RX INT2_1 HPF cut off", cf_int2_1_enum),
3309 SOC_ENUM("RX INT2_2 HPF cut off", cf_int2_2_enum),
3310 SOC_ENUM("RX INT3_1 HPF cut off", cf_int3_1_enum),
3311 SOC_ENUM("RX INT3_2 HPF cut off", cf_int3_2_enum),
3312 SOC_ENUM("RX INT4_1 HPF cut off", cf_int4_1_enum),
3313 SOC_ENUM("RX INT4_2 HPF cut off", cf_int4_2_enum),
3314 SOC_ENUM("RX INT7_1 HPF cut off", cf_int7_1_enum),
3315 SOC_ENUM("RX INT7_2 HPF cut off", cf_int7_2_enum),
3316 SOC_ENUM("RX INT8_1 HPF cut off", cf_int8_1_enum),
3317 SOC_ENUM("RX INT8_2 HPF cut off", cf_int8_2_enum),
3318
3319 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
3320 wcd934x_rx_hph_mode_get, wcd934x_rx_hph_mode_put),
3321
3322 SOC_SINGLE("IIR1 Band1 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
3323 0, 1, 0),
3324 SOC_SINGLE("IIR1 Band2 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
3325 1, 1, 0),
3326 SOC_SINGLE("IIR1 Band3 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
3327 2, 1, 0),
3328 SOC_SINGLE("IIR1 Band4 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
3329 3, 1, 0),
3330 SOC_SINGLE("IIR1 Band5 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
3331 4, 1, 0),
3332 SOC_SINGLE("IIR2 Band1 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
3333 0, 1, 0),
3334 SOC_SINGLE("IIR2 Band2 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
3335 1, 1, 0),
3336 SOC_SINGLE("IIR2 Band3 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
3337 2, 1, 0),
3338 SOC_SINGLE("IIR2 Band4 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
3339 3, 1, 0),
3340 SOC_SINGLE("IIR2 Band5 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
3341 4, 1, 0),
3342 WCD_IIR_FILTER_CTL("IIR0 Band1", IIR0, BAND1),
3343 WCD_IIR_FILTER_CTL("IIR0 Band2", IIR0, BAND2),
3344 WCD_IIR_FILTER_CTL("IIR0 Band3", IIR0, BAND3),
3345 WCD_IIR_FILTER_CTL("IIR0 Band4", IIR0, BAND4),
3346 WCD_IIR_FILTER_CTL("IIR0 Band5", IIR0, BAND5),
3347
3348 WCD_IIR_FILTER_CTL("IIR1 Band1", IIR1, BAND1),
3349 WCD_IIR_FILTER_CTL("IIR1 Band2", IIR1, BAND2),
3350 WCD_IIR_FILTER_CTL("IIR1 Band3", IIR1, BAND3),
3351 WCD_IIR_FILTER_CTL("IIR1 Band4", IIR1, BAND4),
3352 WCD_IIR_FILTER_CTL("IIR1 Band5", IIR1, BAND5),
3353
3354 SOC_SINGLE_EXT("COMP1 Switch", SND_SOC_NOPM, COMPANDER_1, 1, 0,
3355 wcd934x_compander_get, wcd934x_compander_set),
3356 SOC_SINGLE_EXT("COMP2 Switch", SND_SOC_NOPM, COMPANDER_2, 1, 0,
3357 wcd934x_compander_get, wcd934x_compander_set),
3358 SOC_SINGLE_EXT("COMP3 Switch", SND_SOC_NOPM, COMPANDER_3, 1, 0,
3359 wcd934x_compander_get, wcd934x_compander_set),
3360 SOC_SINGLE_EXT("COMP4 Switch", SND_SOC_NOPM, COMPANDER_4, 1, 0,
3361 wcd934x_compander_get, wcd934x_compander_set),
3362 SOC_SINGLE_EXT("COMP7 Switch", SND_SOC_NOPM, COMPANDER_7, 1, 0,
3363 wcd934x_compander_get, wcd934x_compander_set),
3364 SOC_SINGLE_EXT("COMP8 Switch", SND_SOC_NOPM, COMPANDER_8, 1, 0,
3365 wcd934x_compander_get, wcd934x_compander_set),
3366 };
3367
wcd934x_codec_enable_int_port(struct wcd_slim_codec_dai_data * dai,struct snd_soc_component * component)3368 static void wcd934x_codec_enable_int_port(struct wcd_slim_codec_dai_data *dai,
3369 struct snd_soc_component *component)
3370 {
3371 int port_num = 0;
3372 unsigned short reg = 0;
3373 unsigned int val = 0;
3374 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
3375 struct wcd934x_slim_ch *ch;
3376
3377 list_for_each_entry(ch, &dai->slim_ch_list, list) {
3378 if (ch->port >= WCD934X_RX_START) {
3379 port_num = ch->port - WCD934X_RX_START;
3380 reg = WCD934X_SLIM_PGD_PORT_INT_EN0 + (port_num / 8);
3381 } else {
3382 port_num = ch->port;
3383 reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 + (port_num / 8);
3384 }
3385
3386 regmap_read(wcd->if_regmap, reg, &val);
3387 if (!(val & BIT(port_num % 8)))
3388 regmap_write(wcd->if_regmap, reg,
3389 val | BIT(port_num % 8));
3390 }
3391 }
3392
wcd934x_codec_enable_slim(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3393 static int wcd934x_codec_enable_slim(struct snd_soc_dapm_widget *w,
3394 struct snd_kcontrol *kc, int event)
3395 {
3396 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3397 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp);
3398 struct wcd_slim_codec_dai_data *dai = &wcd->dai[w->shift];
3399
3400 switch (event) {
3401 case SND_SOC_DAPM_POST_PMU:
3402 wcd934x_codec_enable_int_port(dai, comp);
3403 break;
3404 }
3405
3406 return 0;
3407 }
3408
wcd934x_codec_hd2_control(struct snd_soc_component * component,u16 interp_idx,int event)3409 static void wcd934x_codec_hd2_control(struct snd_soc_component *component,
3410 u16 interp_idx, int event)
3411 {
3412 u16 hd2_scale_reg;
3413 u16 hd2_enable_reg = 0;
3414
3415 switch (interp_idx) {
3416 case INTERP_HPHL:
3417 hd2_scale_reg = WCD934X_CDC_RX1_RX_PATH_SEC3;
3418 hd2_enable_reg = WCD934X_CDC_RX1_RX_PATH_CFG0;
3419 break;
3420 case INTERP_HPHR:
3421 hd2_scale_reg = WCD934X_CDC_RX2_RX_PATH_SEC3;
3422 hd2_enable_reg = WCD934X_CDC_RX2_RX_PATH_CFG0;
3423 break;
3424 default:
3425 return;
3426 }
3427
3428 if (SND_SOC_DAPM_EVENT_ON(event)) {
3429 snd_soc_component_update_bits(component, hd2_scale_reg,
3430 WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_MASK,
3431 WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_0P3125);
3432 snd_soc_component_update_bits(component, hd2_enable_reg,
3433 WCD934X_CDC_RX_PATH_CFG_HD2_EN_MASK,
3434 WCD934X_CDC_RX_PATH_CFG_HD2_ENABLE);
3435 }
3436
3437 if (SND_SOC_DAPM_EVENT_OFF(event)) {
3438 snd_soc_component_update_bits(component, hd2_enable_reg,
3439 WCD934X_CDC_RX_PATH_CFG_HD2_EN_MASK,
3440 WCD934X_CDC_RX_PATH_CFG_HD2_DISABLE);
3441 snd_soc_component_update_bits(component, hd2_scale_reg,
3442 WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_MASK,
3443 WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_0P0000);
3444 }
3445 }
3446
wcd934x_codec_hphdelay_lutbypass(struct snd_soc_component * comp,u16 interp_idx,int event)3447 static void wcd934x_codec_hphdelay_lutbypass(struct snd_soc_component *comp,
3448 u16 interp_idx, int event)
3449 {
3450 u8 hph_dly_mask;
3451 u16 hph_lut_bypass_reg = 0;
3452
3453 switch (interp_idx) {
3454 case INTERP_HPHL:
3455 hph_dly_mask = 1;
3456 hph_lut_bypass_reg = WCD934X_CDC_TOP_HPHL_COMP_LUT;
3457 break;
3458 case INTERP_HPHR:
3459 hph_dly_mask = 2;
3460 hph_lut_bypass_reg = WCD934X_CDC_TOP_HPHR_COMP_LUT;
3461 break;
3462 default:
3463 return;
3464 }
3465
3466 if (SND_SOC_DAPM_EVENT_ON(event)) {
3467 snd_soc_component_update_bits(comp, WCD934X_CDC_CLSH_TEST0,
3468 hph_dly_mask, 0x0);
3469 snd_soc_component_update_bits(comp, hph_lut_bypass_reg,
3470 WCD934X_HPH_LUT_BYPASS_MASK,
3471 WCD934X_HPH_LUT_BYPASS_ENABLE);
3472 }
3473
3474 if (SND_SOC_DAPM_EVENT_OFF(event)) {
3475 snd_soc_component_update_bits(comp, WCD934X_CDC_CLSH_TEST0,
3476 hph_dly_mask, hph_dly_mask);
3477 snd_soc_component_update_bits(comp, hph_lut_bypass_reg,
3478 WCD934X_HPH_LUT_BYPASS_MASK,
3479 WCD934X_HPH_LUT_BYPASS_DISABLE);
3480 }
3481 }
3482
wcd934x_config_compander(struct snd_soc_component * comp,int interp_n,int event)3483 static int wcd934x_config_compander(struct snd_soc_component *comp,
3484 int interp_n, int event)
3485 {
3486 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
3487 int compander;
3488 u16 comp_ctl0_reg, rx_path_cfg0_reg;
3489
3490 /* EAR does not have compander */
3491 if (!interp_n)
3492 return 0;
3493
3494 compander = interp_n - 1;
3495 if (!wcd->comp_enabled[compander])
3496 return 0;
3497
3498 comp_ctl0_reg = WCD934X_CDC_COMPANDER1_CTL0 + (compander * 8);
3499 rx_path_cfg0_reg = WCD934X_CDC_RX1_RX_PATH_CFG0 + (compander * 20);
3500
3501 switch (event) {
3502 case SND_SOC_DAPM_PRE_PMU:
3503 /* Enable Compander Clock */
3504 snd_soc_component_update_bits(comp, comp_ctl0_reg,
3505 WCD934X_COMP_CLK_EN_MASK,
3506 WCD934X_COMP_CLK_ENABLE);
3507 snd_soc_component_update_bits(comp, comp_ctl0_reg,
3508 WCD934X_COMP_SOFT_RST_MASK,
3509 WCD934X_COMP_SOFT_RST_ENABLE);
3510 snd_soc_component_update_bits(comp, comp_ctl0_reg,
3511 WCD934X_COMP_SOFT_RST_MASK,
3512 WCD934X_COMP_SOFT_RST_DISABLE);
3513 snd_soc_component_update_bits(comp, rx_path_cfg0_reg,
3514 WCD934X_HPH_CMP_EN_MASK,
3515 WCD934X_HPH_CMP_ENABLE);
3516 break;
3517 case SND_SOC_DAPM_POST_PMD:
3518 snd_soc_component_update_bits(comp, rx_path_cfg0_reg,
3519 WCD934X_HPH_CMP_EN_MASK,
3520 WCD934X_HPH_CMP_DISABLE);
3521 snd_soc_component_update_bits(comp, comp_ctl0_reg,
3522 WCD934X_COMP_HALT_MASK,
3523 WCD934X_COMP_HALT);
3524 snd_soc_component_update_bits(comp, comp_ctl0_reg,
3525 WCD934X_COMP_SOFT_RST_MASK,
3526 WCD934X_COMP_SOFT_RST_ENABLE);
3527 snd_soc_component_update_bits(comp, comp_ctl0_reg,
3528 WCD934X_COMP_SOFT_RST_MASK,
3529 WCD934X_COMP_SOFT_RST_DISABLE);
3530 snd_soc_component_update_bits(comp, comp_ctl0_reg,
3531 WCD934X_COMP_CLK_EN_MASK, 0x0);
3532 snd_soc_component_update_bits(comp, comp_ctl0_reg,
3533 WCD934X_COMP_SOFT_RST_MASK, 0x0);
3534 break;
3535 }
3536
3537 return 0;
3538 }
3539
wcd934x_codec_enable_interp_clk(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3540 static int wcd934x_codec_enable_interp_clk(struct snd_soc_dapm_widget *w,
3541 struct snd_kcontrol *kc, int event)
3542 {
3543 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3544 int interp_idx = w->shift;
3545 u16 main_reg = WCD934X_CDC_RX0_RX_PATH_CTL + (interp_idx * 20);
3546
3547 switch (event) {
3548 case SND_SOC_DAPM_PRE_PMU:
3549 /* Clk enable */
3550 snd_soc_component_update_bits(comp, main_reg,
3551 WCD934X_RX_CLK_EN_MASK,
3552 WCD934X_RX_CLK_ENABLE);
3553 wcd934x_codec_hd2_control(comp, interp_idx, event);
3554 wcd934x_codec_hphdelay_lutbypass(comp, interp_idx, event);
3555 wcd934x_config_compander(comp, interp_idx, event);
3556 break;
3557 case SND_SOC_DAPM_POST_PMD:
3558 wcd934x_config_compander(comp, interp_idx, event);
3559 wcd934x_codec_hphdelay_lutbypass(comp, interp_idx, event);
3560 wcd934x_codec_hd2_control(comp, interp_idx, event);
3561 /* Clk Disable */
3562 snd_soc_component_update_bits(comp, main_reg,
3563 WCD934X_RX_CLK_EN_MASK, 0);
3564 /* Reset enable and disable */
3565 snd_soc_component_update_bits(comp, main_reg,
3566 WCD934X_RX_RESET_MASK,
3567 WCD934X_RX_RESET_ENABLE);
3568 snd_soc_component_update_bits(comp, main_reg,
3569 WCD934X_RX_RESET_MASK,
3570 WCD934X_RX_RESET_DISABLE);
3571 /* Reset rate to 48K*/
3572 snd_soc_component_update_bits(comp, main_reg,
3573 WCD934X_RX_PCM_RATE_MASK,
3574 WCD934X_RX_PCM_RATE_F_48K);
3575 break;
3576 }
3577
3578 return 0;
3579 }
3580
wcd934x_codec_enable_mix_path(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3581 static int wcd934x_codec_enable_mix_path(struct snd_soc_dapm_widget *w,
3582 struct snd_kcontrol *kc, int event)
3583 {
3584 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3585 int offset_val = 0;
3586 u16 gain_reg, mix_reg;
3587 int val = 0;
3588
3589 gain_reg = WCD934X_CDC_RX0_RX_VOL_MIX_CTL +
3590 (w->shift * WCD934X_RX_PATH_CTL_OFFSET);
3591 mix_reg = WCD934X_CDC_RX0_RX_PATH_MIX_CTL +
3592 (w->shift * WCD934X_RX_PATH_CTL_OFFSET);
3593
3594 switch (event) {
3595 case SND_SOC_DAPM_PRE_PMU:
3596 /* Clk enable */
3597 snd_soc_component_update_bits(comp, mix_reg,
3598 WCD934X_CDC_RX_MIX_CLK_EN_MASK,
3599 WCD934X_CDC_RX_MIX_CLK_ENABLE);
3600 break;
3601
3602 case SND_SOC_DAPM_POST_PMU:
3603 val = snd_soc_component_read(comp, gain_reg);
3604 val += offset_val;
3605 snd_soc_component_write(comp, gain_reg, val);
3606 break;
3607 }
3608
3609 return 0;
3610 }
3611
wcd934x_codec_set_iir_gain(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)3612 static int wcd934x_codec_set_iir_gain(struct snd_soc_dapm_widget *w,
3613 struct snd_kcontrol *kcontrol, int event)
3614 {
3615 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3616 int reg = w->reg;
3617
3618 switch (event) {
3619 case SND_SOC_DAPM_POST_PMU:
3620 /* B1 GAIN */
3621 snd_soc_component_write(comp, reg,
3622 snd_soc_component_read(comp, reg));
3623 /* B2 GAIN */
3624 reg++;
3625 snd_soc_component_write(comp, reg,
3626 snd_soc_component_read(comp, reg));
3627 /* B3 GAIN */
3628 reg++;
3629 snd_soc_component_write(comp, reg,
3630 snd_soc_component_read(comp, reg));
3631 /* B4 GAIN */
3632 reg++;
3633 snd_soc_component_write(comp, reg,
3634 snd_soc_component_read(comp, reg));
3635 /* B5 GAIN */
3636 reg++;
3637 snd_soc_component_write(comp, reg,
3638 snd_soc_component_read(comp, reg));
3639 break;
3640 default:
3641 break;
3642 }
3643 return 0;
3644 }
3645
wcd934x_codec_enable_main_path(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)3646 static int wcd934x_codec_enable_main_path(struct snd_soc_dapm_widget *w,
3647 struct snd_kcontrol *kcontrol,
3648 int event)
3649 {
3650 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3651 u16 gain_reg;
3652
3653 gain_reg = WCD934X_CDC_RX0_RX_VOL_CTL + (w->shift *
3654 WCD934X_RX_PATH_CTL_OFFSET);
3655
3656 switch (event) {
3657 case SND_SOC_DAPM_POST_PMU:
3658 snd_soc_component_write(comp, gain_reg,
3659 snd_soc_component_read(comp, gain_reg));
3660 break;
3661 }
3662
3663 return 0;
3664 }
3665
wcd934x_codec_ear_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3666 static int wcd934x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
3667 struct snd_kcontrol *kc, int event)
3668 {
3669 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3670 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
3671
3672 switch (event) {
3673 case SND_SOC_DAPM_PRE_PMU:
3674 /* Disable AutoChop timer during power up */
3675 snd_soc_component_update_bits(comp,
3676 WCD934X_HPH_NEW_INT_HPH_TIMER1,
3677 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0);
3678 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
3679 WCD_CLSH_STATE_EAR, CLS_H_NORMAL);
3680
3681 break;
3682 case SND_SOC_DAPM_POST_PMD:
3683 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
3684 WCD_CLSH_STATE_EAR, CLS_H_NORMAL);
3685 break;
3686 }
3687
3688 return 0;
3689 }
3690
wcd934x_codec_hphl_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)3691 static int wcd934x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
3692 struct snd_kcontrol *kcontrol,
3693 int event)
3694 {
3695 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3696 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
3697 int hph_mode = wcd->hph_mode;
3698 u8 dem_inp;
3699
3700 switch (event) {
3701 case SND_SOC_DAPM_PRE_PMU:
3702 /* Read DEM INP Select */
3703 dem_inp = snd_soc_component_read(comp,
3704 WCD934X_CDC_RX1_RX_PATH_SEC0) & 0x03;
3705
3706 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) ||
3707 (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) {
3708 return -EINVAL;
3709 }
3710 if (hph_mode != CLS_H_LP)
3711 /* Ripple freq control enable */
3712 snd_soc_component_update_bits(comp,
3713 WCD934X_SIDO_NEW_VOUT_D_FREQ2,
3714 WCD934X_SIDO_RIPPLE_FREQ_EN_MASK,
3715 WCD934X_SIDO_RIPPLE_FREQ_ENABLE);
3716 /* Disable AutoChop timer during power up */
3717 snd_soc_component_update_bits(comp,
3718 WCD934X_HPH_NEW_INT_HPH_TIMER1,
3719 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0);
3720 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
3721 WCD_CLSH_STATE_HPHL, hph_mode);
3722
3723 break;
3724 case SND_SOC_DAPM_POST_PMD:
3725 /* 1000us required as per HW requirement */
3726 usleep_range(1000, 1100);
3727 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
3728 WCD_CLSH_STATE_HPHL, hph_mode);
3729 if (hph_mode != CLS_H_LP)
3730 /* Ripple freq control disable */
3731 snd_soc_component_update_bits(comp,
3732 WCD934X_SIDO_NEW_VOUT_D_FREQ2,
3733 WCD934X_SIDO_RIPPLE_FREQ_EN_MASK, 0x0);
3734
3735 break;
3736 default:
3737 break;
3738 }
3739
3740 return 0;
3741 }
3742
wcd934x_codec_hphr_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)3743 static int wcd934x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
3744 struct snd_kcontrol *kcontrol,
3745 int event)
3746 {
3747 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3748 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
3749 int hph_mode = wcd->hph_mode;
3750 u8 dem_inp;
3751
3752 switch (event) {
3753 case SND_SOC_DAPM_PRE_PMU:
3754 dem_inp = snd_soc_component_read(comp,
3755 WCD934X_CDC_RX2_RX_PATH_SEC0) & 0x03;
3756 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) ||
3757 (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) {
3758 return -EINVAL;
3759 }
3760 if (hph_mode != CLS_H_LP)
3761 /* Ripple freq control enable */
3762 snd_soc_component_update_bits(comp,
3763 WCD934X_SIDO_NEW_VOUT_D_FREQ2,
3764 WCD934X_SIDO_RIPPLE_FREQ_EN_MASK,
3765 WCD934X_SIDO_RIPPLE_FREQ_ENABLE);
3766 /* Disable AutoChop timer during power up */
3767 snd_soc_component_update_bits(comp,
3768 WCD934X_HPH_NEW_INT_HPH_TIMER1,
3769 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0);
3770 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
3771 WCD_CLSH_STATE_HPHR,
3772 hph_mode);
3773 break;
3774 case SND_SOC_DAPM_POST_PMD:
3775 /* 1000us required as per HW requirement */
3776 usleep_range(1000, 1100);
3777
3778 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
3779 WCD_CLSH_STATE_HPHR, hph_mode);
3780 if (hph_mode != CLS_H_LP)
3781 /* Ripple freq control disable */
3782 snd_soc_component_update_bits(comp,
3783 WCD934X_SIDO_NEW_VOUT_D_FREQ2,
3784 WCD934X_SIDO_RIPPLE_FREQ_EN_MASK, 0x0);
3785 break;
3786 default:
3787 break;
3788 }
3789
3790 return 0;
3791 }
3792
wcd934x_codec_lineout_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3793 static int wcd934x_codec_lineout_dac_event(struct snd_soc_dapm_widget *w,
3794 struct snd_kcontrol *kc, int event)
3795 {
3796 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3797 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
3798
3799 switch (event) {
3800 case SND_SOC_DAPM_PRE_PMU:
3801 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
3802 WCD_CLSH_STATE_LO, CLS_AB);
3803 break;
3804 case SND_SOC_DAPM_POST_PMD:
3805 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
3806 WCD_CLSH_STATE_LO, CLS_AB);
3807 break;
3808 }
3809
3810 return 0;
3811 }
3812
wcd934x_codec_enable_hphl_pa(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)3813 static int wcd934x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
3814 struct snd_kcontrol *kcontrol,
3815 int event)
3816 {
3817 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3818
3819 switch (event) {
3820 case SND_SOC_DAPM_POST_PMU:
3821 /*
3822 * 7ms sleep is required after PA is enabled as per
3823 * HW requirement. If compander is disabled, then
3824 * 20ms delay is needed.
3825 */
3826 usleep_range(20000, 20100);
3827
3828 snd_soc_component_update_bits(comp, WCD934X_HPH_L_TEST,
3829 WCD934X_HPH_OCP_DET_MASK,
3830 WCD934X_HPH_OCP_DET_ENABLE);
3831 /* Remove Mute on primary path */
3832 snd_soc_component_update_bits(comp, WCD934X_CDC_RX1_RX_PATH_CTL,
3833 WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
3834 0);
3835 /* Enable GM3 boost */
3836 snd_soc_component_update_bits(comp, WCD934X_HPH_CNP_WG_CTL,
3837 WCD934X_HPH_GM3_BOOST_EN_MASK,
3838 WCD934X_HPH_GM3_BOOST_ENABLE);
3839 /* Enable AutoChop timer at the end of power up */
3840 snd_soc_component_update_bits(comp,
3841 WCD934X_HPH_NEW_INT_HPH_TIMER1,
3842 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK,
3843 WCD934X_HPH_AUTOCHOP_TIMER_ENABLE);
3844 /* Remove mix path mute */
3845 snd_soc_component_update_bits(comp,
3846 WCD934X_CDC_RX1_RX_PATH_MIX_CTL,
3847 WCD934X_CDC_RX_PGA_MUTE_EN_MASK, 0x00);
3848 break;
3849 case SND_SOC_DAPM_PRE_PMD:
3850 /* Enable DSD Mute before PA disable */
3851 snd_soc_component_update_bits(comp, WCD934X_HPH_L_TEST,
3852 WCD934X_HPH_OCP_DET_MASK,
3853 WCD934X_HPH_OCP_DET_DISABLE);
3854 snd_soc_component_update_bits(comp, WCD934X_CDC_RX1_RX_PATH_CTL,
3855 WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
3856 WCD934X_RX_PATH_PGA_MUTE_ENABLE);
3857 snd_soc_component_update_bits(comp,
3858 WCD934X_CDC_RX1_RX_PATH_MIX_CTL,
3859 WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
3860 WCD934X_RX_PATH_PGA_MUTE_ENABLE);
3861 break;
3862 case SND_SOC_DAPM_POST_PMD:
3863 /*
3864 * 5ms sleep is required after PA disable. If compander is
3865 * disabled, then 20ms delay is needed after PA disable.
3866 */
3867 usleep_range(20000, 20100);
3868 break;
3869 }
3870
3871 return 0;
3872 }
3873
wcd934x_codec_enable_hphr_pa(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)3874 static int wcd934x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
3875 struct snd_kcontrol *kcontrol,
3876 int event)
3877 {
3878 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3879
3880 switch (event) {
3881 case SND_SOC_DAPM_POST_PMU:
3882 /*
3883 * 7ms sleep is required after PA is enabled as per
3884 * HW requirement. If compander is disabled, then
3885 * 20ms delay is needed.
3886 */
3887 usleep_range(20000, 20100);
3888 snd_soc_component_update_bits(comp, WCD934X_HPH_R_TEST,
3889 WCD934X_HPH_OCP_DET_MASK,
3890 WCD934X_HPH_OCP_DET_ENABLE);
3891 /* Remove mute */
3892 snd_soc_component_update_bits(comp, WCD934X_CDC_RX2_RX_PATH_CTL,
3893 WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
3894 0);
3895 /* Enable GM3 boost */
3896 snd_soc_component_update_bits(comp, WCD934X_HPH_CNP_WG_CTL,
3897 WCD934X_HPH_GM3_BOOST_EN_MASK,
3898 WCD934X_HPH_GM3_BOOST_ENABLE);
3899 /* Enable AutoChop timer at the end of power up */
3900 snd_soc_component_update_bits(comp,
3901 WCD934X_HPH_NEW_INT_HPH_TIMER1,
3902 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK,
3903 WCD934X_HPH_AUTOCHOP_TIMER_ENABLE);
3904 /* Remove mix path mute if it is enabled */
3905 if ((snd_soc_component_read(comp,
3906 WCD934X_CDC_RX2_RX_PATH_MIX_CTL)) & 0x10)
3907 snd_soc_component_update_bits(comp,
3908 WCD934X_CDC_RX2_RX_PATH_MIX_CTL,
3909 WCD934X_CDC_RX_PGA_MUTE_EN_MASK,
3910 WCD934X_CDC_RX_PGA_MUTE_DISABLE);
3911 break;
3912 case SND_SOC_DAPM_PRE_PMD:
3913 snd_soc_component_update_bits(comp, WCD934X_HPH_R_TEST,
3914 WCD934X_HPH_OCP_DET_MASK,
3915 WCD934X_HPH_OCP_DET_DISABLE);
3916 snd_soc_component_update_bits(comp, WCD934X_CDC_RX2_RX_PATH_CTL,
3917 WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
3918 WCD934X_RX_PATH_PGA_MUTE_ENABLE);
3919 snd_soc_component_update_bits(comp,
3920 WCD934X_CDC_RX2_RX_PATH_MIX_CTL,
3921 WCD934X_CDC_RX_PGA_MUTE_EN_MASK,
3922 WCD934X_CDC_RX_PGA_MUTE_ENABLE);
3923 break;
3924 case SND_SOC_DAPM_POST_PMD:
3925 /*
3926 * 5ms sleep is required after PA disable. If compander is
3927 * disabled, then 20ms delay is needed after PA disable.
3928 */
3929 usleep_range(20000, 20100);
3930 break;
3931 }
3932
3933 return 0;
3934 }
3935
wcd934x_get_dmic_sample_rate(struct snd_soc_component * comp,unsigned int dmic,struct wcd934x_codec * wcd)3936 static u32 wcd934x_get_dmic_sample_rate(struct snd_soc_component *comp,
3937 unsigned int dmic,
3938 struct wcd934x_codec *wcd)
3939 {
3940 u8 tx_stream_fs;
3941 u8 adc_mux_index = 0, adc_mux_sel = 0;
3942 bool dec_found = false;
3943 u16 adc_mux_ctl_reg, tx_fs_reg;
3944 u32 dmic_fs;
3945
3946 while (!dec_found && adc_mux_index < WCD934X_MAX_VALID_ADC_MUX) {
3947 if (adc_mux_index < 4) {
3948 adc_mux_ctl_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 +
3949 (adc_mux_index * 2);
3950 } else if (adc_mux_index < WCD934X_INVALID_ADC_MUX) {
3951 adc_mux_ctl_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
3952 adc_mux_index - 4;
3953 } else if (adc_mux_index == WCD934X_INVALID_ADC_MUX) {
3954 ++adc_mux_index;
3955 continue;
3956 }
3957 adc_mux_sel = ((snd_soc_component_read(comp, adc_mux_ctl_reg)
3958 & 0xF8) >> 3) - 1;
3959
3960 if (adc_mux_sel == dmic) {
3961 dec_found = true;
3962 break;
3963 }
3964
3965 ++adc_mux_index;
3966 }
3967
3968 if (dec_found && adc_mux_index <= 8) {
3969 tx_fs_reg = WCD934X_CDC_TX0_TX_PATH_CTL + (16 * adc_mux_index);
3970 tx_stream_fs = snd_soc_component_read(comp, tx_fs_reg) & 0x0F;
3971 if (tx_stream_fs <= 4) {
3972 if (wcd->dmic_sample_rate <=
3973 WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ)
3974 dmic_fs = wcd->dmic_sample_rate;
3975 else
3976 dmic_fs = WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ;
3977 } else
3978 dmic_fs = WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ;
3979 } else {
3980 dmic_fs = wcd->dmic_sample_rate;
3981 }
3982
3983 return dmic_fs;
3984 }
3985
wcd934x_get_dmic_clk_val(struct snd_soc_component * comp,u32 mclk_rate,u32 dmic_clk_rate)3986 static u8 wcd934x_get_dmic_clk_val(struct snd_soc_component *comp,
3987 u32 mclk_rate, u32 dmic_clk_rate)
3988 {
3989 u32 div_factor;
3990 u8 dmic_ctl_val;
3991
3992 /* Default value to return in case of error */
3993 if (mclk_rate == WCD934X_MCLK_CLK_9P6MHZ)
3994 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_2;
3995 else
3996 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_3;
3997
3998 if (dmic_clk_rate == 0) {
3999 dev_err(comp->dev,
4000 "%s: dmic_sample_rate cannot be 0\n",
4001 __func__);
4002 goto done;
4003 }
4004
4005 div_factor = mclk_rate / dmic_clk_rate;
4006 switch (div_factor) {
4007 case 2:
4008 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_2;
4009 break;
4010 case 3:
4011 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_3;
4012 break;
4013 case 4:
4014 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_4;
4015 break;
4016 case 6:
4017 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_6;
4018 break;
4019 case 8:
4020 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_8;
4021 break;
4022 case 16:
4023 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_16;
4024 break;
4025 default:
4026 dev_err(comp->dev,
4027 "%s: Invalid div_factor %u, clk_rate(%u), dmic_rate(%u)\n",
4028 __func__, div_factor, mclk_rate, dmic_clk_rate);
4029 break;
4030 }
4031
4032 done:
4033 return dmic_ctl_val;
4034 }
4035
wcd934x_codec_enable_dmic(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)4036 static int wcd934x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
4037 struct snd_kcontrol *kcontrol, int event)
4038 {
4039 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4040 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
4041 u8 dmic_clk_en = 0x01;
4042 u16 dmic_clk_reg;
4043 s32 *dmic_clk_cnt;
4044 u8 dmic_rate_val, dmic_rate_shift = 1;
4045 unsigned int dmic;
4046 u32 dmic_sample_rate;
4047 int ret;
4048 char *wname;
4049
4050 wname = strpbrk(w->name, "012345");
4051 if (!wname) {
4052 dev_err(comp->dev, "%s: widget not found\n", __func__);
4053 return -EINVAL;
4054 }
4055
4056 ret = kstrtouint(wname, 10, &dmic);
4057 if (ret < 0) {
4058 dev_err(comp->dev, "%s: Invalid DMIC line on the codec\n",
4059 __func__);
4060 return -EINVAL;
4061 }
4062
4063 switch (dmic) {
4064 case 0:
4065 case 1:
4066 dmic_clk_cnt = &wcd->dmic_0_1_clk_cnt;
4067 dmic_clk_reg = WCD934X_CPE_SS_DMIC0_CTL;
4068 break;
4069 case 2:
4070 case 3:
4071 dmic_clk_cnt = &wcd->dmic_2_3_clk_cnt;
4072 dmic_clk_reg = WCD934X_CPE_SS_DMIC1_CTL;
4073 break;
4074 case 4:
4075 case 5:
4076 dmic_clk_cnt = &wcd->dmic_4_5_clk_cnt;
4077 dmic_clk_reg = WCD934X_CPE_SS_DMIC2_CTL;
4078 break;
4079 default:
4080 dev_err(comp->dev, "%s: Invalid DMIC Selection\n",
4081 __func__);
4082 return -EINVAL;
4083 }
4084
4085 switch (event) {
4086 case SND_SOC_DAPM_PRE_PMU:
4087 dmic_sample_rate = wcd934x_get_dmic_sample_rate(comp, dmic,
4088 wcd);
4089 dmic_rate_val = wcd934x_get_dmic_clk_val(comp, wcd->rate,
4090 dmic_sample_rate);
4091 (*dmic_clk_cnt)++;
4092 if (*dmic_clk_cnt == 1) {
4093 dmic_rate_val = dmic_rate_val << dmic_rate_shift;
4094 snd_soc_component_update_bits(comp, dmic_clk_reg,
4095 WCD934X_DMIC_RATE_MASK,
4096 dmic_rate_val);
4097 snd_soc_component_update_bits(comp, dmic_clk_reg,
4098 dmic_clk_en, dmic_clk_en);
4099 }
4100
4101 break;
4102 case SND_SOC_DAPM_POST_PMD:
4103 (*dmic_clk_cnt)--;
4104 if (*dmic_clk_cnt == 0)
4105 snd_soc_component_update_bits(comp, dmic_clk_reg,
4106 dmic_clk_en, 0);
4107 break;
4108 }
4109
4110 return 0;
4111 }
4112
wcd934x_codec_find_amic_input(struct snd_soc_component * comp,int adc_mux_n)4113 static int wcd934x_codec_find_amic_input(struct snd_soc_component *comp,
4114 int adc_mux_n)
4115 {
4116 u16 mask, shift, adc_mux_in_reg;
4117 u16 amic_mux_sel_reg;
4118 bool is_amic;
4119
4120 if (adc_mux_n < 0 || adc_mux_n > WCD934X_MAX_VALID_ADC_MUX ||
4121 adc_mux_n == WCD934X_INVALID_ADC_MUX)
4122 return 0;
4123
4124 if (adc_mux_n < 3) {
4125 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 +
4126 adc_mux_n;
4127 mask = 0x03;
4128 shift = 0;
4129 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 +
4130 2 * adc_mux_n;
4131 } else if (adc_mux_n < 4) {
4132 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1;
4133 mask = 0x03;
4134 shift = 0;
4135 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 +
4136 2 * adc_mux_n;
4137 } else if (adc_mux_n < 7) {
4138 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 +
4139 (adc_mux_n - 4);
4140 mask = 0x0C;
4141 shift = 2;
4142 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4143 adc_mux_n - 4;
4144 } else if (adc_mux_n < 8) {
4145 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1;
4146 mask = 0x0C;
4147 shift = 2;
4148 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4149 adc_mux_n - 4;
4150 } else if (adc_mux_n < 12) {
4151 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 +
4152 ((adc_mux_n == 8) ? (adc_mux_n - 8) :
4153 (adc_mux_n - 9));
4154 mask = 0x30;
4155 shift = 4;
4156 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4157 adc_mux_n - 4;
4158 } else if (adc_mux_n < 13) {
4159 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1;
4160 mask = 0x30;
4161 shift = 4;
4162 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4163 adc_mux_n - 4;
4164 } else {
4165 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1;
4166 mask = 0xC0;
4167 shift = 6;
4168 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4169 adc_mux_n - 4;
4170 }
4171
4172 is_amic = (((snd_soc_component_read(comp, adc_mux_in_reg)
4173 & mask) >> shift) == 1);
4174 if (!is_amic)
4175 return 0;
4176
4177 return snd_soc_component_read(comp, amic_mux_sel_reg) & 0x07;
4178 }
4179
wcd934x_codec_get_amic_pwlvl_reg(struct snd_soc_component * comp,int amic)4180 static u16 wcd934x_codec_get_amic_pwlvl_reg(struct snd_soc_component *comp,
4181 int amic)
4182 {
4183 u16 pwr_level_reg = 0;
4184
4185 switch (amic) {
4186 case 1:
4187 case 2:
4188 pwr_level_reg = WCD934X_ANA_AMIC1;
4189 break;
4190
4191 case 3:
4192 case 4:
4193 pwr_level_reg = WCD934X_ANA_AMIC3;
4194 break;
4195 default:
4196 break;
4197 }
4198
4199 return pwr_level_reg;
4200 }
4201
wcd934x_codec_enable_dec(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)4202 static int wcd934x_codec_enable_dec(struct snd_soc_dapm_widget *w,
4203 struct snd_kcontrol *kcontrol, int event)
4204 {
4205 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4206 unsigned int decimator;
4207 char *dec_adc_mux_name = NULL;
4208 char *widget_name = NULL;
4209 char *wname;
4210 int ret = 0, amic_n;
4211 u16 tx_vol_ctl_reg, pwr_level_reg = 0, dec_cfg_reg, hpf_gate_reg;
4212 u16 tx_gain_ctl_reg;
4213 char *dec;
4214 u8 hpf_coff_freq;
4215
4216 widget_name = kstrndup(w->name, 15, GFP_KERNEL);
4217 if (!widget_name)
4218 return -ENOMEM;
4219
4220 wname = widget_name;
4221 dec_adc_mux_name = strsep(&widget_name, " ");
4222 if (!dec_adc_mux_name) {
4223 dev_err(comp->dev, "%s: Invalid decimator = %s\n",
4224 __func__, w->name);
4225 ret = -EINVAL;
4226 goto out;
4227 }
4228 dec_adc_mux_name = widget_name;
4229
4230 dec = strpbrk(dec_adc_mux_name, "012345678");
4231 if (!dec) {
4232 dev_err(comp->dev, "%s: decimator index not found\n",
4233 __func__);
4234 ret = -EINVAL;
4235 goto out;
4236 }
4237
4238 ret = kstrtouint(dec, 10, &decimator);
4239 if (ret < 0) {
4240 dev_err(comp->dev, "%s: Invalid decimator = %s\n",
4241 __func__, wname);
4242 ret = -EINVAL;
4243 goto out;
4244 }
4245
4246 tx_vol_ctl_reg = WCD934X_CDC_TX0_TX_PATH_CTL + 16 * decimator;
4247 hpf_gate_reg = WCD934X_CDC_TX0_TX_PATH_SEC2 + 16 * decimator;
4248 dec_cfg_reg = WCD934X_CDC_TX0_TX_PATH_CFG0 + 16 * decimator;
4249 tx_gain_ctl_reg = WCD934X_CDC_TX0_TX_VOL_CTL + 16 * decimator;
4250
4251 switch (event) {
4252 case SND_SOC_DAPM_PRE_PMU:
4253 amic_n = wcd934x_codec_find_amic_input(comp, decimator);
4254 if (amic_n)
4255 pwr_level_reg = wcd934x_codec_get_amic_pwlvl_reg(comp,
4256 amic_n);
4257
4258 if (!pwr_level_reg)
4259 break;
4260
4261 switch ((snd_soc_component_read(comp, pwr_level_reg) &
4262 WCD934X_AMIC_PWR_LVL_MASK) >>
4263 WCD934X_AMIC_PWR_LVL_SHIFT) {
4264 case WCD934X_AMIC_PWR_LEVEL_LP:
4265 snd_soc_component_update_bits(comp, dec_cfg_reg,
4266 WCD934X_DEC_PWR_LVL_MASK,
4267 WCD934X_DEC_PWR_LVL_LP);
4268 break;
4269 case WCD934X_AMIC_PWR_LEVEL_HP:
4270 snd_soc_component_update_bits(comp, dec_cfg_reg,
4271 WCD934X_DEC_PWR_LVL_MASK,
4272 WCD934X_DEC_PWR_LVL_HP);
4273 break;
4274 case WCD934X_AMIC_PWR_LEVEL_DEFAULT:
4275 case WCD934X_AMIC_PWR_LEVEL_HYBRID:
4276 default:
4277 snd_soc_component_update_bits(comp, dec_cfg_reg,
4278 WCD934X_DEC_PWR_LVL_MASK,
4279 WCD934X_DEC_PWR_LVL_DF);
4280 break;
4281 }
4282 break;
4283 case SND_SOC_DAPM_POST_PMU:
4284 hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) &
4285 TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
4286 if (hpf_coff_freq != CF_MIN_3DB_150HZ) {
4287 snd_soc_component_update_bits(comp, dec_cfg_reg,
4288 TX_HPF_CUT_OFF_FREQ_MASK,
4289 CF_MIN_3DB_150HZ << 5);
4290 snd_soc_component_update_bits(comp, hpf_gate_reg,
4291 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK,
4292 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ);
4293 /*
4294 * Minimum 1 clk cycle delay is required as per
4295 * HW spec.
4296 */
4297 usleep_range(1000, 1010);
4298 snd_soc_component_update_bits(comp, hpf_gate_reg,
4299 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK,
4300 0);
4301 }
4302 /* apply gain after decimator is enabled */
4303 snd_soc_component_write(comp, tx_gain_ctl_reg,
4304 snd_soc_component_read(comp,
4305 tx_gain_ctl_reg));
4306 break;
4307 case SND_SOC_DAPM_PRE_PMD:
4308 hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) &
4309 TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
4310
4311 if (hpf_coff_freq != CF_MIN_3DB_150HZ) {
4312 snd_soc_component_update_bits(comp, dec_cfg_reg,
4313 TX_HPF_CUT_OFF_FREQ_MASK,
4314 hpf_coff_freq << 5);
4315 snd_soc_component_update_bits(comp, hpf_gate_reg,
4316 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK,
4317 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ);
4318 /*
4319 * Minimum 1 clk cycle delay is required as per
4320 * HW spec.
4321 */
4322 usleep_range(1000, 1010);
4323 snd_soc_component_update_bits(comp, hpf_gate_reg,
4324 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK,
4325 0);
4326 }
4327 break;
4328 case SND_SOC_DAPM_POST_PMD:
4329 snd_soc_component_update_bits(comp, tx_vol_ctl_reg,
4330 0x10, 0x00);
4331 snd_soc_component_update_bits(comp, dec_cfg_reg,
4332 WCD934X_DEC_PWR_LVL_MASK,
4333 WCD934X_DEC_PWR_LVL_DF);
4334 break;
4335 }
4336 out:
4337 kfree(wname);
4338 return ret;
4339 }
4340
wcd934x_codec_set_tx_hold(struct snd_soc_component * comp,u16 amic_reg,bool set)4341 static void wcd934x_codec_set_tx_hold(struct snd_soc_component *comp,
4342 u16 amic_reg, bool set)
4343 {
4344 u8 mask = 0x20;
4345 u8 val;
4346
4347 if (amic_reg == WCD934X_ANA_AMIC1 ||
4348 amic_reg == WCD934X_ANA_AMIC3)
4349 mask = 0x40;
4350
4351 val = set ? mask : 0x00;
4352
4353 switch (amic_reg) {
4354 case WCD934X_ANA_AMIC1:
4355 case WCD934X_ANA_AMIC2:
4356 snd_soc_component_update_bits(comp, WCD934X_ANA_AMIC2,
4357 mask, val);
4358 break;
4359 case WCD934X_ANA_AMIC3:
4360 case WCD934X_ANA_AMIC4:
4361 snd_soc_component_update_bits(comp, WCD934X_ANA_AMIC4,
4362 mask, val);
4363 break;
4364 default:
4365 break;
4366 }
4367 }
4368
wcd934x_codec_enable_adc(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)4369 static int wcd934x_codec_enable_adc(struct snd_soc_dapm_widget *w,
4370 struct snd_kcontrol *kcontrol, int event)
4371 {
4372 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4373
4374 switch (event) {
4375 case SND_SOC_DAPM_PRE_PMU:
4376 wcd934x_codec_set_tx_hold(comp, w->reg, true);
4377 break;
4378 default:
4379 break;
4380 }
4381
4382 return 0;
4383 }
4384
4385 static const struct snd_soc_dapm_widget wcd934x_dapm_widgets[] = {
4386 /* Analog Outputs */
4387 SND_SOC_DAPM_OUTPUT("EAR"),
4388 SND_SOC_DAPM_OUTPUT("HPHL"),
4389 SND_SOC_DAPM_OUTPUT("HPHR"),
4390 SND_SOC_DAPM_OUTPUT("LINEOUT1"),
4391 SND_SOC_DAPM_OUTPUT("LINEOUT2"),
4392 SND_SOC_DAPM_OUTPUT("SPK1 OUT"),
4393 SND_SOC_DAPM_OUTPUT("SPK2 OUT"),
4394 SND_SOC_DAPM_OUTPUT("ANC EAR"),
4395 SND_SOC_DAPM_OUTPUT("ANC HPHL"),
4396 SND_SOC_DAPM_OUTPUT("ANC HPHR"),
4397 SND_SOC_DAPM_OUTPUT("WDMA3_OUT"),
4398 SND_SOC_DAPM_OUTPUT("MAD_CPE_OUT1"),
4399 SND_SOC_DAPM_OUTPUT("MAD_CPE_OUT2"),
4400 SND_SOC_DAPM_AIF_IN_E("AIF1 PB", "AIF1 Playback", 0, SND_SOC_NOPM,
4401 AIF1_PB, 0, wcd934x_codec_enable_slim,
4402 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4403 SND_SOC_DAPM_AIF_IN_E("AIF2 PB", "AIF2 Playback", 0, SND_SOC_NOPM,
4404 AIF2_PB, 0, wcd934x_codec_enable_slim,
4405 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4406 SND_SOC_DAPM_AIF_IN_E("AIF3 PB", "AIF3 Playback", 0, SND_SOC_NOPM,
4407 AIF3_PB, 0, wcd934x_codec_enable_slim,
4408 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4409 SND_SOC_DAPM_AIF_IN_E("AIF4 PB", "AIF4 Playback", 0, SND_SOC_NOPM,
4410 AIF4_PB, 0, wcd934x_codec_enable_slim,
4411 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4412
4413 SND_SOC_DAPM_MUX("SLIM RX0 MUX", SND_SOC_NOPM, WCD934X_RX0, 0,
4414 &slim_rx_mux[WCD934X_RX0]),
4415 SND_SOC_DAPM_MUX("SLIM RX1 MUX", SND_SOC_NOPM, WCD934X_RX1, 0,
4416 &slim_rx_mux[WCD934X_RX1]),
4417 SND_SOC_DAPM_MUX("SLIM RX2 MUX", SND_SOC_NOPM, WCD934X_RX2, 0,
4418 &slim_rx_mux[WCD934X_RX2]),
4419 SND_SOC_DAPM_MUX("SLIM RX3 MUX", SND_SOC_NOPM, WCD934X_RX3, 0,
4420 &slim_rx_mux[WCD934X_RX3]),
4421 SND_SOC_DAPM_MUX("SLIM RX4 MUX", SND_SOC_NOPM, WCD934X_RX4, 0,
4422 &slim_rx_mux[WCD934X_RX4]),
4423 SND_SOC_DAPM_MUX("SLIM RX5 MUX", SND_SOC_NOPM, WCD934X_RX5, 0,
4424 &slim_rx_mux[WCD934X_RX5]),
4425 SND_SOC_DAPM_MUX("SLIM RX6 MUX", SND_SOC_NOPM, WCD934X_RX6, 0,
4426 &slim_rx_mux[WCD934X_RX6]),
4427 SND_SOC_DAPM_MUX("SLIM RX7 MUX", SND_SOC_NOPM, WCD934X_RX7, 0,
4428 &slim_rx_mux[WCD934X_RX7]),
4429
4430 SND_SOC_DAPM_MIXER("SLIM RX0", SND_SOC_NOPM, 0, 0, NULL, 0),
4431 SND_SOC_DAPM_MIXER("SLIM RX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4432 SND_SOC_DAPM_MIXER("SLIM RX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4433 SND_SOC_DAPM_MIXER("SLIM RX3", SND_SOC_NOPM, 0, 0, NULL, 0),
4434 SND_SOC_DAPM_MIXER("SLIM RX4", SND_SOC_NOPM, 0, 0, NULL, 0),
4435 SND_SOC_DAPM_MIXER("SLIM RX5", SND_SOC_NOPM, 0, 0, NULL, 0),
4436 SND_SOC_DAPM_MIXER("SLIM RX6", SND_SOC_NOPM, 0, 0, NULL, 0),
4437 SND_SOC_DAPM_MIXER("SLIM RX7", SND_SOC_NOPM, 0, 0, NULL, 0),
4438
4439 SND_SOC_DAPM_MUX_E("RX INT0_2 MUX", SND_SOC_NOPM, INTERP_EAR, 0,
4440 &rx_int0_2_mux, wcd934x_codec_enable_mix_path,
4441 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4442 SND_SOC_DAPM_POST_PMD),
4443 SND_SOC_DAPM_MUX_E("RX INT1_2 MUX", SND_SOC_NOPM, INTERP_HPHL, 0,
4444 &rx_int1_2_mux, wcd934x_codec_enable_mix_path,
4445 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4446 SND_SOC_DAPM_POST_PMD),
4447 SND_SOC_DAPM_MUX_E("RX INT2_2 MUX", SND_SOC_NOPM, INTERP_HPHR, 0,
4448 &rx_int2_2_mux, wcd934x_codec_enable_mix_path,
4449 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4450 SND_SOC_DAPM_POST_PMD),
4451 SND_SOC_DAPM_MUX_E("RX INT3_2 MUX", SND_SOC_NOPM, INTERP_LO1, 0,
4452 &rx_int3_2_mux, wcd934x_codec_enable_mix_path,
4453 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4454 SND_SOC_DAPM_POST_PMD),
4455 SND_SOC_DAPM_MUX_E("RX INT4_2 MUX", SND_SOC_NOPM, INTERP_LO2, 0,
4456 &rx_int4_2_mux, wcd934x_codec_enable_mix_path,
4457 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4458 SND_SOC_DAPM_POST_PMD),
4459 SND_SOC_DAPM_MUX_E("RX INT7_2 MUX", SND_SOC_NOPM, INTERP_SPKR1, 0,
4460 &rx_int7_2_mux, wcd934x_codec_enable_mix_path,
4461 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4462 SND_SOC_DAPM_POST_PMD),
4463 SND_SOC_DAPM_MUX_E("RX INT8_2 MUX", SND_SOC_NOPM, INTERP_SPKR2, 0,
4464 &rx_int8_2_mux, wcd934x_codec_enable_mix_path,
4465 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4466 SND_SOC_DAPM_POST_PMD),
4467
4468 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4469 &rx_int0_1_mix_inp0_mux),
4470 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4471 &rx_int0_1_mix_inp1_mux),
4472 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4473 &rx_int0_1_mix_inp2_mux),
4474 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4475 &rx_int1_1_mix_inp0_mux),
4476 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4477 &rx_int1_1_mix_inp1_mux),
4478 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4479 &rx_int1_1_mix_inp2_mux),
4480 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4481 &rx_int2_1_mix_inp0_mux),
4482 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4483 &rx_int2_1_mix_inp1_mux),
4484 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4485 &rx_int2_1_mix_inp2_mux),
4486 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4487 &rx_int3_1_mix_inp0_mux),
4488 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4489 &rx_int3_1_mix_inp1_mux),
4490 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4491 &rx_int3_1_mix_inp2_mux),
4492 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4493 &rx_int4_1_mix_inp0_mux),
4494 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4495 &rx_int4_1_mix_inp1_mux),
4496 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4497 &rx_int4_1_mix_inp2_mux),
4498 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4499 &rx_int7_1_mix_inp0_mux),
4500 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4501 &rx_int7_1_mix_inp1_mux),
4502 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4503 &rx_int7_1_mix_inp2_mux),
4504 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4505 &rx_int8_1_mix_inp0_mux),
4506 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4507 &rx_int8_1_mix_inp1_mux),
4508 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4509 &rx_int8_1_mix_inp2_mux),
4510 SND_SOC_DAPM_MIXER("RX INT0_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4511 SND_SOC_DAPM_MIXER("RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4512 SND_SOC_DAPM_MIXER("RX INT1_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4513 SND_SOC_DAPM_MIXER("RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0,
4514 rx_int1_asrc_switch,
4515 ARRAY_SIZE(rx_int1_asrc_switch)),
4516 SND_SOC_DAPM_MIXER("RX INT2_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4517 SND_SOC_DAPM_MIXER("RX INT2 SEC MIX", SND_SOC_NOPM, 0, 0,
4518 rx_int2_asrc_switch,
4519 ARRAY_SIZE(rx_int2_asrc_switch)),
4520 SND_SOC_DAPM_MIXER("RX INT3_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4521 SND_SOC_DAPM_MIXER("RX INT3 SEC MIX", SND_SOC_NOPM, 0, 0,
4522 rx_int3_asrc_switch,
4523 ARRAY_SIZE(rx_int3_asrc_switch)),
4524 SND_SOC_DAPM_MIXER("RX INT4_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4525 SND_SOC_DAPM_MIXER("RX INT4 SEC MIX", SND_SOC_NOPM, 0, 0,
4526 rx_int4_asrc_switch,
4527 ARRAY_SIZE(rx_int4_asrc_switch)),
4528 SND_SOC_DAPM_MIXER("RX INT7_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4529 SND_SOC_DAPM_MIXER("RX INT7 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4530 SND_SOC_DAPM_MIXER("RX INT8_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4531 SND_SOC_DAPM_MIXER("RX INT8 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4532 SND_SOC_DAPM_MIXER("RX INT0 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4533 SND_SOC_DAPM_MIXER("RX INT1 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4534 SND_SOC_DAPM_MIXER("RX INT1 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0),
4535 SND_SOC_DAPM_MIXER("RX INT2 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4536 SND_SOC_DAPM_MIXER("RX INT2 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0),
4537 SND_SOC_DAPM_MIXER("RX INT3 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4538 SND_SOC_DAPM_MIXER("RX INT3 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0),
4539 SND_SOC_DAPM_MIXER("RX INT4 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4540 SND_SOC_DAPM_MIXER("RX INT4 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0),
4541
4542 SND_SOC_DAPM_MIXER("RX INT7 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4543 SND_SOC_DAPM_MIXER_E("RX INT7 CHAIN", SND_SOC_NOPM, 0, 0,
4544 NULL, 0, NULL, 0),
4545 SND_SOC_DAPM_MIXER_E("RX INT8 CHAIN", SND_SOC_NOPM, 0, 0,
4546 NULL, 0, NULL, 0),
4547 SND_SOC_DAPM_MUX_E("RX INT0 MIX2 INP", WCD934X_CDC_RX0_RX_PATH_CFG0, 4,
4548 0, &rx_int0_mix2_inp_mux, NULL,
4549 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4550 SND_SOC_DAPM_MUX_E("RX INT1 MIX2 INP", WCD934X_CDC_RX1_RX_PATH_CFG0, 4,
4551 0, &rx_int1_mix2_inp_mux, NULL,
4552 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4553 SND_SOC_DAPM_MUX_E("RX INT2 MIX2 INP", WCD934X_CDC_RX2_RX_PATH_CFG0, 4,
4554 0, &rx_int2_mix2_inp_mux, NULL,
4555 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4556 SND_SOC_DAPM_MUX_E("RX INT3 MIX2 INP", WCD934X_CDC_RX3_RX_PATH_CFG0, 4,
4557 0, &rx_int3_mix2_inp_mux, NULL,
4558 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4559 SND_SOC_DAPM_MUX_E("RX INT4 MIX2 INP", WCD934X_CDC_RX4_RX_PATH_CFG0, 4,
4560 0, &rx_int4_mix2_inp_mux, NULL,
4561 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4562 SND_SOC_DAPM_MUX_E("RX INT7 MIX2 INP", WCD934X_CDC_RX7_RX_PATH_CFG0, 4,
4563 0, &rx_int7_mix2_inp_mux, NULL,
4564 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4565
4566 SND_SOC_DAPM_MUX("IIR0 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp0_mux),
4567 SND_SOC_DAPM_MUX("IIR0 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp1_mux),
4568 SND_SOC_DAPM_MUX("IIR0 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp2_mux),
4569 SND_SOC_DAPM_MUX("IIR0 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp3_mux),
4570 SND_SOC_DAPM_MUX("IIR1 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp0_mux),
4571 SND_SOC_DAPM_MUX("IIR1 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp1_mux),
4572 SND_SOC_DAPM_MUX("IIR1 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp2_mux),
4573 SND_SOC_DAPM_MUX("IIR1 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp3_mux),
4574
4575 SND_SOC_DAPM_PGA_E("IIR0", WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL,
4576 0, 0, NULL, 0, wcd934x_codec_set_iir_gain,
4577 SND_SOC_DAPM_POST_PMU),
4578 SND_SOC_DAPM_PGA_E("IIR1", WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B1_CTL,
4579 1, 0, NULL, 0, wcd934x_codec_set_iir_gain,
4580 SND_SOC_DAPM_POST_PMU),
4581 SND_SOC_DAPM_MIXER("SRC0", WCD934X_CDC_SIDETONE_SRC0_ST_SRC_PATH_CTL,
4582 4, 0, NULL, 0),
4583 SND_SOC_DAPM_MIXER("SRC1", WCD934X_CDC_SIDETONE_SRC1_ST_SRC_PATH_CTL,
4584 4, 0, NULL, 0),
4585 SND_SOC_DAPM_MUX("RX INT0 DEM MUX", SND_SOC_NOPM, 0, 0,
4586 &rx_int0_dem_inp_mux),
4587 SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0,
4588 &rx_int1_dem_inp_mux),
4589 SND_SOC_DAPM_MUX("RX INT2 DEM MUX", SND_SOC_NOPM, 0, 0,
4590 &rx_int2_dem_inp_mux),
4591
4592 SND_SOC_DAPM_MUX_E("RX INT0_1 INTERP", SND_SOC_NOPM, INTERP_EAR, 0,
4593 &rx_int0_1_interp_mux,
4594 wcd934x_codec_enable_main_path,
4595 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4596 SND_SOC_DAPM_POST_PMD),
4597 SND_SOC_DAPM_MUX_E("RX INT1_1 INTERP", SND_SOC_NOPM, INTERP_HPHL, 0,
4598 &rx_int1_1_interp_mux,
4599 wcd934x_codec_enable_main_path,
4600 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4601 SND_SOC_DAPM_POST_PMD),
4602 SND_SOC_DAPM_MUX_E("RX INT2_1 INTERP", SND_SOC_NOPM, INTERP_HPHR, 0,
4603 &rx_int2_1_interp_mux,
4604 wcd934x_codec_enable_main_path,
4605 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4606 SND_SOC_DAPM_POST_PMD),
4607 SND_SOC_DAPM_MUX_E("RX INT3_1 INTERP", SND_SOC_NOPM, INTERP_LO1, 0,
4608 &rx_int3_1_interp_mux,
4609 wcd934x_codec_enable_main_path,
4610 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4611 SND_SOC_DAPM_POST_PMD),
4612 SND_SOC_DAPM_MUX_E("RX INT4_1 INTERP", SND_SOC_NOPM, INTERP_LO2, 0,
4613 &rx_int4_1_interp_mux,
4614 wcd934x_codec_enable_main_path,
4615 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4616 SND_SOC_DAPM_POST_PMD),
4617 SND_SOC_DAPM_MUX_E("RX INT7_1 INTERP", SND_SOC_NOPM, INTERP_SPKR1, 0,
4618 &rx_int7_1_interp_mux,
4619 wcd934x_codec_enable_main_path,
4620 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4621 SND_SOC_DAPM_POST_PMD),
4622 SND_SOC_DAPM_MUX_E("RX INT8_1 INTERP", SND_SOC_NOPM, INTERP_SPKR2, 0,
4623 &rx_int8_1_interp_mux,
4624 wcd934x_codec_enable_main_path,
4625 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4626 SND_SOC_DAPM_POST_PMD),
4627
4628 SND_SOC_DAPM_MUX("RX INT0_2 INTERP", SND_SOC_NOPM, 0, 0,
4629 &rx_int0_2_interp_mux),
4630 SND_SOC_DAPM_MUX("RX INT1_2 INTERP", SND_SOC_NOPM, 0, 0,
4631 &rx_int1_2_interp_mux),
4632 SND_SOC_DAPM_MUX("RX INT2_2 INTERP", SND_SOC_NOPM, 0, 0,
4633 &rx_int2_2_interp_mux),
4634 SND_SOC_DAPM_MUX("RX INT3_2 INTERP", SND_SOC_NOPM, 0, 0,
4635 &rx_int3_2_interp_mux),
4636 SND_SOC_DAPM_MUX("RX INT4_2 INTERP", SND_SOC_NOPM, 0, 0,
4637 &rx_int4_2_interp_mux),
4638 SND_SOC_DAPM_MUX("RX INT7_2 INTERP", SND_SOC_NOPM, 0, 0,
4639 &rx_int7_2_interp_mux),
4640 SND_SOC_DAPM_MUX("RX INT8_2 INTERP", SND_SOC_NOPM, 0, 0,
4641 &rx_int8_2_interp_mux),
4642 SND_SOC_DAPM_DAC_E("RX INT0 DAC", NULL, SND_SOC_NOPM,
4643 0, 0, wcd934x_codec_ear_dac_event,
4644 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4645 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4646 SND_SOC_DAPM_DAC_E("RX INT1 DAC", NULL, WCD934X_ANA_HPH,
4647 5, 0, wcd934x_codec_hphl_dac_event,
4648 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4649 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4650 SND_SOC_DAPM_DAC_E("RX INT2 DAC", NULL, WCD934X_ANA_HPH,
4651 4, 0, wcd934x_codec_hphr_dac_event,
4652 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4653 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4654 SND_SOC_DAPM_DAC_E("RX INT3 DAC", NULL, SND_SOC_NOPM,
4655 0, 0, wcd934x_codec_lineout_dac_event,
4656 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4657 SND_SOC_DAPM_DAC_E("RX INT4 DAC", NULL, SND_SOC_NOPM,
4658 0, 0, wcd934x_codec_lineout_dac_event,
4659 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4660 SND_SOC_DAPM_PGA_E("EAR PA", WCD934X_ANA_EAR, 7, 0, NULL, 0, NULL, 0),
4661 SND_SOC_DAPM_PGA_E("HPHL PA", WCD934X_ANA_HPH, 7, 0, NULL, 0,
4662 wcd934x_codec_enable_hphl_pa,
4663 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4664 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4665 SND_SOC_DAPM_PGA_E("HPHR PA", WCD934X_ANA_HPH, 6, 0, NULL, 0,
4666 wcd934x_codec_enable_hphr_pa,
4667 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4668 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4669 SND_SOC_DAPM_PGA_E("LINEOUT1 PA", WCD934X_ANA_LO_1_2, 7, 0, NULL, 0,
4670 NULL, 0),
4671 SND_SOC_DAPM_PGA_E("LINEOUT2 PA", WCD934X_ANA_LO_1_2, 6, 0, NULL, 0,
4672 NULL, 0),
4673 SND_SOC_DAPM_SUPPLY("RX_BIAS", WCD934X_ANA_RX_SUPPLIES, 0, 0, NULL,
4674 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4675 SND_SOC_DAPM_SUPPLY("SBOOST0", WCD934X_CDC_RX7_RX_PATH_CFG1,
4676 0, 0, NULL, 0),
4677 SND_SOC_DAPM_SUPPLY("SBOOST0_CLK", WCD934X_CDC_BOOST0_BOOST_PATH_CTL,
4678 0, 0, NULL, 0),
4679 SND_SOC_DAPM_SUPPLY("SBOOST1", WCD934X_CDC_RX8_RX_PATH_CFG1,
4680 0, 0, NULL, 0),
4681 SND_SOC_DAPM_SUPPLY("SBOOST1_CLK", WCD934X_CDC_BOOST1_BOOST_PATH_CTL,
4682 0, 0, NULL, 0),
4683 SND_SOC_DAPM_SUPPLY("INT0_CLK", SND_SOC_NOPM, INTERP_EAR, 0,
4684 wcd934x_codec_enable_interp_clk,
4685 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4686 SND_SOC_DAPM_SUPPLY("INT1_CLK", SND_SOC_NOPM, INTERP_HPHL, 0,
4687 wcd934x_codec_enable_interp_clk,
4688 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4689 SND_SOC_DAPM_SUPPLY("INT2_CLK", SND_SOC_NOPM, INTERP_HPHR, 0,
4690 wcd934x_codec_enable_interp_clk,
4691 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4692 SND_SOC_DAPM_SUPPLY("INT3_CLK", SND_SOC_NOPM, INTERP_LO1, 0,
4693 wcd934x_codec_enable_interp_clk,
4694 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4695 SND_SOC_DAPM_SUPPLY("INT4_CLK", SND_SOC_NOPM, INTERP_LO2, 0,
4696 wcd934x_codec_enable_interp_clk,
4697 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4698 SND_SOC_DAPM_SUPPLY("INT7_CLK", SND_SOC_NOPM, INTERP_SPKR1, 0,
4699 wcd934x_codec_enable_interp_clk,
4700 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4701 SND_SOC_DAPM_SUPPLY("INT8_CLK", SND_SOC_NOPM, INTERP_SPKR2, 0,
4702 wcd934x_codec_enable_interp_clk,
4703 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4704 SND_SOC_DAPM_SUPPLY("DSMDEM0_CLK", WCD934X_CDC_RX0_RX_PATH_DSMDEM_CTL,
4705 0, 0, NULL, 0),
4706 SND_SOC_DAPM_SUPPLY("DSMDEM1_CLK", WCD934X_CDC_RX1_RX_PATH_DSMDEM_CTL,
4707 0, 0, NULL, 0),
4708 SND_SOC_DAPM_SUPPLY("DSMDEM2_CLK", WCD934X_CDC_RX2_RX_PATH_DSMDEM_CTL,
4709 0, 0, NULL, 0),
4710 SND_SOC_DAPM_SUPPLY("DSMDEM3_CLK", WCD934X_CDC_RX3_RX_PATH_DSMDEM_CTL,
4711 0, 0, NULL, 0),
4712 SND_SOC_DAPM_SUPPLY("DSMDEM4_CLK", WCD934X_CDC_RX4_RX_PATH_DSMDEM_CTL,
4713 0, 0, NULL, 0),
4714 SND_SOC_DAPM_SUPPLY("DSMDEM7_CLK", WCD934X_CDC_RX7_RX_PATH_DSMDEM_CTL,
4715 0, 0, NULL, 0),
4716 SND_SOC_DAPM_SUPPLY("DSMDEM8_CLK", WCD934X_CDC_RX8_RX_PATH_DSMDEM_CTL,
4717 0, 0, NULL, 0),
4718 SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0,
4719 wcd934x_codec_enable_mclk,
4720 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4721
4722 /* TX */
4723 SND_SOC_DAPM_INPUT("AMIC1"),
4724 SND_SOC_DAPM_INPUT("AMIC2"),
4725 SND_SOC_DAPM_INPUT("AMIC3"),
4726 SND_SOC_DAPM_INPUT("AMIC4"),
4727 SND_SOC_DAPM_INPUT("AMIC5"),
4728 SND_SOC_DAPM_INPUT("DMIC0 Pin"),
4729 SND_SOC_DAPM_INPUT("DMIC1 Pin"),
4730 SND_SOC_DAPM_INPUT("DMIC2 Pin"),
4731 SND_SOC_DAPM_INPUT("DMIC3 Pin"),
4732 SND_SOC_DAPM_INPUT("DMIC4 Pin"),
4733 SND_SOC_DAPM_INPUT("DMIC5 Pin"),
4734
4735 SND_SOC_DAPM_AIF_OUT_E("AIF1 CAP", "AIF1 Capture", 0, SND_SOC_NOPM,
4736 AIF1_CAP, 0, wcd934x_codec_enable_slim,
4737 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4738 SND_SOC_DAPM_AIF_OUT_E("AIF2 CAP", "AIF2 Capture", 0, SND_SOC_NOPM,
4739 AIF2_CAP, 0, wcd934x_codec_enable_slim,
4740 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4741 SND_SOC_DAPM_AIF_OUT_E("AIF3 CAP", "AIF3 Capture", 0, SND_SOC_NOPM,
4742 AIF3_CAP, 0, wcd934x_codec_enable_slim,
4743 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4744
4745 SND_SOC_DAPM_MIXER("SLIM TX0", SND_SOC_NOPM, 0, 0, NULL, 0),
4746 SND_SOC_DAPM_MIXER("SLIM TX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4747 SND_SOC_DAPM_MIXER("SLIM TX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4748 SND_SOC_DAPM_MIXER("SLIM TX3", SND_SOC_NOPM, 0, 0, NULL, 0),
4749 SND_SOC_DAPM_MIXER("SLIM TX4", SND_SOC_NOPM, 0, 0, NULL, 0),
4750 SND_SOC_DAPM_MIXER("SLIM TX5", SND_SOC_NOPM, 0, 0, NULL, 0),
4751 SND_SOC_DAPM_MIXER("SLIM TX6", SND_SOC_NOPM, 0, 0, NULL, 0),
4752 SND_SOC_DAPM_MIXER("SLIM TX7", SND_SOC_NOPM, 0, 0, NULL, 0),
4753 SND_SOC_DAPM_MIXER("SLIM TX8", SND_SOC_NOPM, 0, 0, NULL, 0),
4754 SND_SOC_DAPM_MIXER("SLIM TX9", SND_SOC_NOPM, 0, 0, NULL, 0),
4755 SND_SOC_DAPM_MIXER("SLIM TX10", SND_SOC_NOPM, 0, 0, NULL, 0),
4756 SND_SOC_DAPM_MIXER("SLIM TX11", SND_SOC_NOPM, 0, 0, NULL, 0),
4757 SND_SOC_DAPM_MIXER("SLIM TX13", SND_SOC_NOPM, 0, 0, NULL, 0),
4758
4759 /* Digital Mic Inputs */
4760 SND_SOC_DAPM_ADC_E("DMIC0", NULL, SND_SOC_NOPM, 0, 0,
4761 wcd934x_codec_enable_dmic,
4762 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4763 SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
4764 wcd934x_codec_enable_dmic,
4765 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4766 SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0,
4767 wcd934x_codec_enable_dmic,
4768 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4769 SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 0, 0,
4770 wcd934x_codec_enable_dmic,
4771 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4772 SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 0, 0,
4773 wcd934x_codec_enable_dmic,
4774 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4775 SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 0, 0,
4776 wcd934x_codec_enable_dmic,
4777 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4778 SND_SOC_DAPM_MUX("DMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_dmic_mux0),
4779 SND_SOC_DAPM_MUX("DMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_dmic_mux1),
4780 SND_SOC_DAPM_MUX("DMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_dmic_mux2),
4781 SND_SOC_DAPM_MUX("DMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_dmic_mux3),
4782 SND_SOC_DAPM_MUX("DMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_dmic_mux4),
4783 SND_SOC_DAPM_MUX("DMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_dmic_mux5),
4784 SND_SOC_DAPM_MUX("DMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_dmic_mux6),
4785 SND_SOC_DAPM_MUX("DMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_dmic_mux7),
4786 SND_SOC_DAPM_MUX("DMIC MUX8", SND_SOC_NOPM, 0, 0, &tx_dmic_mux8),
4787 SND_SOC_DAPM_MUX("AMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_amic_mux0),
4788 SND_SOC_DAPM_MUX("AMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_amic_mux1),
4789 SND_SOC_DAPM_MUX("AMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_amic_mux2),
4790 SND_SOC_DAPM_MUX("AMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_amic_mux3),
4791 SND_SOC_DAPM_MUX("AMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_amic_mux4),
4792 SND_SOC_DAPM_MUX("AMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_amic_mux5),
4793 SND_SOC_DAPM_MUX("AMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_amic_mux6),
4794 SND_SOC_DAPM_MUX("AMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_amic_mux7),
4795 SND_SOC_DAPM_MUX("AMIC MUX8", SND_SOC_NOPM, 0, 0, &tx_amic_mux8),
4796 SND_SOC_DAPM_MUX_E("ADC MUX0", WCD934X_CDC_TX0_TX_PATH_CTL, 5, 0,
4797 &tx_adc_mux0_mux, wcd934x_codec_enable_dec,
4798 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4799 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4800 SND_SOC_DAPM_MUX_E("ADC MUX1", WCD934X_CDC_TX1_TX_PATH_CTL, 5, 0,
4801 &tx_adc_mux1_mux, wcd934x_codec_enable_dec,
4802 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4803 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4804 SND_SOC_DAPM_MUX_E("ADC MUX2", WCD934X_CDC_TX2_TX_PATH_CTL, 5, 0,
4805 &tx_adc_mux2_mux, wcd934x_codec_enable_dec,
4806 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4807 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4808 SND_SOC_DAPM_MUX_E("ADC MUX3", WCD934X_CDC_TX3_TX_PATH_CTL, 5, 0,
4809 &tx_adc_mux3_mux, wcd934x_codec_enable_dec,
4810 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4811 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4812 SND_SOC_DAPM_MUX_E("ADC MUX4", WCD934X_CDC_TX4_TX_PATH_CTL, 5, 0,
4813 &tx_adc_mux4_mux, wcd934x_codec_enable_dec,
4814 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4815 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4816 SND_SOC_DAPM_MUX_E("ADC MUX5", WCD934X_CDC_TX5_TX_PATH_CTL, 5, 0,
4817 &tx_adc_mux5_mux, wcd934x_codec_enable_dec,
4818 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4819 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4820 SND_SOC_DAPM_MUX_E("ADC MUX6", WCD934X_CDC_TX6_TX_PATH_CTL, 5, 0,
4821 &tx_adc_mux6_mux, wcd934x_codec_enable_dec,
4822 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4823 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4824 SND_SOC_DAPM_MUX_E("ADC MUX7", WCD934X_CDC_TX7_TX_PATH_CTL, 5, 0,
4825 &tx_adc_mux7_mux, wcd934x_codec_enable_dec,
4826 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4827 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4828 SND_SOC_DAPM_MUX_E("ADC MUX8", WCD934X_CDC_TX8_TX_PATH_CTL, 5, 0,
4829 &tx_adc_mux8_mux, wcd934x_codec_enable_dec,
4830 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4831 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4832 SND_SOC_DAPM_ADC_E("ADC1", NULL, WCD934X_ANA_AMIC1, 7, 0,
4833 wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4834 SND_SOC_DAPM_ADC_E("ADC2", NULL, WCD934X_ANA_AMIC2, 7, 0,
4835 wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4836 SND_SOC_DAPM_ADC_E("ADC3", NULL, WCD934X_ANA_AMIC3, 7, 0,
4837 wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4838 SND_SOC_DAPM_ADC_E("ADC4", NULL, WCD934X_ANA_AMIC4, 7, 0,
4839 wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4840 SND_SOC_DAPM_SUPPLY("MIC BIAS1", WCD934X_ANA_MICB1, 6, 0, NULL,
4841 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4842 SND_SOC_DAPM_SUPPLY("MIC BIAS2", WCD934X_ANA_MICB2, 6, 0, NULL,
4843 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4844 SND_SOC_DAPM_SUPPLY("MIC BIAS3", WCD934X_ANA_MICB3, 6, 0, NULL,
4845 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4846 SND_SOC_DAPM_SUPPLY("MIC BIAS4", WCD934X_ANA_MICB4, 6, 0, NULL,
4847 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4848
4849 SND_SOC_DAPM_MUX("AMIC4_5 SEL", SND_SOC_NOPM, 0, 0, &tx_amic4_5),
4850 SND_SOC_DAPM_MUX("CDC_IF TX0 MUX", SND_SOC_NOPM, WCD934X_TX0, 0,
4851 &cdc_if_tx0_mux),
4852 SND_SOC_DAPM_MUX("CDC_IF TX1 MUX", SND_SOC_NOPM, WCD934X_TX1, 0,
4853 &cdc_if_tx1_mux),
4854 SND_SOC_DAPM_MUX("CDC_IF TX2 MUX", SND_SOC_NOPM, WCD934X_TX2, 0,
4855 &cdc_if_tx2_mux),
4856 SND_SOC_DAPM_MUX("CDC_IF TX3 MUX", SND_SOC_NOPM, WCD934X_TX3, 0,
4857 &cdc_if_tx3_mux),
4858 SND_SOC_DAPM_MUX("CDC_IF TX4 MUX", SND_SOC_NOPM, WCD934X_TX4, 0,
4859 &cdc_if_tx4_mux),
4860 SND_SOC_DAPM_MUX("CDC_IF TX5 MUX", SND_SOC_NOPM, WCD934X_TX5, 0,
4861 &cdc_if_tx5_mux),
4862 SND_SOC_DAPM_MUX("CDC_IF TX6 MUX", SND_SOC_NOPM, WCD934X_TX6, 0,
4863 &cdc_if_tx6_mux),
4864 SND_SOC_DAPM_MUX("CDC_IF TX7 MUX", SND_SOC_NOPM, WCD934X_TX7, 0,
4865 &cdc_if_tx7_mux),
4866 SND_SOC_DAPM_MUX("CDC_IF TX8 MUX", SND_SOC_NOPM, WCD934X_TX8, 0,
4867 &cdc_if_tx8_mux),
4868 SND_SOC_DAPM_MUX("CDC_IF TX9 MUX", SND_SOC_NOPM, WCD934X_TX9, 0,
4869 &cdc_if_tx9_mux),
4870 SND_SOC_DAPM_MUX("CDC_IF TX10 MUX", SND_SOC_NOPM, WCD934X_TX10, 0,
4871 &cdc_if_tx10_mux),
4872 SND_SOC_DAPM_MUX("CDC_IF TX11 MUX", SND_SOC_NOPM, WCD934X_TX11, 0,
4873 &cdc_if_tx11_mux),
4874 SND_SOC_DAPM_MUX("CDC_IF TX11 INP1 MUX", SND_SOC_NOPM, WCD934X_TX11, 0,
4875 &cdc_if_tx11_inp1_mux),
4876 SND_SOC_DAPM_MUX("CDC_IF TX13 MUX", SND_SOC_NOPM, WCD934X_TX13, 0,
4877 &cdc_if_tx13_mux),
4878 SND_SOC_DAPM_MUX("CDC_IF TX13 INP1 MUX", SND_SOC_NOPM, WCD934X_TX13, 0,
4879 &cdc_if_tx13_inp1_mux),
4880 SND_SOC_DAPM_MIXER("AIF1_CAP Mixer", SND_SOC_NOPM, AIF1_CAP, 0,
4881 aif1_slim_cap_mixer,
4882 ARRAY_SIZE(aif1_slim_cap_mixer)),
4883 SND_SOC_DAPM_MIXER("AIF2_CAP Mixer", SND_SOC_NOPM, AIF2_CAP, 0,
4884 aif2_slim_cap_mixer,
4885 ARRAY_SIZE(aif2_slim_cap_mixer)),
4886 SND_SOC_DAPM_MIXER("AIF3_CAP Mixer", SND_SOC_NOPM, AIF3_CAP, 0,
4887 aif3_slim_cap_mixer,
4888 ARRAY_SIZE(aif3_slim_cap_mixer)),
4889 };
4890
4891 static const struct snd_soc_dapm_route wcd934x_audio_map[] = {
4892 /* RX0-RX7 */
4893 WCD934X_SLIM_RX_AIF_PATH(0),
4894 WCD934X_SLIM_RX_AIF_PATH(1),
4895 WCD934X_SLIM_RX_AIF_PATH(2),
4896 WCD934X_SLIM_RX_AIF_PATH(3),
4897 WCD934X_SLIM_RX_AIF_PATH(4),
4898 WCD934X_SLIM_RX_AIF_PATH(5),
4899 WCD934X_SLIM_RX_AIF_PATH(6),
4900 WCD934X_SLIM_RX_AIF_PATH(7),
4901
4902 /* RX0 Ear out */
4903 WCD934X_INTERPOLATOR_PATH(0),
4904 WCD934X_INTERPOLATOR_MIX2(0),
4905 {"RX INT0 DEM MUX", "CLSH_DSM_OUT", "RX INT0 MIX2"},
4906 {"RX INT0 DAC", NULL, "RX INT0 DEM MUX"},
4907 {"RX INT0 DAC", NULL, "RX_BIAS"},
4908 {"EAR PA", NULL, "RX INT0 DAC"},
4909 {"EAR", NULL, "EAR PA"},
4910
4911 /* RX1 Headphone left */
4912 WCD934X_INTERPOLATOR_PATH(1),
4913 WCD934X_INTERPOLATOR_MIX2(1),
4914 {"RX INT1 MIX3", NULL, "RX INT1 MIX2"},
4915 {"RX INT1 DEM MUX", "CLSH_DSM_OUT", "RX INT1 MIX3"},
4916 {"RX INT1 DAC", NULL, "RX INT1 DEM MUX"},
4917 {"RX INT1 DAC", NULL, "RX_BIAS"},
4918 {"HPHL PA", NULL, "RX INT1 DAC"},
4919 {"HPHL", NULL, "HPHL PA"},
4920
4921 /* RX2 Headphone right */
4922 WCD934X_INTERPOLATOR_PATH(2),
4923 WCD934X_INTERPOLATOR_MIX2(2),
4924 {"RX INT2 MIX3", NULL, "RX INT2 MIX2"},
4925 {"RX INT2 DEM MUX", "CLSH_DSM_OUT", "RX INT2 MIX3"},
4926 {"RX INT2 DAC", NULL, "RX INT2 DEM MUX"},
4927 {"RX INT2 DAC", NULL, "RX_BIAS"},
4928 {"HPHR PA", NULL, "RX INT2 DAC"},
4929 {"HPHR", NULL, "HPHR PA"},
4930
4931 /* RX3 HIFi LineOut1 */
4932 WCD934X_INTERPOLATOR_PATH(3),
4933 WCD934X_INTERPOLATOR_MIX2(3),
4934 {"RX INT3 MIX3", NULL, "RX INT3 MIX2"},
4935 {"RX INT3 DAC", NULL, "RX INT3 MIX3"},
4936 {"RX INT3 DAC", NULL, "RX_BIAS"},
4937 {"LINEOUT1 PA", NULL, "RX INT3 DAC"},
4938 {"LINEOUT1", NULL, "LINEOUT1 PA"},
4939
4940 /* RX4 HIFi LineOut2 */
4941 WCD934X_INTERPOLATOR_PATH(4),
4942 WCD934X_INTERPOLATOR_MIX2(4),
4943 {"RX INT4 MIX3", NULL, "RX INT4 MIX2"},
4944 {"RX INT4 DAC", NULL, "RX INT4 MIX3"},
4945 {"RX INT4 DAC", NULL, "RX_BIAS"},
4946 {"LINEOUT2 PA", NULL, "RX INT4 DAC"},
4947 {"LINEOUT2", NULL, "LINEOUT2 PA"},
4948
4949 /* RX7 Speaker Left Out PA */
4950 WCD934X_INTERPOLATOR_PATH(7),
4951 WCD934X_INTERPOLATOR_MIX2(7),
4952 {"RX INT7 CHAIN", NULL, "RX INT7 MIX2"},
4953 {"RX INT7 CHAIN", NULL, "RX_BIAS"},
4954 {"RX INT7 CHAIN", NULL, "SBOOST0"},
4955 {"RX INT7 CHAIN", NULL, "SBOOST0_CLK"},
4956 {"SPK1 OUT", NULL, "RX INT7 CHAIN"},
4957
4958 /* RX8 Speaker Right Out PA */
4959 WCD934X_INTERPOLATOR_PATH(8),
4960 {"RX INT8 CHAIN", NULL, "RX INT8 SEC MIX"},
4961 {"RX INT8 CHAIN", NULL, "RX_BIAS"},
4962 {"RX INT8 CHAIN", NULL, "SBOOST1"},
4963 {"RX INT8 CHAIN", NULL, "SBOOST1_CLK"},
4964 {"SPK2 OUT", NULL, "RX INT8 CHAIN"},
4965
4966 /* Tx */
4967 {"AIF1 CAP", NULL, "AIF1_CAP Mixer"},
4968 {"AIF2 CAP", NULL, "AIF2_CAP Mixer"},
4969 {"AIF3 CAP", NULL, "AIF3_CAP Mixer"},
4970
4971 WCD934X_SLIM_TX_AIF_PATH(0),
4972 WCD934X_SLIM_TX_AIF_PATH(1),
4973 WCD934X_SLIM_TX_AIF_PATH(2),
4974 WCD934X_SLIM_TX_AIF_PATH(3),
4975 WCD934X_SLIM_TX_AIF_PATH(4),
4976 WCD934X_SLIM_TX_AIF_PATH(5),
4977 WCD934X_SLIM_TX_AIF_PATH(6),
4978 WCD934X_SLIM_TX_AIF_PATH(7),
4979 WCD934X_SLIM_TX_AIF_PATH(8),
4980
4981 WCD934X_ADC_MUX(0),
4982 WCD934X_ADC_MUX(1),
4983 WCD934X_ADC_MUX(2),
4984 WCD934X_ADC_MUX(3),
4985 WCD934X_ADC_MUX(4),
4986 WCD934X_ADC_MUX(5),
4987 WCD934X_ADC_MUX(6),
4988 WCD934X_ADC_MUX(7),
4989 WCD934X_ADC_MUX(8),
4990
4991 {"CDC_IF TX0 MUX", "DEC0", "ADC MUX0"},
4992 {"CDC_IF TX1 MUX", "DEC1", "ADC MUX1"},
4993 {"CDC_IF TX2 MUX", "DEC2", "ADC MUX2"},
4994 {"CDC_IF TX3 MUX", "DEC3", "ADC MUX3"},
4995 {"CDC_IF TX4 MUX", "DEC4", "ADC MUX4"},
4996 {"CDC_IF TX5 MUX", "DEC5", "ADC MUX5"},
4997 {"CDC_IF TX6 MUX", "DEC6", "ADC MUX6"},
4998 {"CDC_IF TX7 MUX", "DEC7", "ADC MUX7"},
4999 {"CDC_IF TX8 MUX", "DEC8", "ADC MUX8"},
5000
5001 {"AMIC4_5 SEL", "AMIC4", "AMIC4"},
5002 {"AMIC4_5 SEL", "AMIC5", "AMIC5"},
5003
5004 { "DMIC0", NULL, "DMIC0 Pin" },
5005 { "DMIC1", NULL, "DMIC1 Pin" },
5006 { "DMIC2", NULL, "DMIC2 Pin" },
5007 { "DMIC3", NULL, "DMIC3 Pin" },
5008 { "DMIC4", NULL, "DMIC4 Pin" },
5009 { "DMIC5", NULL, "DMIC5 Pin" },
5010
5011 {"ADC1", NULL, "AMIC1"},
5012 {"ADC2", NULL, "AMIC2"},
5013 {"ADC3", NULL, "AMIC3"},
5014 {"ADC4", NULL, "AMIC4_5 SEL"},
5015
5016 WCD934X_IIR_INP_MUX(0),
5017 WCD934X_IIR_INP_MUX(1),
5018
5019 {"SRC0", NULL, "IIR0"},
5020 {"SRC1", NULL, "IIR1"},
5021 };
5022
5023 static const struct snd_soc_component_driver wcd934x_component_drv = {
5024 .probe = wcd934x_comp_probe,
5025 .remove = wcd934x_comp_remove,
5026 .set_sysclk = wcd934x_comp_set_sysclk,
5027 .controls = wcd934x_snd_controls,
5028 .num_controls = ARRAY_SIZE(wcd934x_snd_controls),
5029 .dapm_widgets = wcd934x_dapm_widgets,
5030 .num_dapm_widgets = ARRAY_SIZE(wcd934x_dapm_widgets),
5031 .dapm_routes = wcd934x_audio_map,
5032 .num_dapm_routes = ARRAY_SIZE(wcd934x_audio_map),
5033 };
5034
wcd934x_codec_parse_data(struct wcd934x_codec * wcd)5035 static int wcd934x_codec_parse_data(struct wcd934x_codec *wcd)
5036 {
5037 struct device *dev = &wcd->sdev->dev;
5038 struct device_node *ifc_dev_np;
5039
5040 ifc_dev_np = of_parse_phandle(dev->of_node, "slim-ifc-dev", 0);
5041 if (!ifc_dev_np) {
5042 dev_err(dev, "No Interface device found\n");
5043 return -EINVAL;
5044 }
5045
5046 wcd->sidev = of_slim_get_device(wcd->sdev->ctrl, ifc_dev_np);
5047 if (!wcd->sidev) {
5048 dev_err(dev, "Unable to get SLIM Interface device\n");
5049 return -EINVAL;
5050 }
5051
5052 slim_get_logical_addr(wcd->sidev);
5053 wcd->if_regmap = regmap_init_slimbus(wcd->sidev,
5054 &wcd934x_ifc_regmap_config);
5055 if (IS_ERR(wcd->if_regmap)) {
5056 dev_err(dev, "Failed to allocate ifc register map\n");
5057 return PTR_ERR(wcd->if_regmap);
5058 }
5059
5060 of_property_read_u32(dev->parent->of_node, "qcom,dmic-sample-rate",
5061 &wcd->dmic_sample_rate);
5062
5063 return 0;
5064 }
5065
wcd934x_codec_probe(struct platform_device * pdev)5066 static int wcd934x_codec_probe(struct platform_device *pdev)
5067 {
5068 struct wcd934x_ddata *data = dev_get_drvdata(pdev->dev.parent);
5069 struct wcd934x_codec *wcd;
5070 struct device *dev = &pdev->dev;
5071 int ret, irq;
5072
5073 wcd = devm_kzalloc(&pdev->dev, sizeof(*wcd), GFP_KERNEL);
5074 if (!wcd)
5075 return -ENOMEM;
5076
5077 wcd->dev = dev;
5078 wcd->regmap = data->regmap;
5079 wcd->extclk = data->extclk;
5080 wcd->sdev = to_slim_device(data->dev);
5081 mutex_init(&wcd->sysclk_mutex);
5082
5083 ret = wcd934x_codec_parse_data(wcd);
5084 if (ret) {
5085 dev_err(wcd->dev, "Failed to get SLIM IRQ\n");
5086 return ret;
5087 }
5088
5089 /* set default rate 9P6MHz */
5090 regmap_update_bits(wcd->regmap, WCD934X_CODEC_RPM_CLK_MCLK_CFG,
5091 WCD934X_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
5092 WCD934X_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ);
5093 memcpy(wcd->rx_chs, wcd934x_rx_chs, sizeof(wcd934x_rx_chs));
5094 memcpy(wcd->tx_chs, wcd934x_tx_chs, sizeof(wcd934x_tx_chs));
5095
5096 irq = regmap_irq_get_virq(data->irq_data, WCD934X_IRQ_SLIMBUS);
5097 if (irq < 0) {
5098 dev_err(wcd->dev, "Failed to get SLIM IRQ\n");
5099 return irq;
5100 }
5101
5102 ret = devm_request_threaded_irq(dev, irq, NULL,
5103 wcd934x_slim_irq_handler,
5104 IRQF_TRIGGER_RISING,
5105 "slim", wcd);
5106 if (ret) {
5107 dev_err(dev, "Failed to request slimbus irq\n");
5108 return ret;
5109 }
5110
5111 wcd934x_register_mclk_output(wcd);
5112 platform_set_drvdata(pdev, wcd);
5113
5114 return devm_snd_soc_register_component(dev, &wcd934x_component_drv,
5115 wcd934x_slim_dais,
5116 ARRAY_SIZE(wcd934x_slim_dais));
5117 }
5118
5119 static const struct platform_device_id wcd934x_driver_id[] = {
5120 {
5121 .name = "wcd934x-codec",
5122 },
5123 {},
5124 };
5125 MODULE_DEVICE_TABLE(platform, wcd934x_driver_id);
5126
5127 static struct platform_driver wcd934x_codec_driver = {
5128 .probe = &wcd934x_codec_probe,
5129 .id_table = wcd934x_driver_id,
5130 .driver = {
5131 .name = "wcd934x-codec",
5132 }
5133 };
5134
5135 MODULE_ALIAS("platform:wcd934x-codec");
5136 module_platform_driver(wcd934x_codec_driver);
5137 MODULE_DESCRIPTION("WCD934x codec driver");
5138 MODULE_LICENSE("GPL v2");
5139