1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef _UAPI_I915_DRM_H_ 20 #define _UAPI_I915_DRM_H_ 21 #include "drm.h" 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 #define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR" 26 #define I915_ERROR_UEVENT "ERROR" 27 #define I915_RESET_UEVENT "RESET" 28 struct i915_user_extension { 29 __u64 next_extension; 30 __u32 name; 31 __u32 flags; 32 __u32 rsvd[4]; 33 }; 34 enum i915_mocs_table_index { 35 I915_MOCS_UNCACHED, 36 I915_MOCS_PTE, 37 I915_MOCS_CACHED, 38 }; 39 enum drm_i915_gem_engine_class { 40 I915_ENGINE_CLASS_RENDER = 0, 41 I915_ENGINE_CLASS_COPY = 1, 42 I915_ENGINE_CLASS_VIDEO = 2, 43 I915_ENGINE_CLASS_VIDEO_ENHANCE = 3, 44 I915_ENGINE_CLASS_INVALID = - 1 45 }; 46 struct i915_engine_class_instance { 47 __u16 engine_class; 48 __u16 engine_instance; 49 #define I915_ENGINE_CLASS_INVALID_NONE - 1 50 #define I915_ENGINE_CLASS_INVALID_VIRTUAL - 2 51 }; 52 enum drm_i915_pmu_engine_sample { 53 I915_SAMPLE_BUSY = 0, 54 I915_SAMPLE_WAIT = 1, 55 I915_SAMPLE_SEMA = 2 56 }; 57 #define I915_PMU_SAMPLE_BITS (4) 58 #define I915_PMU_SAMPLE_MASK (0xf) 59 #define I915_PMU_SAMPLE_INSTANCE_BITS (8) 60 #define I915_PMU_CLASS_SHIFT (I915_PMU_SAMPLE_BITS + I915_PMU_SAMPLE_INSTANCE_BITS) 61 #define __I915_PMU_ENGINE(class,instance,sample) ((class) << I915_PMU_CLASS_SHIFT | (instance) << I915_PMU_SAMPLE_BITS | (sample)) 62 #define I915_PMU_ENGINE_BUSY(class,instance) __I915_PMU_ENGINE(class, instance, I915_SAMPLE_BUSY) 63 #define I915_PMU_ENGINE_WAIT(class,instance) __I915_PMU_ENGINE(class, instance, I915_SAMPLE_WAIT) 64 #define I915_PMU_ENGINE_SEMA(class,instance) __I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA) 65 #define __I915_PMU_OTHER(x) (__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x)) 66 #define I915_PMU_ACTUAL_FREQUENCY __I915_PMU_OTHER(0) 67 #define I915_PMU_REQUESTED_FREQUENCY __I915_PMU_OTHER(1) 68 #define I915_PMU_INTERRUPTS __I915_PMU_OTHER(2) 69 #define I915_PMU_RC6_RESIDENCY __I915_PMU_OTHER(3) 70 #define I915_PMU_LAST I915_PMU_RC6_RESIDENCY 71 #define I915_NR_TEX_REGIONS 255 72 #define I915_LOG_MIN_TEX_REGION_SIZE 14 73 typedef struct _drm_i915_init { 74 enum { 75 I915_INIT_DMA = 0x01, 76 I915_CLEANUP_DMA = 0x02, 77 I915_RESUME_DMA = 0x03 78 } func; 79 unsigned int mmio_offset; 80 int sarea_priv_offset; 81 unsigned int ring_start; 82 unsigned int ring_end; 83 unsigned int ring_size; 84 unsigned int front_offset; 85 unsigned int back_offset; 86 unsigned int depth_offset; 87 unsigned int w; 88 unsigned int h; 89 unsigned int pitch; 90 unsigned int pitch_bits; 91 unsigned int back_pitch; 92 unsigned int depth_pitch; 93 unsigned int cpp; 94 unsigned int chipset; 95 } drm_i915_init_t; 96 typedef struct _drm_i915_sarea { 97 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; 98 int last_upload; 99 int last_enqueue; 100 int last_dispatch; 101 int ctxOwner; 102 int texAge; 103 int pf_enabled; 104 int pf_active; 105 int pf_current_page; 106 int perf_boxes; 107 int width, height; 108 drm_handle_t front_handle; 109 int front_offset; 110 int front_size; 111 drm_handle_t back_handle; 112 int back_offset; 113 int back_size; 114 drm_handle_t depth_handle; 115 int depth_offset; 116 int depth_size; 117 drm_handle_t tex_handle; 118 int tex_offset; 119 int tex_size; 120 int log_tex_granularity; 121 int pitch; 122 int rotation; 123 int rotated_offset; 124 int rotated_size; 125 int rotated_pitch; 126 int virtualX, virtualY; 127 unsigned int front_tiled; 128 unsigned int back_tiled; 129 unsigned int depth_tiled; 130 unsigned int rotated_tiled; 131 unsigned int rotated2_tiled; 132 int pipeA_x; 133 int pipeA_y; 134 int pipeA_w; 135 int pipeA_h; 136 int pipeB_x; 137 int pipeB_y; 138 int pipeB_w; 139 int pipeB_h; 140 drm_handle_t unused_handle; 141 __u32 unused1, unused2, unused3; 142 __u32 front_bo_handle; 143 __u32 back_bo_handle; 144 __u32 unused_bo_handle; 145 __u32 depth_bo_handle; 146 } drm_i915_sarea_t; 147 #define planeA_x pipeA_x 148 #define planeA_y pipeA_y 149 #define planeA_w pipeA_w 150 #define planeA_h pipeA_h 151 #define planeB_x pipeB_x 152 #define planeB_y pipeB_y 153 #define planeB_w pipeB_w 154 #define planeB_h pipeB_h 155 #define I915_BOX_RING_EMPTY 0x1 156 #define I915_BOX_FLIP 0x2 157 #define I915_BOX_WAIT 0x4 158 #define I915_BOX_TEXTURE_LOAD 0x8 159 #define I915_BOX_LOST_CONTEXT 0x10 160 #define DRM_I915_INIT 0x00 161 #define DRM_I915_FLUSH 0x01 162 #define DRM_I915_FLIP 0x02 163 #define DRM_I915_BATCHBUFFER 0x03 164 #define DRM_I915_IRQ_EMIT 0x04 165 #define DRM_I915_IRQ_WAIT 0x05 166 #define DRM_I915_GETPARAM 0x06 167 #define DRM_I915_SETPARAM 0x07 168 #define DRM_I915_ALLOC 0x08 169 #define DRM_I915_FREE 0x09 170 #define DRM_I915_INIT_HEAP 0x0a 171 #define DRM_I915_CMDBUFFER 0x0b 172 #define DRM_I915_DESTROY_HEAP 0x0c 173 #define DRM_I915_SET_VBLANK_PIPE 0x0d 174 #define DRM_I915_GET_VBLANK_PIPE 0x0e 175 #define DRM_I915_VBLANK_SWAP 0x0f 176 #define DRM_I915_HWS_ADDR 0x11 177 #define DRM_I915_GEM_INIT 0x13 178 #define DRM_I915_GEM_EXECBUFFER 0x14 179 #define DRM_I915_GEM_PIN 0x15 180 #define DRM_I915_GEM_UNPIN 0x16 181 #define DRM_I915_GEM_BUSY 0x17 182 #define DRM_I915_GEM_THROTTLE 0x18 183 #define DRM_I915_GEM_ENTERVT 0x19 184 #define DRM_I915_GEM_LEAVEVT 0x1a 185 #define DRM_I915_GEM_CREATE 0x1b 186 #define DRM_I915_GEM_PREAD 0x1c 187 #define DRM_I915_GEM_PWRITE 0x1d 188 #define DRM_I915_GEM_MMAP 0x1e 189 #define DRM_I915_GEM_SET_DOMAIN 0x1f 190 #define DRM_I915_GEM_SW_FINISH 0x20 191 #define DRM_I915_GEM_SET_TILING 0x21 192 #define DRM_I915_GEM_GET_TILING 0x22 193 #define DRM_I915_GEM_GET_APERTURE 0x23 194 #define DRM_I915_GEM_MMAP_GTT 0x24 195 #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 196 #define DRM_I915_GEM_MADVISE 0x26 197 #define DRM_I915_OVERLAY_PUT_IMAGE 0x27 198 #define DRM_I915_OVERLAY_ATTRS 0x28 199 #define DRM_I915_GEM_EXECBUFFER2 0x29 200 #define DRM_I915_GEM_EXECBUFFER2_WR DRM_I915_GEM_EXECBUFFER2 201 #define DRM_I915_GET_SPRITE_COLORKEY 0x2a 202 #define DRM_I915_SET_SPRITE_COLORKEY 0x2b 203 #define DRM_I915_GEM_WAIT 0x2c 204 #define DRM_I915_GEM_CONTEXT_CREATE 0x2d 205 #define DRM_I915_GEM_CONTEXT_DESTROY 0x2e 206 #define DRM_I915_GEM_SET_CACHING 0x2f 207 #define DRM_I915_GEM_GET_CACHING 0x30 208 #define DRM_I915_REG_READ 0x31 209 #define DRM_I915_GET_RESET_STATS 0x32 210 #define DRM_I915_GEM_USERPTR 0x33 211 #define DRM_I915_GEM_CONTEXT_GETPARAM 0x34 212 #define DRM_I915_GEM_CONTEXT_SETPARAM 0x35 213 #define DRM_I915_PERF_OPEN 0x36 214 #define DRM_I915_PERF_ADD_CONFIG 0x37 215 #define DRM_I915_PERF_REMOVE_CONFIG 0x38 216 #define DRM_I915_QUERY 0x39 217 #define DRM_I915_GEM_VM_CREATE 0x3a 218 #define DRM_I915_GEM_VM_DESTROY 0x3b 219 #define DRM_IOCTL_I915_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 220 #define DRM_IOCTL_I915_FLUSH DRM_IO(DRM_COMMAND_BASE + DRM_I915_FLUSH) 221 #define DRM_IOCTL_I915_FLIP DRM_IO(DRM_COMMAND_BASE + DRM_I915_FLIP) 222 #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) 223 #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) 224 #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) 225 #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) 226 #define DRM_IOCTL_I915_SETPARAM DRM_IOW(DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) 227 #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) 228 #define DRM_IOCTL_I915_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) 229 #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW(DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) 230 #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) 231 #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW(DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) 232 #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 233 #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR(DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 234 #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) 235 #define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init) 236 #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) 237 #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) 238 #define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) 239 #define DRM_IOCTL_I915_GEM_EXECBUFFER2_WR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2_WR, struct drm_i915_gem_execbuffer2) 240 #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) 241 #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) 242 #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) 243 #define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching) 244 #define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching) 245 #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) 246 #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) 247 #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) 248 #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) 249 #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) 250 #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) 251 #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) 252 #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) 253 #define DRM_IOCTL_I915_GEM_MMAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_offset) 254 #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) 255 #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) 256 #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) 257 #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) 258 #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) 259 #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) 260 #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) 261 #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) 262 #define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) 263 #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 264 #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 265 #define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) 266 #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) 267 #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create_ext) 268 #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) 269 #define DRM_IOCTL_I915_REG_READ DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) 270 #define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats) 271 #define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr) 272 #define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param) 273 #define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param) 274 #define DRM_IOCTL_I915_PERF_OPEN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param) 275 #define DRM_IOCTL_I915_PERF_ADD_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config) 276 #define DRM_IOCTL_I915_PERF_REMOVE_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64) 277 #define DRM_IOCTL_I915_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query) 278 #define DRM_IOCTL_I915_GEM_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_VM_CREATE, struct drm_i915_gem_vm_control) 279 #define DRM_IOCTL_I915_GEM_VM_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_VM_DESTROY, struct drm_i915_gem_vm_control) 280 typedef struct drm_i915_batchbuffer { 281 int start; 282 int used; 283 int DR1; 284 int DR4; 285 int num_cliprects; 286 struct drm_clip_rect __user * cliprects; 287 } drm_i915_batchbuffer_t; 288 typedef struct _drm_i915_cmdbuffer { 289 char __user * buf; 290 int sz; 291 int DR1; 292 int DR4; 293 int num_cliprects; 294 struct drm_clip_rect __user * cliprects; 295 } drm_i915_cmdbuffer_t; 296 typedef struct drm_i915_irq_emit { 297 int __user * irq_seq; 298 } drm_i915_irq_emit_t; 299 typedef struct drm_i915_irq_wait { 300 int irq_seq; 301 } drm_i915_irq_wait_t; 302 #define I915_GEM_PPGTT_NONE 0 303 #define I915_GEM_PPGTT_ALIASING 1 304 #define I915_GEM_PPGTT_FULL 2 305 #define I915_PARAM_IRQ_ACTIVE 1 306 #define I915_PARAM_ALLOW_BATCHBUFFER 2 307 #define I915_PARAM_LAST_DISPATCH 3 308 #define I915_PARAM_CHIPSET_ID 4 309 #define I915_PARAM_HAS_GEM 5 310 #define I915_PARAM_NUM_FENCES_AVAIL 6 311 #define I915_PARAM_HAS_OVERLAY 7 312 #define I915_PARAM_HAS_PAGEFLIPPING 8 313 #define I915_PARAM_HAS_EXECBUF2 9 314 #define I915_PARAM_HAS_BSD 10 315 #define I915_PARAM_HAS_BLT 11 316 #define I915_PARAM_HAS_RELAXED_FENCING 12 317 #define I915_PARAM_HAS_COHERENT_RINGS 13 318 #define I915_PARAM_HAS_EXEC_CONSTANTS 14 319 #define I915_PARAM_HAS_RELAXED_DELTA 15 320 #define I915_PARAM_HAS_GEN7_SOL_RESET 16 321 #define I915_PARAM_HAS_LLC 17 322 #define I915_PARAM_HAS_ALIASING_PPGTT 18 323 #define I915_PARAM_HAS_WAIT_TIMEOUT 19 324 #define I915_PARAM_HAS_SEMAPHORES 20 325 #define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21 326 #define I915_PARAM_HAS_VEBOX 22 327 #define I915_PARAM_HAS_SECURE_BATCHES 23 328 #define I915_PARAM_HAS_PINNED_BATCHES 24 329 #define I915_PARAM_HAS_EXEC_NO_RELOC 25 330 #define I915_PARAM_HAS_EXEC_HANDLE_LUT 26 331 #define I915_PARAM_HAS_WT 27 332 #define I915_PARAM_CMD_PARSER_VERSION 28 333 #define I915_PARAM_HAS_COHERENT_PHYS_GTT 29 334 #define I915_PARAM_MMAP_VERSION 30 335 #define I915_PARAM_HAS_BSD2 31 336 #define I915_PARAM_REVISION 32 337 #define I915_PARAM_SUBSLICE_TOTAL 33 338 #define I915_PARAM_EU_TOTAL 34 339 #define I915_PARAM_HAS_GPU_RESET 35 340 #define I915_PARAM_HAS_RESOURCE_STREAMER 36 341 #define I915_PARAM_HAS_EXEC_SOFTPIN 37 342 #define I915_PARAM_HAS_POOLED_EU 38 343 #define I915_PARAM_MIN_EU_IN_POOL 39 344 #define I915_PARAM_MMAP_GTT_VERSION 40 345 #define I915_PARAM_HAS_SCHEDULER 41 346 #define I915_SCHEDULER_CAP_ENABLED (1ul << 0) 347 #define I915_SCHEDULER_CAP_PRIORITY (1ul << 1) 348 #define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2) 349 #define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3) 350 #define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4) 351 #define I915_PARAM_HUC_STATUS 42 352 #define I915_PARAM_HAS_EXEC_ASYNC 43 353 #define I915_PARAM_HAS_EXEC_FENCE 44 354 #define I915_PARAM_HAS_EXEC_CAPTURE 45 355 #define I915_PARAM_SLICE_MASK 46 356 #define I915_PARAM_SUBSLICE_MASK 47 357 #define I915_PARAM_HAS_EXEC_BATCH_FIRST 48 358 #define I915_PARAM_HAS_EXEC_FENCE_ARRAY 49 359 #define I915_PARAM_HAS_CONTEXT_ISOLATION 50 360 #define I915_PARAM_CS_TIMESTAMP_FREQUENCY 51 361 #define I915_PARAM_MMAP_GTT_COHERENT 52 362 #define I915_PARAM_HAS_EXEC_SUBMIT_FENCE 53 363 #define I915_PARAM_PERF_REVISION 54 364 #define I915_PARAM_HAS_EXEC_TIMELINE_FENCES 55 365 typedef struct drm_i915_getparam { 366 __s32 param; 367 int __user * value; 368 } drm_i915_getparam_t; 369 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 370 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 371 #define I915_SETPARAM_ALLOW_BATCHBUFFER 3 372 #define I915_SETPARAM_NUM_USED_FENCES 4 373 typedef struct drm_i915_setparam { 374 int param; 375 int value; 376 } drm_i915_setparam_t; 377 #define I915_MEM_REGION_AGP 1 378 typedef struct drm_i915_mem_alloc { 379 int region; 380 int alignment; 381 int size; 382 int __user * region_offset; 383 } drm_i915_mem_alloc_t; 384 typedef struct drm_i915_mem_free { 385 int region; 386 int region_offset; 387 } drm_i915_mem_free_t; 388 typedef struct drm_i915_mem_init_heap { 389 int region; 390 int size; 391 int start; 392 } drm_i915_mem_init_heap_t; 393 typedef struct drm_i915_mem_destroy_heap { 394 int region; 395 } drm_i915_mem_destroy_heap_t; 396 #define DRM_I915_VBLANK_PIPE_A 1 397 #define DRM_I915_VBLANK_PIPE_B 2 398 typedef struct drm_i915_vblank_pipe { 399 int pipe; 400 } drm_i915_vblank_pipe_t; 401 typedef struct drm_i915_vblank_swap { 402 drm_drawable_t drawable; 403 enum drm_vblank_seq_type seqtype; 404 unsigned int sequence; 405 } drm_i915_vblank_swap_t; 406 typedef struct drm_i915_hws_addr { 407 __u64 addr; 408 } drm_i915_hws_addr_t; 409 struct drm_i915_gem_init { 410 __u64 gtt_start; 411 __u64 gtt_end; 412 }; 413 struct drm_i915_gem_create { 414 __u64 size; 415 __u32 handle; 416 __u32 pad; 417 }; 418 struct drm_i915_gem_pread { 419 __u32 handle; 420 __u32 pad; 421 __u64 offset; 422 __u64 size; 423 __u64 data_ptr; 424 }; 425 struct drm_i915_gem_pwrite { 426 __u32 handle; 427 __u32 pad; 428 __u64 offset; 429 __u64 size; 430 __u64 data_ptr; 431 }; 432 struct drm_i915_gem_mmap { 433 __u32 handle; 434 __u32 pad; 435 __u64 offset; 436 __u64 size; 437 __u64 addr_ptr; 438 __u64 flags; 439 #define I915_MMAP_WC 0x1 440 }; 441 struct drm_i915_gem_mmap_gtt { 442 __u32 handle; 443 __u32 pad; 444 __u64 offset; 445 }; 446 struct drm_i915_gem_mmap_offset { 447 __u32 handle; 448 __u32 pad; 449 __u64 offset; 450 __u64 flags; 451 #define I915_MMAP_OFFSET_GTT 0 452 #define I915_MMAP_OFFSET_WC 1 453 #define I915_MMAP_OFFSET_WB 2 454 #define I915_MMAP_OFFSET_UC 3 455 __u64 extensions; 456 }; 457 struct drm_i915_gem_set_domain { 458 __u32 handle; 459 __u32 read_domains; 460 __u32 write_domain; 461 }; 462 struct drm_i915_gem_sw_finish { 463 __u32 handle; 464 }; 465 struct drm_i915_gem_relocation_entry { 466 __u32 target_handle; 467 __u32 delta; 468 __u64 offset; 469 __u64 presumed_offset; 470 __u32 read_domains; 471 __u32 write_domain; 472 }; 473 #define I915_GEM_DOMAIN_CPU 0x00000001 474 #define I915_GEM_DOMAIN_RENDER 0x00000002 475 #define I915_GEM_DOMAIN_SAMPLER 0x00000004 476 #define I915_GEM_DOMAIN_COMMAND 0x00000008 477 #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 478 #define I915_GEM_DOMAIN_VERTEX 0x00000020 479 #define I915_GEM_DOMAIN_GTT 0x00000040 480 #define I915_GEM_DOMAIN_WC 0x00000080 481 struct drm_i915_gem_exec_object { 482 __u32 handle; 483 __u32 relocation_count; 484 __u64 relocs_ptr; 485 __u64 alignment; 486 __u64 offset; 487 }; 488 struct drm_i915_gem_execbuffer { 489 __u64 buffers_ptr; 490 __u32 buffer_count; 491 __u32 batch_start_offset; 492 __u32 batch_len; 493 __u32 DR1; 494 __u32 DR4; 495 __u32 num_cliprects; 496 __u64 cliprects_ptr; 497 }; 498 struct drm_i915_gem_exec_object2 { 499 __u32 handle; 500 __u32 relocation_count; 501 __u64 relocs_ptr; 502 __u64 alignment; 503 __u64 offset; 504 #define EXEC_OBJECT_NEEDS_FENCE (1 << 0) 505 #define EXEC_OBJECT_NEEDS_GTT (1 << 1) 506 #define EXEC_OBJECT_WRITE (1 << 2) 507 #define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1 << 3) 508 #define EXEC_OBJECT_PINNED (1 << 4) 509 #define EXEC_OBJECT_PAD_TO_SIZE (1 << 5) 510 #define EXEC_OBJECT_ASYNC (1 << 6) 511 #define EXEC_OBJECT_CAPTURE (1 << 7) 512 #define __EXEC_OBJECT_UNKNOWN_FLAGS - (EXEC_OBJECT_CAPTURE << 1) 513 __u64 flags; 514 union { 515 __u64 rsvd1; 516 __u64 pad_to_size; 517 }; 518 __u64 rsvd2; 519 }; 520 struct drm_i915_gem_exec_fence { 521 __u32 handle; 522 #define I915_EXEC_FENCE_WAIT (1 << 0) 523 #define I915_EXEC_FENCE_SIGNAL (1 << 1) 524 #define __I915_EXEC_FENCE_UNKNOWN_FLAGS (- (I915_EXEC_FENCE_SIGNAL << 1)) 525 __u32 flags; 526 }; 527 #define DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES 0 528 struct drm_i915_gem_execbuffer_ext_timeline_fences { 529 struct i915_user_extension base; 530 __u64 fence_count; 531 __u64 handles_ptr; 532 __u64 values_ptr; 533 }; 534 struct drm_i915_gem_execbuffer2 { 535 __u64 buffers_ptr; 536 __u32 buffer_count; 537 __u32 batch_start_offset; 538 __u32 batch_len; 539 __u32 DR1; 540 __u32 DR4; 541 __u32 num_cliprects; 542 __u64 cliprects_ptr; 543 #define I915_EXEC_RING_MASK (0x3f) 544 #define I915_EXEC_DEFAULT (0 << 0) 545 #define I915_EXEC_RENDER (1 << 0) 546 #define I915_EXEC_BSD (2 << 0) 547 #define I915_EXEC_BLT (3 << 0) 548 #define I915_EXEC_VEBOX (4 << 0) 549 #define I915_EXEC_CONSTANTS_MASK (3 << 6) 550 #define I915_EXEC_CONSTANTS_REL_GENERAL (0 << 6) 551 #define I915_EXEC_CONSTANTS_ABSOLUTE (1 << 6) 552 #define I915_EXEC_CONSTANTS_REL_SURFACE (2 << 6) 553 __u64 flags; 554 __u64 rsvd1; 555 __u64 rsvd2; 556 }; 557 #define I915_EXEC_GEN7_SOL_RESET (1 << 8) 558 #define I915_EXEC_SECURE (1 << 9) 559 #define I915_EXEC_IS_PINNED (1 << 10) 560 #define I915_EXEC_NO_RELOC (1 << 11) 561 #define I915_EXEC_HANDLE_LUT (1 << 12) 562 #define I915_EXEC_BSD_SHIFT (13) 563 #define I915_EXEC_BSD_MASK (3 << I915_EXEC_BSD_SHIFT) 564 #define I915_EXEC_BSD_DEFAULT (0 << I915_EXEC_BSD_SHIFT) 565 #define I915_EXEC_BSD_RING1 (1 << I915_EXEC_BSD_SHIFT) 566 #define I915_EXEC_BSD_RING2 (2 << I915_EXEC_BSD_SHIFT) 567 #define I915_EXEC_RESOURCE_STREAMER (1 << 15) 568 #define I915_EXEC_FENCE_IN (1 << 16) 569 #define I915_EXEC_FENCE_OUT (1 << 17) 570 #define I915_EXEC_BATCH_FIRST (1 << 18) 571 #define I915_EXEC_FENCE_ARRAY (1 << 19) 572 #define I915_EXEC_FENCE_SUBMIT (1 << 20) 573 #define I915_EXEC_USE_EXTENSIONS (1 << 21) 574 #define __I915_EXEC_UNKNOWN_FLAGS (- (I915_EXEC_USE_EXTENSIONS << 1)) 575 #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) 576 #define i915_execbuffer2_set_context_id(eb2,context) (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK 577 #define i915_execbuffer2_get_context_id(eb2) ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK) 578 struct drm_i915_gem_pin { 579 __u32 handle; 580 __u32 pad; 581 __u64 alignment; 582 __u64 offset; 583 }; 584 struct drm_i915_gem_unpin { 585 __u32 handle; 586 __u32 pad; 587 }; 588 struct drm_i915_gem_busy { 589 __u32 handle; 590 __u32 busy; 591 }; 592 #define I915_CACHING_NONE 0 593 #define I915_CACHING_CACHED 1 594 #define I915_CACHING_DISPLAY 2 595 struct drm_i915_gem_caching { 596 __u32 handle; 597 __u32 caching; 598 }; 599 #define I915_TILING_NONE 0 600 #define I915_TILING_X 1 601 #define I915_TILING_Y 2 602 #define I915_TILING_LAST I915_TILING_Y 603 #define I915_BIT_6_SWIZZLE_NONE 0 604 #define I915_BIT_6_SWIZZLE_9 1 605 #define I915_BIT_6_SWIZZLE_9_10 2 606 #define I915_BIT_6_SWIZZLE_9_11 3 607 #define I915_BIT_6_SWIZZLE_9_10_11 4 608 #define I915_BIT_6_SWIZZLE_UNKNOWN 5 609 #define I915_BIT_6_SWIZZLE_9_17 6 610 #define I915_BIT_6_SWIZZLE_9_10_17 7 611 struct drm_i915_gem_set_tiling { 612 __u32 handle; 613 __u32 tiling_mode; 614 __u32 stride; 615 __u32 swizzle_mode; 616 }; 617 struct drm_i915_gem_get_tiling { 618 __u32 handle; 619 __u32 tiling_mode; 620 __u32 swizzle_mode; 621 __u32 phys_swizzle_mode; 622 }; 623 struct drm_i915_gem_get_aperture { 624 __u64 aper_size; 625 __u64 aper_available_size; 626 }; 627 struct drm_i915_get_pipe_from_crtc_id { 628 __u32 crtc_id; 629 __u32 pipe; 630 }; 631 #define I915_MADV_WILLNEED 0 632 #define I915_MADV_DONTNEED 1 633 #define __I915_MADV_PURGED 2 634 struct drm_i915_gem_madvise { 635 __u32 handle; 636 __u32 madv; 637 __u32 retained; 638 }; 639 #define I915_OVERLAY_TYPE_MASK 0xff 640 #define I915_OVERLAY_YUV_PLANAR 0x01 641 #define I915_OVERLAY_YUV_PACKED 0x02 642 #define I915_OVERLAY_RGB 0x03 643 #define I915_OVERLAY_DEPTH_MASK 0xff00 644 #define I915_OVERLAY_RGB24 0x1000 645 #define I915_OVERLAY_RGB16 0x2000 646 #define I915_OVERLAY_RGB15 0x3000 647 #define I915_OVERLAY_YUV422 0x0100 648 #define I915_OVERLAY_YUV411 0x0200 649 #define I915_OVERLAY_YUV420 0x0300 650 #define I915_OVERLAY_YUV410 0x0400 651 #define I915_OVERLAY_SWAP_MASK 0xff0000 652 #define I915_OVERLAY_NO_SWAP 0x000000 653 #define I915_OVERLAY_UV_SWAP 0x010000 654 #define I915_OVERLAY_Y_SWAP 0x020000 655 #define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 656 #define I915_OVERLAY_FLAGS_MASK 0xff000000 657 #define I915_OVERLAY_ENABLE 0x01000000 658 struct drm_intel_overlay_put_image { 659 __u32 flags; 660 __u32 bo_handle; 661 __u16 stride_Y; 662 __u16 stride_UV; 663 __u32 offset_Y; 664 __u32 offset_U; 665 __u32 offset_V; 666 __u16 src_width; 667 __u16 src_height; 668 __u16 src_scan_width; 669 __u16 src_scan_height; 670 __u32 crtc_id; 671 __u16 dst_x; 672 __u16 dst_y; 673 __u16 dst_width; 674 __u16 dst_height; 675 }; 676 #define I915_OVERLAY_UPDATE_ATTRS (1 << 0) 677 #define I915_OVERLAY_UPDATE_GAMMA (1 << 1) 678 #define I915_OVERLAY_DISABLE_DEST_COLORKEY (1 << 2) 679 struct drm_intel_overlay_attrs { 680 __u32 flags; 681 __u32 color_key; 682 __s32 brightness; 683 __u32 contrast; 684 __u32 saturation; 685 __u32 gamma0; 686 __u32 gamma1; 687 __u32 gamma2; 688 __u32 gamma3; 689 __u32 gamma4; 690 __u32 gamma5; 691 }; 692 #define I915_SET_COLORKEY_NONE (1 << 0) 693 #define I915_SET_COLORKEY_DESTINATION (1 << 1) 694 #define I915_SET_COLORKEY_SOURCE (1 << 2) 695 struct drm_intel_sprite_colorkey { 696 __u32 plane_id; 697 __u32 min_value; 698 __u32 channel_mask; 699 __u32 max_value; 700 __u32 flags; 701 }; 702 struct drm_i915_gem_wait { 703 __u32 bo_handle; 704 __u32 flags; 705 __s64 timeout_ns; 706 }; 707 struct drm_i915_gem_context_create { 708 __u32 ctx_id; 709 __u32 pad; 710 }; 711 struct drm_i915_gem_context_create_ext { 712 __u32 ctx_id; 713 __u32 flags; 714 #define I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS (1u << 0) 715 #define I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE (1u << 1) 716 #define I915_CONTEXT_CREATE_FLAGS_UNKNOWN (- (I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE << 1)) 717 __u64 extensions; 718 }; 719 struct drm_i915_gem_context_param { 720 __u32 ctx_id; 721 __u32 size; 722 __u64 param; 723 #define I915_CONTEXT_PARAM_BAN_PERIOD 0x1 724 #define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2 725 #define I915_CONTEXT_PARAM_GTT_SIZE 0x3 726 #define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4 727 #define I915_CONTEXT_PARAM_BANNABLE 0x5 728 #define I915_CONTEXT_PARAM_PRIORITY 0x6 729 #define I915_CONTEXT_MAX_USER_PRIORITY 1023 730 #define I915_CONTEXT_DEFAULT_PRIORITY 0 731 #define I915_CONTEXT_MIN_USER_PRIORITY - 1023 732 #define I915_CONTEXT_PARAM_SSEU 0x7 733 #define I915_CONTEXT_PARAM_RECOVERABLE 0x8 734 #define I915_CONTEXT_PARAM_VM 0x9 735 #define I915_CONTEXT_PARAM_ENGINES 0xa 736 #define I915_CONTEXT_PARAM_PERSISTENCE 0xb 737 #define I915_CONTEXT_PARAM_RINGSIZE 0xc 738 __u64 value; 739 }; 740 struct drm_i915_gem_context_param_sseu { 741 struct i915_engine_class_instance engine; 742 __u32 flags; 743 #define I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX (1u << 0) 744 __u64 slice_mask; 745 __u64 subslice_mask; 746 __u16 min_eus_per_subslice; 747 __u16 max_eus_per_subslice; 748 __u32 rsvd; 749 }; 750 struct i915_context_engines_load_balance { 751 struct i915_user_extension base; 752 __u16 engine_index; 753 __u16 num_siblings; 754 __u32 flags; 755 __u64 mbz64; 756 struct i915_engine_class_instance engines[0]; 757 } __attribute__((packed)); 758 #define I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(name__,N__) struct { struct i915_user_extension base; __u16 engine_index; __u16 num_siblings; __u32 flags; __u64 mbz64; struct i915_engine_class_instance engines[N__]; \ 759 } __attribute__((packed)) name__ 760 struct i915_context_engines_bond { 761 struct i915_user_extension base; 762 struct i915_engine_class_instance master; 763 __u16 virtual_index; 764 __u16 num_bonds; 765 __u64 flags; 766 __u64 mbz64[4]; 767 struct i915_engine_class_instance engines[0]; 768 } __attribute__((packed)); 769 #define I915_DEFINE_CONTEXT_ENGINES_BOND(name__,N__) struct { struct i915_user_extension base; struct i915_engine_class_instance master; __u16 virtual_index; __u16 num_bonds; __u64 flags; __u64 mbz64[4]; struct i915_engine_class_instance engines[N__]; \ 770 } __attribute__((packed)) name__ 771 struct i915_context_param_engines { 772 __u64 extensions; 773 #define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0 774 #define I915_CONTEXT_ENGINES_EXT_BOND 1 775 struct i915_engine_class_instance engines[0]; 776 } __attribute__((packed)); 777 #define I915_DEFINE_CONTEXT_PARAM_ENGINES(name__,N__) struct { __u64 extensions; struct i915_engine_class_instance engines[N__]; \ 778 } __attribute__((packed)) name__ 779 struct drm_i915_gem_context_create_ext_setparam { 780 #define I915_CONTEXT_CREATE_EXT_SETPARAM 0 781 struct i915_user_extension base; 782 struct drm_i915_gem_context_param param; 783 }; 784 struct drm_i915_gem_context_create_ext_clone { 785 #define I915_CONTEXT_CREATE_EXT_CLONE 1 786 struct i915_user_extension base; 787 __u32 clone_id; 788 __u32 flags; 789 #define I915_CONTEXT_CLONE_ENGINES (1u << 0) 790 #define I915_CONTEXT_CLONE_FLAGS (1u << 1) 791 #define I915_CONTEXT_CLONE_SCHEDATTR (1u << 2) 792 #define I915_CONTEXT_CLONE_SSEU (1u << 3) 793 #define I915_CONTEXT_CLONE_TIMELINE (1u << 4) 794 #define I915_CONTEXT_CLONE_VM (1u << 5) 795 #define I915_CONTEXT_CLONE_UNKNOWN - (I915_CONTEXT_CLONE_VM << 1) 796 __u64 rsvd; 797 }; 798 struct drm_i915_gem_context_destroy { 799 __u32 ctx_id; 800 __u32 pad; 801 }; 802 struct drm_i915_gem_vm_control { 803 __u64 extensions; 804 __u32 flags; 805 __u32 vm_id; 806 }; 807 struct drm_i915_reg_read { 808 __u64 offset; 809 #define I915_REG_READ_8B_WA (1ul << 0) 810 __u64 val; 811 }; 812 struct drm_i915_reset_stats { 813 __u32 ctx_id; 814 __u32 flags; 815 __u32 reset_count; 816 __u32 batch_active; 817 __u32 batch_pending; 818 __u32 pad; 819 }; 820 struct drm_i915_gem_userptr { 821 __u64 user_ptr; 822 __u64 user_size; 823 __u32 flags; 824 #define I915_USERPTR_READ_ONLY 0x1 825 #define I915_USERPTR_UNSYNCHRONIZED 0x80000000 826 __u32 handle; 827 }; 828 enum drm_i915_oa_format { 829 I915_OA_FORMAT_A13 = 1, 830 I915_OA_FORMAT_A29, 831 I915_OA_FORMAT_A13_B8_C8, 832 I915_OA_FORMAT_B4_C8, 833 I915_OA_FORMAT_A45_B8_C8, 834 I915_OA_FORMAT_B4_C8_A16, 835 I915_OA_FORMAT_C4_B8, 836 I915_OA_FORMAT_A12, 837 I915_OA_FORMAT_A12_B8_C8, 838 I915_OA_FORMAT_A32u40_A4u32_B8_C8, 839 I915_OA_FORMAT_MAX 840 }; 841 enum drm_i915_perf_property_id { 842 DRM_I915_PERF_PROP_CTX_HANDLE = 1, 843 DRM_I915_PERF_PROP_SAMPLE_OA, 844 DRM_I915_PERF_PROP_OA_METRICS_SET, 845 DRM_I915_PERF_PROP_OA_FORMAT, 846 DRM_I915_PERF_PROP_OA_EXPONENT, 847 DRM_I915_PERF_PROP_HOLD_PREEMPTION, 848 DRM_I915_PERF_PROP_GLOBAL_SSEU, 849 DRM_I915_PERF_PROP_POLL_OA_PERIOD, 850 DRM_I915_PERF_PROP_MAX 851 }; 852 struct drm_i915_perf_open_param { 853 __u32 flags; 854 #define I915_PERF_FLAG_FD_CLOEXEC (1 << 0) 855 #define I915_PERF_FLAG_FD_NONBLOCK (1 << 1) 856 #define I915_PERF_FLAG_DISABLED (1 << 2) 857 __u32 num_properties; 858 __u64 properties_ptr; 859 }; 860 #define I915_PERF_IOCTL_ENABLE _IO('i', 0x0) 861 #define I915_PERF_IOCTL_DISABLE _IO('i', 0x1) 862 #define I915_PERF_IOCTL_CONFIG _IO('i', 0x2) 863 struct drm_i915_perf_record_header { 864 __u32 type; 865 __u16 pad; 866 __u16 size; 867 }; 868 enum drm_i915_perf_record_type { 869 DRM_I915_PERF_RECORD_SAMPLE = 1, 870 DRM_I915_PERF_RECORD_OA_REPORT_LOST = 2, 871 DRM_I915_PERF_RECORD_OA_BUFFER_LOST = 3, 872 DRM_I915_PERF_RECORD_MAX 873 }; 874 struct drm_i915_perf_oa_config { 875 char uuid[36]; 876 __u32 n_mux_regs; 877 __u32 n_boolean_regs; 878 __u32 n_flex_regs; 879 __u64 mux_regs_ptr; 880 __u64 boolean_regs_ptr; 881 __u64 flex_regs_ptr; 882 }; 883 struct drm_i915_query_item { 884 __u64 query_id; 885 #define DRM_I915_QUERY_TOPOLOGY_INFO 1 886 #define DRM_I915_QUERY_ENGINE_INFO 2 887 #define DRM_I915_QUERY_PERF_CONFIG 3 888 __s32 length; 889 __u32 flags; 890 #define DRM_I915_QUERY_PERF_CONFIG_LIST 1 891 #define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID 2 892 #define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID 3 893 __u64 data_ptr; 894 }; 895 struct drm_i915_query { 896 __u32 num_items; 897 __u32 flags; 898 __u64 items_ptr; 899 }; 900 struct drm_i915_query_topology_info { 901 __u16 flags; 902 __u16 max_slices; 903 __u16 max_subslices; 904 __u16 max_eus_per_subslice; 905 __u16 subslice_offset; 906 __u16 subslice_stride; 907 __u16 eu_offset; 908 __u16 eu_stride; 909 __u8 data[]; 910 }; 911 struct drm_i915_engine_info { 912 struct i915_engine_class_instance engine; 913 __u32 rsvd0; 914 __u64 flags; 915 __u64 capabilities; 916 #define I915_VIDEO_CLASS_CAPABILITY_HEVC (1 << 0) 917 #define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC (1 << 1) 918 __u64 rsvd1[4]; 919 }; 920 struct drm_i915_query_engine_info { 921 __u32 num_engines; 922 __u32 rsvd[3]; 923 struct drm_i915_engine_info engines[]; 924 }; 925 struct drm_i915_query_perf_config { 926 union { 927 __u64 n_configs; 928 __u64 config; 929 char uuid[36]; 930 }; 931 __u32 flags; 932 __u8 data[]; 933 }; 934 #ifdef __cplusplus 935 } 936 #endif 937 #endif 938