1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef VIRTIO_GPU_HW_H 20 #define VIRTIO_GPU_HW_H 21 #include <linux/types.h> 22 #define VIRTIO_GPU_F_VIRGL 0 23 #define VIRTIO_GPU_F_EDID 1 24 #define VIRTIO_GPU_F_RESOURCE_UUID 2 25 enum virtio_gpu_ctrl_type { 26 VIRTIO_GPU_UNDEFINED = 0, 27 VIRTIO_GPU_CMD_GET_DISPLAY_INFO = 0x0100, 28 VIRTIO_GPU_CMD_RESOURCE_CREATE_2D, 29 VIRTIO_GPU_CMD_RESOURCE_UNREF, 30 VIRTIO_GPU_CMD_SET_SCANOUT, 31 VIRTIO_GPU_CMD_RESOURCE_FLUSH, 32 VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D, 33 VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING, 34 VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING, 35 VIRTIO_GPU_CMD_GET_CAPSET_INFO, 36 VIRTIO_GPU_CMD_GET_CAPSET, 37 VIRTIO_GPU_CMD_GET_EDID, 38 VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID, 39 VIRTIO_GPU_CMD_CTX_CREATE = 0x0200, 40 VIRTIO_GPU_CMD_CTX_DESTROY, 41 VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE, 42 VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE, 43 VIRTIO_GPU_CMD_RESOURCE_CREATE_3D, 44 VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D, 45 VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D, 46 VIRTIO_GPU_CMD_SUBMIT_3D, 47 VIRTIO_GPU_CMD_UPDATE_CURSOR = 0x0300, 48 VIRTIO_GPU_CMD_MOVE_CURSOR, 49 VIRTIO_GPU_RESP_OK_NODATA = 0x1100, 50 VIRTIO_GPU_RESP_OK_DISPLAY_INFO, 51 VIRTIO_GPU_RESP_OK_CAPSET_INFO, 52 VIRTIO_GPU_RESP_OK_CAPSET, 53 VIRTIO_GPU_RESP_OK_EDID, 54 VIRTIO_GPU_RESP_OK_RESOURCE_UUID, 55 VIRTIO_GPU_RESP_ERR_UNSPEC = 0x1200, 56 VIRTIO_GPU_RESP_ERR_OUT_OF_MEMORY, 57 VIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID, 58 VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID, 59 VIRTIO_GPU_RESP_ERR_INVALID_CONTEXT_ID, 60 VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER, 61 }; 62 #define VIRTIO_GPU_FLAG_FENCE (1 << 0) 63 struct virtio_gpu_ctrl_hdr { 64 __le32 type; 65 __le32 flags; 66 __le64 fence_id; 67 __le32 ctx_id; 68 __le32 padding; 69 }; 70 struct virtio_gpu_cursor_pos { 71 __le32 scanout_id; 72 __le32 x; 73 __le32 y; 74 __le32 padding; 75 }; 76 struct virtio_gpu_update_cursor { 77 struct virtio_gpu_ctrl_hdr hdr; 78 struct virtio_gpu_cursor_pos pos; 79 __le32 resource_id; 80 __le32 hot_x; 81 __le32 hot_y; 82 __le32 padding; 83 }; 84 struct virtio_gpu_rect { 85 __le32 x; 86 __le32 y; 87 __le32 width; 88 __le32 height; 89 }; 90 struct virtio_gpu_resource_unref { 91 struct virtio_gpu_ctrl_hdr hdr; 92 __le32 resource_id; 93 __le32 padding; 94 }; 95 struct virtio_gpu_resource_create_2d { 96 struct virtio_gpu_ctrl_hdr hdr; 97 __le32 resource_id; 98 __le32 format; 99 __le32 width; 100 __le32 height; 101 }; 102 struct virtio_gpu_set_scanout { 103 struct virtio_gpu_ctrl_hdr hdr; 104 struct virtio_gpu_rect r; 105 __le32 scanout_id; 106 __le32 resource_id; 107 }; 108 struct virtio_gpu_resource_flush { 109 struct virtio_gpu_ctrl_hdr hdr; 110 struct virtio_gpu_rect r; 111 __le32 resource_id; 112 __le32 padding; 113 }; 114 struct virtio_gpu_transfer_to_host_2d { 115 struct virtio_gpu_ctrl_hdr hdr; 116 struct virtio_gpu_rect r; 117 __le64 offset; 118 __le32 resource_id; 119 __le32 padding; 120 }; 121 struct virtio_gpu_mem_entry { 122 __le64 addr; 123 __le32 length; 124 __le32 padding; 125 }; 126 struct virtio_gpu_resource_attach_backing { 127 struct virtio_gpu_ctrl_hdr hdr; 128 __le32 resource_id; 129 __le32 nr_entries; 130 }; 131 struct virtio_gpu_resource_detach_backing { 132 struct virtio_gpu_ctrl_hdr hdr; 133 __le32 resource_id; 134 __le32 padding; 135 }; 136 #define VIRTIO_GPU_MAX_SCANOUTS 16 137 struct virtio_gpu_resp_display_info { 138 struct virtio_gpu_ctrl_hdr hdr; 139 struct virtio_gpu_display_one { 140 struct virtio_gpu_rect r; 141 __le32 enabled; 142 __le32 flags; 143 } pmodes[VIRTIO_GPU_MAX_SCANOUTS]; 144 }; 145 struct virtio_gpu_box { 146 __le32 x, y, z; 147 __le32 w, h, d; 148 }; 149 struct virtio_gpu_transfer_host_3d { 150 struct virtio_gpu_ctrl_hdr hdr; 151 struct virtio_gpu_box box; 152 __le64 offset; 153 __le32 resource_id; 154 __le32 level; 155 __le32 stride; 156 __le32 layer_stride; 157 }; 158 #define VIRTIO_GPU_RESOURCE_FLAG_Y_0_TOP (1 << 0) 159 struct virtio_gpu_resource_create_3d { 160 struct virtio_gpu_ctrl_hdr hdr; 161 __le32 resource_id; 162 __le32 target; 163 __le32 format; 164 __le32 bind; 165 __le32 width; 166 __le32 height; 167 __le32 depth; 168 __le32 array_size; 169 __le32 last_level; 170 __le32 nr_samples; 171 __le32 flags; 172 __le32 padding; 173 }; 174 struct virtio_gpu_ctx_create { 175 struct virtio_gpu_ctrl_hdr hdr; 176 __le32 nlen; 177 __le32 padding; 178 char debug_name[64]; 179 }; 180 struct virtio_gpu_ctx_destroy { 181 struct virtio_gpu_ctrl_hdr hdr; 182 }; 183 struct virtio_gpu_ctx_resource { 184 struct virtio_gpu_ctrl_hdr hdr; 185 __le32 resource_id; 186 __le32 padding; 187 }; 188 struct virtio_gpu_cmd_submit { 189 struct virtio_gpu_ctrl_hdr hdr; 190 __le32 size; 191 __le32 padding; 192 }; 193 #define VIRTIO_GPU_CAPSET_VIRGL 1 194 #define VIRTIO_GPU_CAPSET_VIRGL2 2 195 struct virtio_gpu_get_capset_info { 196 struct virtio_gpu_ctrl_hdr hdr; 197 __le32 capset_index; 198 __le32 padding; 199 }; 200 struct virtio_gpu_resp_capset_info { 201 struct virtio_gpu_ctrl_hdr hdr; 202 __le32 capset_id; 203 __le32 capset_max_version; 204 __le32 capset_max_size; 205 __le32 padding; 206 }; 207 struct virtio_gpu_get_capset { 208 struct virtio_gpu_ctrl_hdr hdr; 209 __le32 capset_id; 210 __le32 capset_version; 211 }; 212 struct virtio_gpu_resp_capset { 213 struct virtio_gpu_ctrl_hdr hdr; 214 __u8 capset_data[]; 215 }; 216 struct virtio_gpu_cmd_get_edid { 217 struct virtio_gpu_ctrl_hdr hdr; 218 __le32 scanout; 219 __le32 padding; 220 }; 221 struct virtio_gpu_resp_edid { 222 struct virtio_gpu_ctrl_hdr hdr; 223 __le32 size; 224 __le32 padding; 225 __u8 edid[1024]; 226 }; 227 #define VIRTIO_GPU_EVENT_DISPLAY (1 << 0) 228 struct virtio_gpu_config { 229 __le32 events_read; 230 __le32 events_clear; 231 __le32 num_scanouts; 232 __le32 num_capsets; 233 }; 234 enum virtio_gpu_formats { 235 VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM = 1, 236 VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM = 2, 237 VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM = 3, 238 VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM = 4, 239 VIRTIO_GPU_FORMAT_R8G8B8A8_UNORM = 67, 240 VIRTIO_GPU_FORMAT_X8B8G8R8_UNORM = 68, 241 VIRTIO_GPU_FORMAT_A8B8G8R8_UNORM = 121, 242 VIRTIO_GPU_FORMAT_R8G8B8X8_UNORM = 134, 243 }; 244 struct virtio_gpu_resource_assign_uuid { 245 struct virtio_gpu_ctrl_hdr hdr; 246 __le32 resource_id; 247 __le32 padding; 248 }; 249 struct virtio_gpu_resp_resource_uuid { 250 struct virtio_gpu_ctrl_hdr hdr; 251 __u8 uuid[16]; 252 }; 253 #endif 254