1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 1997, 1998, 1999, 2000-2003 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __FBSDID("$FreeBSD: releng/12.2/sys/dev/usb/net/if_axe.c 333813 2018-05-18 20:13:34Z mmacy $"); 37 38 /* 39 * ASIX Electronics AX88172/AX88178/AX88778 USB 2.0 ethernet driver. 40 * Used in the LinkSys USB200M and various other adapters. 41 * 42 * Manuals available from: 43 * http://www.asix.com.tw/datasheet/mac/Ax88172.PDF 44 * Note: you need the manual for the AX88170 chip (USB 1.x ethernet 45 * controller) to find the definitions for the RX control register. 46 * http://www.asix.com.tw/datasheet/mac/Ax88170.PDF 47 * 48 * Written by Bill Paul <wpaul@windriver.com> 49 * Senior Engineer 50 * Wind River Systems 51 */ 52 53 /* 54 * The AX88172 provides USB ethernet supports at 10 and 100Mbps. 55 * It uses an external PHY (reference designs use a RealTek chip), 56 * and has a 64-bit multicast hash filter. There is some information 57 * missing from the manual which one needs to know in order to make 58 * the chip function: 59 * 60 * - You must set bit 7 in the RX control register, otherwise the 61 * chip won't receive any packets. 62 * - You must initialize all 3 IPG registers, or you won't be able 63 * to send any packets. 64 * 65 * Note that this device appears to only support loading the station 66 * address via autload from the EEPROM (i.e. there's no way to manaully 67 * set it). 68 * 69 * (Adam Weinberger wanted me to name this driver if_gir.c.) 70 */ 71 72 /* 73 * Ax88178 and Ax88772 support backported from the OpenBSD driver. 74 * 2007/02/12, J.R. Oldroyd, fbsd@opal.com 75 * 76 * Manual here: 77 * http://www.asix.com.tw/FrootAttach/datasheet/AX88178_datasheet_Rev10.pdf 78 * http://www.asix.com.tw/FrootAttach/datasheet/AX88772_datasheet_Rev10.pdf 79 */ 80 81 #include <lwip/netif.h> 82 #include <lwip/dhcp.h> 83 #include <lwip/netifapi.h> 84 #include <lwip/inet.h> 85 86 #include "implementation/global_implementation.h" 87 #include "usb_ethernet.h" 88 #include "if_axereg.h" 89 #include "mii.h" 90 91 /* 92 * AXE_178_MAX_FRAME_BURST 93 * max frame burst size for Ax88178 and Ax88772 94 * 0 2048 bytes 95 * 1 4096 bytes 96 * 2 8192 bytes 97 * 3 16384 bytes 98 * use the largest your system can handle without USB stalling. 99 * 100 * NB: 88772 parts appear to generate lots of input errors with 101 * a 2K rx buffer and 8K is only slightly faster than 4K on an 102 * EHCI port on a T42 so change at your own risk. 103 */ 104 105 #define AXE_178_MAX_FRAME_BURST 1 106 #define AXE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 107 108 #undef USB_DEBUG_VAR 109 #define USB_DEBUG_VAR axe_debug 110 #ifdef LOSCFG_USB_DEBUG 111 static int axe_debug = 0; 112 void 113 usb_axe_debug_func(int level) 114 { 115 axe_debug = level; 116 PRINTK("The level of usb axe debug is %d\n", level); 117 } 118 DEBUG_MODULE(axe, usb_axe_debug_func); 119 #endif 120 121 #define IFF_DRV_OACTIVE IFF_MASTER 122 #define IFF_SIMPLEX IFF_SLAVE 123 124 /* 125 * Various supported device vendors/products. 126 */ 127 static const STRUCT_USB_HOST_ID axe_devs[] = { 128 { USB_VPI(0x0B95, 0x772B, AXE_FLAG_772B) }, 129 { USB_VPI(0x0B95, 0x772A, AXE_FLAG_772A) }, 130 }; 131 132 static device_probe_t axe_probe; 133 static device_attach_t axe_attach; 134 static device_detach_t axe_detach; 135 136 static usb_callback_t axe_bulk_read_callback; 137 static usb_callback_t axe_bulk_write_callback; 138 139 static int axe_miibus_writereg(struct axe_softc *sc, int reg, int val); 140 static uint16_t axe_miibus_readreg(struct axe_softc *sc, int reg); 141 142 static uether_fn_t axe_attach_post; 143 static uether_fn_t axe_init; 144 static uether_fn_t axe_stop; 145 static uether_fn_t axe_start; 146 static uether_fn_t axe_setmulti; 147 static uether_fn_t axe_setpromisc; 148 static uether_fn_t axe_tick; 149 150 static void axe_cmd(struct axe_softc *, int, int, int, void *); 151 static void axe_ax88178_init(struct axe_softc *); 152 static void axe_ax88772_init(struct axe_softc *); 153 static void axe_ax88772_phywake(struct axe_softc *); 154 static void axe_ax88772b_init(struct axe_softc *); 155 static int axe_get_phyno(struct axe_softc *, int); 156 static int axe_rx_frame(struct usb_ether *, struct usb_page_cache *, int); 157 static int axe_rxeof(struct usb_ether *, struct usb_page_cache *, 158 unsigned int offset, unsigned int, struct axe_csum_hdr *); 159 static void axe_csum_cfg(struct usb_ether *); 160 161 static const struct usb_config axe_config[AXE_N_TRANSFER] = { 162 { /* [AXE_BULK_DT_WR] = */ 163 .type = UE_BULK, 164 .endpoint = UE_ADDR_ANY, 165 .direction = UE_DIR_OUT, 166 .frames = USB_AXE_MAX_FRAMES, 167 .bufsize = USB_AXE_MAX_FRAMES * MCLBYTES, 168 .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 169 .callback = axe_bulk_write_callback, 170 .timeout = 10000, /* 10 seconds */ 171 }, 172 { /* [AXE_BULK_DT_RD] = */ 173 .type = UE_BULK, 174 .endpoint = UE_ADDR_ANY, 175 .direction = UE_DIR_IN, 176 .bufsize = 16 * MCLBYTES, /* bytes */ 177 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 178 .callback = axe_bulk_read_callback, 179 .timeout = 0, /* no timeout */ 180 }, 181 }; 182 183 static const struct ax88772b_mfb ax88772b_mfb_table[] = { 184 { 0x8000, 0x8001, 2048 }, 185 { 0x8100, 0x8147, 4096 }, 186 { 0x8200, 0x81EB, 6144 }, 187 { 0x8300, 0x83D7, 8192 }, 188 { 0x84C0, 0x861E, 16384 }, 189 { 0x8500, 0x8666, 20480 }, 190 { 0x8600, 0x87AE, 24576 }, 191 { 0x8700, 0x851E, 32768 } 192 }; 193 194 static device_method_t axe_methods[] = { 195 /* Device interface */ 196 DEVMETHOD(device_probe, axe_probe), 197 DEVMETHOD(device_attach, axe_attach), 198 DEVMETHOD(device_detach, axe_detach), 199 DEVMETHOD_END 200 }; 201 202 static driver_t axe_driver = { 203 .name = "USB_AXE", 204 .methods = axe_methods, 205 .size = sizeof(struct axe_softc), 206 }; 207 208 static devclass_t axe_devclass; 209 DRIVER_MODULE(axe, uhub, axe_driver, axe_devclass, 0, 0); 210 211 static const struct usb_ether_methods axe_ue_methods = { 212 .ue_attach_post = axe_attach_post, 213 .ue_start = axe_start, 214 .ue_init = axe_init, 215 .ue_stop = axe_stop, 216 .ue_setmulti = axe_setmulti, 217 .ue_setpromisc = axe_setpromisc, 218 .ue_tick = axe_tick, 219 }; 220 221 static void 222 axe_cmd(struct axe_softc *sc, int cmd, int index, int val, void *buf) 223 { 224 struct usb_device_request req; 225 usb_error_t err; 226 227 AXE_LOCK_ASSERT(sc, MA_OWNED); 228 229 req.bmRequestType = (AXE_CMD_IS_WRITE(cmd) ? 230 UT_WRITE_VENDOR_DEVICE : 231 UT_READ_VENDOR_DEVICE); 232 req.bRequest = AXE_CMD_CMD(cmd); 233 USETW(req.wValue, val); 234 USETW(req.wIndex, index); 235 USETW(req.wLength, AXE_CMD_LEN(cmd)); 236 237 err = uether_do_request(&sc->sc_ue, &req, buf, 10000); 238 if (err != USB_ERR_NORMAL_COMPLETION) { 239 dprintf("Fatal Error in function [%s]! err:%d\n", __FUNCTION__, err); 240 } 241 } 242 243 static uint16_t 244 axe_miibus_readreg(struct axe_softc *sc, int reg) 245 { 246 uint16_t val; 247 248 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 249 axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, 0x10, &val); 250 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 251 252 val = le16toh(val); 253 if (AXE_IS_772(sc) && reg == MII_BMSR) { 254 /* 255 * BMSR of AX88772 indicates that it supports extended 256 * capability but the extended status register is 257 * revered for embedded ethernet PHY. So clear the 258 * extended capability bit of BMSR. 259 */ 260 val &= ~BMSR_EXTCAP; 261 } 262 return (val); 263 } 264 265 static int 266 axe_miibus_writereg(struct axe_softc *sc, int reg, int val) 267 { 268 val = htole32(val); 269 270 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 271 axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, 0x10, &val); 272 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 273 return (0); 274 } 275 276 static int 277 axe_setmedium(struct axe_softc *sc) 278 { 279 uint16_t val = AXE_178_MEDIA_RX_EN | AXE_178_MEDIA_MAGIC; 280 uint16_t bmcr; 281 int b100 = 0; 282 int bfull = 0; 283 284 bmcr = axe_miibus_readreg(sc, 0); 285 286 if (bmcr & 0x2000) { /* 100Mbps */ 287 val |= AXE_178_MEDIA_100TX; 288 b100 = 1; 289 } 290 291 if (bmcr & 0x100) { /* full-duplex */ 292 val |= AXE_MEDIA_FULL_DUPLEX | AXE_178_MEDIA_TXFLOW_CONTROL_EN | AXE_178_MEDIA_RXFLOW_CONTROL_EN; 293 bfull = 1; 294 } 295 296 if (b100) 297 PRINTK("- 100Mbps/"); 298 else 299 PRINTK("- 10Mbps/"); 300 301 if (bfull) 302 PRINTK("Full\n"); 303 else 304 PRINTK("Half\n"); 305 306 axe_cmd(sc, AXE_CMD_WRITE_MEDIA, 0, val, NULL); 307 return (0); 308 } 309 310 static void 311 axe_setmulti(struct usb_ether *ue) 312 { 313 } 314 315 static int 316 axe_get_phyno(struct axe_softc *sc, int sel) 317 { 318 int phyno; 319 320 switch (AXE_PHY_TYPE(sc->sc_phyaddrs[sel])) { 321 case PHY_TYPE_100_HOME: 322 case PHY_TYPE_GIG: 323 phyno = AXE_PHY_NO(sc->sc_phyaddrs[sel]); 324 break; 325 case PHY_TYPE_SPECIAL: 326 /* FALLTHROUGH */ 327 case PHY_TYPE_RSVD: 328 /* FALLTHROUGH */ 329 case PHY_TYPE_NON_SUP: 330 /* FALLTHROUGH */ 331 default: 332 phyno = -1; 333 break; 334 } 335 336 return (phyno); 337 } 338 339 static void 340 axe_uether_pause(struct usb_ether * usbe, unsigned int t_ick) 341 { 342 (void) uether_pause(usbe, t_ick); 343 } 344 345 #define AXE_GPIO_WRITE(x, y) do { \ 346 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, (x), NULL); \ 347 axe_uether_pause(ue, (y)); \ 348 } while (0) 349 350 static void 351 axe_ax88178_init(struct axe_softc *sc) 352 { 353 struct usb_ether *ue; 354 int gpio0, ledmode, phymode; 355 uint16_t eeprom, val; 356 357 ue = &sc->sc_ue; 358 axe_cmd(sc, AXE_CMD_SROM_WR_ENABLE, 0, 0, NULL); 359 /* XXX magic */ 360 axe_cmd(sc, AXE_CMD_SROM_READ, 0, 0x0017, &eeprom); 361 eeprom = le16toh(eeprom); 362 axe_cmd(sc, AXE_CMD_SROM_WR_DISABLE, 0, 0, NULL); 363 364 /* if EEPROM is invalid we have to use to GPIO0 */ 365 if (eeprom == 0xffff) { 366 phymode = AXE_PHY_MODE_MARVELL; 367 gpio0 = 1; 368 ledmode = 0; 369 } else { 370 phymode = eeprom & 0x7f; 371 gpio0 = (eeprom & 0x80) ? 0 : 1; 372 ledmode = eeprom >> 8; 373 } 374 375 /* Program GPIOs depending on PHY hardware. */ 376 switch (phymode) { 377 case AXE_PHY_MODE_MARVELL: 378 if (gpio0 == 1) { 379 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0_EN, 380 hz / 32); 381 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 382 hz / 32); 383 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2_EN, hz / 4); 384 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 385 hz / 32); 386 } else { 387 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 388 AXE_GPIO1_EN, hz / 3); 389 if (ledmode == 1) { 390 AXE_GPIO_WRITE(AXE_GPIO1_EN, hz / 3); 391 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN, 392 hz / 3); 393 } else { 394 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 395 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 396 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 397 AXE_GPIO2_EN, hz / 4); 398 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 399 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 400 } 401 } 402 break; 403 case AXE_PHY_MODE_CICADA: 404 case AXE_PHY_MODE_CICADA_V2: 405 case AXE_PHY_MODE_CICADA_V2_ASIX: 406 if (gpio0 == 1) 407 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0 | 408 AXE_GPIO0_EN, hz / 32); 409 else 410 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 411 AXE_GPIO1_EN, hz / 32); 412 break; 413 case AXE_PHY_MODE_AGERE: 414 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 415 AXE_GPIO1_EN, hz / 32); 416 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 417 AXE_GPIO2_EN, hz / 32); 418 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2_EN, hz / 4); 419 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 420 AXE_GPIO2_EN, hz / 32); 421 break; 422 case AXE_PHY_MODE_REALTEK_8211CL: 423 case AXE_PHY_MODE_REALTEK_8211BN: 424 case AXE_PHY_MODE_REALTEK_8251CL: 425 val = gpio0 == 1 ? AXE_GPIO0 | AXE_GPIO0_EN : 426 AXE_GPIO1 | AXE_GPIO1_EN; 427 AXE_GPIO_WRITE(val, hz / 32); 428 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 429 AXE_GPIO_WRITE(val | AXE_GPIO2_EN, hz / 4); 430 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 431 if (phymode == AXE_PHY_MODE_REALTEK_8211CL) { 432 (void) axe_miibus_writereg(sc, 0x1F, 0x0005); 433 (void) axe_miibus_writereg(sc, 0x0C, 0x0000); 434 val = axe_miibus_readreg(sc, 0x0001); 435 (void) axe_miibus_writereg(sc, 0x01, val | 0x0080); 436 (void) axe_miibus_writereg(sc, 0x1F, 0x0000); 437 } 438 break; 439 default: 440 /* Unknown PHY model or no need to program GPIOs. */ 441 break; 442 } 443 444 /* soft reset */ 445 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 446 axe_uether_pause(ue, hz / 4); 447 448 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 449 AXE_SW_RESET_PRL | AXE_178_RESET_MAGIC, NULL); 450 axe_uether_pause(ue, hz / 4); 451 /* Enable MII/GMII/RGMII interface to work with external PHY. */ 452 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0, NULL); 453 axe_uether_pause(ue, hz / 4); 454 455 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 456 } 457 458 static void 459 axe_ax88772_init(struct axe_softc *sc) 460 { 461 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, 0x00b0, NULL); 462 axe_uether_pause(&sc->sc_ue, hz / 16); 463 464 if (sc->sc_phyno == AXE_772_PHY_NO_EPHY) { 465 /* ask for the embedded PHY */ 466 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x01, NULL); 467 axe_uether_pause(&sc->sc_ue, hz / 64); 468 469 /* power down and reset state, pin reset state */ 470 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 471 AXE_SW_RESET_CLEAR, NULL); 472 axe_uether_pause(&sc->sc_ue, hz / 16); 473 474 /* power down/reset state, pin operating state */ 475 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 476 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 477 axe_uether_pause(&sc->sc_ue, hz / 4); 478 479 /* power up, reset */ 480 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRL, NULL); 481 482 /* power up, operating */ 483 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 484 AXE_SW_RESET_IPRL | AXE_SW_RESET_PRL, NULL); 485 } else { 486 /* ask for external PHY */ 487 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x00, NULL); 488 axe_uether_pause(&sc->sc_ue, hz / 64); 489 490 /* power down internal PHY */ 491 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 492 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 493 } 494 495 axe_uether_pause(&sc->sc_ue, hz / 4); 496 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 497 } 498 499 static void 500 axe_ax88772_phywake(struct axe_softc *sc) 501 { 502 if (sc->sc_phyno == AXE_772_PHY_NO_EPHY) { 503 /* Manually select internal(embedded) PHY - MAC mode. */ 504 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB | 505 AXE_SW_PHY_SELECT_EMBEDDED | AXE_SW_PHY_SELECT_SS_MII, 506 NULL); 507 axe_uether_pause(&sc->sc_ue, hz / 32); 508 } else { 509 /* 510 * Manually select external PHY - MAC mode. 511 * Reverse MII/RMII is for AX88772A PHY mode. 512 */ 513 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB | 514 AXE_SW_PHY_SELECT_EXT | AXE_SW_PHY_SELECT_SS_MII, NULL); 515 axe_uether_pause(&sc->sc_ue, hz / 32); 516 } 517 /* Take PHY out of power down. */ 518 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPPD | 519 AXE_SW_RESET_IPRL, NULL); 520 axe_uether_pause(&sc->sc_ue, hz / 4); 521 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 522 axe_uether_pause(&sc->sc_ue, hz); 523 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 524 axe_uether_pause(&sc->sc_ue, hz / 32); 525 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 526 axe_uether_pause(&sc->sc_ue, hz / 32); 527 } 528 529 static void 530 axe_ax88772b_init(struct axe_softc *sc) 531 { 532 struct usb_ether *ue = &sc->sc_ue; 533 uint16_t eeprom; 534 uint8_t *eaddr; 535 uint8_t *tmp; 536 uint8_t i; 537 struct los_eth_driver *ifp = ue->ue_drv_sc; 538 539 /* Reload EEPROM. */ 540 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 2); 541 /* 542 * Save PHY power saving configuration(high byte) and 543 * clear EEPROM checksum value(low byte). 544 */ 545 axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_PHY_PWRCFG, &eeprom); 546 sc->sc_pwrcfg = le16toh(eeprom) & 0xFF00; 547 548 /* 549 * Auto-loaded default station address from internal ROM is 550 * 00:00:00:00:00:00 such that an explicit access to EEPROM 551 * is required to get real station address. 552 */ 553 eaddr = ue->ue_eaddr; 554 ifp->ac_if.hwaddr_len = NETIF_MAX_HWADDR_LEN; 555 tmp = (uint8_t *) ifp->ac_if.hwaddr; 556 for (i = 0; i < NETIF_MAX_HWADDR_LEN / 2; i++) { 557 axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_NODE_ID + i, &eeprom); 558 eeprom = le16toh(eeprom); 559 *eaddr++ = (uint8_t)(eeprom & 0xFF); 560 *eaddr++ = (uint8_t)((eeprom >> 8) & 0xFF); 561 *tmp++ = (uint8_t)(eeprom & 0xFF); 562 *tmp++ = (uint8_t)((eeprom >> 8) & 0xFF); 563 } 564 axe_cmd(sc, AXE_178_CMD_WRITE_NODEID, 0, 0, ue->ue_eaddr); 565 566 axe_attach_post(ue); 567 568 /* Wakeup PHY. */ 569 axe_ax88772_phywake(sc); 570 /* Stop MAC. */ 571 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 572 573 ifp = ue->ue_drv_sc; 574 ifp->ac_if.flags |= NETIF_FLAG_UP | NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_ETHERNET; 575 ifp->ac_if.flags &= ~NETIF_FLAG_LINK_UP; 576 sc->sc_flags &= ~AXE_FLAG_LINK; 577 578 usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_RD]); 579 } 580 581 #undef AXE_GPIO_WRITE 582 583 static void 584 axe_reset(struct axe_softc *sc) 585 { 586 struct usb_config_descriptor *cd; 587 usb_error_t err; 588 589 cd = usbd_get_config_descriptor(sc->sc_ue.ue_udev); 590 err = usbd_req_set_config(sc->sc_ue.ue_udev, &sc->sc_mtx, 591 cd->bConfigurationValue); 592 if (err) 593 DPRINTF("reset failed (ignored)\n"); 594 595 /* Wait a little while for the chip to get its brains in order. */ 596 axe_uether_pause(&sc->sc_ue, hz / 100); 597 /* Reinitialize controller to achieve full reset. */ 598 if (sc->sc_flags & AXE_FLAG_178) 599 axe_ax88178_init(sc); 600 else if (sc->sc_flags & AXE_FLAG_772) 601 axe_ax88772_init(sc); 602 else if (sc->sc_flags & AXE_FLAG_772A) 603 axe_ax88772b_init(sc); 604 else if (sc->sc_flags & AXE_FLAG_772B) 605 axe_ax88772b_init(sc); 606 607 axe_cmd(sc, AXE_CMD_WRITE_MEDIA, 0, 608 AXE_MEDIA_FULL_DUPLEX | AXE_178_MEDIA_TXFLOW_CONTROL_EN | AXE_178_MEDIA_RXFLOW_CONTROL_EN 609 | AXE_178_MEDIA_RX_EN | AXE_178_MEDIA_MAGIC, NULL); 610 } 611 612 static void 613 axe_attach_post(struct usb_ether *ue) 614 { 615 struct axe_softc *sc = uether_getsc(ue); 616 /* 617 * Load PHY indexes first. Needed by axe_xxx_init(). 618 */ 619 axe_cmd(sc, AXE_CMD_READ_PHYID, 0, 0, sc->sc_phyaddrs); 620 sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_PRI); 621 if (sc->sc_phyno == -1) 622 sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_SEC); 623 if (sc->sc_phyno == -1) { 624 device_printf(sc->sc_ue.ue_dev, 625 "no valid PHY address found, assuming PHY address 0\n"); 626 sc->sc_phyno = 0; 627 } 628 /* 629 * Fetch IPG values. 630 */ 631 if (sc->sc_flags & (AXE_FLAG_772A | AXE_FLAG_772B)) { 632 /* Set IPG values. */ 633 sc->sc_ipgs[0] = 0x15; 634 sc->sc_ipgs[1] = 0x16; 635 sc->sc_ipgs[2] = 0x1A; 636 } else 637 axe_cmd(sc, AXE_CMD_READ_IPG012, 0, 0, sc->sc_ipgs); 638 } 639 /* 640 * Probe for a AX88172 chip. 641 */ 642 static int 643 axe_probe(device_t dev) 644 { 645 struct usb_attach_arg *uaa = device_get_ivars(dev); 646 647 if (uaa->usb_mode != USB_MODE_HOST) 648 return (ENXIO); 649 if (uaa->info.bConfigIndex != AXE_CONFIG_IDX) 650 return (ENXIO); 651 if (uaa->info.bIfaceIndex != AXE_IFACE_IDX) 652 return (ENXIO); 653 return (usbd_lookup_id_by_uaa(axe_devs, sizeof(axe_devs), uaa)); 654 } 655 656 static void 657 axe_miibus_statchg(struct axe_softc *sc, uint16_t link_status) 658 { 659 struct usb_ether *ue = &sc->sc_ue; 660 struct los_eth_driver *ifp = ue->ue_drv_sc; 661 struct eth_drv_sc *drv_sc = (struct eth_drv_sc *)ifp->driver_context; 662 663 if (drv_sc->state & IFF_DRV_RUNNING) { 664 if (link_status) { 665 if (sc->sc_flags & AXE_FLAG_772A) { 666 PRINTK("\nAX88772A Link Up "); 667 } 668 else if (sc->sc_flags & AXE_FLAG_772B) { 669 PRINTK("\nAX88772B Link Up "); 670 } 671 672 (void) axe_setmedium(sc); 673 axe_start(ue); 674 675 ifp->ac_if.flags |= NETIF_FLAG_LINK_UP; 676 (void)netifapi_netif_set_up(&ifp->ac_if); 677 } else { 678 if (sc->sc_flags & AXE_FLAG_772A) 679 PRINTK("\nAX88772A Link Down\n"); 680 else if (sc->sc_flags & AXE_FLAG_772B) 681 PRINTK("\nAX88772B Link Down\n"); 682 683 ifp->ac_if.flags &= ~NETIF_FLAG_LINK_UP; 684 } 685 } 686 } 687 688 /* 689 * Attach the interface. Allocate softc structures, do ifmedia 690 * setup and ethernet/BPF attach. 691 */ 692 static int 693 axe_attach(device_t dev) 694 { 695 struct usb_attach_arg *uaa = device_get_ivars(dev); 696 struct axe_softc *sc = device_get_softc(dev); 697 struct usb_ether *ue = &sc->sc_ue; 698 uint8_t iface_index; 699 int error; 700 sc->sc_flags = USB_GET_DRIVER_INFO(uaa); 701 sc->sc_link_status = AXE_LINK_MASK; 702 703 device_set_usb_desc(dev); 704 705 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_RECURSE); 706 707 iface_index = AXE_IFACE_IDX; 708 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 709 axe_config, AXE_N_TRANSFER, sc, &sc->sc_mtx); 710 if (error) { 711 device_printf(dev, "allocating USB transfers failed\n"); 712 goto detach; 713 } 714 715 ue->ue_sc = sc; 716 ue->ue_dev = dev; 717 ue->ue_udev = uaa->device; 718 ue->ue_mtx = &sc->sc_mtx; 719 ue->ue_methods = &axe_ue_methods; 720 error = uether_ifattach(ue); 721 if (error) { 722 device_printf(dev, "could not attach interface\n"); 723 goto detach; 724 } 725 return (0); /* success */ 726 727 detach: 728 (void) axe_detach(dev); 729 return (ENXIO); /* failure */ 730 } 731 732 static int 733 axe_detach(device_t dev) 734 { 735 struct axe_softc *sc = device_get_softc(dev); 736 struct usb_ether *ue = &sc->sc_ue; 737 738 usbd_transfer_unsetup(sc->sc_xfer, AXE_N_TRANSFER); 739 uether_ifdetach(ue); 740 mtx_destroy(&sc->sc_mtx); 741 742 return (0); 743 } 744 745 #if (AXE_BULK_BUF_SIZE >= 0x10000) 746 #error "Please update axe_bulk_read_callback()!" 747 #endif 748 749 static void 750 axe_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error) 751 { 752 struct axe_softc *sc = usbd_xfer_softc(xfer); 753 struct usb_ether *ue = &sc->sc_ue; 754 struct usb_page_cache *pc; 755 int actlen; 756 757 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 758 switch (USB_GET_STATE(xfer)) { 759 case USB_ST_TRANSFERRED: 760 pc = usbd_xfer_get_frame(xfer, 0); 761 (void) axe_rx_frame(ue, pc, actlen); 762 /* FALLTHROUGH */ 763 case USB_ST_SETUP: 764 tr_setup: 765 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); 766 usbd_transfer_submit(xfer); 767 uether_rxflush(ue); 768 return; 769 770 default: /* Error */ 771 DPRINTF("bulk read error, %s\n", usbd_errstr(error)); 772 773 if (error != USB_ERR_CANCELLED) { 774 /* try to clear stall first */ 775 usbd_xfer_set_stall(xfer); 776 goto tr_setup; 777 } 778 return; 779 } 780 } 781 782 static int 783 axe_rx_frame(struct usb_ether *ue, struct usb_page_cache *pc, int actlen) 784 { 785 struct axe_softc *sc = ue->ue_sc; 786 struct axe_sframe_hdr hdr; 787 struct axe_csum_hdr csum_hdr; 788 int error, len, pos; 789 790 pos = 0; 791 len = 0; 792 error = 0; 793 794 if ((sc->sc_flags & AXE_FLAG_STD_FRAME) != 0) { 795 while (pos < actlen) { 796 if ((int)(pos + sizeof(hdr)) > actlen) { 797 /* too little data */ 798 error = EINVAL; 799 break; 800 } 801 802 usbd_copy_out(pc, pos, &hdr, sizeof(hdr)); 803 if ((hdr.len ^ hdr.ilen) != sc->sc_lenmask) { 804 /* we lost sync */ 805 error = EINVAL; 806 break; 807 } 808 pos += sizeof(hdr); 809 len = le16toh(hdr.len); 810 if (pos + len > actlen) { 811 /* invalid length */ 812 error = EINVAL; 813 break; 814 } 815 (void) axe_rxeof(ue, pc, pos, len, NULL); 816 pos += len + (len % 2); 817 } 818 } else if ((sc->sc_flags & AXE_FLAG_CSUM_FRAME) != 0) { 819 while (pos < actlen) { 820 if ((int)(pos + sizeof(csum_hdr)) > actlen) { 821 /* too little data */ 822 error = EINVAL; 823 break; 824 } 825 usbd_copy_out(pc, pos, &csum_hdr, sizeof(csum_hdr)); 826 827 csum_hdr.len = le16toh(csum_hdr.len); 828 csum_hdr.ilen = le16toh(csum_hdr.ilen); 829 csum_hdr.cstatus = le16toh(csum_hdr.cstatus); 830 if ((AXE_CSUM_RXBYTES(csum_hdr.len) ^ 831 AXE_CSUM_RXBYTES(csum_hdr.ilen)) != 832 sc->sc_lenmask) { 833 /* we lost sync */ 834 error = EINVAL; 835 break; 836 } 837 /* 838 * Get total transferred frame length including 839 * checksum header. The length should be multiple 840 * of 4. 841 */ 842 len = sizeof(csum_hdr) + AXE_CSUM_RXBYTES(csum_hdr.len); 843 len = (len + 3) & ~3; 844 if (pos + len > actlen) { 845 /* invalid length */ 846 error = EINVAL; 847 break; 848 } 849 (void) axe_rxeof(ue, pc, pos + sizeof(csum_hdr), 850 AXE_CSUM_RXBYTES(csum_hdr.len), &csum_hdr); 851 pos += len; 852 } 853 } else { 854 (void)axe_rxeof(ue, pc, 0, actlen, NULL); 855 } 856 return (error); 857 } 858 859 static int 860 axe_rxeof(struct usb_ether *ue, struct usb_page_cache *pc, unsigned int offset, 861 unsigned int len, struct axe_csum_hdr *csum_hdr) 862 { 863 struct los_eth_driver *ifp = ue->ue_drv_sc; 864 865 struct pbuf *m = pbuf_alloc(PBUF_RAW, len+ETH_PAD_SIZE, PBUF_RAM); 866 struct pbuf *p; 867 868 if (len < ETHER_HDR_LEN) { 869 (void)pbuf_free(m); 870 return (EINVAL); 871 } 872 873 #if ETH_PAD_SIZE 874 /* drop the padding word */ 875 if (pbuf_header(m, -ETH_PAD_SIZE)) { 876 PRINTK("[AXE_ERROR]axe_rxeof : pbuf_header drop failed\n"); 877 (void)pbuf_free(m); 878 return (EINVAL); 879 } 880 #endif 881 882 for (p = m; p != NULL; p = p->next) 883 usbd_copy_out(pc, offset, p->payload, p->len); 884 885 #if ETH_PAD_SIZE 886 /* reclaim the padding word */ 887 if (pbuf_header(m, ETH_PAD_SIZE)) { 888 PRINTK("[AXE_ERROR]axe_rxeof : pbuf_header drop failed\n"); 889 (void)pbuf_free(m); 890 return (EINVAL); 891 } 892 #endif 893 894 driverif_input(&ifp->ac_if, m); 895 return (0); 896 } 897 898 #if ((AXE_BULK_BUF_SIZE >= 0x10000) || (AXE_BULK_BUF_SIZE < (MCLBYTES+4))) 899 #error "Please update axe_bulk_write_callback()!" 900 #endif 901 902 static void 903 axe_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error) 904 { 905 struct axe_softc *sc = usbd_xfer_softc(xfer); 906 struct axe_sframe_hdr hdr; 907 struct usb_ether *ue = &(sc->sc_ue); 908 struct los_eth_driver *ifp = ue->ue_drv_sc; 909 struct eth_drv_sc *drv_sc = (struct eth_drv_sc *)ifp->driver_context; 910 struct usb_page_cache *pc; 911 uint16_t txlen; 912 int nframes, pos; 913 struct pbuf *p; 914 uint8_t ustat; 915 916 ustat = USB_GET_STATE(xfer); 917 tr_setup: 918 switch (ustat) { 919 case USB_ST_TRANSFERRED: 920 DPRINTFN(11, "transfer complete\n"); 921 drv_sc->state &= ~IFF_DRV_OACTIVE; 922 /* FALLTHROUGH */ 923 924 case USB_ST_SETUP: 925 if (drv_sc->state & IFF_DRV_OACTIVE) 926 return; 927 928 UE_LOCK(ue); 929 IF_DEQUEUE(&(ue->ue_txq), p); 930 UE_UNLOCK(ue); 931 932 nframes = 0; 933 while (p) { 934 txlen = p->len; 935 if (txlen <= 0) 936 break; 937 938 usbd_xfer_set_frame_offset(xfer, nframes * MCLBYTES, nframes); 939 pos = 0; 940 pc = usbd_xfer_get_frame(xfer, nframes); 941 if (AXE_IS_178_FAMILY(sc)) { 942 hdr.len = htole16(txlen); 943 hdr.ilen = ~hdr.len; 944 usbd_copy_in(pc, pos, &hdr, sizeof(hdr)); 945 pos += sizeof(hdr); 946 usbd_copy_in(pc, pos, p->payload, txlen); 947 pos += txlen; 948 } else { 949 usbd_copy_in(pc, pos, p->payload, txlen); 950 pos += txlen; 951 } 952 953 /* Set frame length. */ 954 usbd_xfer_set_frame_len(xfer, nframes, pos); 955 956 uether_freebuf(p); 957 nframes++; 958 if (nframes >= USB_AXE_MAX_FRAMES) 959 break; 960 961 UE_LOCK(ue); 962 IF_DEQUEUE(&(ue->ue_txq), p); 963 UE_UNLOCK(ue); 964 } 965 if (nframes != 0) { 966 usbd_xfer_set_frames(xfer, nframes); 967 usbd_transfer_submit(xfer); 968 drv_sc->state |= IFF_DRV_OACTIVE; 969 } 970 break; 971 972 default: /* Error */ 973 DPRINTFN(11, "transfer error, %s\n", 974 usbd_errstr(error)); 975 drv_sc->state &= ~IFF_DRV_OACTIVE; 976 if (error != USB_ERR_CANCELLED) { 977 /* try to clear stall first */ 978 usbd_xfer_set_stall(xfer); 979 ustat = USB_ST_SETUP; 980 goto tr_setup; 981 } 982 break; 983 } 984 } 985 986 static void 987 axe_start(struct usb_ether *ue) 988 { 989 struct axe_softc *sc = ue->ue_sc; 990 991 /* 992 * start the USB transfers, if not already started: 993 */ 994 usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_WR]); 995 usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_RD]); 996 } 997 998 static void 999 axe_csum_cfg(struct usb_ether *ue) 1000 { 1001 (void)ue; 1002 } 1003 1004 static void 1005 axe_init(struct usb_ether *ue) 1006 { 1007 struct axe_softc *sc = uether_getsc(ue); 1008 struct los_eth_driver *ifp = ue->ue_drv_sc; 1009 struct eth_drv_sc *drv_sc = (struct eth_drv_sc *)ifp->driver_context; 1010 uint16_t rxmode; 1011 1012 drv_sc->state = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1013 1014 AXE_LOCK_ASSERT(sc, MA_OWNED); 1015 if ((drv_sc->state & IFF_DRV_RUNNING) != 0) 1016 return; 1017 1018 /* Cancel pending I/O */ 1019 axe_stop(ue); 1020 axe_reset(sc); 1021 1022 /* Set MAC address and transmitter IPG values. */ 1023 if (AXE_IS_178_FAMILY(sc)) { 1024 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr); 1025 axe_cmd(sc, AXE_178_CMD_WRITE_IPG012, sc->sc_ipgs[2], 1026 (sc->sc_ipgs[1] << 8) | (sc->sc_ipgs[0]), NULL); 1027 } else { 1028 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr); 1029 axe_cmd(sc, AXE_172_CMD_WRITE_IPG0, 0, sc->sc_ipgs[0], NULL); 1030 axe_cmd(sc, AXE_172_CMD_WRITE_IPG1, 0, sc->sc_ipgs[1], NULL); 1031 axe_cmd(sc, AXE_172_CMD_WRITE_IPG2, 0, sc->sc_ipgs[2], NULL); 1032 } 1033 if (AXE_IS_178_FAMILY(sc)) { 1034 sc->sc_flags &= ~(AXE_FLAG_STD_FRAME | AXE_FLAG_CSUM_FRAME); 1035 sc->sc_lenmask = AXE_HDR_LEN_MASK; 1036 sc->sc_flags |= AXE_FLAG_STD_FRAME; 1037 } 1038 /* Configure TX/RX checksum offloading. */ 1039 axe_csum_cfg(ue); 1040 if (sc->sc_flags & AXE_FLAG_772B) { 1041 /* AX88772B uses different maximum frame burst configuration. */ 1042 axe_cmd(sc, AXE_772B_CMD_RXCTL_WRITE_CFG, 1043 ax88772b_mfb_table[AX88772B_MFB_16K].threshold, 1044 ax88772b_mfb_table[AX88772B_MFB_16K].byte_cnt, NULL); 1045 } 1046 1047 /* Enable receiver, set RX mode. */ 1048 rxmode = (AXE_RXCMD_ALLMULTI | AXE_RXCMD_MULTICAST | AXE_RXCMD_ENABLE); 1049 if (AXE_IS_178_FAMILY(sc)) { 1050 if (sc->sc_flags & AXE_FLAG_772B) { 1051 /* 1052 * Select RX header format type 1. Aligning IP 1053 * header on 4 byte boundary is not needed when 1054 * checksum offloading feature is not used 1055 * because we always copy the received frame in 1056 * RX handler. When RX checksum offloading is 1057 * active, aligning IP header is required to 1058 * reflect actual frame length including RX 1059 * header size. 1060 */ 1061 rxmode |= AXE_772B_RXCMD_HDR_TYPE_1; 1062 } else { 1063 /* 1064 * Default Rx buffer size is too small to get 1065 * maximum performance. 1066 */ 1067 if (sc->sc_flags & AXE_FLAG_772A) 1068 rxmode |= AXE_178_RXCMD_MFB_16384; 1069 } 1070 } else { 1071 rxmode |= AXE_172_RXCMD_UNICAST; 1072 } 1073 1074 /* If we want promiscuous mode, set the allframes bit. */ 1075 if (drv_sc->state & IFF_PROMISC) 1076 rxmode |= AXE_RXCMD_PROMISC; 1077 1078 if (drv_sc->state & IFF_BROADCAST) 1079 rxmode |= AXE_RXCMD_BROADCAST; 1080 1081 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 1082 1083 /* Load the multicast filter. */ 1084 axe_setmulti(ue); 1085 1086 usbd_xfer_set_stall(sc->sc_xfer[AXE_BULK_DT_WR]); 1087 usbd_xfer_set_stall(sc->sc_xfer[AXE_BULK_DT_RD]); 1088 1089 drv_sc->state |= IFF_DRV_RUNNING; 1090 ifp->ac_if.link_layer_type = ETHERNET_DRIVER_IF; 1091 } 1092 1093 static void 1094 axe_setpromisc(struct usb_ether *ue) 1095 { 1096 struct axe_softc *sc = uether_getsc(ue); 1097 struct los_eth_driver *ifp = ue->ue_drv_sc; 1098 struct eth_drv_sc *drv_sc = (struct eth_drv_sc *)ifp->driver_context; 1099 uint16_t rxmode; 1100 1101 axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode); 1102 1103 rxmode = le16toh(rxmode); 1104 1105 if (drv_sc->state & IFF_PROMISC) { 1106 rxmode |= AXE_RXCMD_PROMISC; 1107 } else { 1108 rxmode &= ~AXE_RXCMD_PROMISC; 1109 } 1110 1111 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 1112 axe_setmulti(ue); 1113 } 1114 1115 static void 1116 axe_tick(struct usb_ether *ue) 1117 { 1118 struct axe_softc *sc = uether_getsc(ue); 1119 uint16_t link_status; 1120 1121 AXE_LOCK_ASSERT(sc, MA_OWNED); 1122 1123 link_status = axe_miibus_readreg(sc, MII_BMSR) & AXE_LINK_MASK; 1124 if (sc->sc_link_status != link_status) { 1125 axe_miibus_statchg(sc, link_status); 1126 sc->sc_link_status = link_status; 1127 } 1128 } 1129 1130 static void 1131 axe_stop(struct usb_ether *ue) 1132 { 1133 struct axe_softc *sc = uether_getsc(ue); 1134 struct los_eth_driver *ifp = ue->ue_drv_sc; 1135 struct eth_drv_sc *drv_sc = (struct eth_drv_sc *)ifp->driver_context; 1136 1137 AXE_LOCK_ASSERT(sc, MA_OWNED); 1138 drv_sc->state &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1139 sc->sc_flags &= ~AXE_FLAG_LINK; 1140 /* 1141 * stop all the transfers, if not already stopped: 1142 */ 1143 usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_WR]); 1144 usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_RD]); 1145 } 1146 1147 #undef USB_DEBUG_VAR 1148