1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 1997, 1998, 1999, 2000-2003 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: releng/12.2/sys/dev/usb/net/if_axereg.h 325966 2017-11-18 14:26:50Z pfg $ 35 */ 36 37 /* 38 * Definitions for the ASIX Electronics AX88172, AX88178 39 * and AX88772 to ethernet controllers. 40 */ 41 42 /* 43 * Vendor specific commands. ASIX conveniently doesn't document the 'set 44 * NODEID' command in their datasheet (thanks a lot guys). 45 * To make handling these commands easier, I added some extra data which is 46 * decided by the axe_cmd() routine. Commands are encoded in 16 bits, with 47 * the format: LDCC. L and D are both nibbles in the high byte. L represents 48 * the data length (0 to 15) and D represents the direction (0 for vendor read, 49 * 1 for vendor write). CC is the command byte, as specified in the manual. 50 */ 51 52 #ifndef LITEOS_USB_AXE_H 53 #define LITEOS_USB_AXE_H 54 55 #define USB_AXE_MAX_FRAMES 16 56 #ifndef MCLSHIFT 57 #define MCLSHIFT 11 /* convert bytes to mbuf clusters */ 58 #endif /* MCLSHIFT */ 59 60 #ifndef MCLBYTES 61 #define MCLBYTES (1 << MCLSHIFT) /* size of an mbuf cluster */ 62 #endif 63 #define ETHER_TYPE_LEN 2 /* length of the Ethernet type field */ 64 65 #define ETHER_HDR_LEN (NETIF_MAX_HWADDR_LEN*2 + ETHER_TYPE_LEN) 66 67 #define ETHER_ALIGN 2 /* driver adjust for IP hdr alignment */ 68 69 #define AXE_LINK_MASK 0x20 70 71 #define AXE_CMD_IS_WRITE(x) (((x) & 0x0F00) >> 8) 72 #define AXE_CMD_LEN(x) (((x) & 0xF000) >> 12) 73 #define AXE_CMD_CMD(x) ((x) & 0x00FF) 74 75 #define AXE_172_CMD_READ_RXTX_SRAM 0x2002 76 #define AXE_182_CMD_READ_RXTX_SRAM 0x8002 77 #define AXE_172_CMD_WRITE_RX_SRAM 0x0103 78 #define AXE_182_CMD_WRITE_RXTX_SRAM 0x8103 79 #define AXE_172_CMD_WRITE_TX_SRAM 0x0104 80 #define AXE_CMD_MII_OPMODE_SW 0x0106 81 #define AXE_CMD_MII_READ_REG 0x2007 82 #define AXE_CMD_MII_WRITE_REG 0x2108 83 #define AXE_CMD_MII_READ_OPMODE 0x1009 84 #define AXE_CMD_MII_OPMODE_HW 0x010A 85 #define AXE_CMD_SROM_READ 0x200B 86 #define AXE_CMD_SROM_WRITE 0x010C 87 #define AXE_CMD_SROM_WR_ENABLE 0x010D 88 #define AXE_CMD_SROM_WR_DISABLE 0x010E 89 #define AXE_CMD_RXCTL_READ 0x200F 90 #define AXE_CMD_RXCTL_WRITE 0x0110 91 #define AXE_CMD_READ_IPG012 0x3011 92 #define AXE_172_CMD_WRITE_IPG0 0x0112 93 #define AXE_178_CMD_WRITE_IPG012 0x0112 94 #define AXE_172_CMD_WRITE_IPG1 0x0113 95 #define AXE_178_CMD_READ_NODEID 0x6013 96 #define AXE_172_CMD_WRITE_IPG2 0x0114 97 #define AXE_178_CMD_WRITE_NODEID 0x6114 98 #define AXE_CMD_READ_MCAST 0x8015 99 #define AXE_CMD_WRITE_MCAST 0x8116 100 #define AXE_172_CMD_READ_NODEID 0x6017 101 #define AXE_172_CMD_WRITE_NODEID 0x6118 102 103 #define AXE_CMD_READ_PHYID 0x2019 104 #define AXE_172_CMD_READ_MEDIA 0x101A 105 #define AXE_178_CMD_READ_MEDIA 0x201A 106 #define AXE_CMD_WRITE_MEDIA 0x011B 107 #define AXE_CMD_READ_MONITOR_MODE 0x101C 108 #define AXE_CMD_WRITE_MONITOR_MODE 0x011D 109 #define AXE_CMD_READ_GPIO 0x101E 110 #define AXE_CMD_WRITE_GPIO 0x011F 111 112 #define AXE_CMD_SW_RESET_REG 0x0120 113 #define AXE_CMD_SW_PHY_STATUS 0x0021 114 #define AXE_CMD_SW_PHY_SELECT 0x0122 115 116 /* AX88772A and AX88772B only. */ 117 #define AXE_CMD_READ_VLAN_CTRL 0x4027 118 #define AXE_CMD_WRITE_VLAN_CTRL 0x4028 119 120 #define AXE_772B_CMD_RXCTL_WRITE_CFG 0x012A 121 #define AXE_772B_CMD_READ_RXCSUM 0x002B 122 #define AXE_772B_CMD_WRITE_RXCSUM 0x012C 123 #define AXE_772B_CMD_READ_TXCSUM 0x002D 124 #define AXE_772B_CMD_WRITE_TXCSUM 0x012E 125 126 #define AXE_SW_RESET_CLEAR 0x00 127 #define AXE_SW_RESET_RR 0x01 128 #define AXE_SW_RESET_RT 0x02 129 #define AXE_SW_RESET_PRTE 0x04 130 #define AXE_SW_RESET_PRL 0x08 131 #define AXE_SW_RESET_BZ 0x10 132 #define AXE_SW_RESET_IPRL 0x20 133 #define AXE_SW_RESET_IPPD 0x40 134 135 /* AX88178 documentation says to always write this bit... */ 136 #define AXE_178_RESET_MAGIC 0x40 137 138 #define AXE_178_MEDIA_GMII 0x0001 139 #define AXE_MEDIA_FULL_DUPLEX 0x0002 140 #define AXE_172_MEDIA_TX_ABORT_ALLOW 0x0004 141 142 /* AX88178/88772 documentation says to always write 1 to bit 2 */ 143 #define AXE_178_MEDIA_MAGIC 0x0004 144 /* AX88772 documentation says to always write 0 to bit 3 */ 145 #define AXE_178_MEDIA_ENCK 0x0008 146 #define AXE_172_MEDIA_FLOW_CONTROL_EN 0x0010 147 #define AXE_178_MEDIA_RXFLOW_CONTROL_EN 0x0010 148 #define AXE_178_MEDIA_TXFLOW_CONTROL_EN 0x0020 149 #define AXE_178_MEDIA_JUMBO_EN 0x0040 150 #define AXE_178_MEDIA_LTPF_ONLY 0x0080 151 #define AXE_178_MEDIA_RX_EN 0x0100 152 #define AXE_178_MEDIA_100TX 0x0200 153 #define AXE_178_MEDIA_SBP 0x0800 154 #define AXE_178_MEDIA_SUPERMAC 0x1000 155 156 #define AXE_RXCMD_PROMISC 0x0001 157 #define AXE_RXCMD_ALLMULTI 0x0002 158 #define AXE_172_RXCMD_UNICAST 0x0004 159 #define AXE_178_RXCMD_KEEP_INVALID_CRC 0x0004 160 #define AXE_RXCMD_BROADCAST 0x0008 161 #define AXE_RXCMD_MULTICAST 0x0010 162 #define AXE_RXCMD_ACCEPT_RUNT 0x0040 /* AX88772B */ 163 #define AXE_RXCMD_ENABLE 0x0080 164 #define AXE_178_RXCMD_MFB_MASK 0x0300 165 #define AXE_178_RXCMD_MFB_2048 0x0000 166 #define AXE_178_RXCMD_MFB_4096 0x0100 167 #define AXE_178_RXCMD_MFB_8192 0x0200 168 #define AXE_178_RXCMD_MFB_16384 0x0300 169 #define AXE_772B_RXCMD_HDR_TYPE_0 0x0000 170 #define AXE_772B_RXCMD_HDR_TYPE_1 0x0100 171 #define AXE_772B_RXCMD_IPHDR_ALIGN 0x0200 172 #define AXE_772B_RXCMD_ADD_CHKSUM 0x0400 173 #define AXE_RXCMD_LOOPBACK 0x1000 /* AX88772A/AX88772B */ 174 175 #define AXE_PHY_SEL_PRI 1 176 #define AXE_PHY_SEL_SEC 0 177 #define AXE_PHY_TYPE_MASK 0xE0 178 #define AXE_PHY_TYPE_SHIFT 5 179 #define AXE_PHY_TYPE(x) \ 180 (((x) & AXE_PHY_TYPE_MASK) >> AXE_PHY_TYPE_SHIFT) 181 182 #define PHY_TYPE_100_HOME 0 /* 10/100 or 1M HOME PHY */ 183 #define PHY_TYPE_GIG 1 /* Gigabit PHY */ 184 #define PHY_TYPE_SPECIAL 4 /* Special case */ 185 #define PHY_TYPE_RSVD 5 /* Reserved */ 186 #define PHY_TYPE_NON_SUP 7 /* Non-supported PHY */ 187 188 #define AXE_PHY_NO_MASK 0x1F 189 #define AXE_PHY_NO(x) ((x) & AXE_PHY_NO_MASK) 190 191 #define AXE_772_PHY_NO_EPHY 0x10 /* Embedded 10/100 PHY of AX88772 */ 192 193 #define AXE_GPIO0_EN 0x01 194 #define AXE_GPIO0 0x02 195 #define AXE_GPIO1_EN 0x04 196 #define AXE_GPIO1 0x08 197 #define AXE_GPIO2_EN 0x10 198 #define AXE_GPIO2 0x20 199 #define AXE_GPIO_RELOAD_EEPROM 0x80 200 201 #define AXE_PHY_MODE_MARVELL 0x00 202 #define AXE_PHY_MODE_CICADA 0x01 203 #define AXE_PHY_MODE_AGERE 0x02 204 #define AXE_PHY_MODE_CICADA_V2 0x05 205 #define AXE_PHY_MODE_AGERE_GMII 0x06 206 #define AXE_PHY_MODE_CICADA_V2_ASIX 0x09 207 #define AXE_PHY_MODE_REALTEK_8211CL 0x0C 208 #define AXE_PHY_MODE_REALTEK_8211BN 0x0D 209 #define AXE_PHY_MODE_REALTEK_8251CL 0x0E 210 #define AXE_PHY_MODE_ATTANSIC 0x40 211 212 /* AX88772A/AX88772B only. */ 213 #define AXE_SW_PHY_SELECT_EXT 0x0000 214 #define AXE_SW_PHY_SELECT_EMBEDDED 0x0001 215 #define AXE_SW_PHY_SELECT_AUTO 0x0002 216 #define AXE_SW_PHY_SELECT_SS_MII 0x0004 217 #define AXE_SW_PHY_SELECT_SS_RVRS_MII 0x0008 218 #define AXE_SW_PHY_SELECT_SS_RVRS_RMII 0x000C 219 #define AXE_SW_PHY_SELECT_SS_ENB 0x0010 220 221 /* AX88772A/AX88772B VLAN control. */ 222 #define AXE_VLAN_CTRL_ENB 0x00001000 223 #define AXE_VLAN_CTRL_STRIP 0x00002000 224 #define AXE_VLAN_CTRL_VID1_MASK 0x00000FFF 225 #define AXE_VLAN_CTRL_VID2_MASK 0x0FFF0000 226 227 #define AXE_RXCSUM_IP 0x0001 228 #define AXE_RXCSUM_IPVE 0x0002 229 #define AXE_RXCSUM_IPV6E 0x0004 230 #define AXE_RXCSUM_TCP 0x0008 231 #define AXE_RXCSUM_UDP 0x0010 232 #define AXE_RXCSUM_ICMP 0x0020 233 #define AXE_RXCSUM_IGMP 0x0040 234 #define AXE_RXCSUM_ICMP6 0x0080 235 #define AXE_RXCSUM_TCPV6 0x0100 236 #define AXE_RXCSUM_UDPV6 0x0200 237 #define AXE_RXCSUM_ICMPV6 0x0400 238 #define AXE_RXCSUM_IGMPV6 0x0800 239 #define AXE_RXCSUM_ICMP6V6 0x1000 240 #define AXE_RXCSUM_FOPC 0x8000 241 242 #define AXE_RXCSUM_64TE 0x0100 243 #define AXE_RXCSUM_PPPOE 0x0200 244 #define AXE_RXCSUM_RPCE 0x8000 245 246 #define AXE_TXCSUM_IP 0x0001 247 #define AXE_TXCSUM_TCP 0x0002 248 #define AXE_TXCSUM_UDP 0x0004 249 #define AXE_TXCSUM_ICMP 0x0008 250 #define AXE_TXCSUM_IGMP 0x0010 251 #define AXE_TXCSUM_ICMP6 0x0020 252 #define AXE_TXCSUM_TCPV6 0x0100 253 #define AXE_TXCSUM_UDPV6 0x0200 254 #define AXE_TXCSUM_ICMPV6 0x0400 255 #define AXE_TXCSUM_IGMPV6 0x0800 256 #define AXE_TXCSUM_ICMP6V6 0x1000 257 258 #define AXE_TXCSUM_64TE 0x0001 259 #define AXE_TXCSUM_PPPOE 0x0002 260 261 #define AXE_BULK_BUF_SIZE 16384 /* bytes */ 262 263 #define AXE_CTL_READ 0x01 264 #define AXE_CTL_WRITE 0x02 265 266 #define AXE_CONFIG_IDX 0 /* config number 1 */ 267 #define AXE_IFACE_IDX 0 268 269 /* EEPROM Map. */ 270 #define AXE_EEPROM_772B_NODE_ID 0x04 271 #define AXE_EEPROM_772B_PHY_PWRCFG 0x18 272 273 struct ax88772b_mfb { 274 int byte_cnt; 275 int threshold; 276 int size; 277 }; 278 #define AX88772B_MFB_2K 0 279 #define AX88772B_MFB_4K 1 280 #define AX88772B_MFB_6K 2 281 #define AX88772B_MFB_8K 3 282 #define AX88772B_MFB_16K 4 283 #define AX88772B_MFB_20K 5 284 #define AX88772B_MFB_24K 6 285 #define AX88772B_MFB_32K 7 286 287 struct axe_sframe_hdr { 288 uint16_t len; 289 #define AXE_HDR_LEN_MASK 0xFFFF 290 uint16_t ilen; 291 } __packed; 292 293 #define AXE_TX_CSUM_PSEUDO_HDR 0x4000 294 #define AXE_TX_CSUM_DIS 0x8000 295 296 /* 297 * When RX checksum offloading is enabled, AX88772B uses new RX header 298 * format and it's not compatible with previous RX header format. In 299 * addition, IP header align option should be enabled to get correct 300 * frame size including RX header. Total transferred size including 301 * the RX header is multiple of 4 and controller will pad necessary 302 * bytes if the length is not multiple of 4. 303 * This driver does not enable partial checksum feature which will 304 * compute 16bit checksum from 14th byte to the end of the frame. If 305 * this feature is enabled, computed checksum value is embedded into 306 * RX header which in turn means it uses different RX header format. 307 */ 308 struct axe_csum_hdr { 309 uint16_t len; 310 #define AXE_CSUM_HDR_LEN_MASK 0x07FF 311 #define AXE_CSUM_HDR_CRC_ERR 0x1000 312 #define AXE_CSUM_HDR_MII_ERR 0x2000 313 #define AXE_CSUM_HDR_RUNT 0x4000 314 #define AXE_CSUM_HDR_BMCAST 0x8000 315 uint16_t ilen; 316 uint16_t cstatus; 317 #define AXE_CSUM_HDR_VLAN_MASK 0x0007 318 #define AXE_CSUM_HDR_VLAN_STRIP 0x0008 319 #define AXE_CSUM_HDR_VLAN_PRI_MASK 0x0070 320 #define AXE_CSUM_HDR_L4_CSUM_ERR 0x0100 321 #define AXE_CSUM_HDR_L3_CSUM_ERR 0x0200 322 #define AXE_CSUM_HDR_L4_TYPE_UDP 0x0400 323 #define AXE_CSUM_HDR_L4_TYPE_ICMP 0x0800 324 #define AXE_CSUM_HDR_L4_TYPE_IGMP 0x0C00 325 #define AXE_CSUM_HDR_L4_TYPE_TCP 0x1000 326 #define AXE_CSUM_HDR_L4_TYPE_TCPV6 0x1400 327 #define AXE_CSUM_HDR_L4_TYPE_MASK 0x1C00 328 #define AXE_CSUM_HDR_L3_TYPE_IPV4 0x2000 329 #define AXE_CSUM_HDR_L3_TYPE_IPV6 0x4000 330 331 #ifdef AXE_APPEND_PARTIAL_CSUM 332 /* 333 * These members present only when partial checksum 334 * offloading is enabled. The checksum value is simple 335 * 16bit sum of received frame starting at offset 14 of 336 * the frame to the end of the frame excluding FCS bytes. 337 */ 338 uint16_t csum_value; 339 uint16_t dummy; 340 #endif 341 } __packed; 342 343 #define AXE_CSUM_RXBYTES(x) ((x) & AXE_CSUM_HDR_LEN_MASK) 344 345 #define GET_MII(sc) uether_getmii(&(sc)->sc_ue) 346 347 /* The interrupt endpoint is currently unused by the ASIX part. */ 348 enum { 349 AXE_BULK_DT_WR, 350 AXE_BULK_DT_RD, 351 AXE_N_TRANSFER, 352 }; 353 354 struct axe_softc { 355 struct usb_ether sc_ue; 356 struct mtx sc_mtx; 357 struct usb_xfer *sc_xfer[AXE_N_TRANSFER]; 358 int sc_phyno; 359 360 unsigned int sc_flags; 361 uint16_t sc_link_status; 362 #define AXE_FLAG_LINK 0x0001 363 #define AXE_FLAG_STD_FRAME 0x0010 364 #define AXE_FLAG_CSUM_FRAME 0x0020 365 #define AXE_FLAG_772 0x1000 /* AX88772 */ 366 #define AXE_FLAG_772A 0x2000 /* AX88772A */ 367 #define AXE_FLAG_772B 0x4000 /* AX88772B */ 368 #define AXE_FLAG_178 0x8000 /* AX88178 */ 369 370 uint8_t sc_ipgs[3]; 371 uint8_t sc_phyaddrs[2]; 372 uint16_t sc_pwrcfg; 373 uint16_t sc_lenmask; 374 uint8_t rx_chklink_cnt; 375 #define EVENT_LINK 0x00000001 376 }; 377 378 #define AXE_IS_178_FAMILY(sc) \ 379 ((sc)->sc_flags & (AXE_FLAG_772 | AXE_FLAG_772A | AXE_FLAG_772B | \ 380 AXE_FLAG_178)) 381 382 #define AXE_IS_772(sc) \ 383 ((sc)->sc_flags & (AXE_FLAG_772 | AXE_FLAG_772A | AXE_FLAG_772B)) 384 385 #define AXE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 386 #define AXE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 387 #define AXE_LOCK_ASSERT(_sc, t) mtx_assert(&(_sc)->sc_mtx, t) 388 389 #endif 390