1/* 2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. 3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without modification, 6 * are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, this list of 9 * conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, this list 12 * of conditions and the following disclaimer in the documentation and/or other materials 13 * provided with the distribution. 14 * 15 * 3. Neither the name of the copyright holder nor the names of its contributors may be used 16 * to endorse or promote products derived from this software without specific prior written 17 * permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 20 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 29 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 .equ CPSR_IRQ_DISABLE, 0x80 33 .equ CPSR_FIQ_DISABLE, 0x40 34 .equ CPSR_THUMB_ENABLE, 0x20 35 .equ CPSR_USER_MODE, 0x10 36 .equ CPSR_FIQ_MODE, 0x11 37 .equ CPSR_IRQ_MODE, 0x12 38 .equ CPSR_SVC_MODE, 0x13 39 .equ CPSR_ABT_MODE, 0x17 40 .equ CPSR_UNDEF_MODE, 0x1B 41 42 .global __exc_stack_top 43 .global __irq_stack_top 44 .global __fiq_stack_top 45 .global __svc_stack_top 46 .global __abt_stack_top 47 .global __undef_stack_top 48 .global __exc_stack 49 .global __irq_stack 50 .global __fiq_stack 51 .global __svc_stack 52 .global __abt_stack 53 .global __undef_stack 54 .global main 55 56 .extern HalExceptFiqHdl 57 .extern HalExceptAddrAbortHdl 58 .extern HalExceptDataAbortHdl 59 .extern HalExceptPrefetchAbortHdl 60 .extern HalExceptSwiHdl 61 .extern HalExceptUndefInstrHdl 62 .extern HalExceptIrqHdl 63 .extern _bss_start 64 .extern _bss_end 65 66 .code 32 67 .text 68 69 .section ".vectors", "ax" 70 .global _vector_start 71 72_vector_start: 73 B HalResetVector 74 B HalExceptUndefInstrHdl 75 B HalExceptSwiHdl 76 B HalExceptPrefetchAbortHdl 77 B HalExceptDataAbortHdl 78 B HalExceptAddrAbortHdl 79 B HalExceptIrqHdl 80 B HalExceptFiqHdl 81 82 .globl HalResetVector 83 .section ".boot", "ax" 84 85HalResetVector: 86 MOV R0, #(CPSR_IRQ_DISABLE | CPSR_FIQ_DISABLE | CPSR_IRQ_MODE) 87 MSR CPSR, R0 88 LDR SP, =__irq_stack_top 89 90 MOV R0, #(CPSR_IRQ_DISABLE | CPSR_FIQ_DISABLE | CPSR_UNDEF_MODE) 91 MSR CPSR, R0 92 LDR SP, =__undef_stack_top 93 94 MOV R0, #(CPSR_IRQ_DISABLE | CPSR_FIQ_DISABLE | CPSR_ABT_MODE) 95 MSR CPSR, R0 96 LDR SP, =__abt_stack_top 97 98 MOV R0, #(CPSR_IRQ_DISABLE | CPSR_FIQ_DISABLE | CPSR_FIQ_MODE) 99 MSR CPSR, R0 100 LDR SP, =__fiq_stack_top 101 102 MOV R0, #(CPSR_IRQ_DISABLE | CPSR_FIQ_DISABLE | CPSR_SVC_MODE) 103 MSR CPSR, R0 104 MSR SPSR, R0 105 LDR SP, =__svc_stack_top 106 107 BL OsBssInit 108 109 B main 110 B . 111 112OsBssInit: 113 LDR R0, =_bss_start 114 LDR R1, =_bss_end 115 116 MOV R3, R1 117 MOV R4, R0 118 MOV R2, #0 1191: CMP R4, R3 120 STRLO R2, [R4], #4 121 BLO 1b 122 BX LR 123 124 .section ".bss", "wa", %nobits 125 .align 3 126__undef_stack: 127 .space 32 128__undef_stack_top: 129 130__abt_stack: 131 .space 32 132__abt_stack_top: 133 134__irq_stack: 135 .space 1024 136__irq_stack_top: 137 138__fiq_stack: 139 .space 1024 140__fiq_stack_top: 141 142__svc_stack: 143 .space 1024 144__svc_stack_top: 145 146__exc_stack: 147 .space 512 148__exc_stack_top: 149 150