1 /* 2 * Copyright (c) 2013-2020, Huawei Technologies Co., Ltd. All rights reserved. 3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without modification, 6 * are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, this list of 9 * conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, this list 12 * of conditions and the following disclaimer in the documentation and/or other materials 13 * provided with the distribution. 14 * 15 * 3. Neither the name of the copyright holder nor the names of its contributors may be used 16 * to endorse or promote products derived from this software without specific prior written 17 * permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 20 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 29 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _SOC_COMMON_H 33 #define _SOC_COMMON_H 34 35 #define LREG lw 36 #define SREG sw 37 #define REGBYTES 4 38 39 #define EXC_SIZE_ON_STACK (36 * REGBYTES) 40 #define INT_SIZE_ON_STACK (32 * REGBYTES) 41 42 /* task TCB offset */ 43 #define TASK_CB_KERNEL_SP 0x0 44 #define TASK_CB_STATUS 0x4 45 46 #define UINT32_CUT_MASK 0xFFFFFFFF 47 #define UINT8_CUT_MASK 0xFF 48 #define OS_MV_32_BIT 32 49 50 /************************ mstatus ************************/ 51 #define RISCV_MSTATUS_UIE 0x00000001 52 #define RISCV_MSTATUS_MIE 0x00000008 53 #define RISCV_MSTATUS_UPIE 0x00000010 54 #define RISCV_MSTATUS_MPIE 0x00000080 55 #define RISCV_MSTATUS_MPP 0x00001800 56 57 /************************ mie ***************************/ 58 #define RISCV_MIE_USIE 0x000000001 59 #define RISCV_MIE_MSIE 0x000000008 60 #define RISCV_MIE_UTIE 0x000000010 61 #define RISCV_MIE_MTIE 0x000000080 62 #define RISCV_MIE_UEIE 0x000000100 63 #define RISCV_MIE_MEIE 0x000000800 64 65 /************************** mcause ***********************/ 66 #define RISCV_MCAUSE_ECALL_U 8 67 68 #define RISCV_USER_SOFT_IRQ 0 69 #define RISCV_MACH_SOFT_IRQ 3 70 #define RISCV_USER_TIMER_IRQ 4 71 #define RISCV_MACH_TIMER_IRQ 7 72 #define RISCV_USER_EXT_IRQ 8 73 #define RISCV_MACH_EXT_IRQ 11 74 75 76 #define READ_CSR(reg) ({ \ 77 UINT32 _tmp; \ 78 __asm__ volatile("csrr %0, " #reg : "=r"(_tmp) : : "memory"); \ 79 _tmp; \ 80 }) 81 82 #define WRITE_CSR(reg, val) ({ \ 83 __asm__ volatile("csrw " #reg ", %0" : : "r"(val) : "memory"); \ 84 }) 85 86 #define SET_CSR(reg, val) ({ \ 87 __asm__ volatile("csrs " #reg ", %0" : : "r"(val) : "memory"); \ 88 }) 89 90 #define CLEAR_CSR(reg, val) ({ \ 91 __asm__ volatile("csrc " #reg ", %0" : : "r"(val) : "memory"); \ 92 }) 93 94 #define READ_CUSTOM_CSR(reg) ({ \ 95 UINT32 _tmp; \ 96 __asm__ volatile("csrr %0, %1" : "=r"(_tmp) : "i"(reg) : "memory"); \ 97 _tmp; \ 98 }) 99 100 #define WRITE_CUSTOM_CSR(reg, val) ({ \ 101 __asm__ volatile("csrw %0, %1" : : "i"(reg), "r"(val) : "memory"); \ 102 }) 103 104 #define SET_CUSTOM_CSR(reg, val) ({ \ 105 __asm__ volatile("csrs " #reg ", %0" : : "r"(val) : "memory"); \ 106 }) 107 108 #define CLEAR_CUSTOM_CSR(reg, val) ({ \ 109 __asm__ volatile("csrc " #reg ", %0" : : "r"(val) : "memory"); \ 110 }) 111 112 #endif 113