Lines Matching refs:temp
60 u32 temp; in xhci_create_usb3_bos_desc() local
99 temp = readl(&xhci->cap_regs->hcc_params); in xhci_create_usb3_bos_desc()
100 if (HCC_LTC(temp)) in xhci_create_usb3_bos_desc()
105 temp = readl(&xhci->cap_regs->hcs_params3); in xhci_create_usb3_bos_desc()
106 buf[12] = HCS_U1_LATENCY(temp); in xhci_create_usb3_bos_desc()
107 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]); in xhci_create_usb3_bos_desc()
172 u16 temp; in xhci_common_hub_descriptor() local
177 temp = 0; in xhci_common_hub_descriptor()
180 temp |= HUB_CHAR_INDV_PORT_LPSM; in xhci_common_hub_descriptor()
182 temp |= HUB_CHAR_NO_LPSM; in xhci_common_hub_descriptor()
185 temp |= HUB_CHAR_INDV_PORT_OCPM; in xhci_common_hub_descriptor()
188 desc->wHubCharacteristics = cpu_to_le16(temp); in xhci_common_hub_descriptor()
196 u16 temp; in xhci_usb2_hub_descriptor() local
206 temp = 1 + (ports / 8); in xhci_usb2_hub_descriptor()
207 desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp; in xhci_usb2_hub_descriptor()
575 u32 temp; in xhci_set_port_power() local
579 temp = readl(port->addr); in xhci_set_port_power()
582 hcd->self.busnum, index + 1, on ? "ON" : "OFF", temp); in xhci_set_port_power()
584 temp = xhci_port_state_to_neutral(temp); in xhci_set_port_power()
588 writel(temp | PORT_POWER, port->addr); in xhci_set_port_power()
592 writel(temp & ~PORT_POWER, port->addr); in xhci_set_port_power()
596 temp = usb_acpi_power_manageable(hcd->self.root_hub, in xhci_set_port_power()
598 if (temp) in xhci_set_port_power()
607 u32 temp; in xhci_port_set_test_mode() local
612 temp = readl(port->addr + PORTPMSC); in xhci_port_set_test_mode()
613 temp |= test_mode << PORT_TEST_MODE_SHIFT; in xhci_port_set_test_mode()
614 writel(temp, port->addr + PORTPMSC); in xhci_port_set_test_mode()
685 u32 temp; in xhci_set_link_state() local
689 temp = xhci_port_state_to_neutral(portsc); in xhci_set_link_state()
690 temp &= ~PORT_PLS_MASK; in xhci_set_link_state()
691 temp |= PORT_LINK_STROBE | link_state; in xhci_set_link_state()
692 writel(temp, port->addr); in xhci_set_link_state()
696 portsc, temp); in xhci_set_link_state()
702 u32 temp; in xhci_set_remote_wake_mask() local
704 temp = readl(port->addr); in xhci_set_remote_wake_mask()
705 temp = xhci_port_state_to_neutral(temp); in xhci_set_remote_wake_mask()
708 temp |= PORT_WKCONN_E; in xhci_set_remote_wake_mask()
710 temp &= ~PORT_WKCONN_E; in xhci_set_remote_wake_mask()
713 temp |= PORT_WKDISC_E; in xhci_set_remote_wake_mask()
715 temp &= ~PORT_WKDISC_E; in xhci_set_remote_wake_mask()
718 temp |= PORT_WKOC_E; in xhci_set_remote_wake_mask()
720 temp &= ~PORT_WKOC_E; in xhci_set_remote_wake_mask()
722 writel(temp, port->addr); in xhci_set_remote_wake_mask()
729 u32 temp; in xhci_test_and_clear_bit() local
731 temp = readl(port->addr); in xhci_test_and_clear_bit()
732 if (temp & port_bit) { in xhci_test_and_clear_bit()
733 temp = xhci_port_state_to_neutral(temp); in xhci_test_and_clear_bit()
734 temp |= port_bit; in xhci_test_and_clear_bit()
735 writel(temp, port->addr); in xhci_test_and_clear_bit()
1098 u32 temp, status; in xhci_hub_control() local
1149 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1150 if (temp == ~(u32)0) { in xhci_hub_control()
1155 trace_xhci_get_port_status(wIndex, temp); in xhci_hub_control()
1156 status = xhci_get_port_status(hcd, bus_state, wIndex, temp, in xhci_hub_control()
1162 hcd->self.busnum, wIndex + 1, temp, status); in xhci_hub_control()
1175 status = xhci_get_ext_port_status(temp, port_li); in xhci_hub_control()
1192 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1193 if (temp == ~(u32)0) { in xhci_hub_control()
1198 temp = xhci_port_state_to_neutral(temp); in xhci_hub_control()
1202 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1203 if ((temp & PORT_PLS_MASK) != XDEV_U0) { in xhci_hub_control()
1215 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1216 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) in xhci_hub_control()
1217 || (temp & PORT_PLS_MASK) >= XDEV_U3) { in xhci_hub_control()
1240 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1244 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1249 temp = xhci_port_state_to_neutral(temp); in xhci_hub_control()
1254 temp |= PORT_CSC | PORT_PEC | PORT_WRC | in xhci_hub_control()
1257 writel(temp | PORT_PE, ports[wIndex]->addr); in xhci_hub_control()
1258 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1268 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1292 if ((temp & PORT_CONNECT)) { in xhci_hub_control()
1302 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1306 if (!(temp & PORT_PE)) { in xhci_hub_control()
1326 u32 pls = temp & PORT_PLS_MASK; in xhci_hub_control()
1352 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1372 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1373 if ((temp & PORT_PLS_MASK) == XDEV_U3) in xhci_hub_control()
1377 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1391 temp = (temp | PORT_RESET); in xhci_hub_control()
1392 writel(temp, ports[wIndex]->addr); in xhci_hub_control()
1394 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1396 hcd->self.busnum, wIndex + 1, temp); in xhci_hub_control()
1401 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1403 hcd->self.busnum, wIndex + 1, temp); in xhci_hub_control()
1406 temp |= PORT_WR; in xhci_hub_control()
1407 writel(temp, ports[wIndex]->addr); in xhci_hub_control()
1408 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1413 temp = readl(ports[wIndex]->addr + PORTPMSC); in xhci_hub_control()
1414 temp &= ~PORT_U1_TIMEOUT_MASK; in xhci_hub_control()
1415 temp |= PORT_U1_TIMEOUT(timeout); in xhci_hub_control()
1416 writel(temp, ports[wIndex]->addr + PORTPMSC); in xhci_hub_control()
1421 temp = readl(ports[wIndex]->addr + PORTPMSC); in xhci_hub_control()
1422 temp &= ~PORT_U2_TIMEOUT_MASK; in xhci_hub_control()
1423 temp |= PORT_U2_TIMEOUT(timeout); in xhci_hub_control()
1424 writel(temp, ports[wIndex]->addr + PORTPMSC); in xhci_hub_control()
1440 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1446 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1447 if (temp == ~(u32)0) { in xhci_hub_control()
1453 temp = xhci_port_state_to_neutral(temp); in xhci_hub_control()
1456 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1458 xhci_dbg(xhci, "PORTSC %04x\n", temp); in xhci_hub_control()
1459 if (temp & PORT_RESET) in xhci_hub_control()
1461 if ((temp & PORT_PLS_MASK) == XDEV_U3) { in xhci_hub_control()
1462 if ((temp & PORT_PE) == 0) in xhci_hub_control()
1498 ports[wIndex]->addr, temp); in xhci_hub_control()
1502 ports[wIndex]->addr, temp); in xhci_hub_control()
1534 u32 temp, status; in xhci_hub_status_data() local
1565 temp = readl(ports[i]->addr); in xhci_hub_status_data()
1566 if (temp == ~(u32)0) { in xhci_hub_status_data()
1571 trace_xhci_hub_status_data(i, temp); in xhci_hub_status_data()
1573 if ((temp & mask) != 0 || in xhci_hub_status_data()
1580 if ((temp & PORT_RC)) in xhci_hub_status_data()
1582 if (temp & PORT_OC) in xhci_hub_status_data()
1762 u32 temp, portsc; in xhci_bus_resume() local
1781 temp = readl(&xhci->op_regs->command); in xhci_bus_resume()
1782 temp &= ~CMD_EIE; in xhci_bus_resume()
1783 writel(temp, &xhci->op_regs->command); in xhci_bus_resume()
1860 temp = readl(&xhci->op_regs->command); in xhci_bus_resume()
1861 temp |= CMD_EIE; in xhci_bus_resume()
1862 writel(temp, &xhci->op_regs->command); in xhci_bus_resume()
1863 temp = readl(&xhci->op_regs->command); in xhci_bus_resume()