1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * xHCI host controller driver
4 *
5 * Copyright (C) 2008 Intel Corp.
6 *
7 * Author: Sarah Sharp
8 * Some code borrowed from the Linux EHCI driver.
9 */
10
11
12 #include <linux/slab.h>
13 #include <asm/unaligned.h>
14
15 #include "xhci.h"
16 #include "xhci-trace.h"
17
18 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
19 #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
20 PORT_RC | PORT_PLC | PORT_PE)
21
22 /* USB 3 BOS descriptor and a capability descriptors, combined.
23 * Fields will be adjusted and added later in xhci_create_usb3_bos_desc()
24 */
25 static u8 usb_bos_descriptor [] = {
26 USB_DT_BOS_SIZE, /* __u8 bLength, 5 bytes */
27 USB_DT_BOS, /* __u8 bDescriptorType */
28 0x0F, 0x00, /* __le16 wTotalLength, 15 bytes */
29 0x1, /* __u8 bNumDeviceCaps */
30 /* First device capability, SuperSpeed */
31 USB_DT_USB_SS_CAP_SIZE, /* __u8 bLength, 10 bytes */
32 USB_DT_DEVICE_CAPABILITY, /* Device Capability */
33 USB_SS_CAP_TYPE, /* bDevCapabilityType, SUPERSPEED_USB */
34 0x00, /* bmAttributes, LTM off by default */
35 USB_5GBPS_OPERATION, 0x00, /* wSpeedsSupported, 5Gbps only */
36 0x03, /* bFunctionalitySupport,
37 USB 3.0 speed only */
38 0x00, /* bU1DevExitLat, set later. */
39 0x00, 0x00, /* __le16 bU2DevExitLat, set later. */
40 /* Second device capability, SuperSpeedPlus */
41 0x1c, /* bLength 28, will be adjusted later */
42 USB_DT_DEVICE_CAPABILITY, /* Device Capability */
43 USB_SSP_CAP_TYPE, /* bDevCapabilityType SUPERSPEED_PLUS */
44 0x00, /* bReserved 0 */
45 0x23, 0x00, 0x00, 0x00, /* bmAttributes, SSAC=3 SSIC=1 */
46 0x01, 0x00, /* wFunctionalitySupport */
47 0x00, 0x00, /* wReserved 0 */
48 /* Default Sublink Speed Attributes, overwrite if custom PSI exists */
49 0x34, 0x00, 0x05, 0x00, /* 5Gbps, symmetric, rx, ID = 4 */
50 0xb4, 0x00, 0x05, 0x00, /* 5Gbps, symmetric, tx, ID = 4 */
51 0x35, 0x40, 0x0a, 0x00, /* 10Gbps, SSP, symmetric, rx, ID = 5 */
52 0xb5, 0x40, 0x0a, 0x00, /* 10Gbps, SSP, symmetric, tx, ID = 5 */
53 };
54
xhci_create_usb3_bos_desc(struct xhci_hcd * xhci,char * buf,u16 wLength)55 static int xhci_create_usb3_bos_desc(struct xhci_hcd *xhci, char *buf,
56 u16 wLength)
57 {
58 struct xhci_port_cap *port_cap = NULL;
59 int i, ssa_count;
60 u32 temp;
61 u16 desc_size, ssp_cap_size, ssa_size = 0;
62 bool usb3_1 = false;
63
64 desc_size = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
65 ssp_cap_size = sizeof(usb_bos_descriptor) - desc_size;
66
67 /* does xhci support USB 3.1 Enhanced SuperSpeed */
68 for (i = 0; i < xhci->num_port_caps; i++) {
69 if (xhci->port_caps[i].maj_rev == 0x03 &&
70 xhci->port_caps[i].min_rev >= 0x01) {
71 usb3_1 = true;
72 port_cap = &xhci->port_caps[i];
73 break;
74 }
75 }
76
77 if (usb3_1) {
78 /* does xhci provide a PSI table for SSA speed attributes? */
79 if (port_cap->psi_count) {
80 /* two SSA entries for each unique PSI ID, RX and TX */
81 ssa_count = port_cap->psi_uid_count * 2;
82 ssa_size = ssa_count * sizeof(u32);
83 ssp_cap_size -= 16; /* skip copying the default SSA */
84 }
85 desc_size += ssp_cap_size;
86 }
87 memcpy(buf, &usb_bos_descriptor, min(desc_size, wLength));
88
89 if (usb3_1) {
90 /* modify bos descriptor bNumDeviceCaps and wTotalLength */
91 buf[4] += 1;
92 put_unaligned_le16(desc_size + ssa_size, &buf[2]);
93 }
94
95 if (wLength < USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE)
96 return wLength;
97
98 /* Indicate whether the host has LTM support. */
99 temp = readl(&xhci->cap_regs->hcc_params);
100 if (HCC_LTC(temp))
101 buf[8] |= USB_LTM_SUPPORT;
102
103 /* Set the U1 and U2 exit latencies. */
104 if ((xhci->quirks & XHCI_LPM_SUPPORT)) {
105 temp = readl(&xhci->cap_regs->hcs_params3);
106 buf[12] = HCS_U1_LATENCY(temp);
107 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
108 }
109
110 /* If PSI table exists, add the custom speed attributes from it */
111 if (usb3_1 && port_cap->psi_count) {
112 u32 ssp_cap_base, bm_attrib, psi, psi_mant, psi_exp;
113 int offset;
114
115 ssp_cap_base = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
116
117 if (wLength < desc_size)
118 return wLength;
119 buf[ssp_cap_base] = ssp_cap_size + ssa_size;
120
121 /* attribute count SSAC bits 4:0 and ID count SSIC bits 8:5 */
122 bm_attrib = (ssa_count - 1) & 0x1f;
123 bm_attrib |= (port_cap->psi_uid_count - 1) << 5;
124 put_unaligned_le32(bm_attrib, &buf[ssp_cap_base + 4]);
125
126 if (wLength < desc_size + ssa_size)
127 return wLength;
128 /*
129 * Create the Sublink Speed Attributes (SSA) array.
130 * The xhci PSI field and USB 3.1 SSA fields are very similar,
131 * but link type bits 7:6 differ for values 01b and 10b.
132 * xhci has also only one PSI entry for a symmetric link when
133 * USB 3.1 requires two SSA entries (RX and TX) for every link
134 */
135 offset = desc_size;
136 for (i = 0; i < port_cap->psi_count; i++) {
137 psi = port_cap->psi[i];
138 psi &= ~USB_SSP_SUBLINK_SPEED_RSVD;
139 psi_exp = XHCI_EXT_PORT_PSIE(psi);
140 psi_mant = XHCI_EXT_PORT_PSIM(psi);
141
142 /* Shift to Gbps and set SSP Link BIT(14) if 10Gpbs */
143 for (; psi_exp < 3; psi_exp++)
144 psi_mant /= 1000;
145 if (psi_mant >= 10)
146 psi |= BIT(14);
147
148 if ((psi & PLT_MASK) == PLT_SYM) {
149 /* Symmetric, create SSA RX and TX from one PSI entry */
150 put_unaligned_le32(psi, &buf[offset]);
151 psi |= 1 << 7; /* turn entry to TX */
152 offset += 4;
153 if (offset >= desc_size + ssa_size)
154 return desc_size + ssa_size;
155 } else if ((psi & PLT_MASK) == PLT_ASYM_RX) {
156 /* Asymetric RX, flip bits 7:6 for SSA */
157 psi ^= PLT_MASK;
158 }
159 put_unaligned_le32(psi, &buf[offset]);
160 offset += 4;
161 if (offset >= desc_size + ssa_size)
162 return desc_size + ssa_size;
163 }
164 }
165 /* ssa_size is 0 for other than usb 3.1 hosts */
166 return desc_size + ssa_size;
167 }
168
xhci_common_hub_descriptor(struct xhci_hcd * xhci,struct usb_hub_descriptor * desc,int ports)169 static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
170 struct usb_hub_descriptor *desc, int ports)
171 {
172 u16 temp;
173
174 desc->bHubContrCurrent = 0;
175
176 desc->bNbrPorts = ports;
177 temp = 0;
178 /* Bits 1:0 - support per-port power switching, or power always on */
179 if (HCC_PPC(xhci->hcc_params))
180 temp |= HUB_CHAR_INDV_PORT_LPSM;
181 else
182 temp |= HUB_CHAR_NO_LPSM;
183 /* Bit 2 - root hubs are not part of a compound device */
184 /* Bits 4:3 - individual port over current protection */
185 temp |= HUB_CHAR_INDV_PORT_OCPM;
186 /* Bits 6:5 - no TTs in root ports */
187 /* Bit 7 - no port indicators */
188 desc->wHubCharacteristics = cpu_to_le16(temp);
189 }
190
191 /* Fill in the USB 2.0 roothub descriptor */
xhci_usb2_hub_descriptor(struct usb_hcd * hcd,struct xhci_hcd * xhci,struct usb_hub_descriptor * desc)192 static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
193 struct usb_hub_descriptor *desc)
194 {
195 int ports;
196 u16 temp;
197 __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
198 u32 portsc;
199 unsigned int i;
200 struct xhci_hub *rhub;
201
202 rhub = &xhci->usb2_rhub;
203 ports = rhub->num_ports;
204 xhci_common_hub_descriptor(xhci, desc, ports);
205 desc->bDescriptorType = USB_DT_HUB;
206 temp = 1 + (ports / 8);
207 desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
208 desc->bPwrOn2PwrGood = 10; /* xhci section 5.4.8 says 20ms */
209
210 /* The Device Removable bits are reported on a byte granularity.
211 * If the port doesn't exist within that byte, the bit is set to 0.
212 */
213 memset(port_removable, 0, sizeof(port_removable));
214 for (i = 0; i < ports; i++) {
215 portsc = readl(rhub->ports[i]->addr);
216 /* If a device is removable, PORTSC reports a 0, same as in the
217 * hub descriptor DeviceRemovable bits.
218 */
219 if (portsc & PORT_DEV_REMOVE)
220 /* This math is hairy because bit 0 of DeviceRemovable
221 * is reserved, and bit 1 is for port 1, etc.
222 */
223 port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
224 }
225
226 /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
227 * ports on it. The USB 2.0 specification says that there are two
228 * variable length fields at the end of the hub descriptor:
229 * DeviceRemovable and PortPwrCtrlMask. But since we can have less than
230 * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
231 * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to
232 * 0xFF, so we initialize the both arrays (DeviceRemovable and
233 * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each
234 * set of ports that actually exist.
235 */
236 memset(desc->u.hs.DeviceRemovable, 0xff,
237 sizeof(desc->u.hs.DeviceRemovable));
238 memset(desc->u.hs.PortPwrCtrlMask, 0xff,
239 sizeof(desc->u.hs.PortPwrCtrlMask));
240
241 for (i = 0; i < (ports + 1 + 7) / 8; i++)
242 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
243 sizeof(__u8));
244 }
245
246 /* Fill in the USB 3.0 roothub descriptor */
xhci_usb3_hub_descriptor(struct usb_hcd * hcd,struct xhci_hcd * xhci,struct usb_hub_descriptor * desc)247 static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
248 struct usb_hub_descriptor *desc)
249 {
250 int ports;
251 u16 port_removable;
252 u32 portsc;
253 unsigned int i;
254 struct xhci_hub *rhub;
255
256 rhub = &xhci->usb3_rhub;
257 ports = rhub->num_ports;
258 xhci_common_hub_descriptor(xhci, desc, ports);
259 desc->bDescriptorType = USB_DT_SS_HUB;
260 desc->bDescLength = USB_DT_SS_HUB_SIZE;
261 desc->bPwrOn2PwrGood = 50; /* usb 3.1 may fail if less than 100ms */
262
263 /* header decode latency should be zero for roothubs,
264 * see section 4.23.5.2.
265 */
266 desc->u.ss.bHubHdrDecLat = 0;
267 desc->u.ss.wHubDelay = 0;
268
269 port_removable = 0;
270 /* bit 0 is reserved, bit 1 is for port 1, etc. */
271 for (i = 0; i < ports; i++) {
272 portsc = readl(rhub->ports[i]->addr);
273 if (portsc & PORT_DEV_REMOVE)
274 port_removable |= 1 << (i + 1);
275 }
276
277 desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable);
278 }
279
xhci_hub_descriptor(struct usb_hcd * hcd,struct xhci_hcd * xhci,struct usb_hub_descriptor * desc)280 static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
281 struct usb_hub_descriptor *desc)
282 {
283
284 if (hcd->speed >= HCD_USB3)
285 xhci_usb3_hub_descriptor(hcd, xhci, desc);
286 else
287 xhci_usb2_hub_descriptor(hcd, xhci, desc);
288
289 }
290
xhci_port_speed(unsigned int port_status)291 static unsigned int xhci_port_speed(unsigned int port_status)
292 {
293 if (DEV_LOWSPEED(port_status))
294 return USB_PORT_STAT_LOW_SPEED;
295 if (DEV_HIGHSPEED(port_status))
296 return USB_PORT_STAT_HIGH_SPEED;
297 /*
298 * FIXME: Yes, we should check for full speed, but the core uses that as
299 * a default in portspeed() in usb/core/hub.c (which is the only place
300 * USB_PORT_STAT_*_SPEED is used).
301 */
302 return 0;
303 }
304
305 /*
306 * These bits are Read Only (RO) and should be saved and written to the
307 * registers: 0, 3, 10:13, 30
308 * connect status, over-current status, port speed, and device removable.
309 * connect status and port speed are also sticky - meaning they're in
310 * the AUX well and they aren't changed by a hot, warm, or cold reset.
311 */
312 #define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
313 /*
314 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
315 * bits 5:8, 9, 14:15, 25:27
316 * link state, port power, port indicator state, "wake on" enable state
317 */
318 #define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
319 /*
320 * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
321 * bit 4 (port reset)
322 */
323 #define XHCI_PORT_RW1S ((1<<4))
324 /*
325 * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
326 * bits 1, 17, 18, 19, 20, 21, 22, 23
327 * port enable/disable, and
328 * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
329 * over-current, reset, link state, and L1 change
330 */
331 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
332 /*
333 * Bit 16 is RW, and writing a '1' to it causes the link state control to be
334 * latched in
335 */
336 #define XHCI_PORT_RW ((1<<16))
337 /*
338 * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
339 * bits 2, 24, 28:31
340 */
341 #define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28))
342
343 /*
344 * Given a port state, this function returns a value that would result in the
345 * port being in the same state, if the value was written to the port status
346 * control register.
347 * Save Read Only (RO) bits and save read/write bits where
348 * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
349 * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
350 */
xhci_port_state_to_neutral(u32 state)351 u32 xhci_port_state_to_neutral(u32 state)
352 {
353 /* Save read-only status and port state */
354 return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
355 }
356
357 /*
358 * find slot id based on port number.
359 * @port: The one-based port number from one of the two split roothubs.
360 */
xhci_find_slot_id_by_port(struct usb_hcd * hcd,struct xhci_hcd * xhci,u16 port)361 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
362 u16 port)
363 {
364 int slot_id;
365 int i;
366 enum usb_device_speed speed;
367
368 slot_id = 0;
369 for (i = 0; i < MAX_HC_SLOTS; i++) {
370 if (!xhci->devs[i] || !xhci->devs[i]->udev)
371 continue;
372 speed = xhci->devs[i]->udev->speed;
373 if (((speed >= USB_SPEED_SUPER) == (hcd->speed >= HCD_USB3))
374 && xhci->devs[i]->fake_port == port) {
375 slot_id = i;
376 break;
377 }
378 }
379
380 return slot_id;
381 }
382
383 /*
384 * Stop device
385 * It issues stop endpoint command for EP 0 to 30. And wait the last command
386 * to complete.
387 * suspend will set to 1, if suspend bit need to set in command.
388 */
xhci_stop_device(struct xhci_hcd * xhci,int slot_id,int suspend)389 static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
390 {
391 struct xhci_virt_device *virt_dev;
392 struct xhci_command *cmd;
393 unsigned long flags;
394 int ret;
395 int i;
396
397 ret = 0;
398 virt_dev = xhci->devs[slot_id];
399 if (!virt_dev)
400 return -ENODEV;
401
402 trace_xhci_stop_device(virt_dev);
403
404 cmd = xhci_alloc_command(xhci, true, GFP_NOIO);
405 if (!cmd)
406 return -ENOMEM;
407
408 spin_lock_irqsave(&xhci->lock, flags);
409 for (i = LAST_EP_INDEX; i > 0; i--) {
410 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) {
411 struct xhci_ep_ctx *ep_ctx;
412 struct xhci_command *command;
413
414 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, i);
415
416 /* Check ep is running, required by AMD SNPS 3.1 xHC */
417 if (GET_EP_CTX_STATE(ep_ctx) != EP_STATE_RUNNING)
418 continue;
419
420 command = xhci_alloc_command(xhci, false, GFP_NOWAIT);
421 if (!command) {
422 spin_unlock_irqrestore(&xhci->lock, flags);
423 ret = -ENOMEM;
424 goto cmd_cleanup;
425 }
426
427 ret = xhci_queue_stop_endpoint(xhci, command, slot_id,
428 i, suspend);
429 if (ret) {
430 spin_unlock_irqrestore(&xhci->lock, flags);
431 xhci_free_command(xhci, command);
432 goto cmd_cleanup;
433 }
434 }
435 }
436 ret = xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend);
437 if (ret) {
438 spin_unlock_irqrestore(&xhci->lock, flags);
439 goto cmd_cleanup;
440 }
441
442 xhci_ring_cmd_db(xhci);
443 spin_unlock_irqrestore(&xhci->lock, flags);
444
445 /* Wait for last stop endpoint command to finish */
446 wait_for_completion(cmd->completion);
447
448 if (cmd->status == COMP_COMMAND_ABORTED ||
449 cmd->status == COMP_COMMAND_RING_STOPPED) {
450 xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n");
451 ret = -ETIME;
452 }
453
454 cmd_cleanup:
455 xhci_free_command(xhci, cmd);
456 return ret;
457 }
458
459 /*
460 * Ring device, it rings the all doorbells unconditionally.
461 */
xhci_ring_device(struct xhci_hcd * xhci,int slot_id)462 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
463 {
464 int i, s;
465 struct xhci_virt_ep *ep;
466
467 for (i = 0; i < LAST_EP_INDEX + 1; i++) {
468 ep = &xhci->devs[slot_id]->eps[i];
469
470 if (ep->ep_state & EP_HAS_STREAMS) {
471 for (s = 1; s < ep->stream_info->num_streams; s++)
472 xhci_ring_ep_doorbell(xhci, slot_id, i, s);
473 } else if (ep->ring && ep->ring->dequeue) {
474 xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
475 }
476 }
477
478 return;
479 }
480
xhci_disable_port(struct usb_hcd * hcd,struct xhci_hcd * xhci,u16 wIndex,__le32 __iomem * addr,u32 port_status)481 static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
482 u16 wIndex, __le32 __iomem *addr, u32 port_status)
483 {
484 /* Don't allow the USB core to disable SuperSpeed ports. */
485 if (hcd->speed >= HCD_USB3) {
486 xhci_dbg(xhci, "Ignoring request to disable "
487 "SuperSpeed port.\n");
488 return;
489 }
490
491 if (xhci->quirks & XHCI_BROKEN_PORT_PED) {
492 xhci_dbg(xhci,
493 "Broken Port Enabled/Disabled, ignoring port disable request.\n");
494 return;
495 }
496
497 /* Write 1 to disable the port */
498 writel(port_status | PORT_PE, addr);
499 port_status = readl(addr);
500 xhci_dbg(xhci, "disable port %d-%d, portsc: 0x%x\n",
501 hcd->self.busnum, wIndex + 1, port_status);
502 }
503
xhci_clear_port_change_bit(struct xhci_hcd * xhci,u16 wValue,u16 wIndex,__le32 __iomem * addr,u32 port_status)504 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
505 u16 wIndex, __le32 __iomem *addr, u32 port_status)
506 {
507 char *port_change_bit;
508 u32 status;
509
510 switch (wValue) {
511 case USB_PORT_FEAT_C_RESET:
512 status = PORT_RC;
513 port_change_bit = "reset";
514 break;
515 case USB_PORT_FEAT_C_BH_PORT_RESET:
516 status = PORT_WRC;
517 port_change_bit = "warm(BH) reset";
518 break;
519 case USB_PORT_FEAT_C_CONNECTION:
520 status = PORT_CSC;
521 port_change_bit = "connect";
522 break;
523 case USB_PORT_FEAT_C_OVER_CURRENT:
524 status = PORT_OCC;
525 port_change_bit = "over-current";
526 break;
527 case USB_PORT_FEAT_C_ENABLE:
528 status = PORT_PEC;
529 port_change_bit = "enable/disable";
530 break;
531 case USB_PORT_FEAT_C_SUSPEND:
532 status = PORT_PLC;
533 port_change_bit = "suspend/resume";
534 break;
535 case USB_PORT_FEAT_C_PORT_LINK_STATE:
536 status = PORT_PLC;
537 port_change_bit = "link state";
538 break;
539 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
540 status = PORT_CEC;
541 port_change_bit = "config error";
542 break;
543 default:
544 /* Should never happen */
545 return;
546 }
547 /* Change bits are all write 1 to clear */
548 writel(port_status | status, addr);
549 port_status = readl(addr);
550
551 xhci_dbg(xhci, "clear port%d %s change, portsc: 0x%x\n",
552 wIndex + 1, port_change_bit, port_status);
553 }
554
xhci_get_rhub(struct usb_hcd * hcd)555 struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd)
556 {
557 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
558
559 if (hcd->speed >= HCD_USB3)
560 return &xhci->usb3_rhub;
561 return &xhci->usb2_rhub;
562 }
563
564 /*
565 * xhci_set_port_power() must be called with xhci->lock held.
566 * It will release and re-aquire the lock while calling ACPI
567 * method.
568 */
xhci_set_port_power(struct xhci_hcd * xhci,struct usb_hcd * hcd,u16 index,bool on,unsigned long * flags)569 static void xhci_set_port_power(struct xhci_hcd *xhci, struct usb_hcd *hcd,
570 u16 index, bool on, unsigned long *flags)
571 __must_hold(&xhci->lock)
572 {
573 struct xhci_hub *rhub;
574 struct xhci_port *port;
575 u32 temp;
576
577 rhub = xhci_get_rhub(hcd);
578 port = rhub->ports[index];
579 temp = readl(port->addr);
580
581 xhci_dbg(xhci, "set port power %d-%d %s, portsc: 0x%x\n",
582 hcd->self.busnum, index + 1, on ? "ON" : "OFF", temp);
583
584 temp = xhci_port_state_to_neutral(temp);
585
586 if (on) {
587 /* Power on */
588 writel(temp | PORT_POWER, port->addr);
589 readl(port->addr);
590 } else {
591 /* Power off */
592 writel(temp & ~PORT_POWER, port->addr);
593 }
594
595 spin_unlock_irqrestore(&xhci->lock, *flags);
596 temp = usb_acpi_power_manageable(hcd->self.root_hub,
597 index);
598 if (temp)
599 usb_acpi_set_power_state(hcd->self.root_hub,
600 index, on);
601 spin_lock_irqsave(&xhci->lock, *flags);
602 }
603
xhci_port_set_test_mode(struct xhci_hcd * xhci,u16 test_mode,u16 wIndex)604 static void xhci_port_set_test_mode(struct xhci_hcd *xhci,
605 u16 test_mode, u16 wIndex)
606 {
607 u32 temp;
608 struct xhci_port *port;
609
610 /* xhci only supports test mode for usb2 ports */
611 port = xhci->usb2_rhub.ports[wIndex];
612 temp = readl(port->addr + PORTPMSC);
613 temp |= test_mode << PORT_TEST_MODE_SHIFT;
614 writel(temp, port->addr + PORTPMSC);
615 xhci->test_mode = test_mode;
616 if (test_mode == USB_TEST_FORCE_ENABLE)
617 xhci_start(xhci);
618 }
619
xhci_enter_test_mode(struct xhci_hcd * xhci,u16 test_mode,u16 wIndex,unsigned long * flags)620 static int xhci_enter_test_mode(struct xhci_hcd *xhci,
621 u16 test_mode, u16 wIndex, unsigned long *flags)
622 __must_hold(&xhci->lock)
623 {
624 int i, retval;
625
626 /* Disable all Device Slots */
627 xhci_dbg(xhci, "Disable all slots\n");
628 spin_unlock_irqrestore(&xhci->lock, *flags);
629 for (i = 1; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
630 if (!xhci->devs[i])
631 continue;
632
633 retval = xhci_disable_slot(xhci, i);
634 xhci_free_virt_device(xhci, i);
635 if (retval)
636 xhci_err(xhci, "Failed to disable slot %d, %d. Enter test mode anyway\n",
637 i, retval);
638 }
639 spin_lock_irqsave(&xhci->lock, *flags);
640 /* Put all ports to the Disable state by clear PP */
641 xhci_dbg(xhci, "Disable all port (PP = 0)\n");
642 /* Power off USB3 ports*/
643 for (i = 0; i < xhci->usb3_rhub.num_ports; i++)
644 xhci_set_port_power(xhci, xhci->shared_hcd, i, false, flags);
645 /* Power off USB2 ports*/
646 for (i = 0; i < xhci->usb2_rhub.num_ports; i++)
647 xhci_set_port_power(xhci, xhci->main_hcd, i, false, flags);
648 /* Stop the controller */
649 xhci_dbg(xhci, "Stop controller\n");
650 retval = xhci_halt(xhci);
651 if (retval)
652 return retval;
653 /* Disable runtime PM for test mode */
654 pm_runtime_forbid(xhci_to_hcd(xhci)->self.controller);
655 /* Set PORTPMSC.PTC field to enter selected test mode */
656 /* Port is selected by wIndex. port_id = wIndex + 1 */
657 xhci_dbg(xhci, "Enter Test Mode: %d, Port_id=%d\n",
658 test_mode, wIndex + 1);
659 xhci_port_set_test_mode(xhci, test_mode, wIndex);
660 return retval;
661 }
662
xhci_exit_test_mode(struct xhci_hcd * xhci)663 static int xhci_exit_test_mode(struct xhci_hcd *xhci)
664 {
665 int retval;
666
667 if (!xhci->test_mode) {
668 xhci_err(xhci, "Not in test mode, do nothing.\n");
669 return 0;
670 }
671 if (xhci->test_mode == USB_TEST_FORCE_ENABLE &&
672 !(xhci->xhc_state & XHCI_STATE_HALTED)) {
673 retval = xhci_halt(xhci);
674 if (retval)
675 return retval;
676 }
677 pm_runtime_allow(xhci_to_hcd(xhci)->self.controller);
678 xhci->test_mode = 0;
679 return xhci_reset(xhci);
680 }
681
xhci_set_link_state(struct xhci_hcd * xhci,struct xhci_port * port,u32 link_state)682 void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port,
683 u32 link_state)
684 {
685 u32 temp;
686 u32 portsc;
687
688 portsc = readl(port->addr);
689 temp = xhci_port_state_to_neutral(portsc);
690 temp &= ~PORT_PLS_MASK;
691 temp |= PORT_LINK_STROBE | link_state;
692 writel(temp, port->addr);
693
694 xhci_dbg(xhci, "Set port %d-%d link state, portsc: 0x%x, write 0x%x",
695 port->rhub->hcd->self.busnum, port->hcd_portnum + 1,
696 portsc, temp);
697 }
698
xhci_set_remote_wake_mask(struct xhci_hcd * xhci,struct xhci_port * port,u16 wake_mask)699 static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
700 struct xhci_port *port, u16 wake_mask)
701 {
702 u32 temp;
703
704 temp = readl(port->addr);
705 temp = xhci_port_state_to_neutral(temp);
706
707 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
708 temp |= PORT_WKCONN_E;
709 else
710 temp &= ~PORT_WKCONN_E;
711
712 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
713 temp |= PORT_WKDISC_E;
714 else
715 temp &= ~PORT_WKDISC_E;
716
717 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
718 temp |= PORT_WKOC_E;
719 else
720 temp &= ~PORT_WKOC_E;
721
722 writel(temp, port->addr);
723 }
724
725 /* Test and clear port RWC bit */
xhci_test_and_clear_bit(struct xhci_hcd * xhci,struct xhci_port * port,u32 port_bit)726 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port,
727 u32 port_bit)
728 {
729 u32 temp;
730
731 temp = readl(port->addr);
732 if (temp & port_bit) {
733 temp = xhci_port_state_to_neutral(temp);
734 temp |= port_bit;
735 writel(temp, port->addr);
736 }
737 }
738
739 /* Updates Link Status for super Speed port */
xhci_hub_report_usb3_link_state(struct xhci_hcd * xhci,u32 * status,u32 status_reg)740 static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci,
741 u32 *status, u32 status_reg)
742 {
743 u32 pls = status_reg & PORT_PLS_MASK;
744
745 /* When the CAS bit is set then warm reset
746 * should be performed on port
747 */
748 if (status_reg & PORT_CAS) {
749 /* The CAS bit can be set while the port is
750 * in any link state.
751 * Only roothubs have CAS bit, so we
752 * pretend to be in compliance mode
753 * unless we're already in compliance
754 * or the inactive state.
755 */
756 if (pls != USB_SS_PORT_LS_COMP_MOD &&
757 pls != USB_SS_PORT_LS_SS_INACTIVE) {
758 pls = USB_SS_PORT_LS_COMP_MOD;
759 }
760 /* Return also connection bit -
761 * hub state machine resets port
762 * when this bit is set.
763 */
764 pls |= USB_PORT_STAT_CONNECTION;
765 } else {
766 /*
767 * Resume state is an xHCI internal state. Do not report it to
768 * usb core, instead, pretend to be U3, thus usb core knows
769 * it's not ready for transfer.
770 */
771 if (pls == XDEV_RESUME) {
772 *status |= USB_SS_PORT_LS_U3;
773 return;
774 }
775
776 /*
777 * If CAS bit isn't set but the Port is already at
778 * Compliance Mode, fake a connection so the USB core
779 * notices the Compliance state and resets the port.
780 * This resolves an issue generated by the SN65LVPE502CP
781 * in which sometimes the port enters compliance mode
782 * caused by a delay on the host-device negotiation.
783 */
784 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
785 (pls == USB_SS_PORT_LS_COMP_MOD))
786 pls |= USB_PORT_STAT_CONNECTION;
787 }
788
789 /* update status field */
790 *status |= pls;
791 }
792
793 /*
794 * Function for Compliance Mode Quirk.
795 *
796 * This Function verifies if all xhc USB3 ports have entered U0, if so,
797 * the compliance mode timer is deleted. A port won't enter
798 * compliance mode if it has previously entered U0.
799 */
xhci_del_comp_mod_timer(struct xhci_hcd * xhci,u32 status,u16 wIndex)800 static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status,
801 u16 wIndex)
802 {
803 u32 all_ports_seen_u0 = ((1 << xhci->usb3_rhub.num_ports) - 1);
804 bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
805
806 if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
807 return;
808
809 if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) {
810 xhci->port_status_u0 |= 1 << wIndex;
811 if (xhci->port_status_u0 == all_ports_seen_u0) {
812 del_timer_sync(&xhci->comp_mode_recovery_timer);
813 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
814 "All USB3 ports have entered U0 already!");
815 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
816 "Compliance Mode Recovery Timer Deleted.");
817 }
818 }
819 }
820
xhci_handle_usb2_port_link_resume(struct xhci_port * port,u32 * status,u32 portsc,unsigned long * flags)821 static int xhci_handle_usb2_port_link_resume(struct xhci_port *port,
822 u32 *status, u32 portsc,
823 unsigned long *flags)
824 {
825 struct xhci_bus_state *bus_state;
826 struct xhci_hcd *xhci;
827 struct usb_hcd *hcd;
828 int slot_id;
829 u32 wIndex;
830
831 hcd = port->rhub->hcd;
832 bus_state = &port->rhub->bus_state;
833 xhci = hcd_to_xhci(hcd);
834 wIndex = port->hcd_portnum;
835
836 if ((portsc & PORT_RESET) || !(portsc & PORT_PE)) {
837 *status = 0xffffffff;
838 return -EINVAL;
839 }
840 /* did port event handler already start resume timing? */
841 if (!bus_state->resume_done[wIndex]) {
842 /* If not, maybe we are in a host initated resume? */
843 if (test_bit(wIndex, &bus_state->resuming_ports)) {
844 /* Host initated resume doesn't time the resume
845 * signalling using resume_done[].
846 * It manually sets RESUME state, sleeps 20ms
847 * and sets U0 state. This should probably be
848 * changed, but not right now.
849 */
850 } else {
851 /* port resume was discovered now and here,
852 * start resume timing
853 */
854 unsigned long timeout = jiffies +
855 msecs_to_jiffies(USB_RESUME_TIMEOUT);
856
857 set_bit(wIndex, &bus_state->resuming_ports);
858 bus_state->resume_done[wIndex] = timeout;
859 mod_timer(&hcd->rh_timer, timeout);
860 usb_hcd_start_port_resume(&hcd->self, wIndex);
861 }
862 /* Has resume been signalled for USB_RESUME_TIME yet? */
863 } else if (time_after_eq(jiffies, bus_state->resume_done[wIndex])) {
864 int time_left;
865
866 xhci_dbg(xhci, "resume USB2 port %d-%d\n",
867 hcd->self.busnum, wIndex + 1);
868
869 bus_state->resume_done[wIndex] = 0;
870 clear_bit(wIndex, &bus_state->resuming_ports);
871
872 set_bit(wIndex, &bus_state->rexit_ports);
873
874 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
875 xhci_set_link_state(xhci, port, XDEV_U0);
876
877 spin_unlock_irqrestore(&xhci->lock, *flags);
878 time_left = wait_for_completion_timeout(
879 &bus_state->rexit_done[wIndex],
880 msecs_to_jiffies(XHCI_MAX_REXIT_TIMEOUT_MS));
881 spin_lock_irqsave(&xhci->lock, *flags);
882
883 if (time_left) {
884 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
885 wIndex + 1);
886 if (!slot_id) {
887 xhci_dbg(xhci, "slot_id is zero\n");
888 *status = 0xffffffff;
889 return -ENODEV;
890 }
891 xhci_ring_device(xhci, slot_id);
892 } else {
893 int port_status = readl(port->addr);
894
895 xhci_warn(xhci, "Port resume timed out, port %d-%d: 0x%x\n",
896 hcd->self.busnum, wIndex + 1, port_status);
897 *status |= USB_PORT_STAT_SUSPEND;
898 clear_bit(wIndex, &bus_state->rexit_ports);
899 }
900
901 usb_hcd_end_port_resume(&hcd->self, wIndex);
902 bus_state->port_c_suspend |= 1 << wIndex;
903 bus_state->suspended_ports &= ~(1 << wIndex);
904 } else {
905 /*
906 * The resume has been signaling for less than
907 * USB_RESUME_TIME. Report the port status as SUSPEND,
908 * let the usbcore check port status again and clear
909 * resume signaling later.
910 */
911 *status |= USB_PORT_STAT_SUSPEND;
912 }
913 return 0;
914 }
915
xhci_get_ext_port_status(u32 raw_port_status,u32 port_li)916 static u32 xhci_get_ext_port_status(u32 raw_port_status, u32 port_li)
917 {
918 u32 ext_stat = 0;
919 int speed_id;
920
921 /* only support rx and tx lane counts of 1 in usb3.1 spec */
922 speed_id = DEV_PORT_SPEED(raw_port_status);
923 ext_stat |= speed_id; /* bits 3:0, RX speed id */
924 ext_stat |= speed_id << 4; /* bits 7:4, TX speed id */
925
926 ext_stat |= PORT_RX_LANES(port_li) << 8; /* bits 11:8 Rx lane count */
927 ext_stat |= PORT_TX_LANES(port_li) << 12; /* bits 15:12 Tx lane count */
928
929 return ext_stat;
930 }
931
xhci_get_usb3_port_status(struct xhci_port * port,u32 * status,u32 portsc)932 static void xhci_get_usb3_port_status(struct xhci_port *port, u32 *status,
933 u32 portsc)
934 {
935 struct xhci_bus_state *bus_state;
936 struct xhci_hcd *xhci;
937 struct usb_hcd *hcd;
938 u32 link_state;
939 u32 portnum;
940
941 bus_state = &port->rhub->bus_state;
942 xhci = hcd_to_xhci(port->rhub->hcd);
943 hcd = port->rhub->hcd;
944 link_state = portsc & PORT_PLS_MASK;
945 portnum = port->hcd_portnum;
946
947 /* USB3 specific wPortChange bits
948 *
949 * Port link change with port in resume state should not be
950 * reported to usbcore, as this is an internal state to be
951 * handled by xhci driver. Reporting PLC to usbcore may
952 * cause usbcore clearing PLC first and port change event
953 * irq won't be generated.
954 */
955
956 if (portsc & PORT_PLC && (link_state != XDEV_RESUME))
957 *status |= USB_PORT_STAT_C_LINK_STATE << 16;
958 if (portsc & PORT_WRC)
959 *status |= USB_PORT_STAT_C_BH_RESET << 16;
960 if (portsc & PORT_CEC)
961 *status |= USB_PORT_STAT_C_CONFIG_ERROR << 16;
962
963 /* USB3 specific wPortStatus bits */
964 if (portsc & PORT_POWER) {
965 *status |= USB_SS_PORT_STAT_POWER;
966 /* link state handling */
967 if (link_state == XDEV_U0)
968 bus_state->suspended_ports &= ~(1 << portnum);
969 }
970
971 /* remote wake resume signaling complete */
972 if (bus_state->port_remote_wakeup & (1 << portnum) &&
973 link_state != XDEV_RESUME &&
974 link_state != XDEV_RECOVERY) {
975 bus_state->port_remote_wakeup &= ~(1 << portnum);
976 usb_hcd_end_port_resume(&hcd->self, portnum);
977 }
978
979 xhci_hub_report_usb3_link_state(xhci, status, portsc);
980 xhci_del_comp_mod_timer(xhci, portsc, portnum);
981 }
982
xhci_get_usb2_port_status(struct xhci_port * port,u32 * status,u32 portsc,unsigned long * flags)983 static void xhci_get_usb2_port_status(struct xhci_port *port, u32 *status,
984 u32 portsc, unsigned long *flags)
985 {
986 struct xhci_bus_state *bus_state;
987 u32 link_state;
988 u32 portnum;
989 int ret;
990
991 bus_state = &port->rhub->bus_state;
992 link_state = portsc & PORT_PLS_MASK;
993 portnum = port->hcd_portnum;
994
995 /* USB2 wPortStatus bits */
996 if (portsc & PORT_POWER) {
997 *status |= USB_PORT_STAT_POWER;
998
999 /* link state is only valid if port is powered */
1000 if (link_state == XDEV_U3)
1001 *status |= USB_PORT_STAT_SUSPEND;
1002 if (link_state == XDEV_U2)
1003 *status |= USB_PORT_STAT_L1;
1004 if (link_state == XDEV_U0) {
1005 bus_state->resume_done[portnum] = 0;
1006 clear_bit(portnum, &bus_state->resuming_ports);
1007 if (bus_state->suspended_ports & (1 << portnum)) {
1008 bus_state->suspended_ports &= ~(1 << portnum);
1009 bus_state->port_c_suspend |= 1 << portnum;
1010 }
1011 }
1012 if (link_state == XDEV_RESUME) {
1013 ret = xhci_handle_usb2_port_link_resume(port, status,
1014 portsc, flags);
1015 if (ret)
1016 return;
1017 }
1018 }
1019 }
1020
1021 /*
1022 * Converts a raw xHCI port status into the format that external USB 2.0 or USB
1023 * 3.0 hubs use.
1024 *
1025 * Possible side effects:
1026 * - Mark a port as being done with device resume,
1027 * and ring the endpoint doorbells.
1028 * - Stop the Synopsys redriver Compliance Mode polling.
1029 * - Drop and reacquire the xHCI lock, in order to wait for port resume.
1030 */
xhci_get_port_status(struct usb_hcd * hcd,struct xhci_bus_state * bus_state,u16 wIndex,u32 raw_port_status,unsigned long * flags)1031 static u32 xhci_get_port_status(struct usb_hcd *hcd,
1032 struct xhci_bus_state *bus_state,
1033 u16 wIndex, u32 raw_port_status,
1034 unsigned long *flags)
1035 __releases(&xhci->lock)
1036 __acquires(&xhci->lock)
1037 {
1038 u32 status = 0;
1039 struct xhci_hub *rhub;
1040 struct xhci_port *port;
1041
1042 rhub = xhci_get_rhub(hcd);
1043 port = rhub->ports[wIndex];
1044
1045 /* common wPortChange bits */
1046 if (raw_port_status & PORT_CSC)
1047 status |= USB_PORT_STAT_C_CONNECTION << 16;
1048 if (raw_port_status & PORT_PEC)
1049 status |= USB_PORT_STAT_C_ENABLE << 16;
1050 if ((raw_port_status & PORT_OCC))
1051 status |= USB_PORT_STAT_C_OVERCURRENT << 16;
1052 if ((raw_port_status & PORT_RC))
1053 status |= USB_PORT_STAT_C_RESET << 16;
1054
1055 /* common wPortStatus bits */
1056 if (raw_port_status & PORT_CONNECT) {
1057 status |= USB_PORT_STAT_CONNECTION;
1058 status |= xhci_port_speed(raw_port_status);
1059 }
1060 if (raw_port_status & PORT_PE)
1061 status |= USB_PORT_STAT_ENABLE;
1062 if (raw_port_status & PORT_OC)
1063 status |= USB_PORT_STAT_OVERCURRENT;
1064 if (raw_port_status & PORT_RESET)
1065 status |= USB_PORT_STAT_RESET;
1066
1067 /* USB2 and USB3 specific bits, including Port Link State */
1068 if (hcd->speed >= HCD_USB3)
1069 xhci_get_usb3_port_status(port, &status, raw_port_status);
1070 else
1071 xhci_get_usb2_port_status(port, &status, raw_port_status,
1072 flags);
1073 /*
1074 * Clear stale usb2 resume signalling variables in case port changed
1075 * state during resume signalling. For example on error
1076 */
1077 if ((bus_state->resume_done[wIndex] ||
1078 test_bit(wIndex, &bus_state->resuming_ports)) &&
1079 (raw_port_status & PORT_PLS_MASK) != XDEV_U3 &&
1080 (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME) {
1081 bus_state->resume_done[wIndex] = 0;
1082 clear_bit(wIndex, &bus_state->resuming_ports);
1083 usb_hcd_end_port_resume(&hcd->self, wIndex);
1084 }
1085
1086 if (bus_state->port_c_suspend & (1 << wIndex))
1087 status |= USB_PORT_STAT_C_SUSPEND << 16;
1088
1089 return status;
1090 }
1091
xhci_hub_control(struct usb_hcd * hcd,u16 typeReq,u16 wValue,u16 wIndex,char * buf,u16 wLength)1092 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
1093 u16 wIndex, char *buf, u16 wLength)
1094 {
1095 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1096 int max_ports;
1097 unsigned long flags;
1098 u32 temp, status;
1099 int retval = 0;
1100 int slot_id;
1101 struct xhci_bus_state *bus_state;
1102 u16 link_state = 0;
1103 u16 wake_mask = 0;
1104 u16 timeout = 0;
1105 u16 test_mode = 0;
1106 struct xhci_hub *rhub;
1107 struct xhci_port **ports;
1108
1109 rhub = xhci_get_rhub(hcd);
1110 ports = rhub->ports;
1111 max_ports = rhub->num_ports;
1112 bus_state = &rhub->bus_state;
1113
1114 spin_lock_irqsave(&xhci->lock, flags);
1115 switch (typeReq) {
1116 case GetHubStatus:
1117 /* No power source, over-current reported per port */
1118 memset(buf, 0, 4);
1119 break;
1120 case GetHubDescriptor:
1121 /* Check to make sure userspace is asking for the USB 3.0 hub
1122 * descriptor for the USB 3.0 roothub. If not, we stall the
1123 * endpoint, like external hubs do.
1124 */
1125 if (hcd->speed >= HCD_USB3 &&
1126 (wLength < USB_DT_SS_HUB_SIZE ||
1127 wValue != (USB_DT_SS_HUB << 8))) {
1128 xhci_dbg(xhci, "Wrong hub descriptor type for "
1129 "USB 3.0 roothub.\n");
1130 goto error;
1131 }
1132 xhci_hub_descriptor(hcd, xhci,
1133 (struct usb_hub_descriptor *) buf);
1134 break;
1135 case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
1136 if ((wValue & 0xff00) != (USB_DT_BOS << 8))
1137 goto error;
1138
1139 if (hcd->speed < HCD_USB3)
1140 goto error;
1141
1142 retval = xhci_create_usb3_bos_desc(xhci, buf, wLength);
1143 spin_unlock_irqrestore(&xhci->lock, flags);
1144 return retval;
1145 case GetPortStatus:
1146 if (!wIndex || wIndex > max_ports)
1147 goto error;
1148 wIndex--;
1149 temp = readl(ports[wIndex]->addr);
1150 if (temp == ~(u32)0) {
1151 xhci_hc_died(xhci);
1152 retval = -ENODEV;
1153 break;
1154 }
1155 trace_xhci_get_port_status(wIndex, temp);
1156 status = xhci_get_port_status(hcd, bus_state, wIndex, temp,
1157 &flags);
1158 if (status == 0xffffffff)
1159 goto error;
1160
1161 xhci_dbg(xhci, "Get port status %d-%d read: 0x%x, return 0x%x",
1162 hcd->self.busnum, wIndex + 1, temp, status);
1163
1164 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
1165 /* if USB 3.1 extended port status return additional 4 bytes */
1166 if (wValue == 0x02) {
1167 u32 port_li;
1168
1169 if (hcd->speed < HCD_USB31 || wLength != 8) {
1170 xhci_err(xhci, "get ext port status invalid parameter\n");
1171 retval = -EINVAL;
1172 break;
1173 }
1174 port_li = readl(ports[wIndex]->addr + PORTLI);
1175 status = xhci_get_ext_port_status(temp, port_li);
1176 put_unaligned_le32(status, &buf[4]);
1177 }
1178 break;
1179 case SetPortFeature:
1180 if (wValue == USB_PORT_FEAT_LINK_STATE)
1181 link_state = (wIndex & 0xff00) >> 3;
1182 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
1183 wake_mask = wIndex & 0xff00;
1184 if (wValue == USB_PORT_FEAT_TEST)
1185 test_mode = (wIndex & 0xff00) >> 8;
1186 /* The MSB of wIndex is the U1/U2 timeout */
1187 timeout = (wIndex & 0xff00) >> 8;
1188 wIndex &= 0xff;
1189 if (!wIndex || wIndex > max_ports)
1190 goto error;
1191 wIndex--;
1192 temp = readl(ports[wIndex]->addr);
1193 if (temp == ~(u32)0) {
1194 xhci_hc_died(xhci);
1195 retval = -ENODEV;
1196 break;
1197 }
1198 temp = xhci_port_state_to_neutral(temp);
1199 /* FIXME: What new port features do we need to support? */
1200 switch (wValue) {
1201 case USB_PORT_FEAT_SUSPEND:
1202 temp = readl(ports[wIndex]->addr);
1203 if ((temp & PORT_PLS_MASK) != XDEV_U0) {
1204 /* Resume the port to U0 first */
1205 xhci_set_link_state(xhci, ports[wIndex],
1206 XDEV_U0);
1207 spin_unlock_irqrestore(&xhci->lock, flags);
1208 msleep(10);
1209 spin_lock_irqsave(&xhci->lock, flags);
1210 }
1211 /* In spec software should not attempt to suspend
1212 * a port unless the port reports that it is in the
1213 * enabled (PED = ‘1’,PLS < ‘3’) state.
1214 */
1215 temp = readl(ports[wIndex]->addr);
1216 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
1217 || (temp & PORT_PLS_MASK) >= XDEV_U3) {
1218 xhci_warn(xhci, "USB core suspending port %d-%d not in U0/U1/U2\n",
1219 hcd->self.busnum, wIndex + 1);
1220 goto error;
1221 }
1222
1223 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1224 wIndex + 1);
1225 if (!slot_id) {
1226 xhci_warn(xhci, "slot_id is zero\n");
1227 goto error;
1228 }
1229 /* unlock to execute stop endpoint commands */
1230 spin_unlock_irqrestore(&xhci->lock, flags);
1231 xhci_stop_device(xhci, slot_id, 1);
1232 spin_lock_irqsave(&xhci->lock, flags);
1233
1234 xhci_set_link_state(xhci, ports[wIndex], XDEV_U3);
1235
1236 spin_unlock_irqrestore(&xhci->lock, flags);
1237 msleep(10); /* wait device to enter */
1238 spin_lock_irqsave(&xhci->lock, flags);
1239
1240 temp = readl(ports[wIndex]->addr);
1241 bus_state->suspended_ports |= 1 << wIndex;
1242 break;
1243 case USB_PORT_FEAT_LINK_STATE:
1244 temp = readl(ports[wIndex]->addr);
1245 /* Disable port */
1246 if (link_state == USB_SS_PORT_LS_SS_DISABLED) {
1247 xhci_dbg(xhci, "Disable port %d-%d\n",
1248 hcd->self.busnum, wIndex + 1);
1249 temp = xhci_port_state_to_neutral(temp);
1250 /*
1251 * Clear all change bits, so that we get a new
1252 * connection event.
1253 */
1254 temp |= PORT_CSC | PORT_PEC | PORT_WRC |
1255 PORT_OCC | PORT_RC | PORT_PLC |
1256 PORT_CEC;
1257 writel(temp | PORT_PE, ports[wIndex]->addr);
1258 temp = readl(ports[wIndex]->addr);
1259 break;
1260 }
1261
1262 /* Put link in RxDetect (enable port) */
1263 if (link_state == USB_SS_PORT_LS_RX_DETECT) {
1264 xhci_dbg(xhci, "Enable port %d-%d\n",
1265 hcd->self.busnum, wIndex + 1);
1266 xhci_set_link_state(xhci, ports[wIndex],
1267 link_state);
1268 temp = readl(ports[wIndex]->addr);
1269 break;
1270 }
1271
1272 /*
1273 * For xHCI 1.1 according to section 4.19.1.2.4.1 a
1274 * root hub port's transition to compliance mode upon
1275 * detecting LFPS timeout may be controlled by an
1276 * Compliance Transition Enabled (CTE) flag (not
1277 * software visible). This flag is set by writing 0xA
1278 * to PORTSC PLS field which will allow transition to
1279 * compliance mode the next time LFPS timeout is
1280 * encountered. A warm reset will clear it.
1281 *
1282 * The CTE flag is only supported if the HCCPARAMS2 CTC
1283 * flag is set, otherwise, the compliance substate is
1284 * automatically entered as on 1.0 and prior.
1285 */
1286 if (link_state == USB_SS_PORT_LS_COMP_MOD) {
1287 if (!HCC2_CTC(xhci->hcc_params2)) {
1288 xhci_dbg(xhci, "CTC flag is 0, port already supports entering compliance mode\n");
1289 break;
1290 }
1291
1292 if ((temp & PORT_CONNECT)) {
1293 xhci_warn(xhci, "Can't set compliance mode when port is connected\n");
1294 goto error;
1295 }
1296
1297 xhci_dbg(xhci, "Enable compliance mode transition for port %d-%d\n",
1298 hcd->self.busnum, wIndex + 1);
1299 xhci_set_link_state(xhci, ports[wIndex],
1300 link_state);
1301
1302 temp = readl(ports[wIndex]->addr);
1303 break;
1304 }
1305 /* Port must be enabled */
1306 if (!(temp & PORT_PE)) {
1307 retval = -ENODEV;
1308 break;
1309 }
1310 /* Can't set port link state above '3' (U3) */
1311 if (link_state > USB_SS_PORT_LS_U3) {
1312 xhci_warn(xhci, "Cannot set port %d-%d link state %d\n",
1313 hcd->self.busnum, wIndex + 1,
1314 link_state);
1315 goto error;
1316 }
1317
1318 /*
1319 * set link to U0, steps depend on current link state.
1320 * U3: set link to U0 and wait for u3exit completion.
1321 * U1/U2: no PLC complete event, only set link to U0.
1322 * Resume/Recovery: device initiated U0, only wait for
1323 * completion
1324 */
1325 if (link_state == USB_SS_PORT_LS_U0) {
1326 u32 pls = temp & PORT_PLS_MASK;
1327 bool wait_u0 = false;
1328
1329 /* already in U0 */
1330 if (pls == XDEV_U0)
1331 break;
1332 if (pls == XDEV_U3 ||
1333 pls == XDEV_RESUME ||
1334 pls == XDEV_RECOVERY) {
1335 wait_u0 = true;
1336 reinit_completion(&bus_state->u3exit_done[wIndex]);
1337 }
1338 if (pls <= XDEV_U3) /* U1, U2, U3 */
1339 xhci_set_link_state(xhci, ports[wIndex],
1340 USB_SS_PORT_LS_U0);
1341 if (!wait_u0) {
1342 if (pls > XDEV_U3)
1343 goto error;
1344 break;
1345 }
1346 spin_unlock_irqrestore(&xhci->lock, flags);
1347 if (!wait_for_completion_timeout(&bus_state->u3exit_done[wIndex],
1348 msecs_to_jiffies(100)))
1349 xhci_dbg(xhci, "missing U0 port change event for port %d-%d\n",
1350 hcd->self.busnum, wIndex + 1);
1351 spin_lock_irqsave(&xhci->lock, flags);
1352 temp = readl(ports[wIndex]->addr);
1353 break;
1354 }
1355
1356 if (link_state == USB_SS_PORT_LS_U3) {
1357 int retries = 16;
1358 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1359 wIndex + 1);
1360 if (slot_id) {
1361 /* unlock to execute stop endpoint
1362 * commands */
1363 spin_unlock_irqrestore(&xhci->lock,
1364 flags);
1365 xhci_stop_device(xhci, slot_id, 1);
1366 spin_lock_irqsave(&xhci->lock, flags);
1367 }
1368 xhci_set_link_state(xhci, ports[wIndex], USB_SS_PORT_LS_U3);
1369 spin_unlock_irqrestore(&xhci->lock, flags);
1370 while (retries--) {
1371 usleep_range(4000, 8000);
1372 temp = readl(ports[wIndex]->addr);
1373 if ((temp & PORT_PLS_MASK) == XDEV_U3)
1374 break;
1375 }
1376 spin_lock_irqsave(&xhci->lock, flags);
1377 temp = readl(ports[wIndex]->addr);
1378 bus_state->suspended_ports |= 1 << wIndex;
1379 }
1380 break;
1381 case USB_PORT_FEAT_POWER:
1382 /*
1383 * Turn on ports, even if there isn't per-port switching.
1384 * HC will report connect events even before this is set.
1385 * However, hub_wq will ignore the roothub events until
1386 * the roothub is registered.
1387 */
1388 xhci_set_port_power(xhci, hcd, wIndex, true, &flags);
1389 break;
1390 case USB_PORT_FEAT_RESET:
1391 temp = (temp | PORT_RESET);
1392 writel(temp, ports[wIndex]->addr);
1393
1394 temp = readl(ports[wIndex]->addr);
1395 xhci_dbg(xhci, "set port reset, actual port %d-%d status = 0x%x\n",
1396 hcd->self.busnum, wIndex + 1, temp);
1397 break;
1398 case USB_PORT_FEAT_REMOTE_WAKE_MASK:
1399 xhci_set_remote_wake_mask(xhci, ports[wIndex],
1400 wake_mask);
1401 temp = readl(ports[wIndex]->addr);
1402 xhci_dbg(xhci, "set port remote wake mask, actual port %d-%d status = 0x%x\n",
1403 hcd->self.busnum, wIndex + 1, temp);
1404 break;
1405 case USB_PORT_FEAT_BH_PORT_RESET:
1406 temp |= PORT_WR;
1407 writel(temp, ports[wIndex]->addr);
1408 temp = readl(ports[wIndex]->addr);
1409 break;
1410 case USB_PORT_FEAT_U1_TIMEOUT:
1411 if (hcd->speed < HCD_USB3)
1412 goto error;
1413 temp = readl(ports[wIndex]->addr + PORTPMSC);
1414 temp &= ~PORT_U1_TIMEOUT_MASK;
1415 temp |= PORT_U1_TIMEOUT(timeout);
1416 writel(temp, ports[wIndex]->addr + PORTPMSC);
1417 break;
1418 case USB_PORT_FEAT_U2_TIMEOUT:
1419 if (hcd->speed < HCD_USB3)
1420 goto error;
1421 temp = readl(ports[wIndex]->addr + PORTPMSC);
1422 temp &= ~PORT_U2_TIMEOUT_MASK;
1423 temp |= PORT_U2_TIMEOUT(timeout);
1424 writel(temp, ports[wIndex]->addr + PORTPMSC);
1425 break;
1426 case USB_PORT_FEAT_TEST:
1427 /* 4.19.6 Port Test Modes (USB2 Test Mode) */
1428 if (hcd->speed != HCD_USB2)
1429 goto error;
1430 if (test_mode > USB_TEST_FORCE_ENABLE ||
1431 test_mode < USB_TEST_J)
1432 goto error;
1433 retval = xhci_enter_test_mode(xhci, test_mode, wIndex,
1434 &flags);
1435 break;
1436 default:
1437 goto error;
1438 }
1439 /* unblock any posted writes */
1440 temp = readl(ports[wIndex]->addr);
1441 break;
1442 case ClearPortFeature:
1443 if (!wIndex || wIndex > max_ports)
1444 goto error;
1445 wIndex--;
1446 temp = readl(ports[wIndex]->addr);
1447 if (temp == ~(u32)0) {
1448 xhci_hc_died(xhci);
1449 retval = -ENODEV;
1450 break;
1451 }
1452 /* FIXME: What new port features do we need to support? */
1453 temp = xhci_port_state_to_neutral(temp);
1454 switch (wValue) {
1455 case USB_PORT_FEAT_SUSPEND:
1456 temp = readl(ports[wIndex]->addr);
1457 xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
1458 xhci_dbg(xhci, "PORTSC %04x\n", temp);
1459 if (temp & PORT_RESET)
1460 goto error;
1461 if ((temp & PORT_PLS_MASK) == XDEV_U3) {
1462 if ((temp & PORT_PE) == 0)
1463 goto error;
1464
1465 set_bit(wIndex, &bus_state->resuming_ports);
1466 usb_hcd_start_port_resume(&hcd->self, wIndex);
1467 xhci_set_link_state(xhci, ports[wIndex],
1468 XDEV_RESUME);
1469 spin_unlock_irqrestore(&xhci->lock, flags);
1470 msleep(USB_RESUME_TIMEOUT);
1471 spin_lock_irqsave(&xhci->lock, flags);
1472 xhci_set_link_state(xhci, ports[wIndex],
1473 XDEV_U0);
1474 clear_bit(wIndex, &bus_state->resuming_ports);
1475 usb_hcd_end_port_resume(&hcd->self, wIndex);
1476 }
1477 bus_state->port_c_suspend |= 1 << wIndex;
1478
1479 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1480 wIndex + 1);
1481 if (!slot_id) {
1482 xhci_dbg(xhci, "slot_id is zero\n");
1483 goto error;
1484 }
1485 xhci_ring_device(xhci, slot_id);
1486 break;
1487 case USB_PORT_FEAT_C_SUSPEND:
1488 bus_state->port_c_suspend &= ~(1 << wIndex);
1489 fallthrough;
1490 case USB_PORT_FEAT_C_RESET:
1491 case USB_PORT_FEAT_C_BH_PORT_RESET:
1492 case USB_PORT_FEAT_C_CONNECTION:
1493 case USB_PORT_FEAT_C_OVER_CURRENT:
1494 case USB_PORT_FEAT_C_ENABLE:
1495 case USB_PORT_FEAT_C_PORT_LINK_STATE:
1496 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
1497 xhci_clear_port_change_bit(xhci, wValue, wIndex,
1498 ports[wIndex]->addr, temp);
1499 break;
1500 case USB_PORT_FEAT_ENABLE:
1501 xhci_disable_port(hcd, xhci, wIndex,
1502 ports[wIndex]->addr, temp);
1503 break;
1504 case USB_PORT_FEAT_POWER:
1505 xhci_set_port_power(xhci, hcd, wIndex, false, &flags);
1506 break;
1507 case USB_PORT_FEAT_TEST:
1508 retval = xhci_exit_test_mode(xhci);
1509 break;
1510 default:
1511 goto error;
1512 }
1513 break;
1514 default:
1515 error:
1516 /* "stall" on error */
1517 retval = -EPIPE;
1518 }
1519 spin_unlock_irqrestore(&xhci->lock, flags);
1520 return retval;
1521 }
1522
1523 /*
1524 * Returns 0 if the status hasn't changed, or the number of bytes in buf.
1525 * Ports are 0-indexed from the HCD point of view,
1526 * and 1-indexed from the USB core pointer of view.
1527 *
1528 * Note that the status change bits will be cleared as soon as a port status
1529 * change event is generated, so we use the saved status from that event.
1530 */
xhci_hub_status_data(struct usb_hcd * hcd,char * buf)1531 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
1532 {
1533 unsigned long flags;
1534 u32 temp, status;
1535 u32 mask;
1536 int i, retval;
1537 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1538 int max_ports;
1539 struct xhci_bus_state *bus_state;
1540 bool reset_change = false;
1541 struct xhci_hub *rhub;
1542 struct xhci_port **ports;
1543
1544 rhub = xhci_get_rhub(hcd);
1545 ports = rhub->ports;
1546 max_ports = rhub->num_ports;
1547 bus_state = &rhub->bus_state;
1548
1549 /* Initial status is no changes */
1550 retval = (max_ports + 8) / 8;
1551 memset(buf, 0, retval);
1552
1553 /*
1554 * Inform the usbcore about resume-in-progress by returning
1555 * a non-zero value even if there are no status changes.
1556 */
1557 spin_lock_irqsave(&xhci->lock, flags);
1558
1559 status = bus_state->resuming_ports;
1560
1561 mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC | PORT_CEC;
1562
1563 /* For each port, did anything change? If so, set that bit in buf. */
1564 for (i = 0; i < max_ports; i++) {
1565 temp = readl(ports[i]->addr);
1566 if (temp == ~(u32)0) {
1567 xhci_hc_died(xhci);
1568 retval = -ENODEV;
1569 break;
1570 }
1571 trace_xhci_hub_status_data(i, temp);
1572
1573 if ((temp & mask) != 0 ||
1574 (bus_state->port_c_suspend & 1 << i) ||
1575 (bus_state->resume_done[i] && time_after_eq(
1576 jiffies, bus_state->resume_done[i]))) {
1577 buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
1578 status = 1;
1579 }
1580 if ((temp & PORT_RC))
1581 reset_change = true;
1582 if (temp & PORT_OC)
1583 status = 1;
1584 }
1585 if (!status && !reset_change) {
1586 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
1587 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1588 }
1589 spin_unlock_irqrestore(&xhci->lock, flags);
1590 return status ? retval : 0;
1591 }
1592
1593 #ifdef CONFIG_PM
1594
xhci_bus_suspend(struct usb_hcd * hcd)1595 int xhci_bus_suspend(struct usb_hcd *hcd)
1596 {
1597 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1598 int max_ports, port_index;
1599 struct xhci_bus_state *bus_state;
1600 unsigned long flags;
1601 struct xhci_hub *rhub;
1602 struct xhci_port **ports;
1603 u32 portsc_buf[USB_MAXCHILDREN];
1604 bool wake_enabled;
1605
1606 rhub = xhci_get_rhub(hcd);
1607 ports = rhub->ports;
1608 max_ports = rhub->num_ports;
1609 bus_state = &rhub->bus_state;
1610 wake_enabled = hcd->self.root_hub->do_remote_wakeup;
1611
1612 spin_lock_irqsave(&xhci->lock, flags);
1613
1614 if (wake_enabled) {
1615 if (bus_state->resuming_ports || /* USB2 */
1616 bus_state->port_remote_wakeup) { /* USB3 */
1617 spin_unlock_irqrestore(&xhci->lock, flags);
1618 xhci_dbg(xhci, "suspend failed because a port is resuming\n");
1619 return -EBUSY;
1620 }
1621 }
1622 /*
1623 * Prepare ports for suspend, but don't write anything before all ports
1624 * are checked and we know bus suspend can proceed
1625 */
1626 bus_state->bus_suspended = 0;
1627 port_index = max_ports;
1628 while (port_index--) {
1629 u32 t1, t2;
1630 int retries = 10;
1631 retry:
1632 t1 = readl(ports[port_index]->addr);
1633 t2 = xhci_port_state_to_neutral(t1);
1634 portsc_buf[port_index] = 0;
1635
1636 /*
1637 * Give a USB3 port in link training time to finish, but don't
1638 * prevent suspend as port might be stuck
1639 */
1640 if ((hcd->speed >= HCD_USB3) && retries-- &&
1641 (t1 & PORT_PLS_MASK) == XDEV_POLLING) {
1642 spin_unlock_irqrestore(&xhci->lock, flags);
1643 msleep(XHCI_PORT_POLLING_LFPS_TIME);
1644 spin_lock_irqsave(&xhci->lock, flags);
1645 xhci_dbg(xhci, "port %d-%d polling in bus suspend, waiting\n",
1646 hcd->self.busnum, port_index + 1);
1647 goto retry;
1648 }
1649 /* bail out if port detected a over-current condition */
1650 if (t1 & PORT_OC) {
1651 bus_state->bus_suspended = 0;
1652 spin_unlock_irqrestore(&xhci->lock, flags);
1653 xhci_dbg(xhci, "Bus suspend bailout, port over-current detected\n");
1654 return -EBUSY;
1655 }
1656 /* suspend ports in U0, or bail out for new connect changes */
1657 if ((t1 & PORT_PE) && (t1 & PORT_PLS_MASK) == XDEV_U0) {
1658 if ((t1 & PORT_CSC) && wake_enabled) {
1659 bus_state->bus_suspended = 0;
1660 spin_unlock_irqrestore(&xhci->lock, flags);
1661 xhci_dbg(xhci, "Bus suspend bailout, port connect change\n");
1662 return -EBUSY;
1663 }
1664 xhci_dbg(xhci, "port %d-%d not suspended\n",
1665 hcd->self.busnum, port_index + 1);
1666 t2 &= ~PORT_PLS_MASK;
1667 t2 |= PORT_LINK_STROBE | XDEV_U3;
1668 set_bit(port_index, &bus_state->bus_suspended);
1669 }
1670 /* USB core sets remote wake mask for USB 3.0 hubs,
1671 * including the USB 3.0 roothub, but only if CONFIG_PM
1672 * is enabled, so also enable remote wake here.
1673 */
1674 if (wake_enabled) {
1675 if (t1 & PORT_CONNECT) {
1676 t2 |= PORT_WKOC_E | PORT_WKDISC_E;
1677 t2 &= ~PORT_WKCONN_E;
1678 } else {
1679 t2 |= PORT_WKOC_E | PORT_WKCONN_E;
1680 t2 &= ~PORT_WKDISC_E;
1681 }
1682
1683 if ((xhci->quirks & XHCI_U2_DISABLE_WAKE) &&
1684 (hcd->speed < HCD_USB3)) {
1685 if (usb_amd_pt_check_port(hcd->self.controller,
1686 port_index))
1687 t2 &= ~PORT_WAKE_BITS;
1688 }
1689 } else
1690 t2 &= ~PORT_WAKE_BITS;
1691
1692 t1 = xhci_port_state_to_neutral(t1);
1693 if (t1 != t2)
1694 portsc_buf[port_index] = t2;
1695 }
1696
1697 /* write port settings, stopping and suspending ports if needed */
1698 port_index = max_ports;
1699 while (port_index--) {
1700 if (!portsc_buf[port_index])
1701 continue;
1702 if (test_bit(port_index, &bus_state->bus_suspended)) {
1703 int slot_id;
1704
1705 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1706 port_index + 1);
1707 if (slot_id) {
1708 spin_unlock_irqrestore(&xhci->lock, flags);
1709 xhci_stop_device(xhci, slot_id, 1);
1710 spin_lock_irqsave(&xhci->lock, flags);
1711 }
1712 }
1713 writel(portsc_buf[port_index], ports[port_index]->addr);
1714 }
1715 hcd->state = HC_STATE_SUSPENDED;
1716 bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
1717 spin_unlock_irqrestore(&xhci->lock, flags);
1718
1719 if (bus_state->bus_suspended)
1720 usleep_range(5000, 10000);
1721
1722 return 0;
1723 }
1724
1725 /*
1726 * Workaround for missing Cold Attach Status (CAS) if device re-plugged in S3.
1727 * warm reset a USB3 device stuck in polling or compliance mode after resume.
1728 * See Intel 100/c230 series PCH specification update Doc #332692-006 Errata #8
1729 */
xhci_port_missing_cas_quirk(struct xhci_port * port)1730 static bool xhci_port_missing_cas_quirk(struct xhci_port *port)
1731 {
1732 u32 portsc;
1733
1734 portsc = readl(port->addr);
1735
1736 /* if any of these are set we are not stuck */
1737 if (portsc & (PORT_CONNECT | PORT_CAS))
1738 return false;
1739
1740 if (((portsc & PORT_PLS_MASK) != XDEV_POLLING) &&
1741 ((portsc & PORT_PLS_MASK) != XDEV_COMP_MODE))
1742 return false;
1743
1744 /* clear wakeup/change bits, and do a warm port reset */
1745 portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1746 portsc |= PORT_WR;
1747 writel(portsc, port->addr);
1748 /* flush write */
1749 readl(port->addr);
1750 return true;
1751 }
1752
xhci_bus_resume(struct usb_hcd * hcd)1753 int xhci_bus_resume(struct usb_hcd *hcd)
1754 {
1755 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1756 struct xhci_bus_state *bus_state;
1757 unsigned long flags;
1758 int max_ports, port_index;
1759 int slot_id;
1760 int sret;
1761 u32 next_state;
1762 u32 temp, portsc;
1763 struct xhci_hub *rhub;
1764 struct xhci_port **ports;
1765
1766 rhub = xhci_get_rhub(hcd);
1767 ports = rhub->ports;
1768 max_ports = rhub->num_ports;
1769 bus_state = &rhub->bus_state;
1770
1771 if (time_before(jiffies, bus_state->next_statechange))
1772 msleep(5);
1773
1774 spin_lock_irqsave(&xhci->lock, flags);
1775 if (!HCD_HW_ACCESSIBLE(hcd)) {
1776 spin_unlock_irqrestore(&xhci->lock, flags);
1777 return -ESHUTDOWN;
1778 }
1779
1780 /* delay the irqs */
1781 temp = readl(&xhci->op_regs->command);
1782 temp &= ~CMD_EIE;
1783 writel(temp, &xhci->op_regs->command);
1784
1785 /* bus specific resume for ports we suspended at bus_suspend */
1786 if (hcd->speed >= HCD_USB3)
1787 next_state = XDEV_U0;
1788 else
1789 next_state = XDEV_RESUME;
1790
1791 port_index = max_ports;
1792 while (port_index--) {
1793 portsc = readl(ports[port_index]->addr);
1794
1795 /* warm reset CAS limited ports stuck in polling/compliance */
1796 if ((xhci->quirks & XHCI_MISSING_CAS) &&
1797 (hcd->speed >= HCD_USB3) &&
1798 xhci_port_missing_cas_quirk(ports[port_index])) {
1799 xhci_dbg(xhci, "reset stuck port %d-%d\n",
1800 hcd->self.busnum, port_index + 1);
1801 clear_bit(port_index, &bus_state->bus_suspended);
1802 continue;
1803 }
1804 /* resume if we suspended the link, and it is still suspended */
1805 if (test_bit(port_index, &bus_state->bus_suspended))
1806 switch (portsc & PORT_PLS_MASK) {
1807 case XDEV_U3:
1808 portsc = xhci_port_state_to_neutral(portsc);
1809 portsc &= ~PORT_PLS_MASK;
1810 portsc |= PORT_LINK_STROBE | next_state;
1811 break;
1812 case XDEV_RESUME:
1813 /* resume already initiated */
1814 break;
1815 default:
1816 /* not in a resumeable state, ignore it */
1817 clear_bit(port_index,
1818 &bus_state->bus_suspended);
1819 break;
1820 }
1821 /* disable wake for all ports, write new link state if needed */
1822 portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1823 writel(portsc, ports[port_index]->addr);
1824 }
1825
1826 /* USB2 specific resume signaling delay and U0 link state transition */
1827 if (hcd->speed < HCD_USB3) {
1828 if (bus_state->bus_suspended) {
1829 spin_unlock_irqrestore(&xhci->lock, flags);
1830 msleep(USB_RESUME_TIMEOUT);
1831 spin_lock_irqsave(&xhci->lock, flags);
1832 }
1833 for_each_set_bit(port_index, &bus_state->bus_suspended,
1834 BITS_PER_LONG) {
1835 /* Clear PLC to poll it later for U0 transition */
1836 xhci_test_and_clear_bit(xhci, ports[port_index],
1837 PORT_PLC);
1838 xhci_set_link_state(xhci, ports[port_index], XDEV_U0);
1839 }
1840 }
1841
1842 /* poll for U0 link state complete, both USB2 and USB3 */
1843 for_each_set_bit(port_index, &bus_state->bus_suspended, BITS_PER_LONG) {
1844 sret = xhci_handshake(ports[port_index]->addr, PORT_PLC,
1845 PORT_PLC, 10 * 1000);
1846 if (sret) {
1847 xhci_warn(xhci, "port %d-%d resume PLC timeout\n",
1848 hcd->self.busnum, port_index + 1);
1849 continue;
1850 }
1851 xhci_test_and_clear_bit(xhci, ports[port_index], PORT_PLC);
1852 slot_id = xhci_find_slot_id_by_port(hcd, xhci, port_index + 1);
1853 if (slot_id)
1854 xhci_ring_device(xhci, slot_id);
1855 }
1856 (void) readl(&xhci->op_regs->command);
1857
1858 bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
1859 /* re-enable irqs */
1860 temp = readl(&xhci->op_regs->command);
1861 temp |= CMD_EIE;
1862 writel(temp, &xhci->op_regs->command);
1863 temp = readl(&xhci->op_regs->command);
1864
1865 spin_unlock_irqrestore(&xhci->lock, flags);
1866 return 0;
1867 }
1868
xhci_get_resuming_ports(struct usb_hcd * hcd)1869 unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd)
1870 {
1871 struct xhci_hub *rhub = xhci_get_rhub(hcd);
1872
1873 /* USB3 port wakeups are reported via usb_wakeup_notification() */
1874 return rhub->bus_state.resuming_ports; /* USB2 ports only */
1875 }
1876
1877 #endif /* CONFIG_PM */
1878