| /kernel/linux/linux-5.10/arch/arm/mm/ |
| D | proc-mohawk.S | 41 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
44 mcr p15, 0, r0, c1, c0, 0 @ disable caches
62 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
63 mcr p15, 0, ip, c7, c10, 4 @ drain WB
64 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
65 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
68 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
81 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
82 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt
92 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
[all …]
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| D | proc-arm946.S | 43 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
46 mcr p15, 0, r0, c1, c0, 0 @ disable caches
57 mcr p15, 0, ip, c7, c5, 0 @ flush I cache
58 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
59 mcr p15, 0, ip, c7, c10, 4 @ drain WB
60 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
63 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
73 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
83 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
103 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
[all …]
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| D | proc-arm926.S | 50 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
53 mcr p15, 0, r0, c1, c0, 0 @ disable caches
69 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
70 mcr p15, 0, ip, c7, c10, 4 @ drain WB
72 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
74 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
77 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
90 mrc p15, 0, r1, c1, c0, 0 @ Read control register
91 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
96 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache
[all …]
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| D | proc-v7.S | 32 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
35 mcr p15, 0, r0, c1, c0, 0 @ disable caches
55 mrc p15, 0, r2, c1, c0, 0 @ ctrl register
58 mcr p15, 0, r2, c1, c0, 0 @ disable MMU
86 2: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
116 mcr p15, 0, r3, c7, c5, 0 @ ICIALLU
121 mcr p15, 0, r3, c7, c5, 6 @ flush BTAC/BTB
134 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
135 mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID
138 mrc p15, 0, r6, c3, c0, 0 @ Domain ID
[all …]
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| D | proc-v6.S | 39 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
42 mcr p15, 0, r0, c1, c0, 0 @ disable caches
57 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
59 mcr p15, 0, r1, c1, c0, 0 @ disable MMU
61 mcr p15, 0, r1, c7, c5, 4 @ ISB
75 mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode
76 mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt
80 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
102 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
103 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
[all …]
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| D | proc-arm940.S | 36 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
39 mcr p15, 0, r0, c1, c0, 0 @ disable caches
50 mcr p15, 0, ip, c7, c5, 0 @ flush I cache
51 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
52 mcr p15, 0, ip, c7, c10, 4 @ drain WB
53 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
56 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
66 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
76 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
108 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
[all …]
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| D | proc-feroceon.S | 47 mrc p15, 0, r0, c0, c0, 1 @ read cache type register
68 mcr p15, 1, r0, c15, c9, 0 @ clean L2
69 mcr p15, 0, r0, c7, c10, 4 @ drain WB
72 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
75 mcr p15, 0, r0, c1, c0, 0 @ disable caches
91 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
92 mcr p15, 0, ip, c7, c10, 4 @ drain WB
94 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
96 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
99 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
[all …]
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| D | proc-arm1020.S | 66 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
69 mcr p15, 0, r0, c1, c0, 0 @ disable caches
85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
86 mcr p15, 0, ip, c7, c10, 4 @ drain WB
88 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
90 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
93 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
103 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
118 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
141 mcr p15, 0, ip, c7, c10, 4 @ drain WB
[all …]
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| D | proc-arm925.S | 81 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
84 mcr p15, 0, r0, c1, c0, 0 @ disable caches
109 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
110 mcr p15, 0, ip, c7, c10, 4 @ drain WB
112 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
114 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
117 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
128 mrc p15, 0, r1, c1, c0, 0 @ Read control register
129 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
131 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache
[all …]
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| D | proc-xsc3.S | 56 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
68 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line
89 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
92 mcr p15, 0, r0, c1, c0, 0 @ disable caches
109 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
112 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
113 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
115 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
118 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
149 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
[all …]
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| D | proc-arm920.S | 58 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
61 mcr p15, 0, r0, c1, c0, 0 @ disable caches
77 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
78 mcr p15, 0, ip, c7, c10, 4 @ drain WB
80 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
82 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
85 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
95 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
108 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
132 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
[all …]
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| D | proc-xscale.S | 69 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
75 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
91 1: mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
93 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
95 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
97 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
116 mrc p15, 0, r1, c1, c0, 1
118 mcr p15, 0, r1, c1, c0, 1
125 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
128 mcr p15, 0, r0, c1, c0, 0 @ disable caches
[all …]
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| D | proc-fa526.S | 36 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
39 mcr p15, 0, r0, c1, c0, 0 @ disable caches
58 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
59 mcr p15, 0, ip, c7, c10, 4 @ drain WB
61 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
63 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
67 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
83 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
87 mcr p15, 0, r0, c7, c10, 4 @ drain WB
104 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
[all …]
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| D | proc-sa1100.S | 41 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
42 mcr p15, 0, r0, c9, c0, 5 @ Allow read-buffer operations from userland
53 mcr p15, 0, ip, c15, c2, 2 @ Disable clock switching
54 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
57 mcr p15, 0, r0, c1, c0, 0 @ disable caches
73 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
74 mcr p15, 0, ip, c7, c10, 4 @ drain WB
76 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
78 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
81 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
[all …]
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| D | proc-arm922.S | 60 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
63 mcr p15, 0, r0, c1, c0, 0 @ disable caches
79 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
80 mcr p15, 0, ip, c7, c10, 4 @ drain WB
82 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
84 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
87 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
97 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
110 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
134 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
[all …]
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| D | proc-arm1026.S | 66 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
69 mcr p15, 0, r0, c1, c0, 0 @ disable caches
85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
86 mcr p15, 0, ip, c7, c10, 4 @ drain WB
88 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
90 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
93 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
103 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
118 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
141 1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test, clean, invalidate
[all …]
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| D | cache-fa.S | 45 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
66 mcr p15, 0, ip, c7, c14, 0 @ clean/invalidate D cache
68 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
69 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
70 mcrne p15, 0, ip, c7, c10, 4 @ drain write buffer
71 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
91 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I line
92 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
97 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
98 mcrne p15, 0, ip, c7, c10, 4 @ data write barrier
[all …]
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| D | proc-arm1022.S | 66 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
69 mcr p15, 0, r0, c1, c0, 0 @ disable caches
85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
86 mcr p15, 0, ip, c7, c10, 4 @ drain WB
88 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
90 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
93 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
103 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
118 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
143 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
[all …]
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| D | proc-arm1020e.S | 66 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
69 mcr p15, 0, r0, c1, c0, 0 @ disable caches
85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
86 mcr p15, 0, ip, c7, c10, 4 @ drain WB
88 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
90 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
93 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
103 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
118 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
141 mcr p15, 0, ip, c7, c10, 4 @ drain WB
[all …]
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| D | cache-v6.S | 40 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
41 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
42 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
43 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
49 mcr p15, 0, r0, c7, c5, 0 @ invalidate I-cache
64 mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate
66 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
71 mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate
134 USER( mcr p15, 0, r0, c7, c10, 1 ) @ clean D line
141 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
[all …]
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| D | proc-arm740.S | 37 mrc p15, 0, r0, c1, c0, 0
40 mcr p15, 0, r0, c1, c0, 0 @ disable caches
51 mcr p15, 0, ip, c7, c0, 0 @ invalidate cache
52 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
54 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
62 mcr p15, 0, r0, c7, c0, 0 @ invalidate caches
64 mcr p15, 0, r0, c6, c3 @ disable area 3~7
65 mcr p15, 0, r0, c6, c4
66 mcr p15, 0, r0, c6, c5
67 mcr p15, 0, r0, c6, c6
[all …]
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| D | proc-sa110.S | 37 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
45 mcr p15, 0, r0, c15, c2, 2 @ Disable clock switching
46 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
49 mcr p15, 0, r0, c1, c0, 0 @ disable caches
65 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
66 mcr p15, 0, ip, c7, c10, 4 @ drain WB
68 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
70 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
73 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
92 mcr p15, 0, ip, c15, c2, 2 @ disable clock switching
[all …]
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| /kernel/liteos_a/arch/arm/arm/include/ |
| D | arm.h | 42 __asm__ volatile("mrc p15, 0, %0, c1,c0,0" : "=r"(val)); in OsArmReadSctlr()
48 __asm__ volatile("mcr p15, 0, %0, c1,c0,0" ::"r"(val)); in OsArmWriteSctlr()
55 __asm__ volatile("mrc p15, 0, %0, c1,c0,1" : "=r"(val)); in OsArmReadActlr()
61 __asm__ volatile("mcr p15, 0, %0, c1,c0,1" ::"r"(val)); in OsArmWriteActlr()
68 __asm__ volatile("mrc p15, 0, %0, c1,c0,2" : "=r"(val)); in OsArmReadCpacr()
74 __asm__ volatile("mcr p15, 0, %0, c1,c0,2" ::"r"(val)); in OsArmWriteCpacr()
81 __asm__ volatile("mrc p15, 0, %0, c2,c0,0" : "=r"(val)); in OsArmReadTtbr()
87 __asm__ volatile("mcr p15, 0, %0, c2,c0,0" ::"r"(val)); in OsArmWriteTtbr()
94 __asm__ volatile("mrc p15, 0, %0, c2,c0,0" : "=r"(val)); in OsArmReadTtbr0()
100 __asm__ volatile("mcr p15, 0, %0, c2,c0,0" ::"r"(val)); in OsArmWriteTtbr0()
[all …]
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| /kernel/linux/linux-5.10/arch/arm/kernel/ |
| D | hyp-stub.S | 114 mcr p15, 4, r7, c12, c0, 0 @ set hypervisor vector base (HVBAR)
118 mcr p15, 4, r7, c1, c1, 0 @ HCR
119 mcr p15, 4, r7, c1, c1, 2 @ HCPTR
120 mcr p15, 4, r7, c1, c1, 3 @ HSTR
124 mcr p15, 4, r7, c1, c0, 0 @ HSCTLR
126 mrc p15, 4, r7, c1, c1, 1 @ HDCR
128 mcr p15, 4, r7, c1, c1, 1 @ HDCR
131 mrc p15, 0, r7, c1, c0, 0 @ SCTLR
135 mcr p15, 0, r7, c1, c0, 0 @ SCTLR
137 mrc p15, 0, r7, c0, c0, 0 @ MIDR
[all …]
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| /kernel/linux/linux-5.10/arch/arm/boot/compressed/ |
| D | head.S | 139 mrc p15, 0, \reg, c1, c0, 0 @ read SCTLR
143 mcr p15, 0, \reg, c1, c0, 0 @ write SCTLR
484 mrc p15, 0, r1, c0, c1, 1 @ read ID_PFR1 register
486 mrrcne p15, 1, r3, r1, c14 @ read CNTVCT
756 mrc p15, 0, \tmp, c0, c0, 1 @ read ctr
791 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
792 mcr p15, 0, r0, c6, c7, 1
795 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
796 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
797 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
[all …]
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