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Searched refs:BITFIELD64_RANGE (Results 1 – 17 of 17) sorted by relevance

/third_party/mesa3d/src/mesa/vbo/
Dvbo_attrib.h111 #define VBO_ATTRIBS_MATERIALS BITFIELD64_RANGE(VBO_ATTRIB_MAT_FRONT_AMBIENT, \
/third_party/mesa3d/src/mesa/swrast_setup/
Dss_context.c147 if (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)) in setup_vertex_format()
158 if (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_GENERIC0, _TNL_NUM_GENERIC)) { in setup_vertex_format()
/third_party/mesa3d/src/mesa/drivers/dri/r200/
Dr200_swtcl.c103 (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)) ) { in r200SetVertexFormat()
163 if (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)) { in r200SetVertexFormat()
258 if ((0 == (tnl->render_inputs_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX))) in r200ChooseVertexState()
264 if (tnl->render_inputs_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)) { in r200ChooseVertexState()
/third_party/mesa3d/src/compiler/nir/
Dnir_gather_info.c451 slot_mask = BITFIELD64_RANGE(semantics.location, semantics.num_slots); in gather_intrinsic_info()
923 shader->info.per_primitive_outputs |= BITFIELD64_RANGE(var->data.location, slots); in nir_shader_gather_info()
934 shader->info.per_primitive_inputs |= BITFIELD64_RANGE(var->data.location, slots); in nir_shader_gather_info()
Dnir_linking_helpers.c368 BITFIELD64_RANGE(var->data.location - loc_offset, num_slots); in mark_all_used_slots()
391 slots_used_tmp[0] = *slots_used & BITFIELD64_RANGE(0, VARYING_SLOT_VAR0); in remap_slots_and_components()
418 BITFIELD64_RANGE(var->data.location - loc_offset, num_slots); in remap_slots_and_components()
/third_party/mesa3d/src/mesa/drivers/dri/radeon/
Dradeon_swtcl.c113 (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX))) { in radeonSetVertexFormat()
176 if (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)) { in radeonSetVertexFormat()
296 (BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX) in radeonChooseVertexState()
/third_party/mesa3d/src/intel/vulkan/
Danv_nir_compute_push_layout.c244 prog_data->zero_push_reg |= BITFIELD64_RANGE(range_start_reg, in anv_nir_compute_push_layout()
DgenX_cmd_buffer.c3367 push->push_reg_mask[stage] |= BITFIELD64_RANGE(range_start_reg, in cmd_buffer_flush_push_constants()
/third_party/mesa3d/src/util/
Dmacros.h401 #define BITFIELD64_RANGE(b, count) \ macro
/third_party/mesa3d/src/mesa/drivers/dri/i915/
Di830_vtbl.c96 if (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)) { in i830_render_start()
127 if (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)) { in i830_render_start()
/third_party/mesa3d/src/compiler/
Dshader_enums.h438 #define VARYING_BITS_TEX_ANY BITFIELD64_RANGE(VARYING_SLOT_TEX0, \
/third_party/mesa3d/src/intel/compiler/
Dbrw_compiler.h1133 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
Dbrw_vec4_generator.cpp1494 if (i % 16 == 0 && (want_zero & BITFIELD64_RANGE(i, 16))) { in generate_zero_oob_push_regs()
Dbrw_fs.cpp1808 if (i % 16 == 0 && (want_zero & BITFIELD64_RANGE(i, 16))) { in assign_curb_setup()
/third_party/mesa3d/src/gallium/drivers/radeonsi/
Dsi_shader_nir.c895 BITFIELD64_BIT(VARYING_SLOT_PNTC) | BITFIELD64_RANGE(VARYING_SLOT_VAR0, 32), in si_lower_nir()
/third_party/mesa3d/src/gallium/drivers/iris/
Diris_program.c2879 BITFIELD64_RANGE(FRAG_RESULT_DATA0, BRW_MAX_DRAW_BUFFERS); in iris_bind_fs_state()
/third_party/mesa3d/src/gallium/drivers/crocus/
Dcrocus_program.c3079 BITFIELD64_RANGE(FRAG_RESULT_DATA0, BRW_MAX_DRAW_BUFFERS); in crocus_bind_fs_state()