1 /* Copyright © 2011 Intel Corporation
2 *
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
9 *
10 * The above copyright notice and this permission notice (including the next
11 * paragraph) shall be included in all copies or substantial portions of the
12 * Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
20 * IN THE SOFTWARE.
21 */
22
23 #include "brw_vec4.h"
24 #include "brw_cfg.h"
25 #include "brw_eu.h"
26 #include "dev/intel_debug.h"
27 #include "util/mesa-sha1.h"
28
29 using namespace brw;
30
31 static void
generate_math1_gfx4(struct brw_codegen * p,vec4_instruction * inst,struct brw_reg dst,struct brw_reg src)32 generate_math1_gfx4(struct brw_codegen *p,
33 vec4_instruction *inst,
34 struct brw_reg dst,
35 struct brw_reg src)
36 {
37 gfx4_math(p,
38 dst,
39 brw_math_function(inst->opcode),
40 inst->base_mrf,
41 src,
42 BRW_MATH_PRECISION_FULL);
43 }
44
45 static void
check_gfx6_math_src_arg(struct brw_reg src)46 check_gfx6_math_src_arg(struct brw_reg src)
47 {
48 /* Source swizzles are ignored. */
49 assert(!src.abs);
50 assert(!src.negate);
51 assert(src.swizzle == BRW_SWIZZLE_XYZW);
52 }
53
54 static void
generate_math_gfx6(struct brw_codegen * p,vec4_instruction * inst,struct brw_reg dst,struct brw_reg src0,struct brw_reg src1)55 generate_math_gfx6(struct brw_codegen *p,
56 vec4_instruction *inst,
57 struct brw_reg dst,
58 struct brw_reg src0,
59 struct brw_reg src1)
60 {
61 /* Can't do writemask because math can't be align16. */
62 assert(dst.writemask == WRITEMASK_XYZW);
63 /* Source swizzles are ignored. */
64 check_gfx6_math_src_arg(src0);
65 if (src1.file == BRW_GENERAL_REGISTER_FILE)
66 check_gfx6_math_src_arg(src1);
67
68 brw_set_default_access_mode(p, BRW_ALIGN_1);
69 gfx6_math(p, dst, brw_math_function(inst->opcode), src0, src1);
70 brw_set_default_access_mode(p, BRW_ALIGN_16);
71 }
72
73 static void
generate_math2_gfx4(struct brw_codegen * p,vec4_instruction * inst,struct brw_reg dst,struct brw_reg src0,struct brw_reg src1)74 generate_math2_gfx4(struct brw_codegen *p,
75 vec4_instruction *inst,
76 struct brw_reg dst,
77 struct brw_reg src0,
78 struct brw_reg src1)
79 {
80 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
81 * "Message Payload":
82 *
83 * "Operand0[7]. For the INT DIV functions, this operand is the
84 * denominator."
85 * ...
86 * "Operand1[7]. For the INT DIV functions, this operand is the
87 * numerator."
88 */
89 bool is_int_div = inst->opcode != SHADER_OPCODE_POW;
90 struct brw_reg &op0 = is_int_div ? src1 : src0;
91 struct brw_reg &op1 = is_int_div ? src0 : src1;
92
93 brw_push_insn_state(p);
94 brw_set_default_saturate(p, false);
95 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
96 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), op1.type), op1);
97 brw_pop_insn_state(p);
98
99 gfx4_math(p,
100 dst,
101 brw_math_function(inst->opcode),
102 inst->base_mrf,
103 op0,
104 BRW_MATH_PRECISION_FULL);
105 }
106
107 static void
generate_tex(struct brw_codegen * p,struct brw_vue_prog_data * prog_data,gl_shader_stage stage,vec4_instruction * inst,struct brw_reg dst,struct brw_reg src,struct brw_reg surface_index,struct brw_reg sampler_index)108 generate_tex(struct brw_codegen *p,
109 struct brw_vue_prog_data *prog_data,
110 gl_shader_stage stage,
111 vec4_instruction *inst,
112 struct brw_reg dst,
113 struct brw_reg src,
114 struct brw_reg surface_index,
115 struct brw_reg sampler_index)
116 {
117 const struct intel_device_info *devinfo = p->devinfo;
118 int msg_type = -1;
119
120 if (devinfo->ver >= 5) {
121 switch (inst->opcode) {
122 case SHADER_OPCODE_TEX:
123 case SHADER_OPCODE_TXL:
124 if (inst->shadow_compare) {
125 msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
126 } else {
127 msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_LOD;
128 }
129 break;
130 case SHADER_OPCODE_TXD:
131 if (inst->shadow_compare) {
132 /* Gfx7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
133 assert(devinfo->is_haswell);
134 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
135 } else {
136 msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
137 }
138 break;
139 case SHADER_OPCODE_TXF:
140 msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_LD;
141 break;
142 case SHADER_OPCODE_TXF_CMS:
143 if (devinfo->ver >= 7)
144 msg_type = GFX7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
145 else
146 msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_LD;
147 break;
148 case SHADER_OPCODE_TXF_MCS:
149 assert(devinfo->ver >= 7);
150 msg_type = GFX7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
151 break;
152 case SHADER_OPCODE_TXS:
153 msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
154 break;
155 case SHADER_OPCODE_TG4:
156 if (inst->shadow_compare) {
157 msg_type = GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
158 } else {
159 msg_type = GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
160 }
161 break;
162 case SHADER_OPCODE_TG4_OFFSET:
163 if (inst->shadow_compare) {
164 msg_type = GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
165 } else {
166 msg_type = GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
167 }
168 break;
169 case SHADER_OPCODE_SAMPLEINFO:
170 msg_type = GFX6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO;
171 break;
172 default:
173 unreachable("should not get here: invalid vec4 texture opcode");
174 }
175 } else {
176 switch (inst->opcode) {
177 case SHADER_OPCODE_TEX:
178 case SHADER_OPCODE_TXL:
179 if (inst->shadow_compare) {
180 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE;
181 assert(inst->mlen == 3);
182 } else {
183 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD;
184 assert(inst->mlen == 2);
185 }
186 break;
187 case SHADER_OPCODE_TXD:
188 /* There is no sample_d_c message; comparisons are done manually. */
189 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS;
190 assert(inst->mlen == 4);
191 break;
192 case SHADER_OPCODE_TXF:
193 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_LD;
194 assert(inst->mlen == 2);
195 break;
196 case SHADER_OPCODE_TXS:
197 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO;
198 assert(inst->mlen == 2);
199 break;
200 default:
201 unreachable("should not get here: invalid vec4 texture opcode");
202 }
203 }
204
205 assert(msg_type != -1);
206
207 assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
208
209 /* Load the message header if present. If there's a texture offset, we need
210 * to set it up explicitly and load the offset bitfield. Otherwise, we can
211 * use an implied move from g0 to the first message register.
212 */
213 if (inst->header_size != 0) {
214 if (devinfo->ver < 6 && !inst->offset) {
215 /* Set up an implied move from g0 to the MRF. */
216 src = brw_vec8_grf(0, 0);
217 } else {
218 struct brw_reg header =
219 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD);
220 uint32_t dw2 = 0;
221
222 /* Explicitly set up the message header by copying g0 to the MRF. */
223 brw_push_insn_state(p);
224 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
225 brw_MOV(p, header, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
226
227 brw_set_default_access_mode(p, BRW_ALIGN_1);
228
229 if (inst->offset)
230 /* Set the texel offset bits in DWord 2. */
231 dw2 = inst->offset;
232
233 /* The VS, DS, and FS stages have the g0.2 payload delivered as 0,
234 * so header0.2 is 0 when g0 is copied. The HS and GS stages do
235 * not, so we must set to to 0 to avoid setting undesirable bits
236 * in the message header.
237 */
238 if (dw2 ||
239 stage == MESA_SHADER_TESS_CTRL ||
240 stage == MESA_SHADER_GEOMETRY) {
241 brw_MOV(p, get_element_ud(header, 2), brw_imm_ud(dw2));
242 }
243
244 brw_adjust_sampler_state_pointer(p, header, sampler_index);
245 brw_pop_insn_state(p);
246 }
247 }
248
249 uint32_t return_format;
250
251 switch (dst.type) {
252 case BRW_REGISTER_TYPE_D:
253 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
254 break;
255 case BRW_REGISTER_TYPE_UD:
256 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
257 break;
258 default:
259 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
260 break;
261 }
262
263 /* Stomp the resinfo output type to UINT32. On gens 4-5, the output type
264 * is set as part of the message descriptor. On gfx4, the PRM seems to
265 * allow UINT32 and FLOAT32 (i965 PRM, Vol. 4 Section 4.8.1.1), but on
266 * later gens UINT32 is required. Once you hit Sandy Bridge, the bit is
267 * gone from the message descriptor entirely and you just get UINT32 all
268 * the time regasrdless. Since we can really only do non-UINT32 on gfx4,
269 * just stomp it to UINT32 all the time.
270 */
271 if (inst->opcode == SHADER_OPCODE_TXS)
272 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
273
274 uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 ||
275 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
276 ? prog_data->base.binding_table.gather_texture_start
277 : prog_data->base.binding_table.texture_start;
278
279 if (surface_index.file == BRW_IMMEDIATE_VALUE &&
280 sampler_index.file == BRW_IMMEDIATE_VALUE) {
281 uint32_t surface = surface_index.ud;
282 uint32_t sampler = sampler_index.ud;
283
284 brw_SAMPLE(p,
285 dst,
286 inst->base_mrf,
287 src,
288 surface + base_binding_table_index,
289 sampler % 16,
290 msg_type,
291 1, /* response length */
292 inst->mlen,
293 inst->header_size != 0,
294 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
295 return_format);
296 } else {
297 /* Non-constant sampler index. */
298
299 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
300 struct brw_reg surface_reg = vec1(retype(surface_index, BRW_REGISTER_TYPE_UD));
301 struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD));
302
303 brw_push_insn_state(p);
304 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
305 brw_set_default_access_mode(p, BRW_ALIGN_1);
306
307 if (brw_regs_equal(&surface_reg, &sampler_reg)) {
308 brw_MUL(p, addr, sampler_reg, brw_imm_uw(0x101));
309 } else {
310 if (sampler_reg.file == BRW_IMMEDIATE_VALUE) {
311 brw_OR(p, addr, surface_reg, brw_imm_ud(sampler_reg.ud << 8));
312 } else {
313 brw_SHL(p, addr, sampler_reg, brw_imm_ud(8));
314 brw_OR(p, addr, addr, surface_reg);
315 }
316 }
317 if (base_binding_table_index)
318 brw_ADD(p, addr, addr, brw_imm_ud(base_binding_table_index));
319 brw_AND(p, addr, addr, brw_imm_ud(0xfff));
320
321 brw_pop_insn_state(p);
322
323 if (inst->base_mrf != -1)
324 gfx6_resolve_implied_move(p, &src, inst->base_mrf);
325
326 /* dst = send(offset, a0.0 | <descriptor>) */
327 brw_send_indirect_message(
328 p, BRW_SFID_SAMPLER, dst, src, addr,
329 brw_message_desc(devinfo, inst->mlen, 1, inst->header_size) |
330 brw_sampler_desc(devinfo,
331 0 /* surface */,
332 0 /* sampler */,
333 msg_type,
334 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
335 return_format),
336 false /* EOT */);
337
338 /* visitor knows more than we do about the surface limit required,
339 * so has already done marking.
340 */
341 }
342 }
343
344 static void
generate_vs_urb_write(struct brw_codegen * p,vec4_instruction * inst)345 generate_vs_urb_write(struct brw_codegen *p, vec4_instruction *inst)
346 {
347 brw_urb_WRITE(p,
348 brw_null_reg(), /* dest */
349 inst->base_mrf, /* starting mrf reg nr */
350 brw_vec8_grf(0, 0), /* src */
351 inst->urb_write_flags,
352 inst->mlen,
353 0, /* response len */
354 inst->offset, /* urb destination offset */
355 BRW_URB_SWIZZLE_INTERLEAVE);
356 }
357
358 static void
generate_gs_urb_write(struct brw_codegen * p,vec4_instruction * inst)359 generate_gs_urb_write(struct brw_codegen *p, vec4_instruction *inst)
360 {
361 struct brw_reg src = brw_message_reg(inst->base_mrf);
362 brw_urb_WRITE(p,
363 brw_null_reg(), /* dest */
364 inst->base_mrf, /* starting mrf reg nr */
365 src,
366 inst->urb_write_flags,
367 inst->mlen,
368 0, /* response len */
369 inst->offset, /* urb destination offset */
370 BRW_URB_SWIZZLE_INTERLEAVE);
371 }
372
373 static void
generate_gs_urb_write_allocate(struct brw_codegen * p,vec4_instruction * inst)374 generate_gs_urb_write_allocate(struct brw_codegen *p, vec4_instruction *inst)
375 {
376 struct brw_reg src = brw_message_reg(inst->base_mrf);
377
378 /* We pass the temporary passed in src0 as the writeback register */
379 brw_urb_WRITE(p,
380 inst->src[0].as_brw_reg(), /* dest */
381 inst->base_mrf, /* starting mrf reg nr */
382 src,
383 BRW_URB_WRITE_ALLOCATE_COMPLETE,
384 inst->mlen,
385 1, /* response len */
386 inst->offset, /* urb destination offset */
387 BRW_URB_SWIZZLE_INTERLEAVE);
388
389 /* Now put allocated urb handle in dst.0 */
390 brw_push_insn_state(p);
391 brw_set_default_access_mode(p, BRW_ALIGN_1);
392 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
393 brw_MOV(p, get_element_ud(inst->dst.as_brw_reg(), 0),
394 get_element_ud(inst->src[0].as_brw_reg(), 0));
395 brw_pop_insn_state(p);
396 }
397
398 static void
generate_gs_thread_end(struct brw_codegen * p,vec4_instruction * inst)399 generate_gs_thread_end(struct brw_codegen *p, vec4_instruction *inst)
400 {
401 struct brw_reg src = brw_message_reg(inst->base_mrf);
402 brw_urb_WRITE(p,
403 brw_null_reg(), /* dest */
404 inst->base_mrf, /* starting mrf reg nr */
405 src,
406 BRW_URB_WRITE_EOT | inst->urb_write_flags,
407 inst->mlen,
408 0, /* response len */
409 0, /* urb destination offset */
410 BRW_URB_SWIZZLE_INTERLEAVE);
411 }
412
413 static void
generate_gs_set_write_offset(struct brw_codegen * p,struct brw_reg dst,struct brw_reg src0,struct brw_reg src1)414 generate_gs_set_write_offset(struct brw_codegen *p,
415 struct brw_reg dst,
416 struct brw_reg src0,
417 struct brw_reg src1)
418 {
419 /* From p22 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
420 * Header: M0.3):
421 *
422 * Slot 0 Offset. This field, after adding to the Global Offset field
423 * in the message descriptor, specifies the offset (in 256-bit units)
424 * from the start of the URB entry, as referenced by URB Handle 0, at
425 * which the data will be accessed.
426 *
427 * Similar text describes DWORD M0.4, which is slot 1 offset.
428 *
429 * Therefore, we want to multiply DWORDs 0 and 4 of src0 (the x components
430 * of the register for geometry shader invocations 0 and 1) by the
431 * immediate value in src1, and store the result in DWORDs 3 and 4 of dst.
432 *
433 * We can do this with the following EU instruction:
434 *
435 * mul(2) dst.3<1>UD src0<8;2,4>UD src1<...>UW { Align1 WE_all }
436 */
437 brw_push_insn_state(p);
438 brw_set_default_access_mode(p, BRW_ALIGN_1);
439 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
440 assert(p->devinfo->ver >= 7 &&
441 src1.file == BRW_IMMEDIATE_VALUE &&
442 src1.type == BRW_REGISTER_TYPE_UD &&
443 src1.ud <= USHRT_MAX);
444 if (src0.file == BRW_IMMEDIATE_VALUE) {
445 brw_MOV(p, suboffset(stride(dst, 2, 2, 1), 3),
446 brw_imm_ud(src0.ud * src1.ud));
447 } else {
448 if (src1.file == BRW_IMMEDIATE_VALUE) {
449 src1 = brw_imm_uw(src1.ud);
450 }
451 brw_MUL(p, suboffset(stride(dst, 2, 2, 1), 3), stride(src0, 8, 2, 4),
452 retype(src1, BRW_REGISTER_TYPE_UW));
453 }
454 brw_pop_insn_state(p);
455 }
456
457 static void
generate_gs_set_vertex_count(struct brw_codegen * p,struct brw_reg dst,struct brw_reg src)458 generate_gs_set_vertex_count(struct brw_codegen *p,
459 struct brw_reg dst,
460 struct brw_reg src)
461 {
462 brw_push_insn_state(p);
463 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
464
465 /* If we think of the src and dst registers as composed of 8 DWORDs each,
466 * we want to pick up the contents of DWORDs 0 and 4 from src, truncate
467 * them to WORDs, and then pack them into DWORD 2 of dst.
468 *
469 * It's easier to get the EU to do this if we think of the src and dst
470 * registers as composed of 16 WORDS each; then, we want to pick up the
471 * contents of WORDs 0 and 8 from src, and pack them into WORDs 4 and 5
472 * of dst.
473 *
474 * We can do that by the following EU instruction:
475 *
476 * mov (2) dst.4<1>:uw src<8;1,0>:uw { Align1, Q1, NoMask }
477 */
478 brw_set_default_access_mode(p, BRW_ALIGN_1);
479 brw_MOV(p,
480 suboffset(stride(retype(dst, BRW_REGISTER_TYPE_UW), 2, 2, 1), 4),
481 stride(retype(src, BRW_REGISTER_TYPE_UW), 8, 1, 0));
482
483 brw_pop_insn_state(p);
484 }
485
486 static void
generate_gs_svb_write(struct brw_codegen * p,vec4_instruction * inst,struct brw_reg dst,struct brw_reg src0,struct brw_reg src1)487 generate_gs_svb_write(struct brw_codegen *p,
488 vec4_instruction *inst,
489 struct brw_reg dst,
490 struct brw_reg src0,
491 struct brw_reg src1)
492 {
493 int binding = inst->sol_binding;
494 bool final_write = inst->sol_final_write;
495
496 brw_push_insn_state(p);
497 brw_set_default_exec_size(p, BRW_EXECUTE_4);
498 /* Copy Vertex data into M0.x */
499 brw_MOV(p, stride(dst, 4, 4, 1),
500 stride(retype(src0, BRW_REGISTER_TYPE_UD), 4, 4, 1));
501 brw_pop_insn_state(p);
502
503 brw_push_insn_state(p);
504 /* Send SVB Write */
505 brw_svb_write(p,
506 final_write ? src1 : brw_null_reg(), /* dest == src1 */
507 1, /* msg_reg_nr */
508 dst, /* src0 == previous dst */
509 BRW_GFX6_SOL_BINDING_START + binding, /* binding_table_index */
510 final_write); /* send_commit_msg */
511
512 /* Finally, wait for the write commit to occur so that we can proceed to
513 * other things safely.
514 *
515 * From the Sandybridge PRM, Volume 4, Part 1, Section 3.3:
516 *
517 * The write commit does not modify the destination register, but
518 * merely clears the dependency associated with the destination
519 * register. Thus, a simple “mov” instruction using the register as a
520 * source is sufficient to wait for the write commit to occur.
521 */
522 if (final_write) {
523 brw_MOV(p, src1, src1);
524 }
525 brw_pop_insn_state(p);
526 }
527
528 static void
generate_gs_svb_set_destination_index(struct brw_codegen * p,vec4_instruction * inst,struct brw_reg dst,struct brw_reg src)529 generate_gs_svb_set_destination_index(struct brw_codegen *p,
530 vec4_instruction *inst,
531 struct brw_reg dst,
532 struct brw_reg src)
533 {
534 int vertex = inst->sol_vertex;
535 brw_push_insn_state(p);
536 brw_set_default_access_mode(p, BRW_ALIGN_1);
537 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
538 brw_MOV(p, get_element_ud(dst, 5), get_element_ud(src, vertex));
539 brw_pop_insn_state(p);
540 }
541
542 static void
generate_gs_set_dword_2(struct brw_codegen * p,struct brw_reg dst,struct brw_reg src)543 generate_gs_set_dword_2(struct brw_codegen *p,
544 struct brw_reg dst,
545 struct brw_reg src)
546 {
547 brw_push_insn_state(p);
548 brw_set_default_access_mode(p, BRW_ALIGN_1);
549 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
550 brw_MOV(p, suboffset(vec1(dst), 2), suboffset(vec1(src), 0));
551 brw_pop_insn_state(p);
552 }
553
554 static void
generate_gs_prepare_channel_masks(struct brw_codegen * p,struct brw_reg dst)555 generate_gs_prepare_channel_masks(struct brw_codegen *p,
556 struct brw_reg dst)
557 {
558 /* We want to left shift just DWORD 4 (the x component belonging to the
559 * second geometry shader invocation) by 4 bits. So generate the
560 * instruction:
561 *
562 * shl(1) dst.4<1>UD dst.4<0,1,0>UD 4UD { align1 WE_all }
563 */
564 dst = suboffset(vec1(dst), 4);
565 brw_push_insn_state(p);
566 brw_set_default_access_mode(p, BRW_ALIGN_1);
567 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
568 brw_SHL(p, dst, dst, brw_imm_ud(4));
569 brw_pop_insn_state(p);
570 }
571
572 static void
generate_gs_set_channel_masks(struct brw_codegen * p,struct brw_reg dst,struct brw_reg src)573 generate_gs_set_channel_masks(struct brw_codegen *p,
574 struct brw_reg dst,
575 struct brw_reg src)
576 {
577 /* From p21 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
578 * Header: M0.5):
579 *
580 * 15 Vertex 1 DATA [3] / Vertex 0 DATA[7] Channel Mask
581 *
582 * When Swizzle Control = URB_INTERLEAVED this bit controls Vertex 1
583 * DATA[3], when Swizzle Control = URB_NOSWIZZLE this bit controls
584 * Vertex 0 DATA[7]. This bit is ANDed with the corresponding
585 * channel enable to determine the final channel enable. For the
586 * URB_READ_OWORD & URB_READ_HWORD messages, when final channel
587 * enable is 1 it indicates that Vertex 1 DATA [3] will be included
588 * in the writeback message. For the URB_WRITE_OWORD &
589 * URB_WRITE_HWORD messages, when final channel enable is 1 it
590 * indicates that Vertex 1 DATA [3] will be written to the surface.
591 *
592 * 0: Vertex 1 DATA [3] / Vertex 0 DATA[7] channel not included
593 * 1: Vertex DATA [3] / Vertex 0 DATA[7] channel included
594 *
595 * 14 Vertex 1 DATA [2] Channel Mask
596 * 13 Vertex 1 DATA [1] Channel Mask
597 * 12 Vertex 1 DATA [0] Channel Mask
598 * 11 Vertex 0 DATA [3] Channel Mask
599 * 10 Vertex 0 DATA [2] Channel Mask
600 * 9 Vertex 0 DATA [1] Channel Mask
601 * 8 Vertex 0 DATA [0] Channel Mask
602 *
603 * (This is from a section of the PRM that is agnostic to the particular
604 * type of shader being executed, so "Vertex 0" and "Vertex 1" refer to
605 * geometry shader invocations 0 and 1, respectively). Since we have the
606 * enable flags for geometry shader invocation 0 in bits 3:0 of DWORD 0,
607 * and the enable flags for geometry shader invocation 1 in bits 7:0 of
608 * DWORD 4, we just need to OR them together and store the result in bits
609 * 15:8 of DWORD 5.
610 *
611 * It's easier to get the EU to do this if we think of the src and dst
612 * registers as composed of 32 bytes each; then, we want to pick up the
613 * contents of bytes 0 and 16 from src, OR them together, and store them in
614 * byte 21.
615 *
616 * We can do that by the following EU instruction:
617 *
618 * or(1) dst.21<1>UB src<0,1,0>UB src.16<0,1,0>UB { align1 WE_all }
619 *
620 * Note: this relies on the source register having zeros in (a) bits 7:4 of
621 * DWORD 0 and (b) bits 3:0 of DWORD 4. We can rely on (b) because the
622 * source register was prepared by GS_OPCODE_PREPARE_CHANNEL_MASKS (which
623 * shifts DWORD 4 left by 4 bits), and we can rely on (a) because prior to
624 * the execution of GS_OPCODE_PREPARE_CHANNEL_MASKS, DWORDs 0 and 4 need to
625 * contain valid channel mask values (which are in the range 0x0-0xf).
626 */
627 dst = retype(dst, BRW_REGISTER_TYPE_UB);
628 src = retype(src, BRW_REGISTER_TYPE_UB);
629 brw_push_insn_state(p);
630 brw_set_default_access_mode(p, BRW_ALIGN_1);
631 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
632 brw_OR(p, suboffset(vec1(dst), 21), vec1(src), suboffset(vec1(src), 16));
633 brw_pop_insn_state(p);
634 }
635
636 static void
generate_gs_get_instance_id(struct brw_codegen * p,struct brw_reg dst)637 generate_gs_get_instance_id(struct brw_codegen *p,
638 struct brw_reg dst)
639 {
640 /* We want to right shift R0.0 & R0.1 by GFX7_GS_PAYLOAD_INSTANCE_ID_SHIFT
641 * and store into dst.0 & dst.4. So generate the instruction:
642 *
643 * shr(8) dst<1> R0<1,4,0> GFX7_GS_PAYLOAD_INSTANCE_ID_SHIFT { align1 WE_normal 1Q }
644 */
645 brw_push_insn_state(p);
646 brw_set_default_access_mode(p, BRW_ALIGN_1);
647 dst = retype(dst, BRW_REGISTER_TYPE_UD);
648 struct brw_reg r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
649 brw_SHR(p, dst, stride(r0, 1, 4, 0),
650 brw_imm_ud(GFX7_GS_PAYLOAD_INSTANCE_ID_SHIFT));
651 brw_pop_insn_state(p);
652 }
653
654 static void
generate_gs_ff_sync_set_primitives(struct brw_codegen * p,struct brw_reg dst,struct brw_reg src0,struct brw_reg src1,struct brw_reg src2)655 generate_gs_ff_sync_set_primitives(struct brw_codegen *p,
656 struct brw_reg dst,
657 struct brw_reg src0,
658 struct brw_reg src1,
659 struct brw_reg src2)
660 {
661 brw_push_insn_state(p);
662 brw_set_default_access_mode(p, BRW_ALIGN_1);
663 /* Save src0 data in 16:31 bits of dst.0 */
664 brw_AND(p, suboffset(vec1(dst), 0), suboffset(vec1(src0), 0),
665 brw_imm_ud(0xffffu));
666 brw_SHL(p, suboffset(vec1(dst), 0), suboffset(vec1(dst), 0), brw_imm_ud(16));
667 /* Save src1 data in 0:15 bits of dst.0 */
668 brw_AND(p, suboffset(vec1(src2), 0), suboffset(vec1(src1), 0),
669 brw_imm_ud(0xffffu));
670 brw_OR(p, suboffset(vec1(dst), 0),
671 suboffset(vec1(dst), 0),
672 suboffset(vec1(src2), 0));
673 brw_pop_insn_state(p);
674 }
675
676 static void
generate_gs_ff_sync(struct brw_codegen * p,vec4_instruction * inst,struct brw_reg dst,struct brw_reg src0,struct brw_reg src1)677 generate_gs_ff_sync(struct brw_codegen *p,
678 vec4_instruction *inst,
679 struct brw_reg dst,
680 struct brw_reg src0,
681 struct brw_reg src1)
682 {
683 /* This opcode uses an implied MRF register for:
684 * - the header of the ff_sync message. And as such it is expected to be
685 * initialized to r0 before calling here.
686 * - the destination where we will write the allocated URB handle.
687 */
688 struct brw_reg header =
689 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD);
690
691 /* Overwrite dword 0 of the header (SO vertices to write) and
692 * dword 1 (number of primitives written).
693 */
694 brw_push_insn_state(p);
695 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
696 brw_set_default_access_mode(p, BRW_ALIGN_1);
697 brw_MOV(p, get_element_ud(header, 0), get_element_ud(src1, 0));
698 brw_MOV(p, get_element_ud(header, 1), get_element_ud(src0, 0));
699 brw_pop_insn_state(p);
700
701 /* Allocate URB handle in dst */
702 brw_ff_sync(p,
703 dst,
704 0,
705 header,
706 1, /* allocate */
707 1, /* response length */
708 0 /* eot */);
709
710 /* Now put allocated urb handle in header.0 */
711 brw_push_insn_state(p);
712 brw_set_default_access_mode(p, BRW_ALIGN_1);
713 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
714 brw_MOV(p, get_element_ud(header, 0), get_element_ud(dst, 0));
715
716 /* src1 is not an immediate when we use transform feedback */
717 if (src1.file != BRW_IMMEDIATE_VALUE) {
718 brw_set_default_exec_size(p, BRW_EXECUTE_4);
719 brw_MOV(p, brw_vec4_grf(src1.nr, 0), brw_vec4_grf(dst.nr, 1));
720 }
721
722 brw_pop_insn_state(p);
723 }
724
725 static void
generate_gs_set_primitive_id(struct brw_codegen * p,struct brw_reg dst)726 generate_gs_set_primitive_id(struct brw_codegen *p, struct brw_reg dst)
727 {
728 /* In gfx6, PrimitiveID is delivered in R0.1 of the payload */
729 struct brw_reg src = brw_vec8_grf(0, 0);
730 brw_push_insn_state(p);
731 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
732 brw_set_default_access_mode(p, BRW_ALIGN_1);
733 brw_MOV(p, get_element_ud(dst, 0), get_element_ud(src, 1));
734 brw_pop_insn_state(p);
735 }
736
737 static void
generate_tcs_get_instance_id(struct brw_codegen * p,struct brw_reg dst)738 generate_tcs_get_instance_id(struct brw_codegen *p, struct brw_reg dst)
739 {
740 const struct intel_device_info *devinfo = p->devinfo;
741 const bool ivb = devinfo->is_ivybridge || devinfo->is_baytrail;
742
743 /* "Instance Count" comes as part of the payload in r0.2 bits 23:17.
744 *
745 * Since we operate in SIMD4x2 mode, we need run half as many threads
746 * as necessary. So we assign (2i + 1, 2i) as the thread counts. We
747 * shift right by one less to accomplish the multiplication by two.
748 */
749 dst = retype(dst, BRW_REGISTER_TYPE_UD);
750 struct brw_reg r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
751
752 brw_push_insn_state(p);
753 brw_set_default_access_mode(p, BRW_ALIGN_1);
754
755 const int mask = ivb ? INTEL_MASK(22, 16) : INTEL_MASK(23, 17);
756 const int shift = ivb ? 16 : 17;
757
758 brw_AND(p, get_element_ud(dst, 0), get_element_ud(r0, 2), brw_imm_ud(mask));
759 brw_SHR(p, get_element_ud(dst, 0), get_element_ud(dst, 0),
760 brw_imm_ud(shift - 1));
761 brw_ADD(p, get_element_ud(dst, 4), get_element_ud(dst, 0), brw_imm_ud(1));
762
763 brw_pop_insn_state(p);
764 }
765
766 static void
generate_tcs_urb_write(struct brw_codegen * p,vec4_instruction * inst,struct brw_reg urb_header)767 generate_tcs_urb_write(struct brw_codegen *p,
768 vec4_instruction *inst,
769 struct brw_reg urb_header)
770 {
771 const struct intel_device_info *devinfo = p->devinfo;
772
773 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
774 brw_set_dest(p, send, brw_null_reg());
775 brw_set_src0(p, send, urb_header);
776 brw_set_desc(p, send, brw_message_desc(devinfo, inst->mlen, 0, true));
777
778 brw_inst_set_sfid(devinfo, send, BRW_SFID_URB);
779 brw_inst_set_urb_opcode(devinfo, send, BRW_URB_OPCODE_WRITE_OWORD);
780 brw_inst_set_urb_global_offset(devinfo, send, inst->offset);
781 if (inst->urb_write_flags & BRW_URB_WRITE_EOT) {
782 brw_inst_set_eot(devinfo, send, 1);
783 } else {
784 brw_inst_set_urb_per_slot_offset(devinfo, send, 1);
785 brw_inst_set_urb_swizzle_control(devinfo, send, BRW_URB_SWIZZLE_INTERLEAVE);
786 }
787
788 /* what happens to swizzles? */
789 }
790
791
792 static void
generate_tcs_input_urb_offsets(struct brw_codegen * p,struct brw_reg dst,struct brw_reg vertex,struct brw_reg offset)793 generate_tcs_input_urb_offsets(struct brw_codegen *p,
794 struct brw_reg dst,
795 struct brw_reg vertex,
796 struct brw_reg offset)
797 {
798 /* Generates an URB read/write message header for HS/DS operation.
799 * Inputs are a vertex index, and a byte offset from the beginning of
800 * the vertex. */
801
802 /* If `vertex` is not an immediate, we clobber a0.0 */
803
804 assert(vertex.file == BRW_IMMEDIATE_VALUE || vertex.file == BRW_GENERAL_REGISTER_FILE);
805 assert(vertex.type == BRW_REGISTER_TYPE_UD || vertex.type == BRW_REGISTER_TYPE_D);
806
807 assert(dst.file == BRW_GENERAL_REGISTER_FILE);
808
809 brw_push_insn_state(p);
810 brw_set_default_access_mode(p, BRW_ALIGN_1);
811 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
812 brw_MOV(p, dst, brw_imm_ud(0));
813
814 /* m0.5 bits 8-15 are channel enables */
815 brw_MOV(p, get_element_ud(dst, 5), brw_imm_ud(0xff00));
816
817 /* m0.0-0.1: URB handles */
818 if (vertex.file == BRW_IMMEDIATE_VALUE) {
819 uint32_t vertex_index = vertex.ud;
820 struct brw_reg index_reg = brw_vec1_grf(
821 1 + (vertex_index >> 3), vertex_index & 7);
822
823 brw_MOV(p, vec2(get_element_ud(dst, 0)),
824 retype(index_reg, BRW_REGISTER_TYPE_UD));
825 } else {
826 /* Use indirect addressing. ICP Handles are DWords (single channels
827 * of a register) and start at g1.0.
828 *
829 * In order to start our region at g1.0, we add 8 to the vertex index,
830 * effectively skipping over the 8 channels in g0.0. This gives us a
831 * DWord offset to the ICP Handle.
832 *
833 * Indirect addressing works in terms of bytes, so we then multiply
834 * the DWord offset by 4 (by shifting left by 2).
835 */
836 struct brw_reg addr = brw_address_reg(0);
837
838 /* bottom half: m0.0 = g[1.0 + vertex.0]UD */
839 brw_ADD(p, addr, retype(get_element_ud(vertex, 0), BRW_REGISTER_TYPE_UW),
840 brw_imm_uw(0x8));
841 brw_SHL(p, addr, addr, brw_imm_uw(2));
842 brw_MOV(p, get_element_ud(dst, 0), deref_1ud(brw_indirect(0, 0), 0));
843
844 /* top half: m0.1 = g[1.0 + vertex.4]UD */
845 brw_ADD(p, addr, retype(get_element_ud(vertex, 4), BRW_REGISTER_TYPE_UW),
846 brw_imm_uw(0x8));
847 brw_SHL(p, addr, addr, brw_imm_uw(2));
848 brw_MOV(p, get_element_ud(dst, 1), deref_1ud(brw_indirect(0, 0), 0));
849 }
850
851 /* m0.3-0.4: 128bit-granular offsets into the URB from the handles */
852 if (offset.file != ARF)
853 brw_MOV(p, vec2(get_element_ud(dst, 3)), stride(offset, 4, 1, 0));
854
855 brw_pop_insn_state(p);
856 }
857
858
859 static void
generate_tcs_output_urb_offsets(struct brw_codegen * p,struct brw_reg dst,struct brw_reg write_mask,struct brw_reg offset)860 generate_tcs_output_urb_offsets(struct brw_codegen *p,
861 struct brw_reg dst,
862 struct brw_reg write_mask,
863 struct brw_reg offset)
864 {
865 /* Generates an URB read/write message header for HS/DS operation, for the patch URB entry. */
866 assert(dst.file == BRW_GENERAL_REGISTER_FILE || dst.file == BRW_MESSAGE_REGISTER_FILE);
867
868 assert(write_mask.file == BRW_IMMEDIATE_VALUE);
869 assert(write_mask.type == BRW_REGISTER_TYPE_UD);
870
871 brw_push_insn_state(p);
872
873 brw_set_default_access_mode(p, BRW_ALIGN_1);
874 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
875 brw_MOV(p, dst, brw_imm_ud(0));
876
877 unsigned mask = write_mask.ud;
878
879 /* m0.5 bits 15:12 and 11:8 are channel enables */
880 brw_MOV(p, get_element_ud(dst, 5), brw_imm_ud((mask << 8) | (mask << 12)));
881
882 /* HS patch URB handle is delivered in r0.0 */
883 struct brw_reg urb_handle = brw_vec1_grf(0, 0);
884
885 /* m0.0-0.1: URB handles */
886 brw_MOV(p, vec2(get_element_ud(dst, 0)),
887 retype(urb_handle, BRW_REGISTER_TYPE_UD));
888
889 /* m0.3-0.4: 128bit-granular offsets into the URB from the handles */
890 if (offset.file != ARF)
891 brw_MOV(p, vec2(get_element_ud(dst, 3)), stride(offset, 4, 1, 0));
892
893 brw_pop_insn_state(p);
894 }
895
896 static void
generate_tes_create_input_read_header(struct brw_codegen * p,struct brw_reg dst)897 generate_tes_create_input_read_header(struct brw_codegen *p,
898 struct brw_reg dst)
899 {
900 brw_push_insn_state(p);
901 brw_set_default_access_mode(p, BRW_ALIGN_1);
902 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
903
904 /* Initialize the register to 0 */
905 brw_MOV(p, dst, brw_imm_ud(0));
906
907 /* Enable all the channels in m0.5 bits 15:8 */
908 brw_MOV(p, get_element_ud(dst, 5), brw_imm_ud(0xff00));
909
910 /* Copy g1.3 (the patch URB handle) to m0.0 and m0.1. For safety,
911 * mask out irrelevant "Reserved" bits, as they're not marked MBZ.
912 */
913 brw_AND(p, vec2(get_element_ud(dst, 0)),
914 retype(brw_vec1_grf(1, 3), BRW_REGISTER_TYPE_UD),
915 brw_imm_ud(0x1fff));
916 brw_pop_insn_state(p);
917 }
918
919 static void
generate_tes_add_indirect_urb_offset(struct brw_codegen * p,struct brw_reg dst,struct brw_reg header,struct brw_reg offset)920 generate_tes_add_indirect_urb_offset(struct brw_codegen *p,
921 struct brw_reg dst,
922 struct brw_reg header,
923 struct brw_reg offset)
924 {
925 brw_push_insn_state(p);
926 brw_set_default_access_mode(p, BRW_ALIGN_1);
927 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
928
929 brw_MOV(p, dst, header);
930
931 /* Uniforms will have a stride <0;4,1>, and we need to convert to <0;1,0>.
932 * Other values get <4;1,0>.
933 */
934 struct brw_reg restrided_offset;
935 if (offset.vstride == BRW_VERTICAL_STRIDE_0 &&
936 offset.width == BRW_WIDTH_4 &&
937 offset.hstride == BRW_HORIZONTAL_STRIDE_1) {
938 restrided_offset = stride(offset, 0, 1, 0);
939 } else {
940 restrided_offset = stride(offset, 4, 1, 0);
941 }
942
943 /* m0.3-0.4: 128-bit-granular offsets into the URB from the handles */
944 brw_MOV(p, vec2(get_element_ud(dst, 3)), restrided_offset);
945
946 brw_pop_insn_state(p);
947 }
948
949 static void
generate_vec4_urb_read(struct brw_codegen * p,vec4_instruction * inst,struct brw_reg dst,struct brw_reg header)950 generate_vec4_urb_read(struct brw_codegen *p,
951 vec4_instruction *inst,
952 struct brw_reg dst,
953 struct brw_reg header)
954 {
955 const struct intel_device_info *devinfo = p->devinfo;
956
957 assert(header.file == BRW_GENERAL_REGISTER_FILE);
958 assert(header.type == BRW_REGISTER_TYPE_UD);
959
960 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
961 brw_set_dest(p, send, dst);
962 brw_set_src0(p, send, header);
963
964 brw_set_desc(p, send, brw_message_desc(devinfo, 1, 1, true));
965
966 brw_inst_set_sfid(devinfo, send, BRW_SFID_URB);
967 brw_inst_set_urb_opcode(devinfo, send, BRW_URB_OPCODE_READ_OWORD);
968 brw_inst_set_urb_swizzle_control(devinfo, send, BRW_URB_SWIZZLE_INTERLEAVE);
969 brw_inst_set_urb_per_slot_offset(devinfo, send, 1);
970
971 brw_inst_set_urb_global_offset(devinfo, send, inst->offset);
972 }
973
974 static void
generate_tcs_release_input(struct brw_codegen * p,struct brw_reg header,struct brw_reg vertex,struct brw_reg is_unpaired)975 generate_tcs_release_input(struct brw_codegen *p,
976 struct brw_reg header,
977 struct brw_reg vertex,
978 struct brw_reg is_unpaired)
979 {
980 const struct intel_device_info *devinfo = p->devinfo;
981
982 assert(vertex.file == BRW_IMMEDIATE_VALUE);
983 assert(vertex.type == BRW_REGISTER_TYPE_UD);
984
985 /* m0.0-0.1: URB handles */
986 struct brw_reg urb_handles =
987 retype(brw_vec2_grf(1 + (vertex.ud >> 3), vertex.ud & 7),
988 BRW_REGISTER_TYPE_UD);
989
990 brw_push_insn_state(p);
991 brw_set_default_access_mode(p, BRW_ALIGN_1);
992 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
993 brw_MOV(p, header, brw_imm_ud(0));
994 brw_MOV(p, vec2(get_element_ud(header, 0)), urb_handles);
995 brw_pop_insn_state(p);
996
997 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
998 brw_set_dest(p, send, brw_null_reg());
999 brw_set_src0(p, send, header);
1000 brw_set_desc(p, send, brw_message_desc(devinfo, 1, 0, true));
1001
1002 brw_inst_set_sfid(devinfo, send, BRW_SFID_URB);
1003 brw_inst_set_urb_opcode(devinfo, send, BRW_URB_OPCODE_READ_OWORD);
1004 brw_inst_set_urb_complete(devinfo, send, 1);
1005 brw_inst_set_urb_swizzle_control(devinfo, send, is_unpaired.ud ?
1006 BRW_URB_SWIZZLE_NONE :
1007 BRW_URB_SWIZZLE_INTERLEAVE);
1008 }
1009
1010 static void
generate_tcs_thread_end(struct brw_codegen * p,vec4_instruction * inst)1011 generate_tcs_thread_end(struct brw_codegen *p, vec4_instruction *inst)
1012 {
1013 struct brw_reg header = brw_message_reg(inst->base_mrf);
1014
1015 brw_push_insn_state(p);
1016 brw_set_default_access_mode(p, BRW_ALIGN_1);
1017 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1018 brw_MOV(p, header, brw_imm_ud(0));
1019 brw_MOV(p, get_element_ud(header, 5), brw_imm_ud(WRITEMASK_X << 8));
1020 brw_MOV(p, get_element_ud(header, 0),
1021 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD));
1022 brw_MOV(p, brw_message_reg(inst->base_mrf + 1), brw_imm_ud(0u));
1023 brw_pop_insn_state(p);
1024
1025 brw_urb_WRITE(p,
1026 brw_null_reg(), /* dest */
1027 inst->base_mrf, /* starting mrf reg nr */
1028 header,
1029 BRW_URB_WRITE_EOT | BRW_URB_WRITE_OWORD |
1030 BRW_URB_WRITE_USE_CHANNEL_MASKS,
1031 inst->mlen,
1032 0, /* response len */
1033 0, /* urb destination offset */
1034 0);
1035 }
1036
1037 static void
generate_tes_get_primitive_id(struct brw_codegen * p,struct brw_reg dst)1038 generate_tes_get_primitive_id(struct brw_codegen *p, struct brw_reg dst)
1039 {
1040 brw_push_insn_state(p);
1041 brw_set_default_access_mode(p, BRW_ALIGN_1);
1042 brw_MOV(p, dst, retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_D));
1043 brw_pop_insn_state(p);
1044 }
1045
1046 static void
generate_tcs_get_primitive_id(struct brw_codegen * p,struct brw_reg dst)1047 generate_tcs_get_primitive_id(struct brw_codegen *p, struct brw_reg dst)
1048 {
1049 brw_push_insn_state(p);
1050 brw_set_default_access_mode(p, BRW_ALIGN_1);
1051 brw_MOV(p, dst, retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD));
1052 brw_pop_insn_state(p);
1053 }
1054
1055 static void
generate_tcs_create_barrier_header(struct brw_codegen * p,struct brw_vue_prog_data * prog_data,struct brw_reg dst)1056 generate_tcs_create_barrier_header(struct brw_codegen *p,
1057 struct brw_vue_prog_data *prog_data,
1058 struct brw_reg dst)
1059 {
1060 const struct intel_device_info *devinfo = p->devinfo;
1061 const bool ivb = devinfo->is_ivybridge || devinfo->is_baytrail;
1062 struct brw_reg m0_2 = get_element_ud(dst, 2);
1063 unsigned instances = ((struct brw_tcs_prog_data *) prog_data)->instances;
1064
1065 brw_push_insn_state(p);
1066 brw_set_default_access_mode(p, BRW_ALIGN_1);
1067 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1068
1069 /* Zero the message header */
1070 brw_MOV(p, retype(dst, BRW_REGISTER_TYPE_UD), brw_imm_ud(0u));
1071
1072 /* Copy "Barrier ID" from r0.2, bits 16:13 (Gfx7.5+) or 15:12 (Gfx7) */
1073 brw_AND(p, m0_2,
1074 retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD),
1075 brw_imm_ud(ivb ? INTEL_MASK(15, 12) : INTEL_MASK(16, 13)));
1076
1077 /* Shift it up to bits 27:24. */
1078 brw_SHL(p, m0_2, get_element_ud(dst, 2), brw_imm_ud(ivb ? 12 : 11));
1079
1080 /* Set the Barrier Count and the enable bit */
1081 brw_OR(p, m0_2, m0_2, brw_imm_ud(instances << 9 | (1 << 15)));
1082
1083 brw_pop_insn_state(p);
1084 }
1085
1086 static void
generate_oword_dual_block_offsets(struct brw_codegen * p,struct brw_reg m1,struct brw_reg index)1087 generate_oword_dual_block_offsets(struct brw_codegen *p,
1088 struct brw_reg m1,
1089 struct brw_reg index)
1090 {
1091 int second_vertex_offset;
1092
1093 if (p->devinfo->ver >= 6)
1094 second_vertex_offset = 1;
1095 else
1096 second_vertex_offset = 16;
1097
1098 m1 = retype(m1, BRW_REGISTER_TYPE_D);
1099
1100 /* Set up M1 (message payload). Only the block offsets in M1.0 and
1101 * M1.4 are used, and the rest are ignored.
1102 */
1103 struct brw_reg m1_0 = suboffset(vec1(m1), 0);
1104 struct brw_reg m1_4 = suboffset(vec1(m1), 4);
1105 struct brw_reg index_0 = suboffset(vec1(index), 0);
1106 struct brw_reg index_4 = suboffset(vec1(index), 4);
1107
1108 brw_push_insn_state(p);
1109 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1110 brw_set_default_access_mode(p, BRW_ALIGN_1);
1111
1112 brw_MOV(p, m1_0, index_0);
1113
1114 if (index.file == BRW_IMMEDIATE_VALUE) {
1115 index_4.ud += second_vertex_offset;
1116 brw_MOV(p, m1_4, index_4);
1117 } else {
1118 brw_ADD(p, m1_4, index_4, brw_imm_d(second_vertex_offset));
1119 }
1120
1121 brw_pop_insn_state(p);
1122 }
1123
1124 static void
generate_unpack_flags(struct brw_codegen * p,struct brw_reg dst)1125 generate_unpack_flags(struct brw_codegen *p,
1126 struct brw_reg dst)
1127 {
1128 brw_push_insn_state(p);
1129 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1130 brw_set_default_access_mode(p, BRW_ALIGN_1);
1131
1132 struct brw_reg flags = brw_flag_reg(0, 0);
1133 struct brw_reg dst_0 = suboffset(vec1(dst), 0);
1134 struct brw_reg dst_4 = suboffset(vec1(dst), 4);
1135
1136 brw_AND(p, dst_0, flags, brw_imm_ud(0x0f));
1137 brw_AND(p, dst_4, flags, brw_imm_ud(0xf0));
1138 brw_SHR(p, dst_4, dst_4, brw_imm_ud(4));
1139
1140 brw_pop_insn_state(p);
1141 }
1142
1143 static void
generate_scratch_read(struct brw_codegen * p,vec4_instruction * inst,struct brw_reg dst,struct brw_reg index)1144 generate_scratch_read(struct brw_codegen *p,
1145 vec4_instruction *inst,
1146 struct brw_reg dst,
1147 struct brw_reg index)
1148 {
1149 const struct intel_device_info *devinfo = p->devinfo;
1150 struct brw_reg header = brw_vec8_grf(0, 0);
1151
1152 gfx6_resolve_implied_move(p, &header, inst->base_mrf);
1153
1154 generate_oword_dual_block_offsets(p, brw_message_reg(inst->base_mrf + 1),
1155 index);
1156
1157 uint32_t msg_type;
1158
1159 if (devinfo->ver >= 6)
1160 msg_type = GFX6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1161 else if (devinfo->ver == 5 || devinfo->is_g4x)
1162 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1163 else
1164 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1165
1166 const unsigned target_cache =
1167 devinfo->ver >= 7 ? GFX7_SFID_DATAPORT_DATA_CACHE :
1168 devinfo->ver >= 6 ? GFX6_SFID_DATAPORT_RENDER_CACHE :
1169 BRW_SFID_DATAPORT_READ;
1170
1171 /* Each of the 8 channel enables is considered for whether each
1172 * dword is written.
1173 */
1174 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1175 brw_inst_set_sfid(devinfo, send, target_cache);
1176 brw_set_dest(p, send, dst);
1177 brw_set_src0(p, send, header);
1178 if (devinfo->ver < 6)
1179 brw_inst_set_cond_modifier(devinfo, send, inst->base_mrf);
1180 brw_set_desc(p, send,
1181 brw_message_desc(devinfo, 2, 1, true) |
1182 brw_dp_read_desc(devinfo,
1183 brw_scratch_surface_idx(p),
1184 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
1185 msg_type, BRW_DATAPORT_READ_TARGET_RENDER_CACHE));
1186 }
1187
1188 static void
generate_scratch_write(struct brw_codegen * p,vec4_instruction * inst,struct brw_reg dst,struct brw_reg src,struct brw_reg index)1189 generate_scratch_write(struct brw_codegen *p,
1190 vec4_instruction *inst,
1191 struct brw_reg dst,
1192 struct brw_reg src,
1193 struct brw_reg index)
1194 {
1195 const struct intel_device_info *devinfo = p->devinfo;
1196 const unsigned target_cache =
1197 (devinfo->ver >= 7 ? GFX7_SFID_DATAPORT_DATA_CACHE :
1198 devinfo->ver >= 6 ? GFX6_SFID_DATAPORT_RENDER_CACHE :
1199 BRW_SFID_DATAPORT_WRITE);
1200 struct brw_reg header = brw_vec8_grf(0, 0);
1201 bool write_commit;
1202
1203 /* If the instruction is predicated, we'll predicate the send, not
1204 * the header setup.
1205 */
1206 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1207
1208 gfx6_resolve_implied_move(p, &header, inst->base_mrf);
1209
1210 generate_oword_dual_block_offsets(p, brw_message_reg(inst->base_mrf + 1),
1211 index);
1212
1213 brw_MOV(p,
1214 retype(brw_message_reg(inst->base_mrf + 2), BRW_REGISTER_TYPE_D),
1215 retype(src, BRW_REGISTER_TYPE_D));
1216
1217 uint32_t msg_type;
1218
1219 if (devinfo->ver >= 7)
1220 msg_type = GFX7_DATAPORT_DC_OWORD_DUAL_BLOCK_WRITE;
1221 else if (devinfo->ver == 6)
1222 msg_type = GFX6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
1223 else
1224 msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
1225
1226 brw_set_default_predicate_control(p, inst->predicate);
1227
1228 /* Pre-gfx6, we have to specify write commits to ensure ordering
1229 * between reads and writes within a thread. Afterwards, that's
1230 * guaranteed and write commits only matter for inter-thread
1231 * synchronization.
1232 */
1233 if (devinfo->ver >= 6) {
1234 write_commit = false;
1235 } else {
1236 /* The visitor set up our destination register to be g0. This
1237 * means that when the next read comes along, we will end up
1238 * reading from g0 and causing a block on the write commit. For
1239 * write-after-read, we are relying on the value of the previous
1240 * read being used (and thus blocking on completion) before our
1241 * write is executed. This means we have to be careful in
1242 * instruction scheduling to not violate this assumption.
1243 */
1244 write_commit = true;
1245 }
1246
1247 /* Each of the 8 channel enables is considered for whether each
1248 * dword is written.
1249 */
1250 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1251 brw_inst_set_sfid(p->devinfo, send, target_cache);
1252 brw_set_dest(p, send, dst);
1253 brw_set_src0(p, send, header);
1254 if (devinfo->ver < 6)
1255 brw_inst_set_cond_modifier(p->devinfo, send, inst->base_mrf);
1256 brw_set_desc(p, send,
1257 brw_message_desc(devinfo, 3, write_commit, true) |
1258 brw_dp_write_desc(devinfo,
1259 brw_scratch_surface_idx(p),
1260 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
1261 msg_type,
1262 write_commit));
1263 }
1264
1265 static void
generate_pull_constant_load(struct brw_codegen * p,vec4_instruction * inst,struct brw_reg dst,struct brw_reg index,struct brw_reg offset)1266 generate_pull_constant_load(struct brw_codegen *p,
1267 vec4_instruction *inst,
1268 struct brw_reg dst,
1269 struct brw_reg index,
1270 struct brw_reg offset)
1271 {
1272 const struct intel_device_info *devinfo = p->devinfo;
1273 const unsigned target_cache =
1274 (devinfo->ver >= 6 ? GFX6_SFID_DATAPORT_SAMPLER_CACHE :
1275 BRW_SFID_DATAPORT_READ);
1276 assert(index.file == BRW_IMMEDIATE_VALUE &&
1277 index.type == BRW_REGISTER_TYPE_UD);
1278 uint32_t surf_index = index.ud;
1279
1280 struct brw_reg header = brw_vec8_grf(0, 0);
1281
1282 gfx6_resolve_implied_move(p, &header, inst->base_mrf);
1283
1284 if (devinfo->ver >= 6) {
1285 if (offset.file == BRW_IMMEDIATE_VALUE) {
1286 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1),
1287 BRW_REGISTER_TYPE_D),
1288 brw_imm_d(offset.ud >> 4));
1289 } else {
1290 brw_SHR(p, retype(brw_message_reg(inst->base_mrf + 1),
1291 BRW_REGISTER_TYPE_D),
1292 offset, brw_imm_d(4));
1293 }
1294 } else {
1295 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1),
1296 BRW_REGISTER_TYPE_D),
1297 offset);
1298 }
1299
1300 uint32_t msg_type;
1301
1302 if (devinfo->ver >= 6)
1303 msg_type = GFX6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1304 else if (devinfo->ver == 5 || devinfo->is_g4x)
1305 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1306 else
1307 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1308
1309 /* Each of the 8 channel enables is considered for whether each
1310 * dword is written.
1311 */
1312 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1313 brw_inst_set_sfid(devinfo, send, target_cache);
1314 brw_set_dest(p, send, dst);
1315 brw_set_src0(p, send, header);
1316 if (devinfo->ver < 6)
1317 brw_inst_set_cond_modifier(p->devinfo, send, inst->base_mrf);
1318 brw_set_desc(p, send,
1319 brw_message_desc(devinfo, 2, 1, true) |
1320 brw_dp_read_desc(devinfo, surf_index,
1321 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
1322 msg_type,
1323 BRW_DATAPORT_READ_TARGET_DATA_CACHE));
1324 }
1325
1326 static void
generate_get_buffer_size(struct brw_codegen * p,vec4_instruction * inst,struct brw_reg dst,struct brw_reg src,struct brw_reg surf_index)1327 generate_get_buffer_size(struct brw_codegen *p,
1328 vec4_instruction *inst,
1329 struct brw_reg dst,
1330 struct brw_reg src,
1331 struct brw_reg surf_index)
1332 {
1333 assert(p->devinfo->ver >= 7);
1334 assert(surf_index.type == BRW_REGISTER_TYPE_UD &&
1335 surf_index.file == BRW_IMMEDIATE_VALUE);
1336
1337 brw_SAMPLE(p,
1338 dst,
1339 inst->base_mrf,
1340 src,
1341 surf_index.ud,
1342 0,
1343 GFX5_SAMPLER_MESSAGE_SAMPLE_RESINFO,
1344 1, /* response length */
1345 inst->mlen,
1346 inst->header_size > 0,
1347 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1348 BRW_SAMPLER_RETURN_FORMAT_SINT32);
1349 }
1350
1351 static void
generate_pull_constant_load_gfx7(struct brw_codegen * p,vec4_instruction * inst,struct brw_reg dst,struct brw_reg surf_index,struct brw_reg offset)1352 generate_pull_constant_load_gfx7(struct brw_codegen *p,
1353 vec4_instruction *inst,
1354 struct brw_reg dst,
1355 struct brw_reg surf_index,
1356 struct brw_reg offset)
1357 {
1358 const struct intel_device_info *devinfo = p->devinfo;
1359 assert(surf_index.type == BRW_REGISTER_TYPE_UD);
1360
1361 if (surf_index.file == BRW_IMMEDIATE_VALUE) {
1362
1363 brw_inst *insn = brw_next_insn(p, BRW_OPCODE_SEND);
1364 brw_inst_set_sfid(devinfo, insn, BRW_SFID_SAMPLER);
1365 brw_set_dest(p, insn, dst);
1366 brw_set_src0(p, insn, offset);
1367 brw_set_desc(p, insn,
1368 brw_message_desc(devinfo, inst->mlen, 1, inst->header_size) |
1369 brw_sampler_desc(devinfo, surf_index.ud,
1370 0, /* LD message ignores sampler unit */
1371 GFX5_SAMPLER_MESSAGE_SAMPLE_LD,
1372 BRW_SAMPLER_SIMD_MODE_SIMD4X2, 0));
1373 } else {
1374
1375 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1376
1377 brw_push_insn_state(p);
1378 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1379 brw_set_default_access_mode(p, BRW_ALIGN_1);
1380
1381 /* a0.0 = surf_index & 0xff */
1382 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1383 brw_inst_set_exec_size(devinfo, insn_and, BRW_EXECUTE_1);
1384 brw_set_dest(p, insn_and, addr);
1385 brw_set_src0(p, insn_and, vec1(retype(surf_index, BRW_REGISTER_TYPE_UD)));
1386 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1387
1388 brw_pop_insn_state(p);
1389
1390 /* dst = send(offset, a0.0 | <descriptor>) */
1391 brw_send_indirect_message(
1392 p, BRW_SFID_SAMPLER, dst, offset, addr,
1393 brw_message_desc(devinfo, inst->mlen, 1, inst->header_size) |
1394 brw_sampler_desc(devinfo,
1395 0 /* surface */,
1396 0 /* sampler */,
1397 GFX5_SAMPLER_MESSAGE_SAMPLE_LD,
1398 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1399 0),
1400 false /* EOT */);
1401 }
1402 }
1403
1404 static void
generate_mov_indirect(struct brw_codegen * p,vec4_instruction *,struct brw_reg dst,struct brw_reg reg,struct brw_reg indirect)1405 generate_mov_indirect(struct brw_codegen *p,
1406 vec4_instruction *,
1407 struct brw_reg dst, struct brw_reg reg,
1408 struct brw_reg indirect)
1409 {
1410 assert(indirect.type == BRW_REGISTER_TYPE_UD);
1411 assert(p->devinfo->ver >= 6);
1412
1413 unsigned imm_byte_offset = reg.nr * REG_SIZE + reg.subnr * (REG_SIZE / 2);
1414
1415 /* This instruction acts in align1 mode */
1416 assert(dst.writemask == WRITEMASK_XYZW);
1417
1418 if (indirect.file == BRW_IMMEDIATE_VALUE) {
1419 imm_byte_offset += indirect.ud;
1420
1421 reg.nr = imm_byte_offset / REG_SIZE;
1422 reg.subnr = (imm_byte_offset / (REG_SIZE / 2)) % 2;
1423 unsigned shift = (imm_byte_offset / 4) % 4;
1424 reg.swizzle += BRW_SWIZZLE4(shift, shift, shift, shift);
1425
1426 brw_MOV(p, dst, reg);
1427 } else {
1428 brw_push_insn_state(p);
1429 brw_set_default_access_mode(p, BRW_ALIGN_1);
1430 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1431
1432 struct brw_reg addr = vec8(brw_address_reg(0));
1433
1434 /* We need to move the indirect value into the address register. In
1435 * order to make things make some sense, we want to respect at least the
1436 * X component of the swizzle. In order to do that, we need to convert
1437 * the subnr (probably 0) to an align1 subnr and add in the swizzle.
1438 */
1439 assert(brw_is_single_value_swizzle(indirect.swizzle));
1440 indirect.subnr = (indirect.subnr * 4 + BRW_GET_SWZ(indirect.swizzle, 0));
1441
1442 /* We then use a region of <8,4,0>:uw to pick off the first 2 bytes of
1443 * the indirect and splat it out to all four channels of the given half
1444 * of a0.
1445 */
1446 indirect.subnr *= 2;
1447 indirect = stride(retype(indirect, BRW_REGISTER_TYPE_UW), 8, 4, 0);
1448 brw_ADD(p, addr, indirect, brw_imm_uw(imm_byte_offset));
1449
1450 /* Now we need to incorporate the swizzle from the source register */
1451 if (reg.swizzle != BRW_SWIZZLE_XXXX) {
1452 uint32_t uv_swiz = BRW_GET_SWZ(reg.swizzle, 0) << 2 |
1453 BRW_GET_SWZ(reg.swizzle, 1) << 6 |
1454 BRW_GET_SWZ(reg.swizzle, 2) << 10 |
1455 BRW_GET_SWZ(reg.swizzle, 3) << 14;
1456 uv_swiz |= uv_swiz << 16;
1457
1458 brw_ADD(p, addr, addr, brw_imm_uv(uv_swiz));
1459 }
1460
1461 brw_MOV(p, dst, retype(brw_VxH_indirect(0, 0), reg.type));
1462
1463 brw_pop_insn_state(p);
1464 }
1465 }
1466
1467 static void
generate_zero_oob_push_regs(struct brw_codegen * p,struct brw_stage_prog_data * prog_data,struct brw_reg scratch,struct brw_reg bit_mask_in)1468 generate_zero_oob_push_regs(struct brw_codegen *p,
1469 struct brw_stage_prog_data *prog_data,
1470 struct brw_reg scratch,
1471 struct brw_reg bit_mask_in)
1472 {
1473 const uint64_t want_zero = prog_data->zero_push_reg;
1474 assert(want_zero);
1475
1476 assert(bit_mask_in.file == BRW_GENERAL_REGISTER_FILE);
1477 assert(BRW_GET_SWZ(bit_mask_in.swizzle, 1) ==
1478 BRW_GET_SWZ(bit_mask_in.swizzle, 0) + 1);
1479 bit_mask_in.subnr += BRW_GET_SWZ(bit_mask_in.swizzle, 0) * 4;
1480 bit_mask_in.type = BRW_REGISTER_TYPE_W;
1481
1482 /* Scratch should be 3 registers in the GRF */
1483 assert(scratch.file == BRW_GENERAL_REGISTER_FILE);
1484 scratch = vec8(scratch);
1485 struct brw_reg mask_w16 = retype(scratch, BRW_REGISTER_TYPE_W);
1486 struct brw_reg mask_d16 = retype(byte_offset(scratch, REG_SIZE),
1487 BRW_REGISTER_TYPE_D);
1488
1489 brw_push_insn_state(p);
1490 brw_set_default_access_mode(p, BRW_ALIGN_1);
1491 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1492
1493 for (unsigned i = 0; i < 64; i++) {
1494 if (i % 16 == 0 && (want_zero & BITFIELD64_RANGE(i, 16))) {
1495 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1496 brw_SHL(p, suboffset(mask_w16, 8),
1497 vec1(byte_offset(bit_mask_in, i / 8)),
1498 brw_imm_v(0x01234567));
1499 brw_SHL(p, mask_w16, suboffset(mask_w16, 8), brw_imm_w(8));
1500
1501 brw_set_default_exec_size(p, BRW_EXECUTE_16);
1502 brw_ASR(p, mask_d16, mask_w16, brw_imm_w(15));
1503 }
1504
1505 if (want_zero & BITFIELD64_BIT(i)) {
1506 unsigned push_start = prog_data->dispatch_grf_start_reg;
1507 struct brw_reg push_reg =
1508 retype(brw_vec8_grf(push_start + i, 0), BRW_REGISTER_TYPE_D);
1509
1510 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1511 brw_AND(p, push_reg, push_reg, vec1(suboffset(mask_d16, i)));
1512 }
1513 }
1514
1515 brw_pop_insn_state(p);
1516 }
1517
1518 static void
generate_code(struct brw_codegen * p,const struct brw_compiler * compiler,void * log_data,const nir_shader * nir,struct brw_vue_prog_data * prog_data,const struct cfg_t * cfg,const performance & perf,struct brw_compile_stats * stats,bool debug_enabled)1519 generate_code(struct brw_codegen *p,
1520 const struct brw_compiler *compiler,
1521 void *log_data,
1522 const nir_shader *nir,
1523 struct brw_vue_prog_data *prog_data,
1524 const struct cfg_t *cfg,
1525 const performance &perf,
1526 struct brw_compile_stats *stats,
1527 bool debug_enabled)
1528 {
1529 const struct intel_device_info *devinfo = p->devinfo;
1530 const char *stage_abbrev = _mesa_shader_stage_to_abbrev(nir->info.stage);
1531 struct disasm_info *disasm_info = disasm_initialize(devinfo, cfg);
1532
1533 /* `send_count` explicitly does not include spills or fills, as we'd
1534 * like to use it as a metric for intentional memory access or other
1535 * shared function use. Otherwise, subtle changes to scheduling or
1536 * register allocation could cause it to fluctuate wildly - and that
1537 * effect is already counted in spill/fill counts.
1538 */
1539 int spill_count = 0, fill_count = 0;
1540 int loop_count = 0, send_count = 0;
1541
1542 foreach_block_and_inst (block, vec4_instruction, inst, cfg) {
1543 struct brw_reg src[3], dst;
1544
1545 if (unlikely(debug_enabled))
1546 disasm_annotate(disasm_info, inst, p->next_insn_offset);
1547
1548 for (unsigned int i = 0; i < 3; i++) {
1549 src[i] = inst->src[i].as_brw_reg();
1550 }
1551 dst = inst->dst.as_brw_reg();
1552
1553 brw_set_default_predicate_control(p, inst->predicate);
1554 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1555 brw_set_default_flag_reg(p, inst->flag_subreg / 2, inst->flag_subreg % 2);
1556 brw_set_default_saturate(p, inst->saturate);
1557 brw_set_default_mask_control(p, inst->force_writemask_all);
1558 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1559
1560 assert(inst->group % inst->exec_size == 0);
1561 assert(inst->group % 4 == 0);
1562
1563 /* There are some instructions where the destination is 64-bit
1564 * but we retype it to a smaller type. In that case, we cannot
1565 * double the exec_size.
1566 */
1567 const bool is_df = (get_exec_type_size(inst) == 8 ||
1568 inst->dst.type == BRW_REGISTER_TYPE_DF) &&
1569 inst->opcode != VEC4_OPCODE_PICK_LOW_32BIT &&
1570 inst->opcode != VEC4_OPCODE_PICK_HIGH_32BIT &&
1571 inst->opcode != VEC4_OPCODE_SET_LOW_32BIT &&
1572 inst->opcode != VEC4_OPCODE_SET_HIGH_32BIT;
1573
1574 unsigned exec_size = inst->exec_size;
1575 if (devinfo->verx10 == 70 && is_df)
1576 exec_size *= 2;
1577
1578 brw_set_default_exec_size(p, cvt(exec_size) - 1);
1579
1580 if (!inst->force_writemask_all)
1581 brw_set_default_group(p, inst->group);
1582
1583 assert(inst->base_mrf + inst->mlen <= BRW_MAX_MRF(devinfo->ver));
1584 assert(inst->mlen <= BRW_MAX_MSG_LENGTH);
1585
1586 unsigned pre_emit_nr_insn = p->nr_insn;
1587
1588 switch (inst->opcode) {
1589 case VEC4_OPCODE_UNPACK_UNIFORM:
1590 case BRW_OPCODE_MOV:
1591 case VEC4_OPCODE_MOV_FOR_SCRATCH:
1592 brw_MOV(p, dst, src[0]);
1593 break;
1594 case BRW_OPCODE_ADD:
1595 brw_ADD(p, dst, src[0], src[1]);
1596 break;
1597 case BRW_OPCODE_MUL:
1598 brw_MUL(p, dst, src[0], src[1]);
1599 break;
1600 case BRW_OPCODE_MACH:
1601 brw_MACH(p, dst, src[0], src[1]);
1602 break;
1603
1604 case BRW_OPCODE_MAD:
1605 assert(devinfo->ver >= 6);
1606 brw_MAD(p, dst, src[0], src[1], src[2]);
1607 break;
1608
1609 case BRW_OPCODE_FRC:
1610 brw_FRC(p, dst, src[0]);
1611 break;
1612 case BRW_OPCODE_RNDD:
1613 brw_RNDD(p, dst, src[0]);
1614 break;
1615 case BRW_OPCODE_RNDE:
1616 brw_RNDE(p, dst, src[0]);
1617 break;
1618 case BRW_OPCODE_RNDZ:
1619 brw_RNDZ(p, dst, src[0]);
1620 break;
1621
1622 case BRW_OPCODE_AND:
1623 brw_AND(p, dst, src[0], src[1]);
1624 break;
1625 case BRW_OPCODE_OR:
1626 brw_OR(p, dst, src[0], src[1]);
1627 break;
1628 case BRW_OPCODE_XOR:
1629 brw_XOR(p, dst, src[0], src[1]);
1630 break;
1631 case BRW_OPCODE_NOT:
1632 brw_NOT(p, dst, src[0]);
1633 break;
1634 case BRW_OPCODE_ASR:
1635 brw_ASR(p, dst, src[0], src[1]);
1636 break;
1637 case BRW_OPCODE_SHR:
1638 brw_SHR(p, dst, src[0], src[1]);
1639 break;
1640 case BRW_OPCODE_SHL:
1641 brw_SHL(p, dst, src[0], src[1]);
1642 break;
1643
1644 case BRW_OPCODE_CMP:
1645 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1646 break;
1647 case BRW_OPCODE_CMPN:
1648 brw_CMPN(p, dst, inst->conditional_mod, src[0], src[1]);
1649 break;
1650 case BRW_OPCODE_SEL:
1651 brw_SEL(p, dst, src[0], src[1]);
1652 break;
1653
1654 case BRW_OPCODE_DPH:
1655 brw_DPH(p, dst, src[0], src[1]);
1656 break;
1657
1658 case BRW_OPCODE_DP4:
1659 brw_DP4(p, dst, src[0], src[1]);
1660 break;
1661
1662 case BRW_OPCODE_DP3:
1663 brw_DP3(p, dst, src[0], src[1]);
1664 break;
1665
1666 case BRW_OPCODE_DP2:
1667 brw_DP2(p, dst, src[0], src[1]);
1668 break;
1669
1670 case BRW_OPCODE_F32TO16:
1671 assert(devinfo->ver >= 7);
1672 brw_F32TO16(p, dst, src[0]);
1673 break;
1674
1675 case BRW_OPCODE_F16TO32:
1676 assert(devinfo->ver >= 7);
1677 brw_F16TO32(p, dst, src[0]);
1678 break;
1679
1680 case BRW_OPCODE_LRP:
1681 assert(devinfo->ver >= 6);
1682 brw_LRP(p, dst, src[0], src[1], src[2]);
1683 break;
1684
1685 case BRW_OPCODE_BFREV:
1686 assert(devinfo->ver >= 7);
1687 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1688 retype(src[0], BRW_REGISTER_TYPE_UD));
1689 break;
1690 case BRW_OPCODE_FBH:
1691 assert(devinfo->ver >= 7);
1692 brw_FBH(p, retype(dst, src[0].type), src[0]);
1693 break;
1694 case BRW_OPCODE_FBL:
1695 assert(devinfo->ver >= 7);
1696 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD),
1697 retype(src[0], BRW_REGISTER_TYPE_UD));
1698 break;
1699 case BRW_OPCODE_LZD:
1700 brw_LZD(p, dst, src[0]);
1701 break;
1702 case BRW_OPCODE_CBIT:
1703 assert(devinfo->ver >= 7);
1704 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD),
1705 retype(src[0], BRW_REGISTER_TYPE_UD));
1706 break;
1707 case BRW_OPCODE_ADDC:
1708 assert(devinfo->ver >= 7);
1709 brw_ADDC(p, dst, src[0], src[1]);
1710 break;
1711 case BRW_OPCODE_SUBB:
1712 assert(devinfo->ver >= 7);
1713 brw_SUBB(p, dst, src[0], src[1]);
1714 break;
1715 case BRW_OPCODE_MAC:
1716 brw_MAC(p, dst, src[0], src[1]);
1717 break;
1718
1719 case BRW_OPCODE_BFE:
1720 assert(devinfo->ver >= 7);
1721 brw_BFE(p, dst, src[0], src[1], src[2]);
1722 break;
1723
1724 case BRW_OPCODE_BFI1:
1725 assert(devinfo->ver >= 7);
1726 brw_BFI1(p, dst, src[0], src[1]);
1727 break;
1728 case BRW_OPCODE_BFI2:
1729 assert(devinfo->ver >= 7);
1730 brw_BFI2(p, dst, src[0], src[1], src[2]);
1731 break;
1732
1733 case BRW_OPCODE_IF:
1734 if (!inst->src[0].is_null()) {
1735 /* The instruction has an embedded compare (only allowed on gfx6) */
1736 assert(devinfo->ver == 6);
1737 gfx6_IF(p, inst->conditional_mod, src[0], src[1]);
1738 } else {
1739 brw_inst *if_inst = brw_IF(p, BRW_EXECUTE_8);
1740 brw_inst_set_pred_control(p->devinfo, if_inst, inst->predicate);
1741 }
1742 break;
1743
1744 case BRW_OPCODE_ELSE:
1745 brw_ELSE(p);
1746 break;
1747 case BRW_OPCODE_ENDIF:
1748 brw_ENDIF(p);
1749 break;
1750
1751 case BRW_OPCODE_DO:
1752 brw_DO(p, BRW_EXECUTE_8);
1753 break;
1754
1755 case BRW_OPCODE_BREAK:
1756 brw_BREAK(p);
1757 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1758 break;
1759 case BRW_OPCODE_CONTINUE:
1760 brw_CONT(p);
1761 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1762 break;
1763
1764 case BRW_OPCODE_WHILE:
1765 brw_WHILE(p);
1766 loop_count++;
1767 break;
1768
1769 case SHADER_OPCODE_RCP:
1770 case SHADER_OPCODE_RSQ:
1771 case SHADER_OPCODE_SQRT:
1772 case SHADER_OPCODE_EXP2:
1773 case SHADER_OPCODE_LOG2:
1774 case SHADER_OPCODE_SIN:
1775 case SHADER_OPCODE_COS:
1776 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1777 if (devinfo->ver >= 7) {
1778 gfx6_math(p, dst, brw_math_function(inst->opcode), src[0],
1779 brw_null_reg());
1780 } else if (devinfo->ver == 6) {
1781 generate_math_gfx6(p, inst, dst, src[0], brw_null_reg());
1782 } else {
1783 generate_math1_gfx4(p, inst, dst, src[0]);
1784 send_count++;
1785 }
1786 break;
1787
1788 case SHADER_OPCODE_POW:
1789 case SHADER_OPCODE_INT_QUOTIENT:
1790 case SHADER_OPCODE_INT_REMAINDER:
1791 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1792 if (devinfo->ver >= 7) {
1793 gfx6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
1794 } else if (devinfo->ver == 6) {
1795 generate_math_gfx6(p, inst, dst, src[0], src[1]);
1796 } else {
1797 generate_math2_gfx4(p, inst, dst, src[0], src[1]);
1798 send_count++;
1799 }
1800 break;
1801
1802 case SHADER_OPCODE_TEX:
1803 case SHADER_OPCODE_TXD:
1804 case SHADER_OPCODE_TXF:
1805 case SHADER_OPCODE_TXF_CMS:
1806 case SHADER_OPCODE_TXF_CMS_W:
1807 case SHADER_OPCODE_TXF_MCS:
1808 case SHADER_OPCODE_TXL:
1809 case SHADER_OPCODE_TXS:
1810 case SHADER_OPCODE_TG4:
1811 case SHADER_OPCODE_TG4_OFFSET:
1812 case SHADER_OPCODE_SAMPLEINFO:
1813 generate_tex(p, prog_data, nir->info.stage,
1814 inst, dst, src[0], src[1], src[2]);
1815 send_count++;
1816 break;
1817
1818 case SHADER_OPCODE_GET_BUFFER_SIZE:
1819 generate_get_buffer_size(p, inst, dst, src[0], src[1]);
1820 send_count++;
1821 break;
1822
1823 case VS_OPCODE_URB_WRITE:
1824 generate_vs_urb_write(p, inst);
1825 send_count++;
1826 break;
1827
1828 case SHADER_OPCODE_GFX4_SCRATCH_READ:
1829 generate_scratch_read(p, inst, dst, src[0]);
1830 fill_count++;
1831 break;
1832
1833 case SHADER_OPCODE_GFX4_SCRATCH_WRITE:
1834 generate_scratch_write(p, inst, dst, src[0], src[1]);
1835 spill_count++;
1836 break;
1837
1838 case VS_OPCODE_PULL_CONSTANT_LOAD:
1839 generate_pull_constant_load(p, inst, dst, src[0], src[1]);
1840 send_count++;
1841 break;
1842
1843 case VS_OPCODE_PULL_CONSTANT_LOAD_GFX7:
1844 generate_pull_constant_load_gfx7(p, inst, dst, src[0], src[1]);
1845 send_count++;
1846 break;
1847
1848 case GS_OPCODE_URB_WRITE:
1849 generate_gs_urb_write(p, inst);
1850 send_count++;
1851 break;
1852
1853 case GS_OPCODE_URB_WRITE_ALLOCATE:
1854 generate_gs_urb_write_allocate(p, inst);
1855 send_count++;
1856 break;
1857
1858 case GS_OPCODE_SVB_WRITE:
1859 generate_gs_svb_write(p, inst, dst, src[0], src[1]);
1860 send_count++;
1861 break;
1862
1863 case GS_OPCODE_SVB_SET_DST_INDEX:
1864 generate_gs_svb_set_destination_index(p, inst, dst, src[0]);
1865 break;
1866
1867 case GS_OPCODE_THREAD_END:
1868 generate_gs_thread_end(p, inst);
1869 send_count++;
1870 break;
1871
1872 case GS_OPCODE_SET_WRITE_OFFSET:
1873 generate_gs_set_write_offset(p, dst, src[0], src[1]);
1874 break;
1875
1876 case GS_OPCODE_SET_VERTEX_COUNT:
1877 generate_gs_set_vertex_count(p, dst, src[0]);
1878 break;
1879
1880 case GS_OPCODE_FF_SYNC:
1881 generate_gs_ff_sync(p, inst, dst, src[0], src[1]);
1882 send_count++;
1883 break;
1884
1885 case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
1886 generate_gs_ff_sync_set_primitives(p, dst, src[0], src[1], src[2]);
1887 break;
1888
1889 case GS_OPCODE_SET_PRIMITIVE_ID:
1890 generate_gs_set_primitive_id(p, dst);
1891 break;
1892
1893 case GS_OPCODE_SET_DWORD_2:
1894 generate_gs_set_dword_2(p, dst, src[0]);
1895 break;
1896
1897 case GS_OPCODE_PREPARE_CHANNEL_MASKS:
1898 generate_gs_prepare_channel_masks(p, dst);
1899 break;
1900
1901 case GS_OPCODE_SET_CHANNEL_MASKS:
1902 generate_gs_set_channel_masks(p, dst, src[0]);
1903 break;
1904
1905 case GS_OPCODE_GET_INSTANCE_ID:
1906 generate_gs_get_instance_id(p, dst);
1907 break;
1908
1909 case SHADER_OPCODE_SHADER_TIME_ADD:
1910 brw_shader_time_add(p, src[0],
1911 prog_data->base.binding_table.shader_time_start);
1912 send_count++;
1913 break;
1914
1915 case VEC4_OPCODE_UNTYPED_ATOMIC:
1916 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1917 brw_untyped_atomic(p, dst, src[0], src[1], src[2].ud, inst->mlen,
1918 !inst->dst.is_null(), inst->header_size);
1919 send_count++;
1920 break;
1921
1922 case VEC4_OPCODE_UNTYPED_SURFACE_READ:
1923 assert(!inst->header_size);
1924 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1925 brw_untyped_surface_read(p, dst, src[0], src[1], inst->mlen,
1926 src[2].ud);
1927 send_count++;
1928 break;
1929
1930 case VEC4_OPCODE_UNTYPED_SURFACE_WRITE:
1931 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1932 brw_untyped_surface_write(p, src[0], src[1], inst->mlen,
1933 src[2].ud, inst->header_size);
1934 send_count++;
1935 break;
1936
1937 case SHADER_OPCODE_MEMORY_FENCE:
1938 brw_memory_fence(p, dst, src[0], BRW_OPCODE_SEND,
1939 brw_message_target(inst->sfid),
1940 /* commit_enable */ false,
1941 /* bti */ 0);
1942 send_count++;
1943 break;
1944
1945 case SHADER_OPCODE_FIND_LIVE_CHANNEL: {
1946 const struct brw_reg mask =
1947 brw_stage_has_packed_dispatch(devinfo, nir->info.stage,
1948 &prog_data->base) ? brw_imm_ud(~0u) :
1949 brw_dmask_reg();
1950 brw_find_live_channel(p, dst, mask);
1951 break;
1952 }
1953
1954 case SHADER_OPCODE_BROADCAST:
1955 assert(inst->force_writemask_all);
1956 brw_broadcast(p, dst, src[0], src[1]);
1957 break;
1958
1959 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
1960 generate_unpack_flags(p, dst);
1961 break;
1962
1963 case VEC4_OPCODE_MOV_BYTES: {
1964 /* Moves the low byte from each channel, using an Align1 access mode
1965 * and a <4,1,0> source region.
1966 */
1967 assert(src[0].type == BRW_REGISTER_TYPE_UB ||
1968 src[0].type == BRW_REGISTER_TYPE_B);
1969
1970 brw_set_default_access_mode(p, BRW_ALIGN_1);
1971 src[0].vstride = BRW_VERTICAL_STRIDE_4;
1972 src[0].width = BRW_WIDTH_1;
1973 src[0].hstride = BRW_HORIZONTAL_STRIDE_0;
1974 brw_MOV(p, dst, src[0]);
1975 brw_set_default_access_mode(p, BRW_ALIGN_16);
1976 break;
1977 }
1978
1979 case VEC4_OPCODE_DOUBLE_TO_F32:
1980 case VEC4_OPCODE_DOUBLE_TO_D32:
1981 case VEC4_OPCODE_DOUBLE_TO_U32: {
1982 assert(type_sz(src[0].type) == 8);
1983 assert(type_sz(dst.type) == 8);
1984
1985 brw_reg_type dst_type;
1986
1987 switch (inst->opcode) {
1988 case VEC4_OPCODE_DOUBLE_TO_F32:
1989 dst_type = BRW_REGISTER_TYPE_F;
1990 break;
1991 case VEC4_OPCODE_DOUBLE_TO_D32:
1992 dst_type = BRW_REGISTER_TYPE_D;
1993 break;
1994 case VEC4_OPCODE_DOUBLE_TO_U32:
1995 dst_type = BRW_REGISTER_TYPE_UD;
1996 break;
1997 default:
1998 unreachable("Not supported conversion");
1999 }
2000 dst = retype(dst, dst_type);
2001
2002 brw_set_default_access_mode(p, BRW_ALIGN_1);
2003
2004 /* When converting from DF->F, we set destination's stride as 2 as an
2005 * aligment requirement. But in IVB/BYT, each DF implicitly writes
2006 * two floats, being the first one the converted value. So we don't
2007 * need to explicitly set stride 2, but 1.
2008 */
2009 struct brw_reg spread_dst;
2010 if (devinfo->verx10 == 70)
2011 spread_dst = stride(dst, 8, 4, 1);
2012 else
2013 spread_dst = stride(dst, 8, 4, 2);
2014
2015 brw_MOV(p, spread_dst, src[0]);
2016
2017 brw_set_default_access_mode(p, BRW_ALIGN_16);
2018 break;
2019 }
2020
2021 case VEC4_OPCODE_TO_DOUBLE: {
2022 assert(type_sz(src[0].type) == 4);
2023 assert(type_sz(dst.type) == 8);
2024
2025 brw_set_default_access_mode(p, BRW_ALIGN_1);
2026
2027 brw_MOV(p, dst, src[0]);
2028
2029 brw_set_default_access_mode(p, BRW_ALIGN_16);
2030 break;
2031 }
2032
2033 case VEC4_OPCODE_PICK_LOW_32BIT:
2034 case VEC4_OPCODE_PICK_HIGH_32BIT: {
2035 /* Stores the low/high 32-bit of each 64-bit element in src[0] into
2036 * dst using ALIGN1 mode and a <8,4,2>:UD region on the source.
2037 */
2038 assert(type_sz(src[0].type) == 8);
2039 assert(type_sz(dst.type) == 4);
2040
2041 brw_set_default_access_mode(p, BRW_ALIGN_1);
2042
2043 dst = retype(dst, BRW_REGISTER_TYPE_UD);
2044 dst.hstride = BRW_HORIZONTAL_STRIDE_1;
2045
2046 src[0] = retype(src[0], BRW_REGISTER_TYPE_UD);
2047 if (inst->opcode == VEC4_OPCODE_PICK_HIGH_32BIT)
2048 src[0] = suboffset(src[0], 1);
2049 src[0] = spread(src[0], 2);
2050 brw_MOV(p, dst, src[0]);
2051
2052 brw_set_default_access_mode(p, BRW_ALIGN_16);
2053 break;
2054 }
2055
2056 case VEC4_OPCODE_SET_LOW_32BIT:
2057 case VEC4_OPCODE_SET_HIGH_32BIT: {
2058 /* Reads consecutive 32-bit elements from src[0] and writes
2059 * them to the low/high 32-bit of each 64-bit element in dst.
2060 */
2061 assert(type_sz(src[0].type) == 4);
2062 assert(type_sz(dst.type) == 8);
2063
2064 brw_set_default_access_mode(p, BRW_ALIGN_1);
2065
2066 dst = retype(dst, BRW_REGISTER_TYPE_UD);
2067 if (inst->opcode == VEC4_OPCODE_SET_HIGH_32BIT)
2068 dst = suboffset(dst, 1);
2069 dst.hstride = BRW_HORIZONTAL_STRIDE_2;
2070
2071 src[0] = retype(src[0], BRW_REGISTER_TYPE_UD);
2072 brw_MOV(p, dst, src[0]);
2073
2074 brw_set_default_access_mode(p, BRW_ALIGN_16);
2075 break;
2076 }
2077
2078 case VEC4_OPCODE_PACK_BYTES: {
2079 /* Is effectively:
2080 *
2081 * mov(8) dst<16,4,1>:UB src<4,1,0>:UB
2082 *
2083 * but destinations' only regioning is horizontal stride, so instead we
2084 * have to use two instructions:
2085 *
2086 * mov(4) dst<1>:UB src<4,1,0>:UB
2087 * mov(4) dst.16<1>:UB src.16<4,1,0>:UB
2088 *
2089 * where they pack the four bytes from the low and high four DW.
2090 */
2091 assert(util_is_power_of_two_nonzero(dst.writemask));
2092 unsigned offset = __builtin_ctz(dst.writemask);
2093
2094 dst.type = BRW_REGISTER_TYPE_UB;
2095
2096 brw_set_default_access_mode(p, BRW_ALIGN_1);
2097
2098 src[0].type = BRW_REGISTER_TYPE_UB;
2099 src[0].vstride = BRW_VERTICAL_STRIDE_4;
2100 src[0].width = BRW_WIDTH_1;
2101 src[0].hstride = BRW_HORIZONTAL_STRIDE_0;
2102 dst.subnr = offset * 4;
2103 struct brw_inst *insn = brw_MOV(p, dst, src[0]);
2104 brw_inst_set_exec_size(p->devinfo, insn, BRW_EXECUTE_4);
2105 brw_inst_set_no_dd_clear(p->devinfo, insn, true);
2106 brw_inst_set_no_dd_check(p->devinfo, insn, inst->no_dd_check);
2107
2108 src[0].subnr = 16;
2109 dst.subnr = 16 + offset * 4;
2110 insn = brw_MOV(p, dst, src[0]);
2111 brw_inst_set_exec_size(p->devinfo, insn, BRW_EXECUTE_4);
2112 brw_inst_set_no_dd_clear(p->devinfo, insn, inst->no_dd_clear);
2113 brw_inst_set_no_dd_check(p->devinfo, insn, true);
2114
2115 brw_set_default_access_mode(p, BRW_ALIGN_16);
2116 break;
2117 }
2118
2119 case VEC4_OPCODE_ZERO_OOB_PUSH_REGS:
2120 generate_zero_oob_push_regs(p, &prog_data->base, dst, src[0]);
2121 break;
2122
2123 case TCS_OPCODE_URB_WRITE:
2124 generate_tcs_urb_write(p, inst, src[0]);
2125 send_count++;
2126 break;
2127
2128 case VEC4_OPCODE_URB_READ:
2129 generate_vec4_urb_read(p, inst, dst, src[0]);
2130 send_count++;
2131 break;
2132
2133 case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
2134 generate_tcs_input_urb_offsets(p, dst, src[0], src[1]);
2135 break;
2136
2137 case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
2138 generate_tcs_output_urb_offsets(p, dst, src[0], src[1]);
2139 break;
2140
2141 case TCS_OPCODE_GET_INSTANCE_ID:
2142 generate_tcs_get_instance_id(p, dst);
2143 break;
2144
2145 case TCS_OPCODE_GET_PRIMITIVE_ID:
2146 generate_tcs_get_primitive_id(p, dst);
2147 break;
2148
2149 case TCS_OPCODE_CREATE_BARRIER_HEADER:
2150 generate_tcs_create_barrier_header(p, prog_data, dst);
2151 break;
2152
2153 case TES_OPCODE_CREATE_INPUT_READ_HEADER:
2154 generate_tes_create_input_read_header(p, dst);
2155 break;
2156
2157 case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
2158 generate_tes_add_indirect_urb_offset(p, dst, src[0], src[1]);
2159 break;
2160
2161 case TES_OPCODE_GET_PRIMITIVE_ID:
2162 generate_tes_get_primitive_id(p, dst);
2163 break;
2164
2165 case TCS_OPCODE_SRC0_010_IS_ZERO:
2166 /* If src_reg had stride like fs_reg, we wouldn't need this. */
2167 brw_MOV(p, brw_null_reg(), stride(src[0], 0, 1, 0));
2168 break;
2169
2170 case TCS_OPCODE_RELEASE_INPUT:
2171 generate_tcs_release_input(p, dst, src[0], src[1]);
2172 send_count++;
2173 break;
2174
2175 case TCS_OPCODE_THREAD_END:
2176 generate_tcs_thread_end(p, inst);
2177 send_count++;
2178 break;
2179
2180 case SHADER_OPCODE_BARRIER:
2181 brw_barrier(p, src[0]);
2182 brw_WAIT(p);
2183 send_count++;
2184 break;
2185
2186 case SHADER_OPCODE_MOV_INDIRECT:
2187 generate_mov_indirect(p, inst, dst, src[0], src[1]);
2188 break;
2189
2190 case BRW_OPCODE_DIM:
2191 assert(devinfo->is_haswell);
2192 assert(src[0].type == BRW_REGISTER_TYPE_DF);
2193 assert(dst.type == BRW_REGISTER_TYPE_DF);
2194 brw_DIM(p, dst, retype(src[0], BRW_REGISTER_TYPE_F));
2195 break;
2196
2197 default:
2198 unreachable("Unsupported opcode");
2199 }
2200
2201 if (inst->opcode == VEC4_OPCODE_PACK_BYTES) {
2202 /* Handled dependency hints in the generator. */
2203
2204 assert(!inst->conditional_mod);
2205 } else if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
2206 assert(p->nr_insn == pre_emit_nr_insn + 1 ||
2207 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2208 "emitting more than 1 instruction");
2209
2210 brw_inst *last = &p->store[pre_emit_nr_insn];
2211
2212 if (inst->conditional_mod)
2213 brw_inst_set_cond_modifier(p->devinfo, last, inst->conditional_mod);
2214 brw_inst_set_no_dd_clear(p->devinfo, last, inst->no_dd_clear);
2215 brw_inst_set_no_dd_check(p->devinfo, last, inst->no_dd_check);
2216 }
2217 }
2218
2219 brw_set_uip_jip(p, 0);
2220
2221 /* end of program sentinel */
2222 disasm_new_inst_group(disasm_info, p->next_insn_offset);
2223
2224 #ifndef NDEBUG
2225 bool validated =
2226 #else
2227 if (unlikely(debug_enabled))
2228 #endif
2229 brw_validate_instructions(devinfo, p->store,
2230 0, p->next_insn_offset,
2231 disasm_info);
2232
2233 int before_size = p->next_insn_offset;
2234 brw_compact_instructions(p, 0, disasm_info);
2235 int after_size = p->next_insn_offset;
2236
2237 if (unlikely(debug_enabled)) {
2238 unsigned char sha1[21];
2239 char sha1buf[41];
2240
2241 _mesa_sha1_compute(p->store, p->next_insn_offset, sha1);
2242 _mesa_sha1_format(sha1buf, sha1);
2243
2244 fprintf(stderr, "Native code for %s %s shader %s (sha1 %s):\n",
2245 nir->info.label ? nir->info.label : "unnamed",
2246 _mesa_shader_stage_to_string(nir->info.stage), nir->info.name,
2247 sha1buf);
2248
2249 fprintf(stderr, "%s vec4 shader: %d instructions. %d loops. %u cycles. %d:%d "
2250 "spills:fills, %u sends. Compacted %d to %d bytes (%.0f%%)\n",
2251 stage_abbrev, before_size / 16, loop_count, perf.latency,
2252 spill_count, fill_count, send_count, before_size, after_size,
2253 100.0f * (before_size - after_size) / before_size);
2254
2255 /* overriding the shader makes disasm_info invalid */
2256 if (!brw_try_override_assembly(p, 0, sha1buf)) {
2257 dump_assembly(p->store, 0, p->next_insn_offset,
2258 disasm_info, perf.block_latency);
2259 } else {
2260 fprintf(stderr, "Successfully overrode shader with sha1 %s\n\n", sha1buf);
2261 }
2262 }
2263 ralloc_free(disasm_info);
2264 assert(validated);
2265
2266 brw_shader_debug_log(compiler, log_data,
2267 "%s vec4 shader: %d inst, %d loops, %u cycles, "
2268 "%d:%d spills:fills, %u sends, "
2269 "compacted %d to %d bytes.\n",
2270 stage_abbrev, before_size / 16,
2271 loop_count, perf.latency, spill_count,
2272 fill_count, send_count, before_size, after_size);
2273 if (stats) {
2274 stats->dispatch_width = 0;
2275 stats->instructions = before_size / 16;
2276 stats->sends = send_count;
2277 stats->loops = loop_count;
2278 stats->cycles = perf.latency;
2279 stats->spills = spill_count;
2280 stats->fills = fill_count;
2281 }
2282 }
2283
2284 extern "C" const unsigned *
brw_vec4_generate_assembly(const struct brw_compiler * compiler,void * log_data,void * mem_ctx,const nir_shader * nir,struct brw_vue_prog_data * prog_data,const struct cfg_t * cfg,const performance & perf,struct brw_compile_stats * stats,bool debug_enabled)2285 brw_vec4_generate_assembly(const struct brw_compiler *compiler,
2286 void *log_data,
2287 void *mem_ctx,
2288 const nir_shader *nir,
2289 struct brw_vue_prog_data *prog_data,
2290 const struct cfg_t *cfg,
2291 const performance &perf,
2292 struct brw_compile_stats *stats,
2293 bool debug_enabled)
2294 {
2295 struct brw_codegen *p = rzalloc(mem_ctx, struct brw_codegen);
2296 brw_init_codegen(compiler->devinfo, p, mem_ctx);
2297 brw_set_default_access_mode(p, BRW_ALIGN_16);
2298
2299 generate_code(p, compiler, log_data, nir, prog_data, cfg, perf, stats,
2300 debug_enabled);
2301
2302 assert(prog_data->base.const_data_size == 0);
2303 if (nir->constant_data_size > 0) {
2304 prog_data->base.const_data_size = nir->constant_data_size;
2305 prog_data->base.const_data_offset =
2306 brw_append_data(p, nir->constant_data, nir->constant_data_size, 32);
2307 }
2308
2309 return brw_get_program(p, &prog_data->base.program_size);
2310 }
2311