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Searched refs:BRW_ALIGN_1 (Results 1 – 14 of 14) sorted by relevance

/third_party/mesa3d/src/intel/compiler/
Dtest_eu_compact.cpp44 case BRW_ALIGN_1: in get_compact_params_name()
236 CompactParams{ 50, BRW_ALIGN_1 }, CompactParams{ 50, BRW_ALIGN_16 },
237 CompactParams{ 60, BRW_ALIGN_1 }, CompactParams{ 60, BRW_ALIGN_16 },
238 CompactParams{ 70, BRW_ALIGN_1 }, CompactParams{ 70, BRW_ALIGN_16 },
239 CompactParams{ 75, BRW_ALIGN_1 }, CompactParams{ 75, BRW_ALIGN_16 },
240 CompactParams{ 80, BRW_ALIGN_1 }, CompactParams{ 80, BRW_ALIGN_16 },
241 CompactParams{ 90, BRW_ALIGN_1 }, CompactParams{ 90, BRW_ALIGN_16 },
242 CompactParams{ 110, BRW_ALIGN_1 },
243 CompactParams{ 120, BRW_ALIGN_1 },
244 CompactParams{ 125, BRW_ALIGN_1 }
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Dbrw_vec4_generator.cpp68 brw_set_default_access_mode(p, BRW_ALIGN_1); in generate_math_gfx6()
227 brw_set_default_access_mode(p, BRW_ALIGN_1); in generate_tex()
305 brw_set_default_access_mode(p, BRW_ALIGN_1); in generate_tex()
391 brw_set_default_access_mode(p, BRW_ALIGN_1); in generate_gs_urb_write_allocate()
438 brw_set_default_access_mode(p, BRW_ALIGN_1); in generate_gs_set_write_offset()
478 brw_set_default_access_mode(p, BRW_ALIGN_1); in generate_gs_set_vertex_count()
536 brw_set_default_access_mode(p, BRW_ALIGN_1); in generate_gs_svb_set_destination_index()
548 brw_set_default_access_mode(p, BRW_ALIGN_1); in generate_gs_set_dword_2()
566 brw_set_default_access_mode(p, BRW_ALIGN_1); in generate_gs_prepare_channel_masks()
630 brw_set_default_access_mode(p, BRW_ALIGN_1); in generate_gs_set_channel_masks()
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Dbrw_eu_emit.c146 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { in brw_set_dest()
169 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { in brw_set_dest()
283 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { in brw_set_src0()
291 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { in brw_set_src0()
298 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { in brw_set_src0()
399 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { in brw_set_src1()
405 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { in brw_set_src1()
827 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { in brw_alu3()
1133 brw_get_default_access_mode(p) == BRW_ALIGN_1 && in ALU1()
1274 brw_set_default_access_mode(p, BRW_ALIGN_1); in brw_F32TO16()
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Dbrw_clip_util.c96 brw_set_default_access_mode(p, BRW_ALIGN_1); in brw_clip_project_position()
211 brw_set_default_access_mode(p, BRW_ALIGN_1); in brw_clip_interp_vertex()
232 brw_set_default_access_mode(p, BRW_ALIGN_1); in brw_clip_interp_vertex()
Dbrw_disasm.c922 } else if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { in dest()
974 bool is_align1 = brw_inst_3src_access_mode(devinfo, inst) == BRW_ALIGN_1; in dest_3src()
1254 bool is_align1 = brw_inst_3src_access_mode(devinfo, inst) == BRW_ALIGN_1; in src0_3src()
1341 bool is_align1 = brw_inst_3src_access_mode(devinfo, inst) == BRW_ALIGN_1; in src1_3src()
1415 bool is_align1 = brw_inst_3src_access_mode(devinfo, inst) == BRW_ALIGN_1; in src2_3src()
1637 } else if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { in src0()
1699 } else if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { in src1()
1893 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { in brw_disassemble_inst()
Dbrw_eu_validate.c317 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { in invalid_values()
850 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { in general_restrictions_based_on_operand_types()
896 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1 && in general_restrictions_based_on_operand_types()
1696 unsigned dst_subreg = brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1 ? in vector_immediate_restrictions()
1822 brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1 && in special_requirements_for_handling_double_precision_data_types()
Dbrw_compile_ff_gs.c480 brw_set_default_access_mode(p, BRW_ALIGN_1); in gfx6_sol_program()
Dbrw_clip_unfilled.c86 brw_set_default_access_mode(p, BRW_ALIGN_1); in compute_tri_direction()
Dbrw_inst.h319 FK(access_mode, /* 4+ */ 8, 8, /* 12+ */ BRW_ALIGN_1)
374 FK(3src_access_mode, /* 4+ */ 8, 8, /* 12+ */ BRW_ALIGN_1)
Dbrw_eu_defines.h98 #define BRW_ALIGN_1 0 macro
Dbrw_compile_sf.c663 brw_set_default_access_mode(p, BRW_ALIGN_1); in brw_emit_point_sprite_setup()
Dtest_eu_validate.cpp494 brw_set_default_access_mode(p, BRW_ALIGN_1); in TEST_P()
566 { BRW_ALIGN_1, devinfo.ver >= 10 },
Dbrw_fs_generator.cpp2026 brw_set_default_access_mode(p, BRW_ALIGN_1); in generate_code()
/third_party/mesa3d/src/intel/tools/
Di965_gram.y546 options->access_mode = BRW_ALIGN_1; in add_instruction_option()