| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86InstrFMA.td | 1 //===-- X86InstrFMA.td - FMA Instruction Set ---------------*- tablegen -*-===//
9 // This file describes FMA (Fused Multiply-Add) instructions.
17 // For all FMA opcodes declared in fma3p_rm_* and fma3s_rm_* multiclasses
23 // FMA*213*:
27 // FMA*132*:
31 // FMA*231*:
168 // All source register operands of FMA opcodes defined in fma3s_rm multiclass
170 // adjustment, for example, commuting the operands 1 and 2 in FMA*132 form
171 // would require an opcode change to FMA*231:
172 // FMA*132* reg1, reg2, reg3; // reg1 * reg3 + reg2;
[all …]
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| /third_party/mesa3d/src/panfrost/bifrost/valhall/test/ |
| D | negative-cases.txt | 25 FMA.f32 r0, u0, u1, 0x0
26 FMA.f32 r0, u0, 0x40490FDB, 0x0
27 FMA.f32 r0, 0x3F317218, 0x40490FDB, 0x0
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| D | assembler-cases.txt | 57 00 dd c0 08 14 c2 b2 00 FMA.f32 r2, r0, 0x44000000.neg.h1, 0x0.neg
58 41 88 c0 00 04 c1 b2 00 FMA.f32 r1, `r1, u8, 0x0.neg
59 40 88 c0 00 04 c0 b2 10 FMA.f32.wait1 r0, `r0, u8, 0x0.neg
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| /third_party/flutter/skia/src/core/ |
| D | SkCpu.h | 23 FMA = 1 << 8, enumerator
28 HSW = AVX2 | BMI1 | BMI2 | F16C | FMA,
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| D | SkCpu.cpp | 64 if (abcd[2] & (1<<12)) { features |= SkCpu:: FMA; } in read_cpu_features()
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| /third_party/skia/src/core/ |
| D | SkCpu.h | 23 FMA = 1 << 8, enumerator
28 HSW = AVX2 | BMI1 | BMI2 | F16C | FMA,
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| D | SkCpu.cpp | 54 if (abcd[2] & (1<<12)) { features |= SkCpu:: FMA; } in read_cpu_features()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUFeatures.td | 16 "FMA",
18 "Enable single precision FMA (not as fast as mul+add, but fused)"
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| D | AMDGPUSubtarget.h | 320 bool FMA; variable
550 return FMA; in hasFMA()
1224 bool FMA; variable
1309 bool hasFMA() const { return FMA; } in hasFMA()
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| D | SIISelLowering.cpp | 521 setOperationAction(ISD::FMA, MVT::f16, Legal); in SITargetLowering()
627 setOperationAction(ISD::FMA, MVT::v2f16, Legal); in SITargetLowering()
654 setOperationAction(ISD::FMA, MVT::v4f16, Custom); in SITargetLowering()
726 setTargetDAGCombine(ISD::FMA); in SITargetLowering()
783 (Opcode == ISD::FMA && Subtarget->hasFmaMixInsts())) && in isFPExtFoldable()
4087 case ISD::FMA: in LowerOperation()
7627 case ISD::FMA: in getFPTernOp()
7760 SDValue Fma0 = getFPTernOp(DAG, ISD::FMA, SL, MVT::f32, NegDivScale0, in LowerFDIV32()
7763 SDValue Fma1 = getFPTernOp(DAG, ISD::FMA, SL, MVT::f32, Fma0, ApproxRcp, in LowerFDIV32()
7769 SDValue Fma2 = getFPTernOp(DAG, ISD::FMA, SL, MVT::f32, NegDivScale0, Mul, in LowerFDIV32()
[all …]
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| /third_party/openh264/codec/common/x86/ |
| D | cpuid.asm | 190 ; refer to detection of FMA addressed in INTEL AVX manual document
192 cmp ecx, 018001000H ; check OSXSAVE, AVX, FMA feature flags
194 ; processor supports AVX,FMA instructions and XGETBV is enabled by OS
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| /third_party/ffmpeg/libavcodec/x86/ |
| D | synth_filter.asm | 64 %else ; non-FMA
93 %else ; non-FMA
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| D | jpeg2000dsp.asm | 89 %else ; non FMA
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/ |
| D | ConstrainedOps.def | 63 FUNCTION(fma, 3, 1, experimental_constrained_fma, FMA)
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| /third_party/mesa3d/src/gallium/drivers/swr/rasterizer/common/ |
| D | simdlib_128_avx2.inl | 33 // Also, add native support for FMA operations
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| D | isa.hpp | 59 bool FMA(void) { return CPU_Rep.f_1_ECX_[12]; } in FMA() function in InstructionSet
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| /third_party/mesa3d/src/panfrost/bifrost/ |
| D | Notes.txt | 41 // These instructions in the FMA slot, together with LSHIFT_ADD_HIGH32.i32
51 // FMA to ADD instead of being passed explicitly. Hence, these two must be
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 356 FMA, enumerator
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| /third_party/mesa3d/docs/relnotes/ |
| D | 20.1.8.rst | 89 - Revert "ac: generate FMA for inexact instructions for radeonsi"
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| D | 18.2.5.rst | 114 - glsl_to_tgsi: don't create 64-bit integer MAD/FMA
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| D | 17.0.3.rst | 104 - nvc0/ir: treat FMA like MAD for operand propagation
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/IR/ |
| D | AutoUpgrade.cpp | 3141 Function *FMA = Intrinsic::getDeclaration(CI->getModule(), IID); in UpgradeIntrinsicCall() local
3142 Rep = Builder.CreateCall(FMA, Ops); in UpgradeIntrinsicCall()
3144 Function *FMA = Intrinsic::getDeclaration(CI->getModule(), in UpgradeIntrinsicCall() local
3147 Rep = Builder.CreateCall(FMA, { A, B, C }); in UpgradeIntrinsicCall()
3201 Function *FMA = Intrinsic::getDeclaration(CI->getModule(), in UpgradeIntrinsicCall() local
3204 Rep = Builder.CreateCall(FMA, { A, B, C }); in UpgradeIntrinsicCall()
3220 Function *FMA = Intrinsic::getDeclaration(CI->getModule(), Intrinsic::fma, in UpgradeIntrinsicCall() local
3222 Value *Odd = Builder.CreateCall(FMA, Ops); in UpgradeIntrinsicCall()
3224 Value *Even = Builder.CreateCall(FMA, Ops); in UpgradeIntrinsicCall()
3267 Function *FMA = Intrinsic::getDeclaration(CI->getModule(), Intrinsic::fma, in UpgradeIntrinsicCall() local
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | InterleavedLoadCombinePass.cpp | 1184 auto FMA = MSSA.getMemoryAccess(First); in combine() local
1187 if (!MSSA.dominates(MADef, FMA)) in combine()
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| /third_party/mesa3d/src/gallium/auxiliary/tgsi/ |
| D | tgsi_info_opcodes.h | 20 OPCODE(1, 3, COMP, FMA)
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| /third_party/glib/glib/gnulib/ |
| D | meson.build | 41 'FMA',
|