Searched refs:MI_FLUSH_DW (Results 1 – 7 of 7) sorted by relevance
9 0x12300020: 0x13000002: MI_FLUSH_DW post_sync_op='no write'
42 #define MI_FLUSH_DW (CMD_MI | (0x26 << 23) | 2) macro
88 - i965: Program DWord Length in MI_FLUSH_DW89 - i965/gen8+: Fix the number of dwords programmed in MI_FLUSH_DW
2900 - i965: Use MI_FLUSH_DW for blt ring flush on sandybridge
2364 - intel/genxml: Fix MI_FLUSH_DW to actually specify the length properly
91 OUT_BATCH(MI_FLUSH_DW | (n_dwords - 2)); in set_blitter_tiling()
1437 #define MI_FLUSH_DW (CMD_MI | (0x26 << 23)) macro