Home
last modified time | relevance | path

Searched refs:OUT_BATCH (Results 1 – 25 of 42) sorted by relevance

12

/third_party/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_misc_state.c62 OUT_BATCH(MI_FLUSH); in upload_pipelined_state_pointers()
67 OUT_BATCH(_3DSTATE_PIPELINED_POINTERS << 16 | (7 - 2)); in upload_pipelined_state_pointers()
72 OUT_BATCH(0); in upload_pipelined_state_pointers()
293 OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2)); in brw_emit_depth_stencil_hiz()
294 OUT_BATCH((depth_mt ? depth_mt->surf.row_pitch_B - 1 : 0) | in brw_emit_depth_stencil_hiz()
303 OUT_BATCH(0); in brw_emit_depth_stencil_hiz()
306 OUT_BATCH(((width + tile_x - 1) << 6) | in brw_emit_depth_stencil_hiz()
308 OUT_BATCH(0); in brw_emit_depth_stencil_hiz()
311 OUT_BATCH(tile_x | (tile_y << 16)); in brw_emit_depth_stencil_hiz()
316 OUT_BATCH(0); in brw_emit_depth_stencil_hiz()
[all …]
Dhsw_sol.c105 OUT_BATCH(HSW_MI_MATH | (9 - 2)); in tally_prims_written()
107 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCA, R2)); in tally_prims_written()
108 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCB, R1)); in tally_prims_written()
109 OUT_BATCH(MI_MATH_ALU0(SUB)); in tally_prims_written()
110 OUT_BATCH(MI_MATH_ALU2(STORE, R1, ACCU)); in tally_prims_written()
112 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCA, R0)); in tally_prims_written()
113 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCB, R1)); in tally_prims_written()
114 OUT_BATCH(MI_MATH_ALU0(ADD)); in tally_prims_written()
115 OUT_BATCH(MI_MATH_ALU2(STORE, R0, ACCU)); in tally_prims_written()
128 OUT_BATCH(HSW_MI_MATH | (5 - 2)); in tally_prims_written()
[all …]
Dgfx8_multisample_state.c37 OUT_BATCH(_3DSTATE_SAMPLE_PATTERN << 16 | (9 - 2)); in gfx8_emit_3dstate_sample_pattern()
40 OUT_BATCH(brw_multisample_positions_16x[0]); /* positions 3, 2, 1, 0 */ in gfx8_emit_3dstate_sample_pattern()
41 OUT_BATCH(brw_multisample_positions_16x[1]); /* positions 7, 6, 5, 4 */ in gfx8_emit_3dstate_sample_pattern()
42 OUT_BATCH(brw_multisample_positions_16x[2]); /* positions 11, 10, 9, 8 */ in gfx8_emit_3dstate_sample_pattern()
43 OUT_BATCH(brw_multisample_positions_16x[3]); /* positions 15, 14, 13, 12 */ in gfx8_emit_3dstate_sample_pattern()
46 OUT_BATCH(brw_multisample_positions_8x[1]); /* sample positions 7654 */ in gfx8_emit_3dstate_sample_pattern()
47 OUT_BATCH(brw_multisample_positions_8x[0]); /* sample positions 3210 */ in gfx8_emit_3dstate_sample_pattern()
50 OUT_BATCH(brw_multisample_positions_4x); in gfx8_emit_3dstate_sample_pattern()
53 OUT_BATCH(brw_multisample_positions_1x_2x); in gfx8_emit_3dstate_sample_pattern()
Dbrw_binding_tables.c89 OUT_BATCH(packet_name << 16 | (2 - 2)); in brw_upload_binding_table()
93 OUT_BATCH(stage_state->bind_bo_offset); in brw_upload_binding_table()
252 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS << 16 | (6 - 2)); in gfx4_upload_binding_table_pointers()
253 OUT_BATCH(brw->vs.base.bind_bo_offset); in gfx4_upload_binding_table_pointers()
254 OUT_BATCH(0); /* gs */ in gfx4_upload_binding_table_pointers()
255 OUT_BATCH(0); /* clip */ in gfx4_upload_binding_table_pointers()
256 OUT_BATCH(0); /* sf */ in gfx4_upload_binding_table_pointers()
257 OUT_BATCH(brw->wm.base.bind_bo_offset); in gfx4_upload_binding_table_pointers()
282 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS << 16 | in gfx6_upload_binding_table_pointers()
287 OUT_BATCH(brw->vs.base.bind_bo_offset); /* vs */ in gfx6_upload_binding_table_pointers()
[all …]
Dbrw_blit.c91 OUT_BATCH(MI_FLUSH_DW | (n_dwords - 2)); in set_blitter_tiling()
92 OUT_BATCH(0); in set_blitter_tiling()
93 OUT_BATCH(0); in set_blitter_tiling()
94 OUT_BATCH(0); in set_blitter_tiling()
96 OUT_BATCH(0); in set_blitter_tiling()
98 OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2)); in set_blitter_tiling()
99 OUT_BATCH(BCS_SWCTRL); in set_blitter_tiling()
100 OUT_BATCH((BCS_SWCTRL_DST_Y | BCS_SWCTRL_SRC_Y) << 16 | in set_blitter_tiling()
357 OUT_BATCH(CMD | (length - 2)); in emit_copy_blit()
358 OUT_BATCH(BR13 | (uint16_t)dst_pitch); in emit_copy_blit()
[all …]
Dgfx7_urb.c148 OUT_BATCH(_3DSTATE_PUSH_CONSTANT_ALLOC_VS << 16 | (2 - 2)); in gfx7_emit_push_constant_state()
149 OUT_BATCH(vs_size | offset << GFX7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT); in gfx7_emit_push_constant_state()
152 OUT_BATCH(_3DSTATE_PUSH_CONSTANT_ALLOC_HS << 16 | (2 - 2)); in gfx7_emit_push_constant_state()
153 OUT_BATCH(hs_size | offset << GFX7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT); in gfx7_emit_push_constant_state()
156 OUT_BATCH(_3DSTATE_PUSH_CONSTANT_ALLOC_DS << 16 | (2 - 2)); in gfx7_emit_push_constant_state()
157 OUT_BATCH(ds_size | offset << GFX7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT); in gfx7_emit_push_constant_state()
160 OUT_BATCH(_3DSTATE_PUSH_CONSTANT_ALLOC_GS << 16 | (2 - 2)); in gfx7_emit_push_constant_state()
161 OUT_BATCH(gs_size | offset << GFX7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT); in gfx7_emit_push_constant_state()
164 OUT_BATCH(_3DSTATE_PUSH_CONSTANT_ALLOC_PS << 16 | (2 - 2)); in gfx7_emit_push_constant_state()
165 OUT_BATCH(fs_size | offset << GFX7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT); in gfx7_emit_push_constant_state()
[all …]
Dbrw_batch.c650 OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (2 - 2)); in brw_finish_batch()
651 OUT_BATCH(brw->cc.state_offset | 1); in brw_finish_batch()
938 OUT_BATCH(MI_BATCH_BUFFER_END); in brw_batch_maybe_noop()
1127 OUT_BATCH(GFX7_MI_LOAD_REGISTER_MEM | (4 - 2)); in load_sized_register_mem()
1128 OUT_BATCH(reg + i * 4); in load_sized_register_mem()
1135 OUT_BATCH(GFX7_MI_LOAD_REGISTER_MEM | (3 - 2)); in load_sized_register_mem()
1136 OUT_BATCH(reg + i * 4); in load_sized_register_mem()
1174 OUT_BATCH(MI_STORE_REGISTER_MEM | (4 - 2)); in brw_store_register_mem32()
1175 OUT_BATCH(reg); in brw_store_register_mem32()
1180 OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2)); in brw_store_register_mem32()
[all …]
Dhsw_queryobj.c75 OUT_BATCH(HSW_MI_MATH | (1 + ARRAY_SIZE(maths) - 2)); in mult_gpr0_by_80()
78 OUT_BATCH(maths[m]); in mult_gpr0_by_80()
100 OUT_BATCH(HSW_MI_MATH | (1 + ARRAY_SIZE(maths) - 2)); in keep_gpr0_lower_n_bits()
103 OUT_BATCH(maths[m]); in keep_gpr0_lower_n_bits()
137 OUT_BATCH(HSW_MI_MATH | (cmd_len - 2)); in shl_gpr0_by_30_bits()
140 OUT_BATCH(shl_maths[m]); in shl_gpr0_by_30_bits()
179 OUT_BATCH(HSW_MI_MATH | (1 + ARRAY_SIZE(maths) - 2)); in gpr0_to_bool()
182 OUT_BATCH(maths[m]); in gpr0_to_bool()
235 OUT_BATCH(HSW_MI_MATH | (1 + ARRAY_SIZE(maths) - 2)); in calc_overflow_for_stream()
238 OUT_BATCH(maths[m]); in calc_overflow_for_stream()
[all …]
Dgfx7_l3_state.c147 OUT_BATCH(MI_LOAD_REGISTER_IMM | (7 - 2)); in setup_l3_config()
150 OUT_BATCH(GFX7_L3SQCREG1); in setup_l3_config()
151 OUT_BATCH((devinfo->is_haswell ? HSW_L3SQCREG1_SQGHPCI_DEFAULT : in setup_l3_config()
160 OUT_BATCH(GFX7_L3CNTLREG2); in setup_l3_config()
161 OUT_BATCH((has_slm ? GFX7_L3CNTLREG2_SLM_ENABLE : 0) | in setup_l3_config()
167 OUT_BATCH(GFX7_L3CNTLREG3); in setup_l3_config()
168 OUT_BATCH(SET_FIELD(cfg->n[INTEL_L3P_IS], GFX7_L3CNTLREG3_IS_ALLOC) | in setup_l3_config()
179 OUT_BATCH(MI_LOAD_REGISTER_IMM | (5 - 2)); in setup_l3_config()
180 OUT_BATCH(HSW_SCRATCH1); in setup_l3_config()
181 OUT_BATCH(has_dc ? 0 : HSW_SCRATCH1_L3_ATOMIC_DISABLE); in setup_l3_config()
[all …]
Dgfx6_sol.c419 OUT_BATCH(_3DSTATE_GS_SVB_INDEX << 16 | (4 - 2)); in brw_begin_transform_feedback()
420 OUT_BATCH(0); /* SVBI 0 */ in brw_begin_transform_feedback()
421 OUT_BATCH(0); /* starting index */ in brw_begin_transform_feedback()
422 OUT_BATCH(brw_obj->max_index); in brw_begin_transform_feedback()
431 OUT_BATCH(_3DSTATE_GS_SVB_INDEX << 16 | (4 - 2)); in brw_begin_transform_feedback()
432 OUT_BATCH(i << SVB_INDEX_SHIFT); in brw_begin_transform_feedback()
433 OUT_BATCH(0); /* starting index */ in brw_begin_transform_feedback()
434 OUT_BATCH(0xffffffff); in brw_begin_transform_feedback()
501 OUT_BATCH(_3DSTATE_GS_SVB_INDEX << 16 | (4 - 2)); in brw_resume_transform_feedback()
502 OUT_BATCH(0); /* SVBI 0 */ in brw_resume_transform_feedback()
[all …]
Dgfx6_sampler_state.c37 OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS << 16 | in upload_sampler_state_pointers()
42 OUT_BATCH(brw->vs.base.sampler_offset); /* VS */ in upload_sampler_state_pointers()
43 OUT_BATCH(brw->gs.base.sampler_offset); /* GS */ in upload_sampler_state_pointers()
44 OUT_BATCH(brw->wm.base.sampler_offset); in upload_sampler_state_pointers()
Dbrw_state_upload.c129 OUT_BATCH(_3DSTATE_SLICE_TABLE_STATE_POINTERS << 16 | (2 - 2)); in brw_upload_gfx11_slice_hashing_state()
146 OUT_BATCH(_3DSTATE_3D_MODE << 16 | (2 - 2)); in brw_upload_gfx11_slice_hashing_state()
147 OUT_BATCH(0xffff0000 | SLICE_HASHING_TABLE_ENABLE); in brw_upload_gfx11_slice_hashing_state()
220 OUT_BATCH(_3DSTATE_WM_HZ_OP << 16 | (5 - 2)); in brw_upload_initial_gpu_state()
221 OUT_BATCH(0); in brw_upload_initial_gpu_state()
222 OUT_BATCH(0); in brw_upload_initial_gpu_state()
223 OUT_BATCH(0); in brw_upload_initial_gpu_state()
224 OUT_BATCH(0); in brw_upload_initial_gpu_state()
228 OUT_BATCH(_3DSTATE_WM_CHROMAKEY << 16 | (2 - 2)); in brw_upload_initial_gpu_state()
229 OUT_BATCH(0); in brw_upload_initial_gpu_state()
[all …]
Dbrw_curbe.c169 OUT_BATCH(CMD_CS_URB_STATE << 16 | (2-2)); in brw_upload_cs_urb_state()
173 OUT_BATCH(0); in brw_upload_cs_urb_state()
177 OUT_BATCH((brw->urb.csize - 1) << 4 | brw->urb.nr_cs_entries); in brw_upload_cs_urb_state()
308 OUT_BATCH((CMD_CONST_BUFFER << 16) | (2 - 2)); in brw_upload_constant_buffer()
309 OUT_BATCH(0); in brw_upload_constant_buffer()
311 OUT_BATCH((CMD_CONST_BUFFER << 16) | (1 << 8) | (2 - 2)); in brw_upload_constant_buffer()
337 OUT_BATCH(_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP << 16 | (2 - 2)); in brw_upload_constant_buffer()
338 OUT_BATCH(0); in brw_upload_constant_buffer()
Dgfx7_sol_state.c114 OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2)); in gfx7_pause_transform_feedback()
115 OUT_BATCH(GFX7_SO_WRITE_OFFSET(i)); in gfx7_pause_transform_feedback()
141 OUT_BATCH(GFX7_MI_LOAD_REGISTER_MEM | (3 - 2)); in gfx7_resume_transform_feedback()
142 OUT_BATCH(GFX7_SO_WRITE_OFFSET(i)); in gfx7_resume_transform_feedback()
/third_party/mesa3d/src/gallium/drivers/i915/
Di915_clear.c134 OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT); in i915_clear_emit()
136 OUT_BATCH(_3DSTATE_CLEAR_PARAMETERS); in i915_clear_emit()
137 OUT_BATCH(CLEARPARAM_WRITE_COLOR | CLEARPARAM_CLEAR_RECT); in i915_clear_emit()
139 OUT_BATCH(clear_color); in i915_clear_emit()
140 OUT_BATCH(clear_depth); in i915_clear_emit()
142 OUT_BATCH(clear_color8888); in i915_clear_emit()
144 OUT_BATCH(clear_stencil); in i915_clear_emit()
146 OUT_BATCH(_3DPRIMITIVE | PRIM3D_CLEAR_RECT | 5); in i915_clear_emit()
154 OUT_BATCH(_3DSTATE_CLEAR_PARAMETERS); in i915_clear_emit()
155 OUT_BATCH((clear_params & ~CLEARPARAM_WRITE_COLOR) | in i915_clear_emit()
[all …]
Di915_state_emit.c66 OUT_BATCH(MI_FLUSH | FLUSH_MAP_CACHE); in emit_flush()
68 OUT_BATCH(MI_FLUSH | INHIBIT_FLUSH_RENDER_CACHE); in emit_flush()
142 OUT_BATCH(imm); in emit_immediate_s5()
157 OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | dirty << 4 | (num - 1)); in emit_immediate()
164 OUT_BATCH(0); in emit_immediate()
172 OUT_BATCH(i915->current.immediate[i]); in emit_immediate()
190 OUT_BATCH(i915->current.dynamic[i]); in emit_dynamic()
222 OUT_BATCH(_3DSTATE_BUF_INFO_CMD); in emit_static()
223 OUT_BATCH(i915->current.cbuf_flags); in emit_static()
230 OUT_BATCH(_3DSTATE_BUF_INFO_CMD); in emit_static()
[all …]
Di915_blit.c68 OUT_BATCH(CMD); in i915_fill_blit()
69 OUT_BATCH(BR13); in i915_fill_blit()
70 OUT_BATCH((y << 16) | x); in i915_fill_blit()
71 OUT_BATCH(((y + h) << 16) | (x + w)); in i915_fill_blit()
73 OUT_BATCH(color); in i915_fill_blit()
131 OUT_BATCH(CMD); in i915_copy_blit()
132 OUT_BATCH(BR13); in i915_copy_blit()
133 OUT_BATCH((dst_y << 16) | dst_x); in i915_copy_blit()
134 OUT_BATCH((dst_y2 << 16) | dst_x2); in i915_copy_blit()
136 OUT_BATCH((src_y << 16) | src_x); in i915_copy_blit()
[all …]
Di915_prim_emit.c77 OUT_BATCH(fui(attrib[0])); in emit_hw_vertex()
81 OUT_BATCH(fui(attrib[0])); in emit_hw_vertex()
82 OUT_BATCH(fui(attrib[1])); in emit_hw_vertex()
86 OUT_BATCH(fui(attrib[0])); in emit_hw_vertex()
87 OUT_BATCH(fui(attrib[1])); in emit_hw_vertex()
88 OUT_BATCH(fui(attrib[2])); in emit_hw_vertex()
92 OUT_BATCH(fui(attrib[0])); in emit_hw_vertex()
93 OUT_BATCH(fui(attrib[1])); in emit_hw_vertex()
94 OUT_BATCH(fui(attrib[2])); in emit_hw_vertex()
95 OUT_BATCH(fui(attrib[3])); in emit_hw_vertex()
[all …]
Di915_prim_vbuf.c357 OUT_BATCH((i + 0) | (i + 1) << 16); in draw_arrays_generate_indices()
359 OUT_BATCH(i); in draw_arrays_generate_indices()
364 OUT_BATCH((i - 1) | (i + 0) << 16); in draw_arrays_generate_indices()
365 OUT_BATCH((i - 1) | (start) << 16); in draw_arrays_generate_indices()
370 OUT_BATCH((i + 0) | (i + 1) << 16); in draw_arrays_generate_indices()
371 OUT_BATCH((i + 3) | (i + 1) << 16); in draw_arrays_generate_indices()
372 OUT_BATCH((i + 2) | (i + 3) << 16); in draw_arrays_generate_indices()
377 OUT_BATCH((i + 0) | (i + 1) << 16); in draw_arrays_generate_indices()
378 OUT_BATCH((i + 3) | (i + 2) << 16); in draw_arrays_generate_indices()
379 OUT_BATCH((i + 0) | (i + 3) << 16); in draw_arrays_generate_indices()
[all …]
/third_party/mesa3d/src/mesa/drivers/dri/i915/
Di830_vtbl.c304 OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD); in i830_emit_invarient_state()
305 OUT_BATCH(0); in i830_emit_invarient_state()
307 OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD); in i830_emit_invarient_state()
308 OUT_BATCH(0); in i830_emit_invarient_state()
310 OUT_BATCH(_3DSTATE_DFLT_Z_CMD); in i830_emit_invarient_state()
311 OUT_BATCH(0); in i830_emit_invarient_state()
313 OUT_BATCH(_3DSTATE_FOG_MODE_CMD); in i830_emit_invarient_state()
314 OUT_BATCH(FOGFUNC_ENABLE | in i830_emit_invarient_state()
316 OUT_BATCH(0); in i830_emit_invarient_state()
317 OUT_BATCH(0); in i830_emit_invarient_state()
[all …]
Di915_vtbl.c180 OUT_BATCH(_3DSTATE_AA_CMD | in i915_emit_invarient_state()
185 OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD); in i915_emit_invarient_state()
186 OUT_BATCH(0); in i915_emit_invarient_state()
188 OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD); in i915_emit_invarient_state()
189 OUT_BATCH(0); in i915_emit_invarient_state()
191 OUT_BATCH(_3DSTATE_DFLT_Z_CMD); in i915_emit_invarient_state()
192 OUT_BATCH(0); in i915_emit_invarient_state()
195 OUT_BATCH(_3DSTATE_COORD_SET_BINDINGS | in i915_emit_invarient_state()
202 OUT_BATCH(_3DSTATE_SCISSOR_RECT_0_CMD); in i915_emit_invarient_state()
203 OUT_BATCH(0); in i915_emit_invarient_state()
[all …]
Dintel_blit.c182 OUT_BATCH(CMD | (8 - 2)); in emit_copy_blit()
183 OUT_BATCH(BR13 | (uint16_t)dst_pitch); in emit_copy_blit()
184 OUT_BATCH((dst_y << 16) | dst_x); in emit_copy_blit()
185 OUT_BATCH((dst_y2 << 16) | dst_x2); in emit_copy_blit()
189 OUT_BATCH((src_y << 16) | src_x); in emit_copy_blit()
190 OUT_BATCH((uint16_t)src_pitch); in emit_copy_blit()
476 OUT_BATCH(CMD | (6 - 2)); in intelClearWithBlit()
477 OUT_BATCH(BR13); in intelClearWithBlit()
478 OUT_BATCH((y1 << 16) | x1); in intelClearWithBlit()
479 OUT_BATCH((y2 << 16) | x2); in intelClearWithBlit()
[all …]
/third_party/mesa3d/src/mesa/drivers/dri/radeon/
Dradeon_ioctl.c101 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 0)); in radeonEmitScissor()
102 OUT_BATCH(rmesa->hw.ctx.cmd[CTX_PP_CNTL] | RADEON_SCISSOR_ENABLE); in radeonEmitScissor()
103 OUT_BATCH(CP_PACKET0(RADEON_RE_TOP_LEFT, 0)); in radeonEmitScissor()
104 OUT_BATCH((rmesa->radeon.state.scissor.rect.y1 << 16) | in radeonEmitScissor()
106 OUT_BATCH(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0)); in radeonEmitScissor()
107 OUT_BATCH(((rmesa->radeon.state.scissor.rect.y2) << 16) | in radeonEmitScissor()
112 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 0)); in radeonEmitScissor()
113 OUT_BATCH(rmesa->hw.ctx.cmd[CTX_PP_CNTL] & ~RADEON_SCISSOR_ENABLE); in radeonEmitScissor()
136 OUT_BATCH(rmesa->ioctl.vertex_offset); in radeonEmitVbufPrim()
138 OUT_BATCH(vertex_nr); in radeonEmitVbufPrim()
[all …]
Dradeon_state_init.c243 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
244 OUT_BATCH(0); \
245 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
246 OUT_BATCH(h.vectors.offset | (h.vectors.stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \
247 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, h.vectors.count - 1)); \
254 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \
255 OUT_BATCH((h.scalars.offset) | (h.scalars.stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); \
256 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_SCALAR_DATA_REG, h.scalars.count - 1)); \
375 OUT_BATCH(CP_PACKET0(packet[0].start, 3)); in ctx_emit_cs()
379 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHOFFSET, 0)); in ctx_emit_cs()
[all …]
/third_party/mesa3d/src/mesa/drivers/dri/r200/
Dr200_cmdbuf.c132 OUT_BATCH(primitive | R200_VF_PRIM_WALK_LIST | R200_VF_COLOR_ORDER_RGBA | in r200EmitVbufPrim()
144 OUT_BATCH(R200_VF_PRIM_WALK_IND | in r200FireEB()
150 OUT_BATCH((0x80 << 24) | (0 << 16) | 0x810); in r200FireEB()
151 OUT_BATCH(rmesa->radeon.tcl.elt_dma_offset); in r200FireEB()
152 OUT_BATCH((vertex_count + 1)/2); in r200FireEB()
215 OUT_BATCH(CP_PACKET0(R200_SE_VF_MAX_VTX_INDX, 0)); in r200EmitMaxVtxIndex()
216 OUT_BATCH(count); in r200EmitMaxVtxIndex()
233 OUT_BATCH(1); in r200EmitVertexAOS()
234 OUT_BATCH(vertex_size | (vertex_size << 8)); in r200EmitVertexAOS()
252 OUT_BATCH(nr); in r200EmitAOS()
[all …]

12