Home
last modified time | relevance | path

Searched refs:PIPE_CONTROL_STATE_CACHE_INVALIDATE (Results 1 – 12 of 12) sorted by relevance

/third_party/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_pipe_control.h63 PIPE_CONTROL_STATE_CACHE_INVALIDATE = (1 << 22), enumerator
73 (PIPE_CONTROL_STATE_CACHE_INVALIDATE | PIPE_CONTROL_CONST_CACHE_INVALIDATE | \
DgenX_pipe_control.c224 (flags & PIPE_CONTROL_STATE_CACHE_INVALIDATE)) { in genX()
486 flags & PIPE_CONTROL_STATE_CACHE_INVALIDATE; in genX()
Dbrw_misc_state.c539 PIPE_CONTROL_STATE_CACHE_INVALIDATE | in brw_emit_select_pipeline()
896 PIPE_CONTROL_STATE_CACHE_INVALIDATE | in brw_upload_state_base_address()
Dgfx7_l3_state.c109 PIPE_CONTROL_STATE_CACHE_INVALIDATE); in setup_l3_config()
Dbrw_mipmap_tree.c3217 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_STATE_CACHE_INVALIDATE); in brw_miptree_set_clear_color()
DgenX_state_upload.c2229 PIPE_CONTROL_STATE_CACHE_INVALIDATE);
/third_party/mesa3d/src/gallium/drivers/crocus/
Dcrocus_pipe_control.c292 PIPE_CONTROL_STATE_CACHE_INVALIDATE); in crocus_flush_all_caches()
Dcrocus_context.h256 PIPE_CONTROL_STATE_CACHE_INVALIDATE = (1 << 22), enumerator
268 (PIPE_CONTROL_STATE_CACHE_INVALIDATE | \
Dcrocus_state.c484 PIPE_CONTROL_STATE_CACHE_INVALIDATE); in flush_after_state_base_change()
1103 PIPE_CONTROL_STATE_CACHE_INVALIDATE); in setup_l3_config()
1261 PIPE_CONTROL_STATE_CACHE_INVALIDATE | in emit_pipeline_select()
6811 PIPE_CONTROL_STATE_CACHE_INVALIDATE);
8601 if (GFX_VER >= 7 && (flags & PIPE_CONTROL_STATE_CACHE_INVALIDATE)) {
8841 (flags & PIPE_CONTROL_STATE_CACHE_INVALIDATE) ? "State " : "",
8874 flags & PIPE_CONTROL_STATE_CACHE_INVALIDATE;
/third_party/mesa3d/src/gallium/drivers/iris/
Diris_pipe_control.c304 PIPE_CONTROL_STATE_CACHE_INVALIDATE); in iris_flush_all_caches()
Diris_context.h336 PIPE_CONTROL_STATE_CACHE_INVALIDATE = (1 << 22), enumerator
350 (PIPE_CONTROL_STATE_CACHE_INVALIDATE | \
Diris_state.c470 PIPE_CONTROL_STATE_CACHE_INVALIDATE); in flush_after_state_base_change()
665 PIPE_CONTROL_STATE_CACHE_INVALIDATE | in emit_pipeline_select()
4734 PIPE_CONTROL_STATE_CACHE_INVALIDATE); in surf_state_update_clear_value()
7609 if (GFX_VER <= 8 && (flags & PIPE_CONTROL_STATE_CACHE_INVALIDATE)) { in iris_emit_raw_pipe_control()
7823 (flags & PIPE_CONTROL_STATE_CACHE_INVALIDATE) ? "State " : "", in iris_emit_raw_pipe_control()
7863 flags & PIPE_CONTROL_STATE_CACHE_INVALIDATE; in iris_emit_raw_pipe_control()