Searched refs:__IOM (Results 1 – 15 of 15) sorted by relevance
203 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ macro355 __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */357 …__IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */359 __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */361 …__IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register …363 __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */365 …__IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Regist…367 __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */386 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis…388 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */[all …]
288 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ macro470 __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */472 …__IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */474 __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */476 …__IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register …478 __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */480 …__IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Regist…482 …__IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit…507 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis…508 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */[all …]
180 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ macro347 __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */349 …__IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */351 __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */353 …__IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register …355 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */357 …__IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit…382 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis…383 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */384 …__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset C…[all …]
232 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ macro413 __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */415 …__IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */417 __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */419 …__IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register …421 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */423 …__IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit…448 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis…449 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */450 …__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset C…[all …]
247 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ macro428 __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */430 …__IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */432 __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */434 …__IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register …436 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */438 …__IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit…463 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis…464 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */465 …__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset C…[all …]
295 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ macro477 __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */479 …__IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */481 __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */483 …__IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register …485 __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */487 …__IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Regist…489 …__IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit…514 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis…515 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */[all …]
180 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ macro327 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */329 …__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */331 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */333 …__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register …336 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */355 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis…356 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */357 …__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset C…358 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */[all …]
180 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ macro330 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */332 …__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */334 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */336 …__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register …339 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */358 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis…360 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */364 …__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset C…365 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */[all …]
170 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ macro316 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */318 …__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */320 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */322 …__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register …325 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */344 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis…346 …__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset C…347 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */348 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */[all …]