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Searched refs:b1001 (Results 1 – 25 of 25) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td67 def : AT<"S1E1RP", 0b000, 0b0111, 0b1001, 0b000>;
68 def : AT<"S1E1WP", 0b000, 0b0111, 0b1001, 0b001>;
559 def : ROSysReg<"PMCEID0_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b110>;
560 def : ROSysReg<"PMCEID1_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b111>;
627 def : ROSysReg<"TRCIDR1", 0b10, 0b001, 0b0000, 0b1001, 0b111>;
648 def : ROSysReg<"TRCPIDR1", 0b10, 0b001, 0b0111, 0b1001, 0b111>;
708 def : WOSysReg<"PMSWINC_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b100>;
746 def : RWSysReg<"DBGBVR9_EL1", 0b10, 0b000, 0b0000, 0b1001, 0b100>;
762 def : RWSysReg<"DBGBCR9_EL1", 0b10, 0b000, 0b0000, 0b1001, 0b101>;
778 def : RWSysReg<"DBGWVR9_EL1", 0b10, 0b000, 0b0000, 0b1001, 0b110>;
[all …]
DAArch64SVEInstrInfo.td202 defm FSCALE_ZPmZ : sve_fp_2op_p_zds_fscale<0b1001, "fscale", int_aarch64_sve_fscale>;
321 defm ORN_PPzPP : sve_int_pred_log<0b1001, "orn", int_aarch64_sve_orn_z>;
351 defm LD1SH_S_IMM : sve_mem_cld_si<0b1001, "ld1sh", Z_s, ZPR32>;
397 defm LD1SH_S : sve_mem_cld_ss<0b1001, "ld1sh", Z_s, ZPR32, GPR64NoXZRshifted16>;
415 defm LDNF1SH_S_IMM : sve_mem_cldnf_si<0b1001, "ldnf1sh", Z_s, ZPR32>;
433 defm LDFF1SH_S : sve_mem_cldff_ss<0b1001, "ldff1sh", Z_s, ZPR32, GPR64shifted16>;
515 …defm GLDFF1SW_D : sve_mem_64b_gld_vi_64_ptrs<0b1001, "ldff1sw", uimm5s4, null_frag, …
532 …defm GLDFF1SW_D : sve_mem_64b_gld_vs2_64_unscaled<0b1001, "ldff1sw", null_frag, nxv2i32>;
545 …defm GLDFF1SW_D : sve_mem_64b_gld_sv2_64_scaled<0b1001, "ldff1sw", null_frag, ZP…
562 …defm GLDFF1SW_D : sve_mem_64b_gld_vs_32_unscaled<0b1001, "ldff1sw", null_frag, nul…
[all …]
DSVEInstrFormats.td1869 def _HtoS : sve2_fp_convert_precision<0b1001, asm, ZPR32, ZPR16>;
4505 let Inst{15-12} = 0b1001;
5375 let Inst{21-18} = 0b1001;
DAArch64InstrInfo.td3426 defm FRINTP : SingleOperandFPData<0b1001, "frintp", fceil>;
4495 defm SQDMLAL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1001, "sqdmlal",
5604 defm FMULX : SIMDFPIndexed<1, 0b1001, "fmulx", int_aarch64_neon_fmulx>;
5605 defm FMUL : SIMDFPIndexed<0, 0b1001, "fmul", fmul>;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/
DMSP430InstrInfo.td732 def CMP8rr : I8rr<0b1001,
736 def CMP16rr : I16rr<0b1001,
741 def CMP8rc : I8rc<0b1001,
745 def CMP16rc : I16rc<0b1001,
750 def CMP8ri : I8ri<0b1001,
754 def CMP16ri : I16ri<0b1001,
759 def CMP8mc : I8mc<0b1001,
764 def CMP16mc : I16mc<0b1001,
770 def CMP8mi : I8mi<0b1001,
775 def CMP16mi : I16mi<0b1001,
[all …]
/third_party/vk-gl-cts/external/vulkancts/modules/vulkan/conditional_rendering/
DvktConditionalDrawAndClearTests.cpp136 b1001 = 0x9, enumerator
155 { true, true, true, b1001, b1001, b0110, false, NONE },
157 { true, true, true, b1001, b1001, b1111, true, FILL },
158 { false, true, true, b1001, b1001, b0110, true, FILL },
160 { true, true, true, b1001, b1001, b1111, true, COPY },
161 { false, true, true, b1001, b1001, b0110, true, COPY },
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/
DAVRInstrFormats.td103 let Inst{15-12} = 0b1001;
228 let Inst{15-12} = 0b1001;
368 let Inst{15-12} = 0b1001;
414 let Inst{15-12} = 0b1001;
500 let Inst{31-28} = 0b1001;
519 let Inst{15-12} = 0b1001;
DAVRInstrInfo.td524 def INCRd : FRd<0b1001,
531 def DECRd : FRd<0b1001,
549 def MULRdRr : FRdRr<0b1001, 0b11,
712 def COMRd : FRd<0b1001,
730 def NEGRd : FRd<0b1001,
1572 def PUSHRr : FRd<0b1001,
1590 def POPRd : FRd<0b1001,
1650 def LSRRd : FRd<0b1001,
1662 def ASRRd : FRd<0b1001,
1694 def RORRd : FRd<0b1001,
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
DSparcInstrAliases.td270 defm : int_cond_alias<"ne", 0b1001>;
287 defm : int_cond_alias<"nz", 0b1001>; // same as ne
302 defm : fp_cond_alias<"e", 0b1001>;
313 defm : fp_cond_alias<"z", 0b1001>; // same as e
325 defm : cp_cond_alias<"0", 0b1001>;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrVFP.td1250 def VMOVRH : AVConv2I<0b11100001, 0b1001,
1272 def VMOVHR : AVConv4I<0b11100000, 0b1001,
1391 def VSITOH : AVConv1IHs_Encode<0b11101, 0b11, 0b1000, 0b1001,
1437 def VUITOH : AVConv1IHs_Encode<0b11101, 0b11, 0b1000, 0b1001,
1542 def VTOSIZH : AVConv1IsH_Encode<0b11101, 0b11, 0b1101, 0b1001,
1589 def VTOUIZH : AVConv1IsH_Encode<0b11101, 0b11, 0b1100, 0b1001,
1619 def VTOSIRH : AVConv1IsH_Encode<0b11101, 0b11, 0b1101, 0b1001,
1644 def VTOUIRH : AVConv1IsH_Encode<0b11101, 0b11, 0b1100, 0b1001,
1655 def VJCVT : AVConv1IsD_Encode<0b11101, 0b11, 0b1001, 0b1011,
1700 def VTOSHH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1001, 0,
[all …]
DARMInstrNEON.td872 def VLD2b8 : VLD2<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VLD2,
874 def VLD2b16 : VLD2<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VLD2,
876 def VLD2b32 : VLD2<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VLD2,
878 defm VLD2b8wb : VLD2WB<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VLD2u,
880 defm VLD2b16wb : VLD2WB<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VLD2u,
882 defm VLD2b32wb : VLD2WB<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VLD2u,
1157 def VLD2LNd32 : VLD2LN<0b1001, {?,0,0,?}, "32"> {
1169 def VLD2LNq32 : VLD2LN<0b1001, {?,1,0,?}, "32"> {
1193 def VLD2LNd32_UPD : VLD2LNWB<0b1001, {?,0,0,?}, "32"> {
1204 def VLD2LNq32_UPD : VLD2LNWB<0b1001, {?,1,0,?}, "32"> {
[all …]
DARMInstrFormats.td674 let Inst{7-4} = 0b1001;
937 let Inst{7-4} = 0b1001;
945 let Inst{7-4} = 0b1001;
1278 class T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative
1653 let Inst{11-8} = 0b1001; // Half precision
2003 let Inst{11-8} = 0b1001; // Half precision
2033 let Inst{11-8} = 0b1001; // Half precision
2061 let Inst{11-8} = 0b1001; // Half precision
2092 let Inst{11-8} = 0b1001; // Half precision
DARMInstrThumb.td1282 T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn),
DARMInstrThumb2.td2432 def t2QDADD : T2I_pam_intrinsics_rev<0b000, 0b1001, "qdadd">;
3045 def t2SMLALBT : T2MlaLong<0b100, 0b1001, "smlalbt">,
5400 def t2CSINC : CS<"csinc", 0b1001>;
DARMInstrMVE.td1412 def MVE_VORRIZ0v8i16 : MVE_VORR<"i16", 0b1001, expzero00>;
1441 def MVE_VBICIZ0v8i16 : MVE_VBIC<"i16", 0b1001, expzero00>;
DARMInstrInfo.td4785 defm TEQ : AI1_cmp_irs<0b1001, "teq",
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVInstrInfoC.td528 def C_EBREAK : RVInst16CR<0b1001, 0b10, (outs), (ins), "c.ebreak", "">, Sched<[]>;
532 def C_JALR : RVInst16CR<0b1001, 0b10, (outs), (ins GPRNoX0:$rs1),
536 def C_ADD : RVInst16CR<0b1001, 0b10, (outs GPRNoX0:$rs1_wb),
639 def C_ADD_HINT : RVInst16CR<0b1001, 0b10, (outs GPRX0:$rs1_wb),
/third_party/mesa3d/src/gallium/drivers/freedreno/a3xx/
Dfd3_program.c390 unsigned mask = coord_mode ? 0b1101 : 0b1001; in fd3_program_emit()
/third_party/mesa3d/src/gallium/drivers/freedreno/a4xx/
Dfd4_program.c509 unsigned mask = coord_mode ? 0b1101 : 0b1001; in fd4_program_emit()
/third_party/mesa3d/src/gallium/drivers/freedreno/a5xx/
Dfd5_program.c652 unsigned mask = coord_mode ? 0b1101 : 0b1001; in fd5_program_emit()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td767 class FSOR_W_ENC : MSA_3RF_FMT<0b1001, 0b0, 0b011100>;
768 class FSOR_D_ENC : MSA_3RF_FMT<0b1001, 0b1, 0b011100>;
785 class FSUN_W_ENC : MSA_3RF_FMT<0b1001, 0b0, 0b011010>;
786 class FSUN_D_ENC : MSA_3RF_FMT<0b1001, 0b1, 0b011010>;
1077 class ST_B_ENC : MSA_MI10_FMT<0b00, 0b1001>;
1078 class ST_H_ENC : MSA_MI10_FMT<0b01, 0b1001>;
1079 class ST_W_ENC : MSA_MI10_FMT<0b10, 0b1001>;
1080 class ST_D_ENC : MSA_MI10_FMT<0b11, 0b1001>;
DMicroMips32r6InstrInfo.td210 class OR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1001>;
/third_party/mesa3d/src/gallium/drivers/freedreno/a6xx/
Dfd6_program.c1150 unsigned mask = coord_mode ? 0b1101 : 0b1001; in emit_interp_state()
/third_party/openssl/crypto/perlasm/
Dsparcv9_modes.pl1611 my %desopf = ( "des_round" => 0b1001,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonDepInstrInfo.td2689 let Inst{13-10} = 0b1001;
2745 let Inst{13-10} = 0b1001;
2801 let Inst{13-10} = 0b1001;
2857 let Inst{13-10} = 0b1001;
2913 let Inst{13-10} = 0b1001;
2969 let Inst{13-10} = 0b1001;
9782 let Inst{24-21} = 0b1001;
9888 let Inst{24-21} = 0b1001;
17652 let Inst{24-21} = 0b1001;
30120 let Inst{13-10} = 0b1001;