1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "pipe/p_state.h"
28 #include "util/bitset.h"
29 #include "util/format/u_format.h"
30 #include "util/u_inlines.h"
31 #include "util/u_memory.h"
32 #include "util/u_string.h"
33
34 #include "freedreno_program.h"
35
36 #include "fd5_emit.h"
37 #include "fd5_format.h"
38 #include "fd5_program.h"
39 #include "fd5_texture.h"
40
41 #include "ir3_cache.h"
42
43 void
fd5_emit_shader(struct fd_ringbuffer * ring,const struct ir3_shader_variant * so)44 fd5_emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
45 {
46 const struct ir3_info *si = &so->info;
47 enum a4xx_state_block sb = fd4_stage2shadersb(so->type);
48 enum a4xx_state_src src;
49 uint32_t i, sz, *bin;
50
51 if (FD_DBG(DIRECT)) {
52 sz = si->sizedwords;
53 src = SS4_DIRECT;
54 bin = fd_bo_map(so->bo);
55 } else {
56 sz = 0;
57 src = SS4_INDIRECT;
58 bin = NULL;
59 }
60
61 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + sz);
62 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
63 CP_LOAD_STATE4_0_STATE_SRC(src) |
64 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
65 CP_LOAD_STATE4_0_NUM_UNIT(so->instrlen));
66 if (bin) {
67 OUT_RING(ring, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
68 CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER));
69 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
70 } else {
71 OUT_RELOC(ring, so->bo, 0, CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER), 0);
72 }
73
74 /* for how clever coverity is, it is sometimes rather dull, and
75 * doesn't realize that the only case where bin==NULL, sz==0:
76 */
77 assume(bin || (sz == 0));
78
79 for (i = 0; i < sz; i++) {
80 OUT_RING(ring, bin[i]);
81 }
82 }
83
84 /* TODO maybe some of this we could pre-compute once rather than having
85 * so much draw-time logic?
86 */
87 static void
emit_stream_out(struct fd_ringbuffer * ring,const struct ir3_shader_variant * v,struct ir3_shader_linkage * l)88 emit_stream_out(struct fd_ringbuffer *ring, const struct ir3_shader_variant *v,
89 struct ir3_shader_linkage *l)
90 {
91 const struct ir3_stream_output_info *strmout = &v->shader->stream_output;
92 unsigned ncomp[PIPE_MAX_SO_BUFFERS] = {0};
93 unsigned prog[align(l->max_loc, 2) / 2];
94
95 memset(prog, 0, sizeof(prog));
96
97 for (unsigned i = 0; i < strmout->num_outputs; i++) {
98 const struct ir3_stream_output *out = &strmout->output[i];
99 unsigned k = out->register_index;
100 unsigned idx;
101
102 ncomp[out->output_buffer] += out->num_components;
103
104 /* linkage map sorted by order frag shader wants things, so
105 * a bit less ideal here..
106 */
107 for (idx = 0; idx < l->cnt; idx++)
108 if (l->var[idx].regid == v->outputs[k].regid)
109 break;
110
111 debug_assert(idx < l->cnt);
112
113 for (unsigned j = 0; j < out->num_components; j++) {
114 unsigned c = j + out->start_component;
115 unsigned loc = l->var[idx].loc + c;
116 unsigned off = j + out->dst_offset; /* in dwords */
117
118 if (loc & 1) {
119 prog[loc / 2] |= A5XX_VPC_SO_PROG_B_EN |
120 A5XX_VPC_SO_PROG_B_BUF(out->output_buffer) |
121 A5XX_VPC_SO_PROG_B_OFF(off * 4);
122 } else {
123 prog[loc / 2] |= A5XX_VPC_SO_PROG_A_EN |
124 A5XX_VPC_SO_PROG_A_BUF(out->output_buffer) |
125 A5XX_VPC_SO_PROG_A_OFF(off * 4);
126 }
127 }
128 }
129
130 OUT_PKT7(ring, CP_CONTEXT_REG_BUNCH, 12 + (2 * ARRAY_SIZE(prog)));
131 OUT_RING(ring, REG_A5XX_VPC_SO_BUF_CNTL);
132 OUT_RING(ring, A5XX_VPC_SO_BUF_CNTL_ENABLE |
133 COND(ncomp[0] > 0, A5XX_VPC_SO_BUF_CNTL_BUF0) |
134 COND(ncomp[1] > 0, A5XX_VPC_SO_BUF_CNTL_BUF1) |
135 COND(ncomp[2] > 0, A5XX_VPC_SO_BUF_CNTL_BUF2) |
136 COND(ncomp[3] > 0, A5XX_VPC_SO_BUF_CNTL_BUF3));
137 OUT_RING(ring, REG_A5XX_VPC_SO_NCOMP(0));
138 OUT_RING(ring, ncomp[0]);
139 OUT_RING(ring, REG_A5XX_VPC_SO_NCOMP(1));
140 OUT_RING(ring, ncomp[1]);
141 OUT_RING(ring, REG_A5XX_VPC_SO_NCOMP(2));
142 OUT_RING(ring, ncomp[2]);
143 OUT_RING(ring, REG_A5XX_VPC_SO_NCOMP(3));
144 OUT_RING(ring, ncomp[3]);
145 OUT_RING(ring, REG_A5XX_VPC_SO_CNTL);
146 OUT_RING(ring, A5XX_VPC_SO_CNTL_ENABLE);
147 for (unsigned i = 0; i < ARRAY_SIZE(prog); i++) {
148 OUT_RING(ring, REG_A5XX_VPC_SO_PROG);
149 OUT_RING(ring, prog[i]);
150 }
151 }
152
153 struct stage {
154 const struct ir3_shader_variant *v;
155 const struct ir3_info *i;
156 /* const sizes are in units of 4 * vec4 */
157 uint8_t constoff;
158 uint8_t constlen;
159 /* instr sizes are in units of 16 instructions */
160 uint8_t instroff;
161 uint8_t instrlen;
162 };
163
164 enum { VS = 0, FS = 1, HS = 2, DS = 3, GS = 4, MAX_STAGES };
165
166 static void
setup_stages(struct fd5_emit * emit,struct stage * s)167 setup_stages(struct fd5_emit *emit, struct stage *s)
168 {
169 unsigned i;
170
171 s[VS].v = fd5_emit_get_vp(emit);
172 s[FS].v = fd5_emit_get_fp(emit);
173
174 s[HS].v = s[DS].v = s[GS].v = NULL; /* for now */
175
176 for (i = 0; i < MAX_STAGES; i++) {
177 if (s[i].v) {
178 s[i].i = &s[i].v->info;
179 /* constlen is in units of 4 * vec4: */
180 assert(s[i].v->constlen % 4 == 0);
181 s[i].constlen = s[i].v->constlen / 4;
182 /* instrlen is already in units of 16 instr.. although
183 * probably we should ditch that and not make the compiler
184 * care about instruction group size of a3xx vs a5xx
185 */
186 s[i].instrlen = s[i].v->instrlen;
187 } else {
188 s[i].i = NULL;
189 s[i].constlen = 0;
190 s[i].instrlen = 0;
191 }
192 }
193
194 /* NOTE: at least for gles2, blob partitions VS at bottom of const
195 * space and FS taking entire remaining space. We probably don't
196 * need to do that the same way, but for now mimic what the blob
197 * does to make it easier to diff against register values from blob
198 *
199 * NOTE: if VS.instrlen + FS.instrlen > 64, then one or both shaders
200 * is run from external memory.
201 */
202 if ((s[VS].instrlen + s[FS].instrlen) > 64) {
203 /* prioritize FS for internal memory: */
204 if (s[FS].instrlen < 64) {
205 /* if FS can fit, kick VS out to external memory: */
206 s[VS].instrlen = 0;
207 } else if (s[VS].instrlen < 64) {
208 /* otherwise if VS can fit, kick out FS: */
209 s[FS].instrlen = 0;
210 } else {
211 /* neither can fit, run both from external memory: */
212 s[VS].instrlen = 0;
213 s[FS].instrlen = 0;
214 }
215 }
216
217 unsigned constoff = 0;
218 for (i = 0; i < MAX_STAGES; i++) {
219 s[i].constoff = constoff;
220 constoff += s[i].constlen;
221 }
222
223 s[VS].instroff = 0;
224 s[FS].instroff = 64 - s[FS].instrlen;
225 s[HS].instroff = s[DS].instroff = s[GS].instroff = s[FS].instroff;
226 }
227
228 static inline uint32_t
next_regid(uint32_t reg,uint32_t increment)229 next_regid(uint32_t reg, uint32_t increment)
230 {
231 if (VALIDREG(reg))
232 return reg + increment;
233 else
234 return regid(63, 0);
235 }
236 void
fd5_program_emit(struct fd_context * ctx,struct fd_ringbuffer * ring,struct fd5_emit * emit)237 fd5_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
238 struct fd5_emit *emit)
239 {
240 struct stage s[MAX_STAGES];
241 uint32_t pos_regid, psize_regid, color_regid[8];
242 uint32_t face_regid, coord_regid, zwcoord_regid, samp_id_regid,
243 samp_mask_regid;
244 uint32_t ij_regid[IJ_COUNT], vertex_regid, instance_regid, clip0_regid,
245 clip1_regid;
246 enum a3xx_threadsize fssz;
247 uint8_t psize_loc = ~0;
248 int i, j;
249
250 setup_stages(emit, s);
251
252 bool do_streamout = (s[VS].v->shader->stream_output.num_outputs > 0);
253 uint8_t clip_mask = s[VS].v->clip_mask, cull_mask = s[VS].v->cull_mask;
254 uint8_t clip_cull_mask = clip_mask | cull_mask;
255
256 fssz = (s[FS].i->double_threadsize) ? FOUR_QUADS : TWO_QUADS;
257
258 pos_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_POS);
259 psize_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_PSIZ);
260 clip0_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_CLIP_DIST0);
261 clip1_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_CLIP_DIST1);
262 vertex_regid =
263 ir3_find_sysval_regid(s[VS].v, SYSTEM_VALUE_VERTEX_ID_ZERO_BASE);
264 instance_regid = ir3_find_sysval_regid(s[VS].v, SYSTEM_VALUE_INSTANCE_ID);
265
266 if (s[FS].v->color0_mrt) {
267 color_regid[0] = color_regid[1] = color_regid[2] = color_regid[3] =
268 color_regid[4] = color_regid[5] = color_regid[6] = color_regid[7] =
269 ir3_find_output_regid(s[FS].v, FRAG_RESULT_COLOR);
270 } else {
271 color_regid[0] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA0);
272 color_regid[1] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA1);
273 color_regid[2] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA2);
274 color_regid[3] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA3);
275 color_regid[4] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA4);
276 color_regid[5] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA5);
277 color_regid[6] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA6);
278 color_regid[7] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA7);
279 }
280
281 samp_id_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_SAMPLE_ID);
282 samp_mask_regid =
283 ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_SAMPLE_MASK_IN);
284 face_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_FRONT_FACE);
285 coord_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_FRAG_COORD);
286 zwcoord_regid = next_regid(coord_regid, 2);
287 for (unsigned i = 0; i < ARRAY_SIZE(ij_regid); i++)
288 ij_regid[i] = ir3_find_sysval_regid(
289 s[FS].v, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL + i);
290
291 /* we could probably divide this up into things that need to be
292 * emitted if frag-prog is dirty vs if vert-prog is dirty..
293 */
294
295 OUT_PKT4(ring, REG_A5XX_HLSQ_VS_CONFIG, 5);
296 OUT_RING(ring, A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET(s[VS].constoff) |
297 A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET(s[VS].instroff) |
298 COND(s[VS].v, A5XX_HLSQ_VS_CONFIG_ENABLED));
299 OUT_RING(ring, A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET(s[FS].constoff) |
300 A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET(s[FS].instroff) |
301 COND(s[FS].v, A5XX_HLSQ_FS_CONFIG_ENABLED));
302 OUT_RING(ring, A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET(s[HS].constoff) |
303 A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET(s[HS].instroff) |
304 COND(s[HS].v, A5XX_HLSQ_HS_CONFIG_ENABLED));
305 OUT_RING(ring, A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET(s[DS].constoff) |
306 A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET(s[DS].instroff) |
307 COND(s[DS].v, A5XX_HLSQ_DS_CONFIG_ENABLED));
308 OUT_RING(ring, A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET(s[GS].constoff) |
309 A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET(s[GS].instroff) |
310 COND(s[GS].v, A5XX_HLSQ_GS_CONFIG_ENABLED));
311
312 OUT_PKT4(ring, REG_A5XX_HLSQ_CS_CONFIG, 1);
313 OUT_RING(ring, 0x00000000);
314
315 OUT_PKT4(ring, REG_A5XX_HLSQ_VS_CNTL, 5);
316 OUT_RING(ring, A5XX_HLSQ_VS_CNTL_INSTRLEN(s[VS].instrlen) |
317 COND(s[VS].v && s[VS].v->has_ssbo,
318 A5XX_HLSQ_VS_CNTL_SSBO_ENABLE));
319 OUT_RING(ring, A5XX_HLSQ_FS_CNTL_INSTRLEN(s[FS].instrlen) |
320 COND(s[FS].v && s[FS].v->has_ssbo,
321 A5XX_HLSQ_FS_CNTL_SSBO_ENABLE));
322 OUT_RING(ring, A5XX_HLSQ_HS_CNTL_INSTRLEN(s[HS].instrlen) |
323 COND(s[HS].v && s[HS].v->has_ssbo,
324 A5XX_HLSQ_HS_CNTL_SSBO_ENABLE));
325 OUT_RING(ring, A5XX_HLSQ_DS_CNTL_INSTRLEN(s[DS].instrlen) |
326 COND(s[DS].v && s[DS].v->has_ssbo,
327 A5XX_HLSQ_DS_CNTL_SSBO_ENABLE));
328 OUT_RING(ring, A5XX_HLSQ_GS_CNTL_INSTRLEN(s[GS].instrlen) |
329 COND(s[GS].v && s[GS].v->has_ssbo,
330 A5XX_HLSQ_GS_CNTL_SSBO_ENABLE));
331
332 OUT_PKT4(ring, REG_A5XX_SP_VS_CONFIG, 5);
333 OUT_RING(ring, A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET(s[VS].constoff) |
334 A5XX_SP_VS_CONFIG_SHADEROBJOFFSET(s[VS].instroff) |
335 COND(s[VS].v, A5XX_SP_VS_CONFIG_ENABLED));
336 OUT_RING(ring, A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET(s[FS].constoff) |
337 A5XX_SP_FS_CONFIG_SHADEROBJOFFSET(s[FS].instroff) |
338 COND(s[FS].v, A5XX_SP_FS_CONFIG_ENABLED));
339 OUT_RING(ring, A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET(s[HS].constoff) |
340 A5XX_SP_HS_CONFIG_SHADEROBJOFFSET(s[HS].instroff) |
341 COND(s[HS].v, A5XX_SP_HS_CONFIG_ENABLED));
342 OUT_RING(ring, A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET(s[DS].constoff) |
343 A5XX_SP_DS_CONFIG_SHADEROBJOFFSET(s[DS].instroff) |
344 COND(s[DS].v, A5XX_SP_DS_CONFIG_ENABLED));
345 OUT_RING(ring, A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET(s[GS].constoff) |
346 A5XX_SP_GS_CONFIG_SHADEROBJOFFSET(s[GS].instroff) |
347 COND(s[GS].v, A5XX_SP_GS_CONFIG_ENABLED));
348
349 OUT_PKT4(ring, REG_A5XX_SP_CS_CONFIG, 1);
350 OUT_RING(ring, 0x00000000);
351
352 OUT_PKT4(ring, REG_A5XX_HLSQ_VS_CONSTLEN, 2);
353 OUT_RING(ring, s[VS].constlen); /* HLSQ_VS_CONSTLEN */
354 OUT_RING(ring, s[VS].instrlen); /* HLSQ_VS_INSTRLEN */
355
356 OUT_PKT4(ring, REG_A5XX_HLSQ_FS_CONSTLEN, 2);
357 OUT_RING(ring, s[FS].constlen); /* HLSQ_FS_CONSTLEN */
358 OUT_RING(ring, s[FS].instrlen); /* HLSQ_FS_INSTRLEN */
359
360 OUT_PKT4(ring, REG_A5XX_HLSQ_HS_CONSTLEN, 2);
361 OUT_RING(ring, s[HS].constlen); /* HLSQ_HS_CONSTLEN */
362 OUT_RING(ring, s[HS].instrlen); /* HLSQ_HS_INSTRLEN */
363
364 OUT_PKT4(ring, REG_A5XX_HLSQ_DS_CONSTLEN, 2);
365 OUT_RING(ring, s[DS].constlen); /* HLSQ_DS_CONSTLEN */
366 OUT_RING(ring, s[DS].instrlen); /* HLSQ_DS_INSTRLEN */
367
368 OUT_PKT4(ring, REG_A5XX_HLSQ_GS_CONSTLEN, 2);
369 OUT_RING(ring, s[GS].constlen); /* HLSQ_GS_CONSTLEN */
370 OUT_RING(ring, s[GS].instrlen); /* HLSQ_GS_INSTRLEN */
371
372 OUT_PKT4(ring, REG_A5XX_HLSQ_CS_CONSTLEN, 2);
373 OUT_RING(ring, 0x00000000); /* HLSQ_CS_CONSTLEN */
374 OUT_RING(ring, 0x00000000); /* HLSQ_CS_INSTRLEN */
375
376 OUT_PKT4(ring, REG_A5XX_SP_VS_CTRL_REG0, 1);
377 OUT_RING(
378 ring,
379 A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(s[VS].i->max_half_reg + 1) |
380 A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(s[VS].i->max_reg + 1) |
381 0x6 | /* XXX seems to be always set? */
382 A5XX_SP_VS_CTRL_REG0_BRANCHSTACK(ir3_shader_branchstack_hw(s[VS].v)) |
383 COND(s[VS].v->need_pixlod, A5XX_SP_VS_CTRL_REG0_PIXLODENABLE));
384
385 /* If we have streamout, link against the real FS in the binning program,
386 * rather than the dummy FS used for binning pass state, to ensure the
387 * OUTLOC's match. Depending on whether we end up doing sysmem or gmem, the
388 * actual streamout could happen with either the binning pass or draw pass
389 * program, but the same streamout stateobj is used in either case:
390 */
391 const struct ir3_shader_variant *link_fs = s[FS].v;
392 if (do_streamout && emit->binning_pass)
393 link_fs = emit->prog->fs;
394 struct ir3_shader_linkage l = {0};
395 ir3_link_shaders(&l, s[VS].v, link_fs, true);
396
397 uint8_t clip0_loc = l.clip0_loc;
398 uint8_t clip1_loc = l.clip1_loc;
399
400 OUT_PKT4(ring, REG_A5XX_VPC_VAR_DISABLE(0), 4);
401 OUT_RING(ring, ~l.varmask[0]); /* VPC_VAR[0].DISABLE */
402 OUT_RING(ring, ~l.varmask[1]); /* VPC_VAR[1].DISABLE */
403 OUT_RING(ring, ~l.varmask[2]); /* VPC_VAR[2].DISABLE */
404 OUT_RING(ring, ~l.varmask[3]); /* VPC_VAR[3].DISABLE */
405
406 /* Add stream out outputs after computing the VPC_VAR_DISABLE bitmask. */
407 ir3_link_stream_out(&l, s[VS].v);
408
409 /* a5xx appends pos/psize to end of the linkage map: */
410 if (VALIDREG(pos_regid))
411 ir3_link_add(&l, pos_regid, 0xf, l.max_loc);
412
413 if (VALIDREG(psize_regid)) {
414 psize_loc = l.max_loc;
415 ir3_link_add(&l, psize_regid, 0x1, l.max_loc);
416 }
417
418 /* Handle the case where clip/cull distances aren't read by the FS. Make
419 * sure to avoid adding an output with an empty writemask if the user
420 * disables all the clip distances in the API so that the slot is unused.
421 */
422 if (clip0_loc == 0xff && VALIDREG(clip0_regid) &&
423 (clip_cull_mask & 0xf) != 0) {
424 clip0_loc = l.max_loc;
425 ir3_link_add(&l, clip0_regid, clip_cull_mask & 0xf, l.max_loc);
426 }
427
428 if (clip1_loc == 0xff && VALIDREG(clip1_regid) &&
429 (clip_cull_mask >> 4) != 0) {
430 clip1_loc = l.max_loc;
431 ir3_link_add(&l, clip1_regid, clip_cull_mask >> 4, l.max_loc);
432 }
433
434 /* If we have stream-out, we use the full shader for binning
435 * pass, rather than the optimized binning pass one, so that we
436 * have all the varying outputs available for xfb. So streamout
437 * state should always be derived from the non-binning pass
438 * program:
439 */
440 if (do_streamout && !emit->binning_pass)
441 emit_stream_out(ring, s[VS].v, &l);
442
443 for (i = 0, j = 0; (i < 16) && (j < l.cnt); i++) {
444 uint32_t reg = 0;
445
446 OUT_PKT4(ring, REG_A5XX_SP_VS_OUT_REG(i), 1);
447
448 reg |= A5XX_SP_VS_OUT_REG_A_REGID(l.var[j].regid);
449 reg |= A5XX_SP_VS_OUT_REG_A_COMPMASK(l.var[j].compmask);
450 j++;
451
452 reg |= A5XX_SP_VS_OUT_REG_B_REGID(l.var[j].regid);
453 reg |= A5XX_SP_VS_OUT_REG_B_COMPMASK(l.var[j].compmask);
454 j++;
455
456 OUT_RING(ring, reg);
457 }
458
459 for (i = 0, j = 0; (i < 8) && (j < l.cnt); i++) {
460 uint32_t reg = 0;
461
462 OUT_PKT4(ring, REG_A5XX_SP_VS_VPC_DST_REG(i), 1);
463
464 reg |= A5XX_SP_VS_VPC_DST_REG_OUTLOC0(l.var[j++].loc);
465 reg |= A5XX_SP_VS_VPC_DST_REG_OUTLOC1(l.var[j++].loc);
466 reg |= A5XX_SP_VS_VPC_DST_REG_OUTLOC2(l.var[j++].loc);
467 reg |= A5XX_SP_VS_VPC_DST_REG_OUTLOC3(l.var[j++].loc);
468
469 OUT_RING(ring, reg);
470 }
471
472 OUT_PKT4(ring, REG_A5XX_SP_VS_OBJ_START_LO, 2);
473 OUT_RELOC(ring, s[VS].v->bo, 0, 0, 0); /* SP_VS_OBJ_START_LO/HI */
474
475 if (s[VS].instrlen)
476 fd5_emit_shader(ring, s[VS].v);
477
478 // TODO depending on other bits in this reg (if any) set somewhere else?
479 OUT_PKT4(ring, REG_A5XX_PC_PRIM_VTX_CNTL, 1);
480 OUT_RING(ring, COND(s[VS].v->writes_psize, A5XX_PC_PRIM_VTX_CNTL_PSIZE));
481
482 OUT_PKT4(ring, REG_A5XX_SP_PRIMITIVE_CNTL, 1);
483 OUT_RING(ring, A5XX_SP_PRIMITIVE_CNTL_VSOUT(l.cnt));
484
485 OUT_PKT4(ring, REG_A5XX_VPC_CNTL_0, 1);
486 OUT_RING(ring, A5XX_VPC_CNTL_0_STRIDE_IN_VPC(l.max_loc) |
487 COND(s[FS].v->total_in > 0, A5XX_VPC_CNTL_0_VARYING) |
488 0x10000); // XXX
489
490 fd5_context(ctx)->max_loc = l.max_loc;
491
492 if (emit->binning_pass) {
493 OUT_PKT4(ring, REG_A5XX_SP_FS_OBJ_START_LO, 2);
494 OUT_RING(ring, 0x00000000); /* SP_FS_OBJ_START_LO */
495 OUT_RING(ring, 0x00000000); /* SP_FS_OBJ_START_HI */
496 } else {
497 OUT_PKT4(ring, REG_A5XX_SP_FS_OBJ_START_LO, 2);
498 OUT_RELOC(ring, s[FS].v->bo, 0, 0, 0); /* SP_FS_OBJ_START_LO/HI */
499 }
500
501 OUT_PKT4(ring, REG_A5XX_HLSQ_CONTROL_0_REG, 5);
502 OUT_RING(ring, A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(fssz) |
503 A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE(TWO_QUADS) |
504 0x00000880); /* XXX HLSQ_CONTROL_0 */
505 OUT_RING(ring, A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(63));
506 OUT_RING(ring, A5XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
507 A5XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) |
508 A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(samp_mask_regid) |
509 A5XX_HLSQ_CONTROL_2_REG_SIZE(ij_regid[IJ_PERSP_SIZE]));
510 OUT_RING(
511 ring,
512 A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(ij_regid[IJ_PERSP_PIXEL]) |
513 A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(ij_regid[IJ_LINEAR_PIXEL]) |
514 A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(
515 ij_regid[IJ_PERSP_CENTROID]) |
516 A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(
517 ij_regid[IJ_LINEAR_CENTROID]));
518 OUT_RING(
519 ring,
520 A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
521 A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
522 A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(ij_regid[IJ_PERSP_SAMPLE]) |
523 A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(ij_regid[IJ_LINEAR_SAMPLE]));
524
525 OUT_PKT4(ring, REG_A5XX_SP_FS_CTRL_REG0, 1);
526 OUT_RING(
527 ring,
528 COND(s[FS].v->total_in > 0, A5XX_SP_FS_CTRL_REG0_VARYING) |
529 0x40006 | /* XXX set pretty much everywhere */
530 A5XX_SP_FS_CTRL_REG0_THREADSIZE(fssz) |
531 A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(s[FS].i->max_half_reg + 1) |
532 A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(s[FS].i->max_reg + 1) |
533 A5XX_SP_FS_CTRL_REG0_BRANCHSTACK(ir3_shader_branchstack_hw(s[FS].v)) |
534 COND(s[FS].v->need_pixlod, A5XX_SP_FS_CTRL_REG0_PIXLODENABLE));
535
536 OUT_PKT4(ring, REG_A5XX_HLSQ_UPDATE_CNTL, 1);
537 OUT_RING(ring, 0x020fffff); /* XXX */
538
539 OUT_PKT4(ring, REG_A5XX_VPC_GS_SIV_CNTL, 1);
540 OUT_RING(ring, 0x0000ffff); /* XXX */
541
542 OUT_PKT4(ring, REG_A5XX_SP_SP_CNTL, 1);
543 OUT_RING(ring, 0x00000010); /* XXX */
544
545 OUT_PKT4(ring, REG_A5XX_GRAS_CNTL, 1);
546 OUT_RING(ring,
547 CONDREG(ij_regid[IJ_PERSP_PIXEL], A5XX_GRAS_CNTL_IJ_PERSP_PIXEL) |
548 CONDREG(ij_regid[IJ_PERSP_CENTROID],
549 A5XX_GRAS_CNTL_IJ_PERSP_CENTROID) |
550 CONDREG(ij_regid[IJ_PERSP_SAMPLE],
551 A5XX_GRAS_CNTL_IJ_PERSP_SAMPLE) |
552 CONDREG(ij_regid[IJ_LINEAR_PIXEL], A5XX_GRAS_CNTL_IJ_LINEAR_PIXEL) |
553 CONDREG(ij_regid[IJ_LINEAR_CENTROID],
554 A5XX_GRAS_CNTL_IJ_LINEAR_CENTROID) |
555 CONDREG(ij_regid[IJ_LINEAR_SAMPLE],
556 A5XX_GRAS_CNTL_IJ_LINEAR_SAMPLE) |
557 COND(s[FS].v->fragcoord_compmask != 0,
558 A5XX_GRAS_CNTL_COORD_MASK(s[FS].v->fragcoord_compmask) |
559 A5XX_GRAS_CNTL_IJ_LINEAR_PIXEL) |
560 COND(s[FS].v->frag_face, A5XX_GRAS_CNTL_IJ_LINEAR_PIXEL) |
561 CONDREG(ij_regid[IJ_LINEAR_PIXEL], A5XX_GRAS_CNTL_IJ_LINEAR_PIXEL));
562
563 OUT_PKT4(ring, REG_A5XX_RB_RENDER_CONTROL0, 2);
564 OUT_RING(
565 ring,
566 CONDREG(ij_regid[IJ_PERSP_PIXEL],
567 A5XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL) |
568 CONDREG(ij_regid[IJ_PERSP_CENTROID],
569 A5XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID) |
570 CONDREG(ij_regid[IJ_PERSP_SAMPLE],
571 A5XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE) |
572 CONDREG(ij_regid[IJ_LINEAR_PIXEL],
573 A5XX_RB_RENDER_CONTROL0_IJ_LINEAR_PIXEL) |
574 CONDREG(ij_regid[IJ_LINEAR_CENTROID],
575 A5XX_RB_RENDER_CONTROL0_IJ_LINEAR_CENTROID) |
576 CONDREG(ij_regid[IJ_LINEAR_SAMPLE],
577 A5XX_RB_RENDER_CONTROL0_IJ_LINEAR_SAMPLE) |
578 COND(s[FS].v->fragcoord_compmask != 0,
579 A5XX_RB_RENDER_CONTROL0_COORD_MASK(s[FS].v->fragcoord_compmask) |
580 A5XX_RB_RENDER_CONTROL0_IJ_LINEAR_PIXEL) |
581 COND(s[FS].v->frag_face, A5XX_RB_RENDER_CONTROL0_IJ_LINEAR_PIXEL) |
582 CONDREG(ij_regid[IJ_LINEAR_PIXEL], A5XX_RB_RENDER_CONTROL0_IJ_LINEAR_PIXEL));
583 OUT_RING(ring,
584 CONDREG(samp_mask_regid, A5XX_RB_RENDER_CONTROL1_SAMPLEMASK) |
585 COND(s[FS].v->frag_face, A5XX_RB_RENDER_CONTROL1_FACENESS) |
586 CONDREG(samp_id_regid, A5XX_RB_RENDER_CONTROL1_SAMPLEID));
587
588 OUT_PKT4(ring, REG_A5XX_SP_FS_OUTPUT_REG(0), 8);
589 for (i = 0; i < 8; i++) {
590 OUT_RING(ring, A5XX_SP_FS_OUTPUT_REG_REGID(color_regid[i]) |
591 COND(color_regid[i] & HALF_REG_ID,
592 A5XX_SP_FS_OUTPUT_REG_HALF_PRECISION));
593 }
594
595 OUT_PKT4(ring, REG_A5XX_VPC_PACK, 1);
596 OUT_RING(ring, A5XX_VPC_PACK_NUMNONPOSVAR(s[FS].v->total_in) |
597 A5XX_VPC_PACK_PSIZELOC(psize_loc));
598
599 if (!emit->binning_pass) {
600 uint32_t vinterp[8], vpsrepl[8];
601
602 memset(vinterp, 0, sizeof(vinterp));
603 memset(vpsrepl, 0, sizeof(vpsrepl));
604
605 /* looks like we need to do int varyings in the frag
606 * shader on a5xx (no flatshad reg? or a420.0 bug?):
607 *
608 * (sy)(ss)nop
609 * (sy)ldlv.u32 r0.x,l[r0.x], 1
610 * ldlv.u32 r0.y,l[r0.x+1], 1
611 * (ss)bary.f (ei)r63.x, 0, r0.x
612 * (ss)(rpt1)cov.s32f16 hr0.x, (r)r0.x
613 * (rpt5)nop
614 * sam (f16)(xyzw)hr0.x, hr0.x, s#0, t#0
615 *
616 * Possibly on later a5xx variants we'll be able to use
617 * something like the code below instead of workaround
618 * in the shader:
619 */
620 /* figure out VARYING_INTERP / VARYING_PS_REPL register values: */
621 for (j = -1;
622 (j = ir3_next_varying(s[FS].v, j)) < (int)s[FS].v->inputs_count;) {
623 /* NOTE: varyings are packed, so if compmask is 0xb
624 * then first, third, and fourth component occupy
625 * three consecutive varying slots:
626 */
627 unsigned compmask = s[FS].v->inputs[j].compmask;
628
629 uint32_t inloc = s[FS].v->inputs[j].inloc;
630
631 if (s[FS].v->inputs[j].flat ||
632 (s[FS].v->inputs[j].rasterflat && emit->rasterflat)) {
633 uint32_t loc = inloc;
634
635 for (i = 0; i < 4; i++) {
636 if (compmask & (1 << i)) {
637 vinterp[loc / 16] |= 1 << ((loc % 16) * 2);
638 // flatshade[loc / 32] |= 1 << (loc % 32);
639 loc++;
640 }
641 }
642 }
643
644 bool coord_mode = emit->sprite_coord_mode;
645 if (ir3_point_sprite(s[FS].v, j, emit->sprite_coord_enable,
646 &coord_mode)) {
647 /* mask is two 2-bit fields, where:
648 * '01' -> S
649 * '10' -> T
650 * '11' -> 1 - T (flip mode)
651 */
652 unsigned mask = coord_mode ? 0b1101 : 0b1001;
653 uint32_t loc = inloc;
654 if (compmask & 0x1) {
655 vpsrepl[loc / 16] |= ((mask >> 0) & 0x3) << ((loc % 16) * 2);
656 loc++;
657 }
658 if (compmask & 0x2) {
659 vpsrepl[loc / 16] |= ((mask >> 2) & 0x3) << ((loc % 16) * 2);
660 loc++;
661 }
662 if (compmask & 0x4) {
663 /* .z <- 0.0f */
664 vinterp[loc / 16] |= 0b10 << ((loc % 16) * 2);
665 loc++;
666 }
667 if (compmask & 0x8) {
668 /* .w <- 1.0f */
669 vinterp[loc / 16] |= 0b11 << ((loc % 16) * 2);
670 loc++;
671 }
672 }
673 }
674
675 OUT_PKT4(ring, REG_A5XX_VPC_VARYING_INTERP_MODE(0), 8);
676 for (i = 0; i < 8; i++)
677 OUT_RING(ring, vinterp[i]); /* VPC_VARYING_INTERP[i].MODE */
678
679 OUT_PKT4(ring, REG_A5XX_VPC_VARYING_PS_REPL_MODE(0), 8);
680 for (i = 0; i < 8; i++)
681 OUT_RING(ring, vpsrepl[i]); /* VPC_VARYING_PS_REPL[i] */
682 }
683
684 OUT_PKT4(ring, REG_A5XX_GRAS_VS_CL_CNTL, 1);
685 OUT_RING(ring, A5XX_GRAS_VS_CL_CNTL_CLIP_MASK(clip_mask) |
686 A5XX_GRAS_VS_CL_CNTL_CULL_MASK(cull_mask));
687
688 OUT_PKT4(ring, REG_A5XX_VPC_CLIP_CNTL, 1);
689 OUT_RING(ring, A5XX_VPC_CLIP_CNTL_CLIP_MASK(clip_cull_mask) |
690 A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC(clip0_loc) |
691 A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC(clip1_loc));
692
693 OUT_PKT4(ring, REG_A5XX_PC_CLIP_CNTL, 1);
694 OUT_RING(ring, A5XX_PC_CLIP_CNTL_CLIP_MASK(clip_mask));
695
696 if (!emit->binning_pass)
697 if (s[FS].instrlen)
698 fd5_emit_shader(ring, s[FS].v);
699
700 OUT_PKT4(ring, REG_A5XX_VFD_CONTROL_1, 5);
701 OUT_RING(ring, A5XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
702 A5XX_VFD_CONTROL_1_REGID4INST(instance_regid) | 0xfc0000);
703 OUT_RING(ring, 0x0000fcfc); /* VFD_CONTROL_2 */
704 OUT_RING(ring, 0x0000fcfc); /* VFD_CONTROL_3 */
705 OUT_RING(ring, 0x000000fc); /* VFD_CONTROL_4 */
706 OUT_RING(ring, 0x00000000); /* VFD_CONTROL_5 */
707 }
708
709 static struct ir3_program_state *
fd5_program_create(void * data,struct ir3_shader_variant * bs,struct ir3_shader_variant * vs,struct ir3_shader_variant * hs,struct ir3_shader_variant * ds,struct ir3_shader_variant * gs,struct ir3_shader_variant * fs,const struct ir3_shader_key * key)710 fd5_program_create(void *data, struct ir3_shader_variant *bs,
711 struct ir3_shader_variant *vs, struct ir3_shader_variant *hs,
712 struct ir3_shader_variant *ds, struct ir3_shader_variant *gs,
713 struct ir3_shader_variant *fs,
714 const struct ir3_shader_key *key) in_dt
715 {
716 struct fd_context *ctx = fd_context(data);
717 struct fd5_program_state *state = CALLOC_STRUCT(fd5_program_state);
718
719 tc_assert_driver_thread(ctx->tc);
720
721 state->bs = bs;
722 state->vs = vs;
723 state->fs = fs;
724
725 return &state->base;
726 }
727
728 static void
fd5_program_destroy(void * data,struct ir3_program_state * state)729 fd5_program_destroy(void *data, struct ir3_program_state *state)
730 {
731 struct fd5_program_state *so = fd5_program_state(state);
732 free(so);
733 }
734
735 static const struct ir3_cache_funcs cache_funcs = {
736 .create_state = fd5_program_create,
737 .destroy_state = fd5_program_destroy,
738 };
739
740 void
fd5_prog_init(struct pipe_context * pctx)741 fd5_prog_init(struct pipe_context *pctx)
742 {
743 struct fd_context *ctx = fd_context(pctx);
744
745 ctx->shader_cache = ir3_cache_create(&cache_funcs, ctx);
746 ir3_prog_init(pctx);
747 fd_prog_init(pctx);
748 }
749