Searched refs:b1010 (Results 1 – 21 of 21) sorted by relevance
117 def : DC<"CVAC", 0b011, 0b0111, 0b1010, 0b001>;118 def : DC<"CSW", 0b000, 0b0111, 0b1010, 0b010>;132 def : DC<"CGSW", 0b000, 0b0111, 0b1010, 0b100>;134 def : DC<"CGVAC", 0b011, 0b0111, 0b1010, 0b011>;141 def : DC<"CGDSW", 0b000, 0b0111, 0b1010, 0b110>;143 def : DC<"CGDVAC", 0b011, 0b0111, 0b1010, 0b101>;628 def : ROSysReg<"TRCIDR2", 0b10, 0b001, 0b0000, 0b1010, 0b111>;636 def : ROSysReg<"TRCDEVAFF0", 0b10, 0b001, 0b0111, 0b1010, 0b110>;649 def : ROSysReg<"TRCPIDR2", 0b10, 0b001, 0b0111, 0b1010, 0b111>;676 def : ROSysReg<"LORID_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b111>;[all …]
203 defm FMULX_ZPmZ : sve_fp_2op_p_zds<0b1010, "fmulx", int_aarch64_sve_fmulx>;322 defm NOR_PPzPP : sve_int_pred_log<0b1010, "nor", int_aarch64_sve_nor_z>;352 defm LD1W_IMM : sve_mem_cld_si<0b1010, "ld1w", Z_s, ZPR32>;398 defm LD1W : sve_mem_cld_ss<0b1010, "ld1w", Z_s, ZPR32, GPR64NoXZRshifted32>;416 defm LDNF1W_IMM : sve_mem_cldnf_si<0b1010, "ldnf1w", Z_s, ZPR32>;434 defm LDFF1W : sve_mem_cldff_ss<0b1010, "ldff1w", Z_s, ZPR32, GPR64shifted32>;479 …defm GLD1W : sve_mem_32b_gld_vs_32_unscaled<0b1010, "ld1w", AArch64ld1_gather_sxtw, AAr…488 …defm GLD1W : sve_mem_32b_gld_sv_32_scaled<0b1010, "ld1w", AArch64ld1_gather_sxtw_scaled, …501 …defm GLD1W : sve_mem_32b_gld_vi_32_ptrs<0b1010, "ld1w", uimm5s4, AArch64ld1_gather_imm, …516 …defm GLD1W_D : sve_mem_64b_gld_vi_64_ptrs<0b1010, "ld1w", uimm5s4, AArch64ld1_gather_imm, …[all …]
2902 let Inst{15-12} = 0b1010;3517 def _B : sve_int_arith_imm<0b00, { 0b1010, opc }, asm, ZPR8, simm8>;3518 def _H : sve_int_arith_imm<0b01, { 0b1010, opc }, asm, ZPR16, simm8>;3519 def _S : sve_int_arith_imm<0b10, { 0b1010, opc }, asm, ZPR32, simm8>;3520 def _D : sve_int_arith_imm<0b11, { 0b1010, opc }, asm, ZPR64, simm8>;3529 def _B : sve_int_arith_imm<0b00, { 0b1010, opc }, asm, ZPR8, imm0_255>;3530 def _H : sve_int_arith_imm<0b01, { 0b1010, opc }, asm, ZPR16, imm0_255>;3531 def _S : sve_int_arith_imm<0b10, { 0b1010, opc }, asm, ZPR32, imm0_255>;3532 def _D : sve_int_arith_imm<0b11, { 0b1010, opc }, asm, ZPR64, imm0_255>;6366 let Inst{15-12} = 0b1010;
3424 defm FRINTM : SingleOperandFPData<0b1010, "frintm", ffloor>;4492 defm SMLSL : SIMDLongThreeVectorTiedBHS<0, 0b1010, "smlsl",4513 defm UMLSL : SIMDLongThreeVectorTiedBHS<1, 0b1010, "umlsl",5632 defm SMULL : SIMDVectorIndexedLongSD<0, 0b1010, "smull",5647 defm UMULL : SIMDVectorIndexedLongSD<1, 0b1010, "umull",
9403 defm Two : BaseSIMDLd1<NAME, "Two", asm, "VecListTwo", 32, 16, 0b1010>;9410 defm Two : BaseSIMDSt1<NAME, "Two", asm, "VecListTwo", 32, 16, 0b1010>;
1071 def VMOVRS : AVConv2I<0b11100001, 0b1010,1095 def VMOVSR : AVConv4I<0b11100000, 0b1010,1150 def VMOVRRS : AVConv3I<0b11000101, 0b1010,1223 def VMOVSRR : AVConv5I<0b11000100, 0b1010,1373 def VSITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,1419 def VUITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,1523 def VTOSIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,1570 def VTOUIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,1611 def VTOSIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,1636 def VTOUIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,[all …]
632 : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd),669 def _fixed : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb),677 def _register : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb),1228 def VLD3LNd32 : VLD3LN<0b1010, {?,0,0,0}, "32"> {1240 def VLD3LNq32 : VLD3LN<0b1010, {?,1,0,0}, "32"> {1266 def VLD3LNd32_UPD : VLD3LNWB<0b1010, {?,0,0,0}, "32"> {1277 def VLD3LNq32_UPD : VLD3LNWB<0b1010, {?,1,0,0}, "32"> {1693 : NLdSt<0,0b00,0b1010,op7_4, (outs), (ins AddrMode:$Rn, VecListDPair:$Vd),1730 def _fixed : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),1738 def _register : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),[all …]
355 let Inst{9-6} = 0b1010;1114 T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm),
2293 defm t2ADC : T2I_adde_sube_irs<0b1010, "adc", ARMadde, 1>;2431 def t2QSUB : T2I_pam_intrinsics_rev<0b000, 0b1010, "qsub">;3047 def t2SMLALTB : T2MlaLong<0b100, 0b1010, "smlaltb">,5401 def t2CSINV : CS<"csinv", 0b1010>;
2425 def Bcc : ABI<0b1010, (outs), (ins arm_br_target:$target),3500 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),4684 defm CMP : AI1_cmp_irs<0b1010, "cmp",
137 b1010 = 0xA, enumerator152 { true, true, false, b1010, b1010, b0101, false, NONE },153 { false, true, true, b1010, b1010, b1111, false, NONE },
51 … {0b1010, ResetterRound::kReconstructSeccrets},
272 defm : int_cond_alias<"g", 0b1010>;303 defm : fp_cond_alias<"ue", 0b1010>;326 defm : cp_cond_alias<"03", 0b1010>;
135 - HCLEN = 0b1010 = 10385 0b1010 8
755 class FSEQ_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011010>;756 class FSEQ_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011010>;788 class FSUNE_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011100>;789 class FSUNE_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011100>;797 class FTQ_H_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011011>;798 class FTQ_W_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011011>;
231 class SDC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"sdc2", 0b1010>;
550 defm DADD : Arith<0b1010, "dadd", MSP430dadd, 1, [SR]>;
399 * New binary literals, e.g. ``0b1010`` (already in 2.6), and
930 [[`BOOST_NO_CXX14_BINARY_LITERALS`][The compiler does not binary literals (e.g. `0b1010`).]]
2647 let Inst{13-10} = 0b1010;2703 let Inst{13-10} = 0b1010;2759 let Inst{13-10} = 0b1010;2815 let Inst{13-10} = 0b1010;2871 let Inst{13-10} = 0b1010;2927 let Inst{13-10} = 0b1010;9532 let Inst{24-21} = 0b1010;9638 let Inst{24-21} = 0b1010;13405 let Inst{13-10} = 0b1010;17606 let Inst{24-21} = 0b1010;[all …]
130 '-0b1010'